2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
34 #include <asm/div64.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
42 #define ATOM_RATIOS 0x66a
43 #define ATOM_VIDS 0x66b
44 #define ATOM_TURBO_RATIOS 0x66c
45 #define ATOM_TURBO_VIDS 0x66d
48 #include <acpi/processor.h>
52 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
53 #define fp_toint(X) ((X) >> FRAC_BITS)
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
60 static inline int32_t mul_fp(int32_t x, int32_t y)
62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
65 static inline int32_t div_fp(s64 x, s64 y)
67 return div64_s64((int64_t)x << FRAC_BITS, y);
70 static inline int ceiling_fp(int32_t x)
75 mask = (1 << FRAC_BITS) - 1;
81 static inline u64 mul_ext_fp(u64 x, u64 y)
83 return (x * y) >> EXT_FRAC_BITS;
86 static inline u64 div_ext_fp(u64 x, u64 y)
88 return div64_u64(x << EXT_FRAC_BITS, y);
92 * struct sample - Store performance sample
93 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
94 * performance during last sample period
95 * @busy_scaled: Scaled busy value which is used to calculate next
96 * P state. This can be different than core_avg_perf
97 * to account for cpu idle period
98 * @aperf: Difference of actual performance frequency clock count
99 * read from APERF MSR between last and current sample
100 * @mperf: Difference of maximum performance frequency clock count
101 * read from MPERF MSR between last and current sample
102 * @tsc: Difference of time stamp counter between last and
104 * @time: Current time from scheduler
106 * This structure is used in the cpudata structure to store performance sample
107 * data for choosing next P State.
110 int32_t core_avg_perf;
119 * struct pstate_data - Store P state data
120 * @current_pstate: Current requested P state
121 * @min_pstate: Min P state possible for this platform
122 * @max_pstate: Max P state possible for this platform
123 * @max_pstate_physical:This is physical Max P state for a processor
124 * This can be higher than the max_pstate which can
125 * be limited by platform thermal design power limits
126 * @scaling: Scaling factor to convert frequency to cpufreq
128 * @turbo_pstate: Max Turbo P state possible for this platform
129 * @max_freq: @max_pstate frequency in cpufreq units
130 * @turbo_freq: @turbo_pstate frequency in cpufreq units
132 * Stores the per cpu model P state limits and current P state.
138 int max_pstate_physical;
141 unsigned int max_freq;
142 unsigned int turbo_freq;
146 * struct vid_data - Stores voltage information data
147 * @min: VID data for this platform corresponding to
149 * @max: VID data corresponding to the highest P State.
150 * @turbo: VID data for turbo P state
151 * @ratio: Ratio of (vid max - vid min) /
152 * (max P state - Min P State)
154 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
155 * This data is used in Atom platforms, where in addition to target P state,
156 * the voltage data needs to be specified to select next P State.
166 * struct _pid - Stores PID data
167 * @setpoint: Target set point for busyness or performance
168 * @integral: Storage for accumulated error values
169 * @p_gain: PID proportional gain
170 * @i_gain: PID integral gain
171 * @d_gain: PID derivative gain
172 * @deadband: PID deadband
173 * @last_err: Last error storage for integral part of PID calculation
175 * Stores PID coefficients and last error for PID controller.
188 * struct perf_limits - Store user and policy limits
189 * @no_turbo: User requested turbo state from intel_pstate sysfs
190 * @turbo_disabled: Platform turbo status either from msr
191 * MSR_IA32_MISC_ENABLE or when maximum available pstate
192 * matches the maximum turbo pstate
193 * @max_perf_pct: Effective maximum performance limit in percentage, this
194 * is minimum of either limits enforced by cpufreq policy
195 * or limits from user set limits via intel_pstate sysfs
196 * @min_perf_pct: Effective minimum performance limit in percentage, this
197 * is maximum of either limits enforced by cpufreq policy
198 * or limits from user set limits via intel_pstate sysfs
199 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
200 * This value is used to limit max pstate
201 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
202 * This value is used to limit min pstate
203 * @max_policy_pct: The maximum performance in percentage enforced by
204 * cpufreq setpolicy interface
205 * @max_sysfs_pct: The maximum performance in percentage enforced by
206 * intel pstate sysfs interface, unused when per cpu
207 * controls are enforced
208 * @min_policy_pct: The minimum performance in percentage enforced by
209 * cpufreq setpolicy interface
210 * @min_sysfs_pct: The minimum performance in percentage enforced by
211 * intel pstate sysfs interface, unused when per cpu
212 * controls are enforced
214 * Storage for user and policy defined limits.
230 * struct cpudata - Per CPU instance data storage
231 * @cpu: CPU number for this instance data
232 * @policy: CPUFreq policy value
233 * @update_util: CPUFreq utility callback information
234 * @update_util_set: CPUFreq utility callback is set
235 * @iowait_boost: iowait-related boost fraction
236 * @last_update: Time of the last update.
237 * @pstate: Stores P state limits for this CPU
238 * @vid: Stores VID limits for this CPU
239 * @pid: Stores PID parameters for this CPU
240 * @last_sample_time: Last Sample time
241 * @prev_aperf: Last APERF value read from APERF MSR
242 * @prev_mperf: Last MPERF value read from MPERF MSR
243 * @prev_tsc: Last timestamp counter (TSC) value
244 * @prev_cummulative_iowait: IO Wait time difference from last and
246 * @sample: Storage for storing last Sample data
247 * @perf_limits: Pointer to perf_limit unique to this CPU
248 * Not all field in the structure are applicable
249 * when per cpu controls are enforced
250 * @acpi_perf_data: Stores ACPI perf information read from _PSS
251 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
252 * @epp_powersave: Last saved HWP energy performance preference
253 * (EPP) or energy performance bias (EPB),
254 * when policy switched to performance
255 * @epp_policy: Last saved policy used to set EPP/EPB
256 * @epp_default: Power on default HWP energy performance
258 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
261 * This structure stores per CPU instance data for all CPUs.
267 struct update_util_data update_util;
268 bool update_util_set;
270 struct pstate_data pstate;
275 u64 last_sample_time;
279 u64 prev_cummulative_iowait;
280 struct sample sample;
281 struct perf_limits *perf_limits;
283 struct acpi_processor_performance acpi_perf_data;
284 bool valid_pss_table;
286 unsigned int iowait_boost;
293 static struct cpudata **all_cpu_data;
296 * struct pstate_adjust_policy - Stores static PID configuration data
297 * @sample_rate_ms: PID calculation sample rate in ms
298 * @sample_rate_ns: Sample rate calculation in ns
299 * @deadband: PID deadband
300 * @setpoint: PID Setpoint
301 * @p_gain_pct: PID proportional gain
302 * @i_gain_pct: PID integral gain
303 * @d_gain_pct: PID derivative gain
305 * Stores per CPU model static PID configuration data.
307 struct pstate_adjust_policy {
318 * struct pstate_funcs - Per CPU model specific callbacks
319 * @get_max: Callback to get maximum non turbo effective P state
320 * @get_max_physical: Callback to get maximum non turbo physical P state
321 * @get_min: Callback to get minimum P state
322 * @get_turbo: Callback to get turbo P state
323 * @get_scaling: Callback to get frequency scaling factor
324 * @get_val: Callback to convert P state to actual MSR write value
325 * @get_vid: Callback to get VID data for Atom platforms
326 * @get_target_pstate: Callback to a function to calculate next P state to use
328 * Core and Atom CPU models have different way to get P State limits. This
329 * structure is used to store those callbacks.
331 struct pstate_funcs {
332 int (*get_max)(void);
333 int (*get_max_physical)(void);
334 int (*get_min)(void);
335 int (*get_turbo)(void);
336 int (*get_scaling)(void);
337 u64 (*get_val)(struct cpudata*, int pstate);
338 void (*get_vid)(struct cpudata *);
339 int32_t (*get_target_pstate)(struct cpudata *);
343 * struct cpu_defaults- Per CPU model default config data
344 * @pid_policy: PID config data
345 * @funcs: Callback function data
347 struct cpu_defaults {
348 struct pstate_adjust_policy pid_policy;
349 struct pstate_funcs funcs;
352 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
353 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
355 static struct pstate_adjust_policy pid_params __read_mostly;
356 static struct pstate_funcs pstate_funcs __read_mostly;
357 static int hwp_active __read_mostly;
358 static bool per_cpu_limits __read_mostly;
361 static bool acpi_ppc;
364 static struct perf_limits performance_limits = {
368 .max_perf = int_ext_tofp(1),
370 .min_perf = int_ext_tofp(1),
371 .max_policy_pct = 100,
372 .max_sysfs_pct = 100,
377 static struct perf_limits powersave_limits = {
381 .max_perf = int_ext_tofp(1),
384 .max_policy_pct = 100,
385 .max_sysfs_pct = 100,
390 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
391 static struct perf_limits *limits = &performance_limits;
393 static struct perf_limits *limits = &powersave_limits;
396 static DEFINE_MUTEX(intel_pstate_limits_lock);
400 static bool intel_pstate_get_ppc_enable_status(void)
402 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
403 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
409 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
418 if (!intel_pstate_get_ppc_enable_status())
421 cpu = all_cpu_data[policy->cpu];
423 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
429 * Check if the control value in _PSS is for PERF_CTL MSR, which should
430 * guarantee that the states returned by it map to the states in our
433 if (cpu->acpi_perf_data.control_register.space_id !=
434 ACPI_ADR_SPACE_FIXED_HARDWARE)
438 * If there is only one entry _PSS, simply ignore _PSS and continue as
439 * usual without taking _PSS into account
441 if (cpu->acpi_perf_data.state_count < 2)
444 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
445 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
446 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
447 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
448 (u32) cpu->acpi_perf_data.states[i].core_frequency,
449 (u32) cpu->acpi_perf_data.states[i].power,
450 (u32) cpu->acpi_perf_data.states[i].control);
454 * The _PSS table doesn't contain whole turbo frequency range.
455 * This just contains +1 MHZ above the max non turbo frequency,
456 * with control value corresponding to max turbo ratio. But
457 * when cpufreq set policy is called, it will call with this
458 * max frequency, which will cause a reduced performance as
459 * this driver uses real max turbo frequency as the max
460 * frequency. So correct this frequency in _PSS table to
461 * correct max turbo frequency based on the turbo state.
462 * Also need to convert to MHz as _PSS freq is in MHz.
464 if (!limits->turbo_disabled)
465 cpu->acpi_perf_data.states[0].core_frequency =
466 policy->cpuinfo.max_freq / 1000;
467 cpu->valid_pss_table = true;
468 pr_debug("_PPC limits will be enforced\n");
473 cpu->valid_pss_table = false;
474 acpi_processor_unregister_performance(policy->cpu);
477 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
481 cpu = all_cpu_data[policy->cpu];
482 if (!cpu->valid_pss_table)
485 acpi_processor_unregister_performance(policy->cpu);
489 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
493 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
498 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
499 int deadband, int integral) {
500 pid->setpoint = int_tofp(setpoint);
501 pid->deadband = int_tofp(deadband);
502 pid->integral = int_tofp(integral);
503 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
506 static inline void pid_p_gain_set(struct _pid *pid, int percent)
508 pid->p_gain = div_fp(percent, 100);
511 static inline void pid_i_gain_set(struct _pid *pid, int percent)
513 pid->i_gain = div_fp(percent, 100);
516 static inline void pid_d_gain_set(struct _pid *pid, int percent)
518 pid->d_gain = div_fp(percent, 100);
521 static signed int pid_calc(struct _pid *pid, int32_t busy)
524 int32_t pterm, dterm, fp_error;
525 int32_t integral_limit;
527 fp_error = pid->setpoint - busy;
529 if (abs(fp_error) <= pid->deadband)
532 pterm = mul_fp(pid->p_gain, fp_error);
534 pid->integral += fp_error;
537 * We limit the integral here so that it will never
538 * get higher than 30. This prevents it from becoming
539 * too large an input over long periods of time and allows
540 * it to get factored out sooner.
542 * The value of 30 was chosen through experimentation.
544 integral_limit = int_tofp(30);
545 if (pid->integral > integral_limit)
546 pid->integral = integral_limit;
547 if (pid->integral < -integral_limit)
548 pid->integral = -integral_limit;
550 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
551 pid->last_err = fp_error;
553 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
554 result = result + (1 << (FRAC_BITS-1));
555 return (signed int)fp_toint(result);
558 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
560 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
561 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
562 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
564 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
567 static inline void intel_pstate_reset_all_pid(void)
571 for_each_online_cpu(cpu) {
572 if (all_cpu_data[cpu])
573 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
577 static inline void update_turbo_state(void)
582 cpu = all_cpu_data[0];
583 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
584 limits->turbo_disabled =
585 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
586 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
589 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
594 if (!static_cpu_has(X86_FEATURE_EPB))
597 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
601 return (s16)(epb & 0x0f);
604 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
608 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
610 * When hwp_req_data is 0, means that caller didn't read
611 * MSR_HWP_REQUEST, so need to read and get EPP.
614 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
619 epp = (hwp_req_data >> 24) & 0xff;
621 /* When there is no EPP present, HWP uses EPB settings */
622 epp = intel_pstate_get_epb(cpu_data);
628 static int intel_pstate_set_epb(int cpu, s16 pref)
633 if (!static_cpu_has(X86_FEATURE_EPB))
636 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
640 epb = (epb & ~0x0f) | pref;
641 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
647 * EPP/EPB display strings corresponding to EPP index in the
648 * energy_perf_strings[]
650 *-------------------------------------
653 * 2 balance_performance
657 static const char * const energy_perf_strings[] = {
660 "balance_performance",
666 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
671 epp = intel_pstate_get_epp(cpu_data, 0);
675 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
678 * 0x00-0x3F : Performance
679 * 0x40-0x7F : Balance performance
680 * 0x80-0xBF : Balance power
682 * The EPP is a 8 bit value, but our ranges restrict the
683 * value which can be set. Here only using top two bits
686 index = (epp >> 6) + 1;
687 } else if (static_cpu_has(X86_FEATURE_EPB)) {
690 * 0x00-0x03 : Performance
691 * 0x04-0x07 : Balance performance
692 * 0x08-0x0B : Balance power
694 * The EPB is a 4 bit value, but our ranges restrict the
695 * value which can be set. Here only using top two bits
698 index = (epp >> 2) + 1;
704 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
711 epp = cpu_data->epp_default;
713 mutex_lock(&intel_pstate_limits_lock);
715 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
718 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
722 value &= ~GENMASK_ULL(31, 24);
725 * If epp is not default, convert from index into
726 * energy_perf_strings to epp value, by shifting 6
727 * bits left to use only top two bits in epp.
728 * The resultant epp need to shifted by 24 bits to
729 * epp position in MSR_HWP_REQUEST.
732 epp = (pref_index - 1) << 6;
734 value |= (u64)epp << 24;
735 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
738 epp = (pref_index - 1) << 2;
739 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
742 mutex_unlock(&intel_pstate_limits_lock);
747 static ssize_t show_energy_performance_available_preferences(
748 struct cpufreq_policy *policy, char *buf)
753 while (energy_perf_strings[i] != NULL)
754 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
756 ret += sprintf(&buf[ret], "\n");
761 cpufreq_freq_attr_ro(energy_performance_available_preferences);
763 static ssize_t store_energy_performance_preference(
764 struct cpufreq_policy *policy, const char *buf, size_t count)
766 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
767 char str_preference[21];
770 ret = sscanf(buf, "%20s", str_preference);
774 while (energy_perf_strings[i] != NULL) {
775 if (!strcmp(str_preference, energy_perf_strings[i])) {
776 intel_pstate_set_energy_pref_index(cpu_data, i);
785 static ssize_t show_energy_performance_preference(
786 struct cpufreq_policy *policy, char *buf)
788 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
791 preference = intel_pstate_get_energy_pref_index(cpu_data);
795 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
798 cpufreq_freq_attr_rw(energy_performance_preference);
800 static struct freq_attr *hwp_cpufreq_attrs[] = {
801 &energy_performance_preference,
802 &energy_performance_available_preferences,
806 static void intel_pstate_hwp_set(const struct cpumask *cpumask)
808 int min, hw_min, max, hw_max, cpu, range, adj_range;
809 struct perf_limits *perf_limits = limits;
812 for_each_cpu(cpu, cpumask) {
813 int max_perf_pct, min_perf_pct;
814 struct cpudata *cpu_data = all_cpu_data[cpu];
818 perf_limits = all_cpu_data[cpu]->perf_limits;
820 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
821 hw_min = HWP_LOWEST_PERF(cap);
822 hw_max = HWP_HIGHEST_PERF(cap);
823 range = hw_max - hw_min;
825 max_perf_pct = perf_limits->max_perf_pct;
826 min_perf_pct = perf_limits->min_perf_pct;
828 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
829 adj_range = min_perf_pct * range / 100;
830 min = hw_min + adj_range;
831 value &= ~HWP_MIN_PERF(~0L);
832 value |= HWP_MIN_PERF(min);
834 adj_range = max_perf_pct * range / 100;
835 max = hw_min + adj_range;
836 if (limits->no_turbo) {
837 hw_max = HWP_GUARANTEED_PERF(cap);
842 value &= ~HWP_MAX_PERF(~0L);
843 value |= HWP_MAX_PERF(max);
845 if (cpu_data->epp_policy == cpu_data->policy)
848 cpu_data->epp_policy = cpu_data->policy;
850 if (cpu_data->epp_saved >= 0) {
851 epp = cpu_data->epp_saved;
852 cpu_data->epp_saved = -EINVAL;
856 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
857 epp = intel_pstate_get_epp(cpu_data, value);
858 cpu_data->epp_powersave = epp;
859 /* If EPP read was failed, then don't try to write */
866 /* skip setting EPP, when saved value is invalid */
867 if (cpu_data->epp_powersave < 0)
871 * No need to restore EPP when it is not zero. This
873 * - Policy is not changed
874 * - user has manually changed
875 * - Error reading EPB
877 epp = intel_pstate_get_epp(cpu_data, value);
881 epp = cpu_data->epp_powersave;
884 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
885 value &= ~GENMASK_ULL(31, 24);
886 value |= (u64)epp << 24;
888 intel_pstate_set_epb(cpu, epp);
891 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
895 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
898 intel_pstate_hwp_set(policy->cpus);
903 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
905 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
910 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
915 static int intel_pstate_resume(struct cpufreq_policy *policy)
920 all_cpu_data[policy->cpu]->epp_policy = 0;
922 return intel_pstate_hwp_set_policy(policy);
925 static void intel_pstate_hwp_set_online_cpus(void)
928 intel_pstate_hwp_set(cpu_online_mask);
932 /************************** debugfs begin ************************/
933 static int pid_param_set(void *data, u64 val)
936 intel_pstate_reset_all_pid();
940 static int pid_param_get(void *data, u64 *val)
945 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
952 static struct pid_param pid_files[] = {
953 {"sample_rate_ms", &pid_params.sample_rate_ms},
954 {"d_gain_pct", &pid_params.d_gain_pct},
955 {"i_gain_pct", &pid_params.i_gain_pct},
956 {"deadband", &pid_params.deadband},
957 {"setpoint", &pid_params.setpoint},
958 {"p_gain_pct", &pid_params.p_gain_pct},
962 static void __init intel_pstate_debug_expose_params(void)
964 struct dentry *debugfs_parent;
968 pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load)
971 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
972 if (IS_ERR_OR_NULL(debugfs_parent))
974 while (pid_files[i].name) {
975 debugfs_create_file(pid_files[i].name, 0660,
976 debugfs_parent, pid_files[i].value,
982 /************************** debugfs end ************************/
984 /************************** sysfs begin ************************/
985 #define show_one(file_name, object) \
986 static ssize_t show_##file_name \
987 (struct kobject *kobj, struct attribute *attr, char *buf) \
989 return sprintf(buf, "%u\n", limits->object); \
992 static ssize_t show_turbo_pct(struct kobject *kobj,
993 struct attribute *attr, char *buf)
996 int total, no_turbo, turbo_pct;
999 cpu = all_cpu_data[0];
1001 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1002 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1003 turbo_fp = div_fp(no_turbo, total);
1004 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1005 return sprintf(buf, "%u\n", turbo_pct);
1008 static ssize_t show_num_pstates(struct kobject *kobj,
1009 struct attribute *attr, char *buf)
1011 struct cpudata *cpu;
1014 cpu = all_cpu_data[0];
1015 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1016 return sprintf(buf, "%u\n", total);
1019 static ssize_t show_no_turbo(struct kobject *kobj,
1020 struct attribute *attr, char *buf)
1024 update_turbo_state();
1025 if (limits->turbo_disabled)
1026 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
1028 ret = sprintf(buf, "%u\n", limits->no_turbo);
1033 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1034 const char *buf, size_t count)
1039 ret = sscanf(buf, "%u", &input);
1043 mutex_lock(&intel_pstate_limits_lock);
1045 update_turbo_state();
1046 if (limits->turbo_disabled) {
1047 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1048 mutex_unlock(&intel_pstate_limits_lock);
1052 limits->no_turbo = clamp_t(int, input, 0, 1);
1055 intel_pstate_hwp_set_online_cpus();
1057 mutex_unlock(&intel_pstate_limits_lock);
1062 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1063 const char *buf, size_t count)
1068 ret = sscanf(buf, "%u", &input);
1072 mutex_lock(&intel_pstate_limits_lock);
1074 limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
1075 limits->max_perf_pct = min(limits->max_policy_pct,
1076 limits->max_sysfs_pct);
1077 limits->max_perf_pct = max(limits->min_policy_pct,
1078 limits->max_perf_pct);
1079 limits->max_perf_pct = max(limits->min_perf_pct,
1080 limits->max_perf_pct);
1081 limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1084 intel_pstate_hwp_set_online_cpus();
1086 mutex_unlock(&intel_pstate_limits_lock);
1091 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1092 const char *buf, size_t count)
1097 ret = sscanf(buf, "%u", &input);
1101 mutex_lock(&intel_pstate_limits_lock);
1103 limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
1104 limits->min_perf_pct = max(limits->min_policy_pct,
1105 limits->min_sysfs_pct);
1106 limits->min_perf_pct = min(limits->max_policy_pct,
1107 limits->min_perf_pct);
1108 limits->min_perf_pct = min(limits->max_perf_pct,
1109 limits->min_perf_pct);
1110 limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1113 intel_pstate_hwp_set_online_cpus();
1115 mutex_unlock(&intel_pstate_limits_lock);
1120 show_one(max_perf_pct, max_perf_pct);
1121 show_one(min_perf_pct, min_perf_pct);
1123 define_one_global_rw(no_turbo);
1124 define_one_global_rw(max_perf_pct);
1125 define_one_global_rw(min_perf_pct);
1126 define_one_global_ro(turbo_pct);
1127 define_one_global_ro(num_pstates);
1129 static struct attribute *intel_pstate_attributes[] = {
1136 static struct attribute_group intel_pstate_attr_group = {
1137 .attrs = intel_pstate_attributes,
1140 static void __init intel_pstate_sysfs_expose_params(void)
1142 struct kobject *intel_pstate_kobject;
1145 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1146 &cpu_subsys.dev_root->kobj);
1147 if (WARN_ON(!intel_pstate_kobject))
1150 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1155 * If per cpu limits are enforced there are no global limits, so
1156 * return without creating max/min_perf_pct attributes
1161 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1164 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1168 /************************** sysfs end ************************/
1170 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1172 /* First disable HWP notification interrupt as we don't process them */
1173 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1174 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1176 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1177 cpudata->epp_policy = 0;
1178 if (cpudata->epp_default == -EINVAL)
1179 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1182 static int atom_get_min_pstate(void)
1186 rdmsrl(ATOM_RATIOS, value);
1187 return (value >> 8) & 0x7F;
1190 static int atom_get_max_pstate(void)
1194 rdmsrl(ATOM_RATIOS, value);
1195 return (value >> 16) & 0x7F;
1198 static int atom_get_turbo_pstate(void)
1202 rdmsrl(ATOM_TURBO_RATIOS, value);
1203 return value & 0x7F;
1206 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1212 val = (u64)pstate << 8;
1213 if (limits->no_turbo && !limits->turbo_disabled)
1214 val |= (u64)1 << 32;
1216 vid_fp = cpudata->vid.min + mul_fp(
1217 int_tofp(pstate - cpudata->pstate.min_pstate),
1218 cpudata->vid.ratio);
1220 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1221 vid = ceiling_fp(vid_fp);
1223 if (pstate > cpudata->pstate.max_pstate)
1224 vid = cpudata->vid.turbo;
1229 static int silvermont_get_scaling(void)
1233 /* Defined in Table 35-6 from SDM (Sept 2015) */
1234 static int silvermont_freq_table[] = {
1235 83300, 100000, 133300, 116700, 80000};
1237 rdmsrl(MSR_FSB_FREQ, value);
1241 return silvermont_freq_table[i];
1244 static int airmont_get_scaling(void)
1248 /* Defined in Table 35-10 from SDM (Sept 2015) */
1249 static int airmont_freq_table[] = {
1250 83300, 100000, 133300, 116700, 80000,
1251 93300, 90000, 88900, 87500};
1253 rdmsrl(MSR_FSB_FREQ, value);
1257 return airmont_freq_table[i];
1260 static void atom_get_vid(struct cpudata *cpudata)
1264 rdmsrl(ATOM_VIDS, value);
1265 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1266 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1267 cpudata->vid.ratio = div_fp(
1268 cpudata->vid.max - cpudata->vid.min,
1269 int_tofp(cpudata->pstate.max_pstate -
1270 cpudata->pstate.min_pstate));
1272 rdmsrl(ATOM_TURBO_VIDS, value);
1273 cpudata->vid.turbo = value & 0x7f;
1276 static int core_get_min_pstate(void)
1280 rdmsrl(MSR_PLATFORM_INFO, value);
1281 return (value >> 40) & 0xFF;
1284 static int core_get_max_pstate_physical(void)
1288 rdmsrl(MSR_PLATFORM_INFO, value);
1289 return (value >> 8) & 0xFF;
1292 static int core_get_max_pstate(void)
1299 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1300 max_pstate = (plat_info >> 8) & 0xFF;
1302 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1304 /* Do some sanity checking for safety */
1305 if (plat_info & 0x600000000) {
1310 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1314 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3);
1315 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1319 /* For level 1 and 2, bits[23:16] contain the ratio */
1323 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1324 if (tdp_ratio - 1 == tar) {
1326 pr_debug("max_pstate=TAC %x\n", max_pstate);
1337 static int core_get_turbo_pstate(void)
1342 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1343 nont = core_get_max_pstate();
1344 ret = (value) & 255;
1350 static inline int core_get_scaling(void)
1355 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1359 val = (u64)pstate << 8;
1360 if (limits->no_turbo && !limits->turbo_disabled)
1361 val |= (u64)1 << 32;
1366 static int knl_get_turbo_pstate(void)
1371 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1372 nont = core_get_max_pstate();
1373 ret = (((value) >> 8) & 0xFF);
1379 static struct cpu_defaults core_params = {
1381 .sample_rate_ms = 10,
1389 .get_max = core_get_max_pstate,
1390 .get_max_physical = core_get_max_pstate_physical,
1391 .get_min = core_get_min_pstate,
1392 .get_turbo = core_get_turbo_pstate,
1393 .get_scaling = core_get_scaling,
1394 .get_val = core_get_val,
1395 .get_target_pstate = get_target_pstate_use_performance,
1399 static const struct cpu_defaults silvermont_params = {
1401 .sample_rate_ms = 10,
1409 .get_max = atom_get_max_pstate,
1410 .get_max_physical = atom_get_max_pstate,
1411 .get_min = atom_get_min_pstate,
1412 .get_turbo = atom_get_turbo_pstate,
1413 .get_val = atom_get_val,
1414 .get_scaling = silvermont_get_scaling,
1415 .get_vid = atom_get_vid,
1416 .get_target_pstate = get_target_pstate_use_cpu_load,
1420 static const struct cpu_defaults airmont_params = {
1422 .sample_rate_ms = 10,
1430 .get_max = atom_get_max_pstate,
1431 .get_max_physical = atom_get_max_pstate,
1432 .get_min = atom_get_min_pstate,
1433 .get_turbo = atom_get_turbo_pstate,
1434 .get_val = atom_get_val,
1435 .get_scaling = airmont_get_scaling,
1436 .get_vid = atom_get_vid,
1437 .get_target_pstate = get_target_pstate_use_cpu_load,
1441 static const struct cpu_defaults knl_params = {
1443 .sample_rate_ms = 10,
1451 .get_max = core_get_max_pstate,
1452 .get_max_physical = core_get_max_pstate_physical,
1453 .get_min = core_get_min_pstate,
1454 .get_turbo = knl_get_turbo_pstate,
1455 .get_scaling = core_get_scaling,
1456 .get_val = core_get_val,
1457 .get_target_pstate = get_target_pstate_use_performance,
1461 static const struct cpu_defaults bxt_params = {
1463 .sample_rate_ms = 10,
1471 .get_max = core_get_max_pstate,
1472 .get_max_physical = core_get_max_pstate_physical,
1473 .get_min = core_get_min_pstate,
1474 .get_turbo = core_get_turbo_pstate,
1475 .get_scaling = core_get_scaling,
1476 .get_val = core_get_val,
1477 .get_target_pstate = get_target_pstate_use_cpu_load,
1481 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1483 int max_perf = cpu->pstate.turbo_pstate;
1486 struct perf_limits *perf_limits = limits;
1488 if (limits->no_turbo || limits->turbo_disabled)
1489 max_perf = cpu->pstate.max_pstate;
1492 perf_limits = cpu->perf_limits;
1495 * performance can be limited by user through sysfs, by cpufreq
1496 * policy, or by cpu specific default values determined through
1499 max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf);
1500 *max = clamp_t(int, max_perf_adj,
1501 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1503 min_perf = fp_ext_toint(max_perf * perf_limits->min_perf);
1504 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1507 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1509 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1510 cpu->pstate.current_pstate = pstate;
1512 * Generally, there is no guarantee that this code will always run on
1513 * the CPU being updated, so force the register update to run on the
1516 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1517 pstate_funcs.get_val(cpu, pstate));
1520 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1522 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1525 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1527 int min_pstate, max_pstate;
1529 update_turbo_state();
1530 intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1531 intel_pstate_set_pstate(cpu, max_pstate);
1534 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1536 cpu->pstate.min_pstate = pstate_funcs.get_min();
1537 cpu->pstate.max_pstate = pstate_funcs.get_max();
1538 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1539 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1540 cpu->pstate.scaling = pstate_funcs.get_scaling();
1541 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1542 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1544 if (pstate_funcs.get_vid)
1545 pstate_funcs.get_vid(cpu);
1547 intel_pstate_set_min_pstate(cpu);
1550 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1552 struct sample *sample = &cpu->sample;
1554 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1557 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1560 unsigned long flags;
1563 local_irq_save(flags);
1564 rdmsrl(MSR_IA32_APERF, aperf);
1565 rdmsrl(MSR_IA32_MPERF, mperf);
1567 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1568 local_irq_restore(flags);
1571 local_irq_restore(flags);
1573 cpu->last_sample_time = cpu->sample.time;
1574 cpu->sample.time = time;
1575 cpu->sample.aperf = aperf;
1576 cpu->sample.mperf = mperf;
1577 cpu->sample.tsc = tsc;
1578 cpu->sample.aperf -= cpu->prev_aperf;
1579 cpu->sample.mperf -= cpu->prev_mperf;
1580 cpu->sample.tsc -= cpu->prev_tsc;
1582 cpu->prev_aperf = aperf;
1583 cpu->prev_mperf = mperf;
1584 cpu->prev_tsc = tsc;
1586 * First time this function is invoked in a given cycle, all of the
1587 * previous sample data fields are equal to zero or stale and they must
1588 * be populated with meaningful numbers for things to work, so assume
1589 * that sample.time will always be reset before setting the utilization
1590 * update hook and make the caller skip the sample then.
1592 return !!cpu->last_sample_time;
1595 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1597 return mul_ext_fp(cpu->sample.core_avg_perf,
1598 cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1601 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1603 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1604 cpu->sample.core_avg_perf);
1607 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1609 struct sample *sample = &cpu->sample;
1610 int32_t busy_frac, boost;
1611 int target, avg_pstate;
1613 busy_frac = div_fp(sample->mperf, sample->tsc);
1615 boost = cpu->iowait_boost;
1616 cpu->iowait_boost >>= 1;
1618 if (busy_frac < boost)
1621 sample->busy_scaled = busy_frac * 100;
1623 target = limits->no_turbo || limits->turbo_disabled ?
1624 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1625 target += target >> 2;
1626 target = mul_fp(target, busy_frac);
1627 if (target < cpu->pstate.min_pstate)
1628 target = cpu->pstate.min_pstate;
1631 * If the average P-state during the previous cycle was higher than the
1632 * current target, add 50% of the difference to the target to reduce
1633 * possible performance oscillations and offset possible performance
1634 * loss related to moving the workload from one CPU to another within
1637 avg_pstate = get_avg_pstate(cpu);
1638 if (avg_pstate > target)
1639 target += (avg_pstate - target) >> 1;
1644 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1646 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1650 * perf_scaled is the ratio of the average P-state during the last
1651 * sampling period to the P-state requested last time (in percent).
1653 * That measures the system's response to the previous P-state
1656 max_pstate = cpu->pstate.max_pstate_physical;
1657 current_pstate = cpu->pstate.current_pstate;
1658 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1659 div_fp(100 * max_pstate, current_pstate));
1662 * Since our utilization update callback will not run unless we are
1663 * in C0, check if the actual elapsed time is significantly greater (3x)
1664 * than our sample interval. If it is, then we were idle for a long
1665 * enough period of time to adjust our performance metric.
1667 duration_ns = cpu->sample.time - cpu->last_sample_time;
1668 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1669 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1670 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1672 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1673 if (sample_ratio < int_tofp(1))
1677 cpu->sample.busy_scaled = perf_scaled;
1678 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1681 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1683 int max_perf, min_perf;
1685 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1686 pstate = clamp_t(int, pstate, min_perf, max_perf);
1687 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1691 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1693 pstate = intel_pstate_prepare_request(cpu, pstate);
1694 if (pstate == cpu->pstate.current_pstate)
1697 cpu->pstate.current_pstate = pstate;
1698 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1701 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1703 int from, target_pstate;
1704 struct sample *sample;
1706 from = cpu->pstate.current_pstate;
1708 target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1709 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
1711 update_turbo_state();
1713 intel_pstate_update_pstate(cpu, target_pstate);
1715 sample = &cpu->sample;
1716 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1717 fp_toint(sample->busy_scaled),
1719 cpu->pstate.current_pstate,
1723 get_avg_frequency(cpu),
1724 fp_toint(cpu->iowait_boost * 100));
1727 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1730 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1733 if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
1734 if (flags & SCHED_CPUFREQ_IOWAIT) {
1735 cpu->iowait_boost = int_tofp(1);
1736 } else if (cpu->iowait_boost) {
1737 /* Clear iowait_boost if the CPU may have been idle. */
1738 delta_ns = time - cpu->last_update;
1739 if (delta_ns > TICK_NSEC)
1740 cpu->iowait_boost = 0;
1742 cpu->last_update = time;
1745 delta_ns = time - cpu->sample.time;
1746 if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1747 bool sample_taken = intel_pstate_sample(cpu, time);
1750 intel_pstate_calc_avg_perf(cpu);
1752 intel_pstate_adjust_busy_pstate(cpu);
1757 #define ICPU(model, policy) \
1758 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1759 (unsigned long)&policy }
1761 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1762 ICPU(INTEL_FAM6_SANDYBRIDGE, core_params),
1763 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params),
1764 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params),
1765 ICPU(INTEL_FAM6_IVYBRIDGE, core_params),
1766 ICPU(INTEL_FAM6_HASWELL_CORE, core_params),
1767 ICPU(INTEL_FAM6_BROADWELL_CORE, core_params),
1768 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params),
1769 ICPU(INTEL_FAM6_HASWELL_X, core_params),
1770 ICPU(INTEL_FAM6_HASWELL_ULT, core_params),
1771 ICPU(INTEL_FAM6_HASWELL_GT3E, core_params),
1772 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params),
1773 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params),
1774 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params),
1775 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1776 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params),
1777 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1778 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params),
1779 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_params),
1780 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params),
1783 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1785 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1786 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1787 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1788 ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1792 static int intel_pstate_init_cpu(unsigned int cpunum)
1794 struct cpudata *cpu;
1796 cpu = all_cpu_data[cpunum];
1799 unsigned int size = sizeof(struct cpudata);
1802 size += sizeof(struct perf_limits);
1804 cpu = kzalloc(size, GFP_KERNEL);
1808 all_cpu_data[cpunum] = cpu;
1810 cpu->perf_limits = (struct perf_limits *)(cpu + 1);
1812 cpu->epp_default = -EINVAL;
1813 cpu->epp_powersave = -EINVAL;
1814 cpu->epp_saved = -EINVAL;
1817 cpu = all_cpu_data[cpunum];
1822 intel_pstate_hwp_enable(cpu);
1823 pid_params.sample_rate_ms = 50;
1824 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
1827 intel_pstate_get_cpu_pstates(cpu);
1829 intel_pstate_busy_pid_reset(cpu);
1831 pr_debug("controlling: cpu %d\n", cpunum);
1836 static unsigned int intel_pstate_get(unsigned int cpu_num)
1838 struct cpudata *cpu = all_cpu_data[cpu_num];
1840 return cpu ? get_avg_frequency(cpu) : 0;
1843 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1845 struct cpudata *cpu = all_cpu_data[cpu_num];
1847 if (cpu->update_util_set)
1850 /* Prevent intel_pstate_update_util() from using stale data. */
1851 cpu->sample.time = 0;
1852 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1853 intel_pstate_update_util);
1854 cpu->update_util_set = true;
1857 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1859 struct cpudata *cpu_data = all_cpu_data[cpu];
1861 if (!cpu_data->update_util_set)
1864 cpufreq_remove_update_util_hook(cpu);
1865 cpu_data->update_util_set = false;
1866 synchronize_sched();
1869 static void intel_pstate_set_performance_limits(struct perf_limits *limits)
1871 limits->no_turbo = 0;
1872 limits->turbo_disabled = 0;
1873 limits->max_perf_pct = 100;
1874 limits->max_perf = int_ext_tofp(1);
1875 limits->min_perf_pct = 100;
1876 limits->min_perf = int_ext_tofp(1);
1877 limits->max_policy_pct = 100;
1878 limits->max_sysfs_pct = 100;
1879 limits->min_policy_pct = 0;
1880 limits->min_sysfs_pct = 0;
1883 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1884 struct perf_limits *limits)
1887 limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
1888 policy->cpuinfo.max_freq);
1889 limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100);
1890 if (policy->max == policy->min) {
1891 limits->min_policy_pct = limits->max_policy_pct;
1893 limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100,
1894 policy->cpuinfo.max_freq);
1895 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct,
1899 /* Normalize user input to [min_policy_pct, max_policy_pct] */
1900 limits->min_perf_pct = max(limits->min_policy_pct,
1901 limits->min_sysfs_pct);
1902 limits->min_perf_pct = min(limits->max_policy_pct,
1903 limits->min_perf_pct);
1904 limits->max_perf_pct = min(limits->max_policy_pct,
1905 limits->max_sysfs_pct);
1906 limits->max_perf_pct = max(limits->min_policy_pct,
1907 limits->max_perf_pct);
1909 /* Make sure min_perf_pct <= max_perf_pct */
1910 limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
1912 limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1913 limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1914 limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
1915 limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
1917 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
1918 limits->max_perf_pct, limits->min_perf_pct);
1921 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1923 struct cpudata *cpu;
1924 struct perf_limits *perf_limits = NULL;
1926 if (!policy->cpuinfo.max_freq)
1929 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1930 policy->cpuinfo.max_freq, policy->max);
1932 cpu = all_cpu_data[policy->cpu];
1933 cpu->policy = policy->policy;
1935 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1936 policy->max < policy->cpuinfo.max_freq &&
1937 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
1938 pr_debug("policy->max > max non turbo frequency\n");
1939 policy->max = policy->cpuinfo.max_freq;
1943 perf_limits = cpu->perf_limits;
1945 mutex_lock(&intel_pstate_limits_lock);
1947 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
1949 limits = &performance_limits;
1950 perf_limits = limits;
1952 if (policy->max >= policy->cpuinfo.max_freq) {
1953 pr_debug("set performance\n");
1954 intel_pstate_set_performance_limits(perf_limits);
1958 pr_debug("set powersave\n");
1960 limits = &powersave_limits;
1961 perf_limits = limits;
1966 intel_pstate_update_perf_limits(policy, perf_limits);
1968 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
1970 * NOHZ_FULL CPUs need this as the governor callback may not
1971 * be invoked on them.
1973 intel_pstate_clear_update_util_hook(policy->cpu);
1974 intel_pstate_max_within_limits(cpu);
1977 intel_pstate_set_update_util_hook(policy->cpu);
1979 intel_pstate_hwp_set_policy(policy);
1981 mutex_unlock(&intel_pstate_limits_lock);
1986 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1988 cpufreq_verify_within_cpu_limits(policy);
1990 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
1991 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
1997 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
1999 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2002 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2004 pr_debug("CPU %d exiting\n", policy->cpu);
2006 intel_pstate_clear_update_util_hook(policy->cpu);
2008 intel_pstate_hwp_save_state(policy);
2010 intel_cpufreq_stop_cpu(policy);
2013 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2015 intel_pstate_exit_perf_limits(policy);
2017 policy->fast_switch_possible = false;
2022 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2024 struct cpudata *cpu;
2027 rc = intel_pstate_init_cpu(policy->cpu);
2031 cpu = all_cpu_data[policy->cpu];
2034 * We need sane value in the cpu->perf_limits, so inherit from global
2035 * perf_limits limits, which are seeded with values based on the
2036 * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up.
2039 memcpy(cpu->perf_limits, limits, sizeof(struct perf_limits));
2041 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2042 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2044 /* cpuinfo and default policy values */
2045 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2046 update_turbo_state();
2047 policy->cpuinfo.max_freq = limits->turbo_disabled ?
2048 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2049 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2051 intel_pstate_init_acpi_perf_limits(policy);
2052 cpumask_set_cpu(policy->cpu, policy->cpus);
2054 policy->fast_switch_possible = true;
2059 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2061 int ret = __intel_pstate_cpu_init(policy);
2066 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2067 if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
2068 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2070 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2075 static struct cpufreq_driver intel_pstate = {
2076 .flags = CPUFREQ_CONST_LOOPS,
2077 .verify = intel_pstate_verify_policy,
2078 .setpolicy = intel_pstate_set_policy,
2079 .suspend = intel_pstate_hwp_save_state,
2080 .resume = intel_pstate_resume,
2081 .get = intel_pstate_get,
2082 .init = intel_pstate_cpu_init,
2083 .exit = intel_pstate_cpu_exit,
2084 .stop_cpu = intel_pstate_stop_cpu,
2085 .name = "intel_pstate",
2088 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2090 struct cpudata *cpu = all_cpu_data[policy->cpu];
2091 struct perf_limits *perf_limits = limits;
2093 update_turbo_state();
2094 policy->cpuinfo.max_freq = limits->turbo_disabled ?
2095 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2097 cpufreq_verify_within_cpu_limits(policy);
2100 perf_limits = cpu->perf_limits;
2102 intel_pstate_update_perf_limits(policy, perf_limits);
2107 static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu,
2108 struct cpufreq_policy *policy,
2109 unsigned int target_freq)
2111 unsigned int max_freq;
2113 update_turbo_state();
2115 max_freq = limits->no_turbo || limits->turbo_disabled ?
2116 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2117 policy->cpuinfo.max_freq = max_freq;
2118 if (policy->max > max_freq)
2119 policy->max = max_freq;
2121 if (target_freq > max_freq)
2122 target_freq = max_freq;
2127 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2128 unsigned int target_freq,
2129 unsigned int relation)
2131 struct cpudata *cpu = all_cpu_data[policy->cpu];
2132 struct cpufreq_freqs freqs;
2135 freqs.old = policy->cur;
2136 freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2138 cpufreq_freq_transition_begin(policy, &freqs);
2140 case CPUFREQ_RELATION_L:
2141 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2143 case CPUFREQ_RELATION_H:
2144 target_pstate = freqs.new / cpu->pstate.scaling;
2147 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2150 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2151 if (target_pstate != cpu->pstate.current_pstate) {
2152 cpu->pstate.current_pstate = target_pstate;
2153 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2154 pstate_funcs.get_val(cpu, target_pstate));
2156 cpufreq_freq_transition_end(policy, &freqs, false);
2161 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2162 unsigned int target_freq)
2164 struct cpudata *cpu = all_cpu_data[policy->cpu];
2167 target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2168 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2169 intel_pstate_update_pstate(cpu, target_pstate);
2173 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2175 int ret = __intel_pstate_cpu_init(policy);
2180 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2181 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2182 policy->cur = policy->cpuinfo.min_freq;
2187 static struct cpufreq_driver intel_cpufreq = {
2188 .flags = CPUFREQ_CONST_LOOPS,
2189 .verify = intel_cpufreq_verify_policy,
2190 .target = intel_cpufreq_target,
2191 .fast_switch = intel_cpufreq_fast_switch,
2192 .init = intel_cpufreq_cpu_init,
2193 .exit = intel_pstate_cpu_exit,
2194 .stop_cpu = intel_cpufreq_stop_cpu,
2195 .name = "intel_cpufreq",
2198 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2200 static int no_load __initdata;
2201 static int no_hwp __initdata;
2202 static int hwp_only __initdata;
2203 static unsigned int force_load __initdata;
2205 static int __init intel_pstate_msrs_not_valid(void)
2207 if (!pstate_funcs.get_max() ||
2208 !pstate_funcs.get_min() ||
2209 !pstate_funcs.get_turbo())
2215 static void __init copy_pid_params(struct pstate_adjust_policy *policy)
2217 pid_params.sample_rate_ms = policy->sample_rate_ms;
2218 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
2219 pid_params.p_gain_pct = policy->p_gain_pct;
2220 pid_params.i_gain_pct = policy->i_gain_pct;
2221 pid_params.d_gain_pct = policy->d_gain_pct;
2222 pid_params.deadband = policy->deadband;
2223 pid_params.setpoint = policy->setpoint;
2227 static void intel_pstate_use_acpi_profile(void)
2229 if (acpi_gbl_FADT.preferred_profile == PM_MOBILE)
2230 pstate_funcs.get_target_pstate =
2231 get_target_pstate_use_cpu_load;
2234 static void intel_pstate_use_acpi_profile(void)
2239 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2241 pstate_funcs.get_max = funcs->get_max;
2242 pstate_funcs.get_max_physical = funcs->get_max_physical;
2243 pstate_funcs.get_min = funcs->get_min;
2244 pstate_funcs.get_turbo = funcs->get_turbo;
2245 pstate_funcs.get_scaling = funcs->get_scaling;
2246 pstate_funcs.get_val = funcs->get_val;
2247 pstate_funcs.get_vid = funcs->get_vid;
2248 pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2250 intel_pstate_use_acpi_profile();
2255 static bool __init intel_pstate_no_acpi_pss(void)
2259 for_each_possible_cpu(i) {
2261 union acpi_object *pss;
2262 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2263 struct acpi_processor *pr = per_cpu(processors, i);
2268 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2269 if (ACPI_FAILURE(status))
2272 pss = buffer.pointer;
2273 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2284 static bool __init intel_pstate_has_acpi_ppc(void)
2288 for_each_possible_cpu(i) {
2289 struct acpi_processor *pr = per_cpu(processors, i);
2293 if (acpi_has_method(pr->handle, "_PPC"))
2304 struct hw_vendor_info {
2306 char oem_id[ACPI_OEM_ID_SIZE];
2307 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2311 /* Hardware vendor-specific info that has its own power management modes */
2312 static struct hw_vendor_info vendor_info[] __initdata = {
2313 {1, "HP ", "ProLiant", PSS},
2314 {1, "ORACLE", "X4-2 ", PPC},
2315 {1, "ORACLE", "X4-2L ", PPC},
2316 {1, "ORACLE", "X4-2B ", PPC},
2317 {1, "ORACLE", "X3-2 ", PPC},
2318 {1, "ORACLE", "X3-2L ", PPC},
2319 {1, "ORACLE", "X3-2B ", PPC},
2320 {1, "ORACLE", "X4470M2 ", PPC},
2321 {1, "ORACLE", "X4270M3 ", PPC},
2322 {1, "ORACLE", "X4270M2 ", PPC},
2323 {1, "ORACLE", "X4170M2 ", PPC},
2324 {1, "ORACLE", "X4170 M3", PPC},
2325 {1, "ORACLE", "X4275 M3", PPC},
2326 {1, "ORACLE", "X6-2 ", PPC},
2327 {1, "ORACLE", "Sudbury ", PPC},
2331 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2333 struct acpi_table_header hdr;
2334 struct hw_vendor_info *v_info;
2335 const struct x86_cpu_id *id;
2338 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2340 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2341 if ( misc_pwr & (1 << 8))
2345 if (acpi_disabled ||
2346 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2349 for (v_info = vendor_info; v_info->valid; v_info++) {
2350 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2351 !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2352 ACPI_OEM_TABLE_ID_SIZE))
2353 switch (v_info->oem_pwr_table) {
2355 return intel_pstate_no_acpi_pss();
2357 return intel_pstate_has_acpi_ppc() &&
2365 static void intel_pstate_request_control_from_smm(void)
2368 * It may be unsafe to request P-states control from SMM if _PPC support
2369 * has not been enabled.
2372 acpi_processor_pstate_control();
2374 #else /* CONFIG_ACPI not enabled */
2375 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2376 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2377 static inline void intel_pstate_request_control_from_smm(void) {}
2378 #endif /* CONFIG_ACPI */
2380 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2381 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2385 static int __init intel_pstate_init(void)
2388 const struct x86_cpu_id *id;
2389 struct cpu_defaults *cpu_def;
2394 if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
2395 copy_cpu_funcs(&core_params.funcs);
2397 intel_pstate.attr = hwp_cpufreq_attrs;
2398 goto hwp_cpu_matched;
2401 id = x86_match_cpu(intel_pstate_cpu_ids);
2405 cpu_def = (struct cpu_defaults *)id->driver_data;
2407 copy_pid_params(&cpu_def->pid_policy);
2408 copy_cpu_funcs(&cpu_def->funcs);
2410 if (intel_pstate_msrs_not_valid())
2415 * The Intel pstate driver will be ignored if the platform
2416 * firmware has its own power management modes.
2418 if (intel_pstate_platform_pwr_mgmt_exists())
2421 pr_info("Intel P-state driver initializing\n");
2423 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2427 if (!hwp_active && hwp_only)
2430 intel_pstate_request_control_from_smm();
2432 rc = cpufreq_register_driver(intel_pstate_driver);
2436 intel_pstate_debug_expose_params();
2437 intel_pstate_sysfs_expose_params();
2440 pr_info("HWP enabled\n");
2445 for_each_online_cpu(cpu) {
2446 if (all_cpu_data[cpu]) {
2447 if (intel_pstate_driver == &intel_pstate)
2448 intel_pstate_clear_update_util_hook(cpu);
2450 kfree(all_cpu_data[cpu]);
2455 vfree(all_cpu_data);
2458 device_initcall(intel_pstate_init);
2460 static int __init intel_pstate_setup(char *str)
2465 if (!strcmp(str, "disable")) {
2467 } else if (!strcmp(str, "passive")) {
2468 pr_info("Passive mode enabled\n");
2469 intel_pstate_driver = &intel_cpufreq;
2472 if (!strcmp(str, "no_hwp")) {
2473 pr_info("HWP disabled\n");
2476 if (!strcmp(str, "force"))
2478 if (!strcmp(str, "hwp_only"))
2480 if (!strcmp(str, "per_cpu_perf_limits"))
2481 per_cpu_limits = true;
2484 if (!strcmp(str, "support_acpi_ppc"))
2490 early_param("intel_pstate", intel_pstate_setup);
2492 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2493 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2494 MODULE_LICENSE("GPL");