2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
34 #include <asm/div64.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
43 #include <acpi/processor.h>
44 #include <acpi/cppc_acpi.h>
48 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
49 #define fp_toint(X) ((X) >> FRAC_BITS)
52 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
53 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
54 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
56 static inline int32_t mul_fp(int32_t x, int32_t y)
58 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
61 static inline int32_t div_fp(s64 x, s64 y)
63 return div64_s64((int64_t)x << FRAC_BITS, y);
66 static inline int ceiling_fp(int32_t x)
71 mask = (1 << FRAC_BITS) - 1;
77 static inline u64 mul_ext_fp(u64 x, u64 y)
79 return (x * y) >> EXT_FRAC_BITS;
82 static inline u64 div_ext_fp(u64 x, u64 y)
84 return div64_u64(x << EXT_FRAC_BITS, y);
87 static inline int32_t percent_ext_fp(int percent)
89 return div_ext_fp(percent, 100);
93 * struct sample - Store performance sample
94 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
95 * performance during last sample period
96 * @busy_scaled: Scaled busy value which is used to calculate next
97 * P state. This can be different than core_avg_perf
98 * to account for cpu idle period
99 * @aperf: Difference of actual performance frequency clock count
100 * read from APERF MSR between last and current sample
101 * @mperf: Difference of maximum performance frequency clock count
102 * read from MPERF MSR between last and current sample
103 * @tsc: Difference of time stamp counter between last and
105 * @time: Current time from scheduler
107 * This structure is used in the cpudata structure to store performance sample
108 * data for choosing next P State.
111 int32_t core_avg_perf;
120 * struct pstate_data - Store P state data
121 * @current_pstate: Current requested P state
122 * @min_pstate: Min P state possible for this platform
123 * @max_pstate: Max P state possible for this platform
124 * @max_pstate_physical:This is physical Max P state for a processor
125 * This can be higher than the max_pstate which can
126 * be limited by platform thermal design power limits
127 * @scaling: Scaling factor to convert frequency to cpufreq
129 * @turbo_pstate: Max Turbo P state possible for this platform
130 * @max_freq: @max_pstate frequency in cpufreq units
131 * @turbo_freq: @turbo_pstate frequency in cpufreq units
133 * Stores the per cpu model P state limits and current P state.
139 int max_pstate_physical;
142 unsigned int max_freq;
143 unsigned int turbo_freq;
147 * struct vid_data - Stores voltage information data
148 * @min: VID data for this platform corresponding to
150 * @max: VID data corresponding to the highest P State.
151 * @turbo: VID data for turbo P state
152 * @ratio: Ratio of (vid max - vid min) /
153 * (max P state - Min P State)
155 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
156 * This data is used in Atom platforms, where in addition to target P state,
157 * the voltage data needs to be specified to select next P State.
167 * struct _pid - Stores PID data
168 * @setpoint: Target set point for busyness or performance
169 * @integral: Storage for accumulated error values
170 * @p_gain: PID proportional gain
171 * @i_gain: PID integral gain
172 * @d_gain: PID derivative gain
173 * @deadband: PID deadband
174 * @last_err: Last error storage for integral part of PID calculation
176 * Stores PID coefficients and last error for PID controller.
189 * struct perf_limits - Store user and policy limits
190 * @no_turbo: User requested turbo state from intel_pstate sysfs
191 * @turbo_disabled: Platform turbo status either from msr
192 * MSR_IA32_MISC_ENABLE or when maximum available pstate
193 * matches the maximum turbo pstate
194 * @max_perf_pct: Effective maximum performance limit in percentage, this
195 * is minimum of either limits enforced by cpufreq policy
196 * or limits from user set limits via intel_pstate sysfs
197 * @min_perf_pct: Effective minimum performance limit in percentage, this
198 * is maximum of either limits enforced by cpufreq policy
199 * or limits from user set limits via intel_pstate sysfs
200 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
201 * This value is used to limit max pstate
202 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
203 * This value is used to limit min pstate
204 * @max_policy_pct: The maximum performance in percentage enforced by
205 * cpufreq setpolicy interface
206 * @max_sysfs_pct: The maximum performance in percentage enforced by
207 * intel pstate sysfs interface, unused when per cpu
208 * controls are enforced
209 * @min_policy_pct: The minimum performance in percentage enforced by
210 * cpufreq setpolicy interface
211 * @min_sysfs_pct: The minimum performance in percentage enforced by
212 * intel pstate sysfs interface, unused when per cpu
213 * controls are enforced
215 * Storage for user and policy defined limits.
231 * struct cpudata - Per CPU instance data storage
232 * @cpu: CPU number for this instance data
233 * @policy: CPUFreq policy value
234 * @update_util: CPUFreq utility callback information
235 * @update_util_set: CPUFreq utility callback is set
236 * @iowait_boost: iowait-related boost fraction
237 * @last_update: Time of the last update.
238 * @pstate: Stores P state limits for this CPU
239 * @vid: Stores VID limits for this CPU
240 * @pid: Stores PID parameters for this CPU
241 * @last_sample_time: Last Sample time
242 * @prev_aperf: Last APERF value read from APERF MSR
243 * @prev_mperf: Last MPERF value read from MPERF MSR
244 * @prev_tsc: Last timestamp counter (TSC) value
245 * @prev_cummulative_iowait: IO Wait time difference from last and
247 * @sample: Storage for storing last Sample data
248 * @perf_limits: Pointer to perf_limit unique to this CPU
249 * Not all field in the structure are applicable
250 * when per cpu controls are enforced
251 * @acpi_perf_data: Stores ACPI perf information read from _PSS
252 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
253 * @epp_powersave: Last saved HWP energy performance preference
254 * (EPP) or energy performance bias (EPB),
255 * when policy switched to performance
256 * @epp_policy: Last saved policy used to set EPP/EPB
257 * @epp_default: Power on default HWP energy performance
259 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
262 * This structure stores per CPU instance data for all CPUs.
268 struct update_util_data update_util;
269 bool update_util_set;
271 struct pstate_data pstate;
276 u64 last_sample_time;
280 u64 prev_cummulative_iowait;
281 struct sample sample;
282 struct perf_limits *perf_limits;
284 struct acpi_processor_performance acpi_perf_data;
285 bool valid_pss_table;
287 unsigned int iowait_boost;
294 static struct cpudata **all_cpu_data;
297 * struct pstate_adjust_policy - Stores static PID configuration data
298 * @sample_rate_ms: PID calculation sample rate in ms
299 * @sample_rate_ns: Sample rate calculation in ns
300 * @deadband: PID deadband
301 * @setpoint: PID Setpoint
302 * @p_gain_pct: PID proportional gain
303 * @i_gain_pct: PID integral gain
304 * @d_gain_pct: PID derivative gain
306 * Stores per CPU model static PID configuration data.
308 struct pstate_adjust_policy {
319 * struct pstate_funcs - Per CPU model specific callbacks
320 * @get_max: Callback to get maximum non turbo effective P state
321 * @get_max_physical: Callback to get maximum non turbo physical P state
322 * @get_min: Callback to get minimum P state
323 * @get_turbo: Callback to get turbo P state
324 * @get_scaling: Callback to get frequency scaling factor
325 * @get_val: Callback to convert P state to actual MSR write value
326 * @get_vid: Callback to get VID data for Atom platforms
327 * @get_target_pstate: Callback to a function to calculate next P state to use
329 * Core and Atom CPU models have different way to get P State limits. This
330 * structure is used to store those callbacks.
332 struct pstate_funcs {
333 int (*get_max)(void);
334 int (*get_max_physical)(void);
335 int (*get_min)(void);
336 int (*get_turbo)(void);
337 int (*get_scaling)(void);
338 u64 (*get_val)(struct cpudata*, int pstate);
339 void (*get_vid)(struct cpudata *);
340 int32_t (*get_target_pstate)(struct cpudata *);
344 * struct cpu_defaults- Per CPU model default config data
345 * @pid_policy: PID config data
346 * @funcs: Callback function data
348 struct cpu_defaults {
349 struct pstate_adjust_policy pid_policy;
350 struct pstate_funcs funcs;
353 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
354 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
356 static struct pstate_adjust_policy pid_params __read_mostly;
357 static struct pstate_funcs pstate_funcs __read_mostly;
358 static int hwp_active __read_mostly;
359 static bool per_cpu_limits __read_mostly;
361 static bool driver_registered __read_mostly;
364 static bool acpi_ppc;
367 static struct perf_limits global;
369 static void intel_pstate_init_limits(struct perf_limits *limits)
371 memset(limits, 0, sizeof(*limits));
372 limits->max_perf_pct = 100;
373 limits->max_perf = int_ext_tofp(1);
374 limits->max_policy_pct = 100;
375 limits->max_sysfs_pct = 100;
378 static DEFINE_MUTEX(intel_pstate_driver_lock);
379 static DEFINE_MUTEX(intel_pstate_limits_lock);
383 static bool intel_pstate_get_ppc_enable_status(void)
385 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
386 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
392 #ifdef CONFIG_ACPI_CPPC_LIB
394 /* The work item is needed to avoid CPU hotplug locking issues */
395 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
397 sched_set_itmt_support();
400 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
402 static void intel_pstate_set_itmt_prio(int cpu)
404 struct cppc_perf_caps cppc_perf;
405 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
408 ret = cppc_get_perf_caps(cpu, &cppc_perf);
413 * The priorities can be set regardless of whether or not
414 * sched_set_itmt_support(true) has been called and it is valid to
415 * update them at any time after it has been called.
417 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
419 if (max_highest_perf <= min_highest_perf) {
420 if (cppc_perf.highest_perf > max_highest_perf)
421 max_highest_perf = cppc_perf.highest_perf;
423 if (cppc_perf.highest_perf < min_highest_perf)
424 min_highest_perf = cppc_perf.highest_perf;
426 if (max_highest_perf > min_highest_perf) {
428 * This code can be run during CPU online under the
429 * CPU hotplug locks, so sched_set_itmt_support()
430 * cannot be called from here. Queue up a work item
433 schedule_work(&sched_itmt_work);
438 static void intel_pstate_set_itmt_prio(int cpu)
443 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
450 intel_pstate_set_itmt_prio(policy->cpu);
454 if (!intel_pstate_get_ppc_enable_status())
457 cpu = all_cpu_data[policy->cpu];
459 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
465 * Check if the control value in _PSS is for PERF_CTL MSR, which should
466 * guarantee that the states returned by it map to the states in our
469 if (cpu->acpi_perf_data.control_register.space_id !=
470 ACPI_ADR_SPACE_FIXED_HARDWARE)
474 * If there is only one entry _PSS, simply ignore _PSS and continue as
475 * usual without taking _PSS into account
477 if (cpu->acpi_perf_data.state_count < 2)
480 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
481 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
482 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
483 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
484 (u32) cpu->acpi_perf_data.states[i].core_frequency,
485 (u32) cpu->acpi_perf_data.states[i].power,
486 (u32) cpu->acpi_perf_data.states[i].control);
490 * The _PSS table doesn't contain whole turbo frequency range.
491 * This just contains +1 MHZ above the max non turbo frequency,
492 * with control value corresponding to max turbo ratio. But
493 * when cpufreq set policy is called, it will call with this
494 * max frequency, which will cause a reduced performance as
495 * this driver uses real max turbo frequency as the max
496 * frequency. So correct this frequency in _PSS table to
497 * correct max turbo frequency based on the turbo state.
498 * Also need to convert to MHz as _PSS freq is in MHz.
500 if (!global.turbo_disabled)
501 cpu->acpi_perf_data.states[0].core_frequency =
502 policy->cpuinfo.max_freq / 1000;
503 cpu->valid_pss_table = true;
504 pr_debug("_PPC limits will be enforced\n");
509 cpu->valid_pss_table = false;
510 acpi_processor_unregister_performance(policy->cpu);
513 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
517 cpu = all_cpu_data[policy->cpu];
518 if (!cpu->valid_pss_table)
521 acpi_processor_unregister_performance(policy->cpu);
524 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
528 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
533 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
534 int deadband, int integral) {
535 pid->setpoint = int_tofp(setpoint);
536 pid->deadband = int_tofp(deadband);
537 pid->integral = int_tofp(integral);
538 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
541 static inline void pid_p_gain_set(struct _pid *pid, int percent)
543 pid->p_gain = div_fp(percent, 100);
546 static inline void pid_i_gain_set(struct _pid *pid, int percent)
548 pid->i_gain = div_fp(percent, 100);
551 static inline void pid_d_gain_set(struct _pid *pid, int percent)
553 pid->d_gain = div_fp(percent, 100);
556 static signed int pid_calc(struct _pid *pid, int32_t busy)
559 int32_t pterm, dterm, fp_error;
560 int32_t integral_limit;
562 fp_error = pid->setpoint - busy;
564 if (abs(fp_error) <= pid->deadband)
567 pterm = mul_fp(pid->p_gain, fp_error);
569 pid->integral += fp_error;
572 * We limit the integral here so that it will never
573 * get higher than 30. This prevents it from becoming
574 * too large an input over long periods of time and allows
575 * it to get factored out sooner.
577 * The value of 30 was chosen through experimentation.
579 integral_limit = int_tofp(30);
580 if (pid->integral > integral_limit)
581 pid->integral = integral_limit;
582 if (pid->integral < -integral_limit)
583 pid->integral = -integral_limit;
585 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
586 pid->last_err = fp_error;
588 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
589 result = result + (1 << (FRAC_BITS-1));
590 return (signed int)fp_toint(result);
593 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
595 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
596 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
597 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
599 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
602 static inline void intel_pstate_reset_all_pid(void)
606 for_each_online_cpu(cpu) {
607 if (all_cpu_data[cpu])
608 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
612 static inline void update_turbo_state(void)
617 cpu = all_cpu_data[0];
618 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
619 global.turbo_disabled =
620 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
621 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
624 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
629 if (!static_cpu_has(X86_FEATURE_EPB))
632 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
636 return (s16)(epb & 0x0f);
639 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
643 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
645 * When hwp_req_data is 0, means that caller didn't read
646 * MSR_HWP_REQUEST, so need to read and get EPP.
649 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
654 epp = (hwp_req_data >> 24) & 0xff;
656 /* When there is no EPP present, HWP uses EPB settings */
657 epp = intel_pstate_get_epb(cpu_data);
663 static int intel_pstate_set_epb(int cpu, s16 pref)
668 if (!static_cpu_has(X86_FEATURE_EPB))
671 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
675 epb = (epb & ~0x0f) | pref;
676 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
682 * EPP/EPB display strings corresponding to EPP index in the
683 * energy_perf_strings[]
685 *-------------------------------------
688 * 2 balance_performance
692 static const char * const energy_perf_strings[] = {
695 "balance_performance",
701 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
706 epp = intel_pstate_get_epp(cpu_data, 0);
710 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
713 * 0x00-0x3F : Performance
714 * 0x40-0x7F : Balance performance
715 * 0x80-0xBF : Balance power
717 * The EPP is a 8 bit value, but our ranges restrict the
718 * value which can be set. Here only using top two bits
721 index = (epp >> 6) + 1;
722 } else if (static_cpu_has(X86_FEATURE_EPB)) {
725 * 0x00-0x03 : Performance
726 * 0x04-0x07 : Balance performance
727 * 0x08-0x0B : Balance power
729 * The EPB is a 4 bit value, but our ranges restrict the
730 * value which can be set. Here only using top two bits
733 index = (epp >> 2) + 1;
739 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
746 epp = cpu_data->epp_default;
748 mutex_lock(&intel_pstate_limits_lock);
750 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
753 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
757 value &= ~GENMASK_ULL(31, 24);
760 * If epp is not default, convert from index into
761 * energy_perf_strings to epp value, by shifting 6
762 * bits left to use only top two bits in epp.
763 * The resultant epp need to shifted by 24 bits to
764 * epp position in MSR_HWP_REQUEST.
767 epp = (pref_index - 1) << 6;
769 value |= (u64)epp << 24;
770 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
773 epp = (pref_index - 1) << 2;
774 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
777 mutex_unlock(&intel_pstate_limits_lock);
782 static ssize_t show_energy_performance_available_preferences(
783 struct cpufreq_policy *policy, char *buf)
788 while (energy_perf_strings[i] != NULL)
789 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
791 ret += sprintf(&buf[ret], "\n");
796 cpufreq_freq_attr_ro(energy_performance_available_preferences);
798 static ssize_t store_energy_performance_preference(
799 struct cpufreq_policy *policy, const char *buf, size_t count)
801 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
802 char str_preference[21];
805 ret = sscanf(buf, "%20s", str_preference);
809 while (energy_perf_strings[i] != NULL) {
810 if (!strcmp(str_preference, energy_perf_strings[i])) {
811 intel_pstate_set_energy_pref_index(cpu_data, i);
820 static ssize_t show_energy_performance_preference(
821 struct cpufreq_policy *policy, char *buf)
823 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
826 preference = intel_pstate_get_energy_pref_index(cpu_data);
830 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
833 cpufreq_freq_attr_rw(energy_performance_preference);
835 static struct freq_attr *hwp_cpufreq_attrs[] = {
836 &energy_performance_preference,
837 &energy_performance_available_preferences,
841 static void intel_pstate_hwp_set(struct cpufreq_policy *policy)
843 int min, hw_min, max, hw_max, cpu;
844 struct perf_limits *perf_limits = &global;
847 for_each_cpu(cpu, policy->cpus) {
848 struct cpudata *cpu_data = all_cpu_data[cpu];
852 perf_limits = all_cpu_data[cpu]->perf_limits;
854 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
855 hw_min = HWP_LOWEST_PERF(cap);
857 hw_max = HWP_GUARANTEED_PERF(cap);
859 hw_max = HWP_HIGHEST_PERF(cap);
861 max = fp_ext_toint(hw_max * perf_limits->max_perf);
862 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
865 min = fp_ext_toint(hw_max * perf_limits->min_perf);
867 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
869 value &= ~HWP_MIN_PERF(~0L);
870 value |= HWP_MIN_PERF(min);
872 value &= ~HWP_MAX_PERF(~0L);
873 value |= HWP_MAX_PERF(max);
875 if (cpu_data->epp_policy == cpu_data->policy)
878 cpu_data->epp_policy = cpu_data->policy;
880 if (cpu_data->epp_saved >= 0) {
881 epp = cpu_data->epp_saved;
882 cpu_data->epp_saved = -EINVAL;
886 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
887 epp = intel_pstate_get_epp(cpu_data, value);
888 cpu_data->epp_powersave = epp;
889 /* If EPP read was failed, then don't try to write */
896 /* skip setting EPP, when saved value is invalid */
897 if (cpu_data->epp_powersave < 0)
901 * No need to restore EPP when it is not zero. This
903 * - Policy is not changed
904 * - user has manually changed
905 * - Error reading EPB
907 epp = intel_pstate_get_epp(cpu_data, value);
911 epp = cpu_data->epp_powersave;
914 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
915 value &= ~GENMASK_ULL(31, 24);
916 value |= (u64)epp << 24;
918 intel_pstate_set_epb(cpu, epp);
921 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
925 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
927 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
932 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
937 static int intel_pstate_resume(struct cpufreq_policy *policy)
942 mutex_lock(&intel_pstate_limits_lock);
944 all_cpu_data[policy->cpu]->epp_policy = 0;
945 intel_pstate_hwp_set(policy);
947 mutex_unlock(&intel_pstate_limits_lock);
952 static void intel_pstate_update_policies(void)
956 for_each_possible_cpu(cpu)
957 cpufreq_update_policy(cpu);
960 /************************** debugfs begin ************************/
961 static int pid_param_set(void *data, u64 val)
964 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
965 intel_pstate_reset_all_pid();
969 static int pid_param_get(void *data, u64 *val)
974 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
976 static struct dentry *debugfs_parent;
981 struct dentry *dentry;
984 static struct pid_param pid_files[] = {
985 {"sample_rate_ms", &pid_params.sample_rate_ms, },
986 {"d_gain_pct", &pid_params.d_gain_pct, },
987 {"i_gain_pct", &pid_params.i_gain_pct, },
988 {"deadband", &pid_params.deadband, },
989 {"setpoint", &pid_params.setpoint, },
990 {"p_gain_pct", &pid_params.p_gain_pct, },
994 static void intel_pstate_debug_expose_params(void)
998 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
999 if (IS_ERR_OR_NULL(debugfs_parent))
1002 for (i = 0; pid_files[i].name; i++) {
1003 struct dentry *dentry;
1005 dentry = debugfs_create_file(pid_files[i].name, 0660,
1006 debugfs_parent, pid_files[i].value,
1008 if (!IS_ERR(dentry))
1009 pid_files[i].dentry = dentry;
1013 static void intel_pstate_debug_hide_params(void)
1017 if (IS_ERR_OR_NULL(debugfs_parent))
1020 for (i = 0; pid_files[i].name; i++) {
1021 debugfs_remove(pid_files[i].dentry);
1022 pid_files[i].dentry = NULL;
1025 debugfs_remove(debugfs_parent);
1026 debugfs_parent = NULL;
1029 /************************** debugfs end ************************/
1031 /************************** sysfs begin ************************/
1032 #define show_one(file_name, object) \
1033 static ssize_t show_##file_name \
1034 (struct kobject *kobj, struct attribute *attr, char *buf) \
1036 return sprintf(buf, "%u\n", global.object); \
1039 static ssize_t intel_pstate_show_status(char *buf);
1040 static int intel_pstate_update_status(const char *buf, size_t size);
1042 static ssize_t show_status(struct kobject *kobj,
1043 struct attribute *attr, char *buf)
1047 mutex_lock(&intel_pstate_driver_lock);
1048 ret = intel_pstate_show_status(buf);
1049 mutex_unlock(&intel_pstate_driver_lock);
1054 static ssize_t store_status(struct kobject *a, struct attribute *b,
1055 const char *buf, size_t count)
1057 char *p = memchr(buf, '\n', count);
1060 mutex_lock(&intel_pstate_driver_lock);
1061 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1062 mutex_unlock(&intel_pstate_driver_lock);
1064 return ret < 0 ? ret : count;
1067 static ssize_t show_turbo_pct(struct kobject *kobj,
1068 struct attribute *attr, char *buf)
1070 struct cpudata *cpu;
1071 int total, no_turbo, turbo_pct;
1074 mutex_lock(&intel_pstate_driver_lock);
1076 if (!driver_registered) {
1077 mutex_unlock(&intel_pstate_driver_lock);
1081 cpu = all_cpu_data[0];
1083 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1084 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1085 turbo_fp = div_fp(no_turbo, total);
1086 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1088 mutex_unlock(&intel_pstate_driver_lock);
1090 return sprintf(buf, "%u\n", turbo_pct);
1093 static ssize_t show_num_pstates(struct kobject *kobj,
1094 struct attribute *attr, char *buf)
1096 struct cpudata *cpu;
1099 mutex_lock(&intel_pstate_driver_lock);
1101 if (!driver_registered) {
1102 mutex_unlock(&intel_pstate_driver_lock);
1106 cpu = all_cpu_data[0];
1107 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1109 mutex_unlock(&intel_pstate_driver_lock);
1111 return sprintf(buf, "%u\n", total);
1114 static ssize_t show_no_turbo(struct kobject *kobj,
1115 struct attribute *attr, char *buf)
1119 mutex_lock(&intel_pstate_driver_lock);
1121 if (!driver_registered) {
1122 mutex_unlock(&intel_pstate_driver_lock);
1126 update_turbo_state();
1127 if (global.turbo_disabled)
1128 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1130 ret = sprintf(buf, "%u\n", global.no_turbo);
1132 mutex_unlock(&intel_pstate_driver_lock);
1137 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1138 const char *buf, size_t count)
1143 ret = sscanf(buf, "%u", &input);
1147 mutex_lock(&intel_pstate_driver_lock);
1149 if (!driver_registered) {
1150 mutex_unlock(&intel_pstate_driver_lock);
1154 mutex_lock(&intel_pstate_limits_lock);
1156 update_turbo_state();
1157 if (global.turbo_disabled) {
1158 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1159 mutex_unlock(&intel_pstate_limits_lock);
1160 mutex_unlock(&intel_pstate_driver_lock);
1164 global.no_turbo = clamp_t(int, input, 0, 1);
1166 mutex_unlock(&intel_pstate_limits_lock);
1168 intel_pstate_update_policies();
1170 mutex_unlock(&intel_pstate_driver_lock);
1175 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1176 const char *buf, size_t count)
1181 ret = sscanf(buf, "%u", &input);
1185 mutex_lock(&intel_pstate_driver_lock);
1187 if (!driver_registered) {
1188 mutex_unlock(&intel_pstate_driver_lock);
1192 mutex_lock(&intel_pstate_limits_lock);
1194 global.max_sysfs_pct = clamp_t(int, input, 0 , 100);
1195 global.max_perf_pct = min(global.max_policy_pct, global.max_sysfs_pct);
1196 global.max_perf_pct = max(global.min_policy_pct, global.max_perf_pct);
1197 global.max_perf_pct = max(global.min_perf_pct, global.max_perf_pct);
1198 global.max_perf = percent_ext_fp(global.max_perf_pct);
1200 mutex_unlock(&intel_pstate_limits_lock);
1202 intel_pstate_update_policies();
1204 mutex_unlock(&intel_pstate_driver_lock);
1209 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1210 const char *buf, size_t count)
1215 ret = sscanf(buf, "%u", &input);
1219 mutex_lock(&intel_pstate_driver_lock);
1221 if (!driver_registered) {
1222 mutex_unlock(&intel_pstate_driver_lock);
1226 mutex_lock(&intel_pstate_limits_lock);
1228 global.min_sysfs_pct = clamp_t(int, input, 0 , 100);
1229 global.min_perf_pct = max(global.min_policy_pct, global.min_sysfs_pct);
1230 global.min_perf_pct = min(global.max_policy_pct, global.min_perf_pct);
1231 global.min_perf_pct = min(global.max_perf_pct, global.min_perf_pct);
1232 global.min_perf = percent_ext_fp(global.min_perf_pct);
1234 mutex_unlock(&intel_pstate_limits_lock);
1236 intel_pstate_update_policies();
1238 mutex_unlock(&intel_pstate_driver_lock);
1243 show_one(max_perf_pct, max_perf_pct);
1244 show_one(min_perf_pct, min_perf_pct);
1246 define_one_global_rw(status);
1247 define_one_global_rw(no_turbo);
1248 define_one_global_rw(max_perf_pct);
1249 define_one_global_rw(min_perf_pct);
1250 define_one_global_ro(turbo_pct);
1251 define_one_global_ro(num_pstates);
1253 static struct attribute *intel_pstate_attributes[] = {
1261 static struct attribute_group intel_pstate_attr_group = {
1262 .attrs = intel_pstate_attributes,
1265 static void __init intel_pstate_sysfs_expose_params(void)
1267 struct kobject *intel_pstate_kobject;
1270 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1271 &cpu_subsys.dev_root->kobj);
1272 if (WARN_ON(!intel_pstate_kobject))
1275 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1280 * If per cpu limits are enforced there are no global limits, so
1281 * return without creating max/min_perf_pct attributes
1286 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1289 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1293 /************************** sysfs end ************************/
1295 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1297 /* First disable HWP notification interrupt as we don't process them */
1298 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1299 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1301 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1302 cpudata->epp_policy = 0;
1303 if (cpudata->epp_default == -EINVAL)
1304 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1307 #define MSR_IA32_POWER_CTL_BIT_EE 19
1309 /* Disable energy efficiency optimization */
1310 static void intel_pstate_disable_ee(int cpu)
1315 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1319 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1320 pr_info("Disabling energy efficiency optimization\n");
1321 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1322 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1326 static int atom_get_min_pstate(void)
1330 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1331 return (value >> 8) & 0x7F;
1334 static int atom_get_max_pstate(void)
1338 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1339 return (value >> 16) & 0x7F;
1342 static int atom_get_turbo_pstate(void)
1346 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1347 return value & 0x7F;
1350 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1356 val = (u64)pstate << 8;
1357 if (global.no_turbo && !global.turbo_disabled)
1358 val |= (u64)1 << 32;
1360 vid_fp = cpudata->vid.min + mul_fp(
1361 int_tofp(pstate - cpudata->pstate.min_pstate),
1362 cpudata->vid.ratio);
1364 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1365 vid = ceiling_fp(vid_fp);
1367 if (pstate > cpudata->pstate.max_pstate)
1368 vid = cpudata->vid.turbo;
1373 static int silvermont_get_scaling(void)
1377 /* Defined in Table 35-6 from SDM (Sept 2015) */
1378 static int silvermont_freq_table[] = {
1379 83300, 100000, 133300, 116700, 80000};
1381 rdmsrl(MSR_FSB_FREQ, value);
1385 return silvermont_freq_table[i];
1388 static int airmont_get_scaling(void)
1392 /* Defined in Table 35-10 from SDM (Sept 2015) */
1393 static int airmont_freq_table[] = {
1394 83300, 100000, 133300, 116700, 80000,
1395 93300, 90000, 88900, 87500};
1397 rdmsrl(MSR_FSB_FREQ, value);
1401 return airmont_freq_table[i];
1404 static void atom_get_vid(struct cpudata *cpudata)
1408 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1409 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1410 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1411 cpudata->vid.ratio = div_fp(
1412 cpudata->vid.max - cpudata->vid.min,
1413 int_tofp(cpudata->pstate.max_pstate -
1414 cpudata->pstate.min_pstate));
1416 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1417 cpudata->vid.turbo = value & 0x7f;
1420 static int core_get_min_pstate(void)
1424 rdmsrl(MSR_PLATFORM_INFO, value);
1425 return (value >> 40) & 0xFF;
1428 static int core_get_max_pstate_physical(void)
1432 rdmsrl(MSR_PLATFORM_INFO, value);
1433 return (value >> 8) & 0xFF;
1436 static int core_get_tdp_ratio(u64 plat_info)
1438 /* Check how many TDP levels present */
1439 if (plat_info & 0x600000000) {
1445 /* Get the TDP level (0, 1, 2) to get ratios */
1446 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1450 /* TDP MSR are continuous starting at 0x648 */
1451 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1452 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1456 /* For level 1 and 2, bits[23:16] contain the ratio */
1457 if (tdp_ctrl & 0x03)
1460 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1461 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1463 return (int)tdp_ratio;
1469 static int core_get_max_pstate(void)
1477 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1478 max_pstate = (plat_info >> 8) & 0xFF;
1480 tdp_ratio = core_get_tdp_ratio(plat_info);
1485 /* Turbo activation ratio is not used on HWP platforms */
1489 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1493 /* Do some sanity checking for safety */
1494 tar_levels = tar & 0xff;
1495 if (tdp_ratio - 1 == tar_levels) {
1496 max_pstate = tar_levels;
1497 pr_debug("max_pstate=TAC %x\n", max_pstate);
1504 static int core_get_turbo_pstate(void)
1509 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1510 nont = core_get_max_pstate();
1511 ret = (value) & 255;
1517 static inline int core_get_scaling(void)
1522 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1526 val = (u64)pstate << 8;
1527 if (global.no_turbo && !global.turbo_disabled)
1528 val |= (u64)1 << 32;
1533 static int knl_get_turbo_pstate(void)
1538 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1539 nont = core_get_max_pstate();
1540 ret = (((value) >> 8) & 0xFF);
1546 static struct cpu_defaults core_params = {
1548 .sample_rate_ms = 10,
1556 .get_max = core_get_max_pstate,
1557 .get_max_physical = core_get_max_pstate_physical,
1558 .get_min = core_get_min_pstate,
1559 .get_turbo = core_get_turbo_pstate,
1560 .get_scaling = core_get_scaling,
1561 .get_val = core_get_val,
1562 .get_target_pstate = get_target_pstate_use_performance,
1566 static const struct cpu_defaults silvermont_params = {
1568 .sample_rate_ms = 10,
1576 .get_max = atom_get_max_pstate,
1577 .get_max_physical = atom_get_max_pstate,
1578 .get_min = atom_get_min_pstate,
1579 .get_turbo = atom_get_turbo_pstate,
1580 .get_val = atom_get_val,
1581 .get_scaling = silvermont_get_scaling,
1582 .get_vid = atom_get_vid,
1583 .get_target_pstate = get_target_pstate_use_cpu_load,
1587 static const struct cpu_defaults airmont_params = {
1589 .sample_rate_ms = 10,
1597 .get_max = atom_get_max_pstate,
1598 .get_max_physical = atom_get_max_pstate,
1599 .get_min = atom_get_min_pstate,
1600 .get_turbo = atom_get_turbo_pstate,
1601 .get_val = atom_get_val,
1602 .get_scaling = airmont_get_scaling,
1603 .get_vid = atom_get_vid,
1604 .get_target_pstate = get_target_pstate_use_cpu_load,
1608 static const struct cpu_defaults knl_params = {
1610 .sample_rate_ms = 10,
1618 .get_max = core_get_max_pstate,
1619 .get_max_physical = core_get_max_pstate_physical,
1620 .get_min = core_get_min_pstate,
1621 .get_turbo = knl_get_turbo_pstate,
1622 .get_scaling = core_get_scaling,
1623 .get_val = core_get_val,
1624 .get_target_pstate = get_target_pstate_use_performance,
1628 static const struct cpu_defaults bxt_params = {
1630 .sample_rate_ms = 10,
1638 .get_max = core_get_max_pstate,
1639 .get_max_physical = core_get_max_pstate_physical,
1640 .get_min = core_get_min_pstate,
1641 .get_turbo = core_get_turbo_pstate,
1642 .get_scaling = core_get_scaling,
1643 .get_val = core_get_val,
1644 .get_target_pstate = get_target_pstate_use_cpu_load,
1648 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1650 int max_perf = cpu->pstate.turbo_pstate;
1653 struct perf_limits *perf_limits = &global;
1655 if (global.no_turbo || global.turbo_disabled)
1656 max_perf = cpu->pstate.max_pstate;
1659 perf_limits = cpu->perf_limits;
1662 * performance can be limited by user through sysfs, by cpufreq
1663 * policy, or by cpu specific default values determined through
1666 max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf);
1667 *max = clamp_t(int, max_perf_adj,
1668 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1670 min_perf = fp_ext_toint(max_perf * perf_limits->min_perf);
1671 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1674 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1676 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1677 cpu->pstate.current_pstate = pstate;
1679 * Generally, there is no guarantee that this code will always run on
1680 * the CPU being updated, so force the register update to run on the
1683 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1684 pstate_funcs.get_val(cpu, pstate));
1687 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1689 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1692 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1694 int min_pstate, max_pstate;
1696 update_turbo_state();
1697 intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1698 intel_pstate_set_pstate(cpu, max_pstate);
1701 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1703 cpu->pstate.min_pstate = pstate_funcs.get_min();
1704 cpu->pstate.max_pstate = pstate_funcs.get_max();
1705 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1706 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1707 cpu->pstate.scaling = pstate_funcs.get_scaling();
1708 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1709 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1711 if (pstate_funcs.get_vid)
1712 pstate_funcs.get_vid(cpu);
1714 intel_pstate_set_min_pstate(cpu);
1717 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1719 struct sample *sample = &cpu->sample;
1721 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1724 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1727 unsigned long flags;
1730 local_irq_save(flags);
1731 rdmsrl(MSR_IA32_APERF, aperf);
1732 rdmsrl(MSR_IA32_MPERF, mperf);
1734 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1735 local_irq_restore(flags);
1738 local_irq_restore(flags);
1740 cpu->last_sample_time = cpu->sample.time;
1741 cpu->sample.time = time;
1742 cpu->sample.aperf = aperf;
1743 cpu->sample.mperf = mperf;
1744 cpu->sample.tsc = tsc;
1745 cpu->sample.aperf -= cpu->prev_aperf;
1746 cpu->sample.mperf -= cpu->prev_mperf;
1747 cpu->sample.tsc -= cpu->prev_tsc;
1749 cpu->prev_aperf = aperf;
1750 cpu->prev_mperf = mperf;
1751 cpu->prev_tsc = tsc;
1753 * First time this function is invoked in a given cycle, all of the
1754 * previous sample data fields are equal to zero or stale and they must
1755 * be populated with meaningful numbers for things to work, so assume
1756 * that sample.time will always be reset before setting the utilization
1757 * update hook and make the caller skip the sample then.
1759 return !!cpu->last_sample_time;
1762 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1764 return mul_ext_fp(cpu->sample.core_avg_perf,
1765 cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1768 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1770 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1771 cpu->sample.core_avg_perf);
1774 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1776 struct sample *sample = &cpu->sample;
1777 int32_t busy_frac, boost;
1778 int target, avg_pstate;
1780 busy_frac = div_fp(sample->mperf, sample->tsc);
1782 boost = cpu->iowait_boost;
1783 cpu->iowait_boost >>= 1;
1785 if (busy_frac < boost)
1788 sample->busy_scaled = busy_frac * 100;
1790 target = global.no_turbo || global.turbo_disabled ?
1791 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1792 target += target >> 2;
1793 target = mul_fp(target, busy_frac);
1794 if (target < cpu->pstate.min_pstate)
1795 target = cpu->pstate.min_pstate;
1798 * If the average P-state during the previous cycle was higher than the
1799 * current target, add 50% of the difference to the target to reduce
1800 * possible performance oscillations and offset possible performance
1801 * loss related to moving the workload from one CPU to another within
1804 avg_pstate = get_avg_pstate(cpu);
1805 if (avg_pstate > target)
1806 target += (avg_pstate - target) >> 1;
1811 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1813 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1817 * perf_scaled is the ratio of the average P-state during the last
1818 * sampling period to the P-state requested last time (in percent).
1820 * That measures the system's response to the previous P-state
1823 max_pstate = cpu->pstate.max_pstate_physical;
1824 current_pstate = cpu->pstate.current_pstate;
1825 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1826 div_fp(100 * max_pstate, current_pstate));
1829 * Since our utilization update callback will not run unless we are
1830 * in C0, check if the actual elapsed time is significantly greater (3x)
1831 * than our sample interval. If it is, then we were idle for a long
1832 * enough period of time to adjust our performance metric.
1834 duration_ns = cpu->sample.time - cpu->last_sample_time;
1835 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1836 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1837 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1839 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1840 if (sample_ratio < int_tofp(1))
1844 cpu->sample.busy_scaled = perf_scaled;
1845 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1848 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1850 int max_perf, min_perf;
1852 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1853 pstate = clamp_t(int, pstate, min_perf, max_perf);
1857 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1859 if (pstate == cpu->pstate.current_pstate)
1862 cpu->pstate.current_pstate = pstate;
1863 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1866 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1868 int from, target_pstate;
1869 struct sample *sample;
1871 from = cpu->pstate.current_pstate;
1873 target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1874 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
1876 update_turbo_state();
1878 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1879 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1880 intel_pstate_update_pstate(cpu, target_pstate);
1882 sample = &cpu->sample;
1883 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1884 fp_toint(sample->busy_scaled),
1886 cpu->pstate.current_pstate,
1890 get_avg_frequency(cpu),
1891 fp_toint(cpu->iowait_boost * 100));
1894 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1897 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1900 if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
1901 if (flags & SCHED_CPUFREQ_IOWAIT) {
1902 cpu->iowait_boost = int_tofp(1);
1903 } else if (cpu->iowait_boost) {
1904 /* Clear iowait_boost if the CPU may have been idle. */
1905 delta_ns = time - cpu->last_update;
1906 if (delta_ns > TICK_NSEC)
1907 cpu->iowait_boost = 0;
1909 cpu->last_update = time;
1912 delta_ns = time - cpu->sample.time;
1913 if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1914 bool sample_taken = intel_pstate_sample(cpu, time);
1917 intel_pstate_calc_avg_perf(cpu);
1919 intel_pstate_adjust_busy_pstate(cpu);
1924 #define ICPU(model, policy) \
1925 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1926 (unsigned long)&policy }
1928 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1929 ICPU(INTEL_FAM6_SANDYBRIDGE, core_params),
1930 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params),
1931 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params),
1932 ICPU(INTEL_FAM6_IVYBRIDGE, core_params),
1933 ICPU(INTEL_FAM6_HASWELL_CORE, core_params),
1934 ICPU(INTEL_FAM6_BROADWELL_CORE, core_params),
1935 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params),
1936 ICPU(INTEL_FAM6_HASWELL_X, core_params),
1937 ICPU(INTEL_FAM6_HASWELL_ULT, core_params),
1938 ICPU(INTEL_FAM6_HASWELL_GT3E, core_params),
1939 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params),
1940 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params),
1941 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params),
1942 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1943 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params),
1944 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1945 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params),
1946 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_params),
1947 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params),
1950 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1952 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1953 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1954 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1955 ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1959 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1960 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params),
1964 static int intel_pstate_init_cpu(unsigned int cpunum)
1966 struct cpudata *cpu;
1968 cpu = all_cpu_data[cpunum];
1971 unsigned int size = sizeof(struct cpudata);
1974 size += sizeof(struct perf_limits);
1976 cpu = kzalloc(size, GFP_KERNEL);
1980 all_cpu_data[cpunum] = cpu;
1982 cpu->perf_limits = (struct perf_limits *)(cpu + 1);
1984 cpu->epp_default = -EINVAL;
1985 cpu->epp_powersave = -EINVAL;
1986 cpu->epp_saved = -EINVAL;
1989 cpu = all_cpu_data[cpunum];
1994 const struct x86_cpu_id *id;
1996 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1998 intel_pstate_disable_ee(cpunum);
2000 intel_pstate_hwp_enable(cpu);
2001 pid_params.sample_rate_ms = 50;
2002 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
2005 intel_pstate_get_cpu_pstates(cpu);
2007 intel_pstate_busy_pid_reset(cpu);
2009 pr_debug("controlling: cpu %d\n", cpunum);
2014 static unsigned int intel_pstate_get(unsigned int cpu_num)
2016 struct cpudata *cpu = all_cpu_data[cpu_num];
2018 return cpu ? get_avg_frequency(cpu) : 0;
2021 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2023 struct cpudata *cpu = all_cpu_data[cpu_num];
2025 if (cpu->update_util_set)
2028 /* Prevent intel_pstate_update_util() from using stale data. */
2029 cpu->sample.time = 0;
2030 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2031 intel_pstate_update_util);
2032 cpu->update_util_set = true;
2035 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2037 struct cpudata *cpu_data = all_cpu_data[cpu];
2039 if (!cpu_data->update_util_set)
2042 cpufreq_remove_update_util_hook(cpu);
2043 cpu_data->update_util_set = false;
2044 synchronize_sched();
2047 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
2048 struct perf_limits *limits)
2050 int32_t max_policy_perf, min_policy_perf;
2052 max_policy_perf = div_ext_fp(policy->max, policy->cpuinfo.max_freq);
2053 max_policy_perf = clamp_t(int32_t, max_policy_perf, 0, int_ext_tofp(1));
2054 if (policy->max == policy->min) {
2055 min_policy_perf = max_policy_perf;
2057 min_policy_perf = div_ext_fp(policy->min,
2058 policy->cpuinfo.max_freq);
2059 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2060 0, max_policy_perf);
2063 /* Normalize user input to [min_perf, max_perf] */
2064 limits->min_perf = max(min_policy_perf,
2065 percent_ext_fp(limits->min_sysfs_pct));
2066 limits->min_perf = min(limits->min_perf, max_policy_perf);
2067 limits->max_perf = min(max_policy_perf,
2068 percent_ext_fp(limits->max_sysfs_pct));
2069 limits->max_perf = max(min_policy_perf, limits->max_perf);
2071 /* Make sure min_perf <= max_perf */
2072 limits->min_perf = min(limits->min_perf, limits->max_perf);
2074 limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
2075 limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
2076 limits->max_perf_pct = fp_ext_toint(limits->max_perf * 100);
2077 limits->min_perf_pct = fp_ext_toint(limits->min_perf * 100);
2079 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2080 limits->max_perf_pct, limits->min_perf_pct);
2083 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2085 struct cpudata *cpu;
2086 struct perf_limits *perf_limits = &global;
2088 if (!policy->cpuinfo.max_freq)
2091 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2092 policy->cpuinfo.max_freq, policy->max);
2094 cpu = all_cpu_data[policy->cpu];
2095 cpu->policy = policy->policy;
2097 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2098 policy->max < policy->cpuinfo.max_freq &&
2099 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
2100 pr_debug("policy->max > max non turbo frequency\n");
2101 policy->max = policy->cpuinfo.max_freq;
2105 perf_limits = cpu->perf_limits;
2107 mutex_lock(&intel_pstate_limits_lock);
2109 intel_pstate_update_perf_limits(policy, perf_limits);
2111 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2113 * NOHZ_FULL CPUs need this as the governor callback may not
2114 * be invoked on them.
2116 intel_pstate_clear_update_util_hook(policy->cpu);
2117 intel_pstate_max_within_limits(cpu);
2120 intel_pstate_set_update_util_hook(policy->cpu);
2123 intel_pstate_hwp_set(policy);
2125 mutex_unlock(&intel_pstate_limits_lock);
2130 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2132 struct cpudata *cpu = all_cpu_data[policy->cpu];
2134 update_turbo_state();
2135 policy->cpuinfo.max_freq = global.turbo_disabled || global.no_turbo ?
2136 cpu->pstate.max_freq :
2137 cpu->pstate.turbo_freq;
2139 cpufreq_verify_within_cpu_limits(policy);
2141 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2142 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2145 /* When per-CPU limits are used, sysfs limits are not used */
2146 if (!per_cpu_limits) {
2147 unsigned int max_freq, min_freq;
2149 max_freq = policy->cpuinfo.max_freq *
2150 global.max_sysfs_pct / 100;
2151 min_freq = policy->cpuinfo.max_freq *
2152 global.min_sysfs_pct / 100;
2153 cpufreq_verify_within_limits(policy, min_freq, max_freq);
2159 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2161 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2164 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2166 pr_debug("CPU %d exiting\n", policy->cpu);
2168 intel_pstate_clear_update_util_hook(policy->cpu);
2170 intel_pstate_hwp_save_state(policy);
2172 intel_cpufreq_stop_cpu(policy);
2175 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2177 intel_pstate_exit_perf_limits(policy);
2179 policy->fast_switch_possible = false;
2184 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2186 struct cpudata *cpu;
2189 rc = intel_pstate_init_cpu(policy->cpu);
2193 cpu = all_cpu_data[policy->cpu];
2196 intel_pstate_init_limits(cpu->perf_limits);
2198 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2199 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2201 /* cpuinfo and default policy values */
2202 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2203 update_turbo_state();
2204 policy->cpuinfo.max_freq = global.turbo_disabled ?
2205 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2206 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2208 intel_pstate_init_acpi_perf_limits(policy);
2209 cpumask_set_cpu(policy->cpu, policy->cpus);
2211 policy->fast_switch_possible = true;
2216 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2218 int ret = __intel_pstate_cpu_init(policy);
2223 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2224 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2225 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2227 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2232 static struct cpufreq_driver intel_pstate = {
2233 .flags = CPUFREQ_CONST_LOOPS,
2234 .verify = intel_pstate_verify_policy,
2235 .setpolicy = intel_pstate_set_policy,
2236 .suspend = intel_pstate_hwp_save_state,
2237 .resume = intel_pstate_resume,
2238 .get = intel_pstate_get,
2239 .init = intel_pstate_cpu_init,
2240 .exit = intel_pstate_cpu_exit,
2241 .stop_cpu = intel_pstate_stop_cpu,
2242 .name = "intel_pstate",
2245 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2247 struct cpudata *cpu = all_cpu_data[policy->cpu];
2249 update_turbo_state();
2250 policy->cpuinfo.max_freq = global.no_turbo || global.turbo_disabled ?
2251 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2253 cpufreq_verify_within_cpu_limits(policy);
2258 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2259 unsigned int target_freq,
2260 unsigned int relation)
2262 struct cpudata *cpu = all_cpu_data[policy->cpu];
2263 struct cpufreq_freqs freqs;
2266 update_turbo_state();
2268 freqs.old = policy->cur;
2269 freqs.new = target_freq;
2271 cpufreq_freq_transition_begin(policy, &freqs);
2273 case CPUFREQ_RELATION_L:
2274 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2276 case CPUFREQ_RELATION_H:
2277 target_pstate = freqs.new / cpu->pstate.scaling;
2280 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2283 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2284 if (target_pstate != cpu->pstate.current_pstate) {
2285 cpu->pstate.current_pstate = target_pstate;
2286 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2287 pstate_funcs.get_val(cpu, target_pstate));
2289 freqs.new = target_pstate * cpu->pstate.scaling;
2290 cpufreq_freq_transition_end(policy, &freqs, false);
2295 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2296 unsigned int target_freq)
2298 struct cpudata *cpu = all_cpu_data[policy->cpu];
2301 update_turbo_state();
2303 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2304 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2305 intel_pstate_update_pstate(cpu, target_pstate);
2306 return target_pstate * cpu->pstate.scaling;
2309 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2311 int ret = __intel_pstate_cpu_init(policy);
2316 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2317 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2318 policy->cur = policy->cpuinfo.min_freq;
2323 static struct cpufreq_driver intel_cpufreq = {
2324 .flags = CPUFREQ_CONST_LOOPS,
2325 .verify = intel_cpufreq_verify_policy,
2326 .target = intel_cpufreq_target,
2327 .fast_switch = intel_cpufreq_fast_switch,
2328 .init = intel_cpufreq_cpu_init,
2329 .exit = intel_pstate_cpu_exit,
2330 .stop_cpu = intel_cpufreq_stop_cpu,
2331 .name = "intel_cpufreq",
2334 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2336 static void intel_pstate_driver_cleanup(void)
2341 for_each_online_cpu(cpu) {
2342 if (all_cpu_data[cpu]) {
2343 if (intel_pstate_driver == &intel_pstate)
2344 intel_pstate_clear_update_util_hook(cpu);
2346 kfree(all_cpu_data[cpu]);
2347 all_cpu_data[cpu] = NULL;
2353 static int intel_pstate_register_driver(void)
2357 intel_pstate_init_limits(&global);
2359 ret = cpufreq_register_driver(intel_pstate_driver);
2361 intel_pstate_driver_cleanup();
2365 mutex_lock(&intel_pstate_limits_lock);
2366 driver_registered = true;
2367 mutex_unlock(&intel_pstate_limits_lock);
2369 if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2370 pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2371 intel_pstate_debug_expose_params();
2376 static int intel_pstate_unregister_driver(void)
2381 if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2382 pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2383 intel_pstate_debug_hide_params();
2385 mutex_lock(&intel_pstate_limits_lock);
2386 driver_registered = false;
2387 mutex_unlock(&intel_pstate_limits_lock);
2389 cpufreq_unregister_driver(intel_pstate_driver);
2390 intel_pstate_driver_cleanup();
2395 static ssize_t intel_pstate_show_status(char *buf)
2397 if (!driver_registered)
2398 return sprintf(buf, "off\n");
2400 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2401 "active" : "passive");
2404 static int intel_pstate_update_status(const char *buf, size_t size)
2408 if (size == 3 && !strncmp(buf, "off", size))
2409 return driver_registered ?
2410 intel_pstate_unregister_driver() : -EINVAL;
2412 if (size == 6 && !strncmp(buf, "active", size)) {
2413 if (driver_registered) {
2414 if (intel_pstate_driver == &intel_pstate)
2417 ret = intel_pstate_unregister_driver();
2422 intel_pstate_driver = &intel_pstate;
2423 return intel_pstate_register_driver();
2426 if (size == 7 && !strncmp(buf, "passive", size)) {
2427 if (driver_registered) {
2428 if (intel_pstate_driver != &intel_pstate)
2431 ret = intel_pstate_unregister_driver();
2436 intel_pstate_driver = &intel_cpufreq;
2437 return intel_pstate_register_driver();
2443 static int no_load __initdata;
2444 static int no_hwp __initdata;
2445 static int hwp_only __initdata;
2446 static unsigned int force_load __initdata;
2448 static int __init intel_pstate_msrs_not_valid(void)
2450 if (!pstate_funcs.get_max() ||
2451 !pstate_funcs.get_min() ||
2452 !pstate_funcs.get_turbo())
2458 static void __init copy_pid_params(struct pstate_adjust_policy *policy)
2460 pid_params.sample_rate_ms = policy->sample_rate_ms;
2461 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
2462 pid_params.p_gain_pct = policy->p_gain_pct;
2463 pid_params.i_gain_pct = policy->i_gain_pct;
2464 pid_params.d_gain_pct = policy->d_gain_pct;
2465 pid_params.deadband = policy->deadband;
2466 pid_params.setpoint = policy->setpoint;
2470 static void intel_pstate_use_acpi_profile(void)
2472 if (acpi_gbl_FADT.preferred_profile == PM_MOBILE)
2473 pstate_funcs.get_target_pstate =
2474 get_target_pstate_use_cpu_load;
2477 static void intel_pstate_use_acpi_profile(void)
2482 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2484 pstate_funcs.get_max = funcs->get_max;
2485 pstate_funcs.get_max_physical = funcs->get_max_physical;
2486 pstate_funcs.get_min = funcs->get_min;
2487 pstate_funcs.get_turbo = funcs->get_turbo;
2488 pstate_funcs.get_scaling = funcs->get_scaling;
2489 pstate_funcs.get_val = funcs->get_val;
2490 pstate_funcs.get_vid = funcs->get_vid;
2491 pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2493 intel_pstate_use_acpi_profile();
2498 static bool __init intel_pstate_no_acpi_pss(void)
2502 for_each_possible_cpu(i) {
2504 union acpi_object *pss;
2505 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2506 struct acpi_processor *pr = per_cpu(processors, i);
2511 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2512 if (ACPI_FAILURE(status))
2515 pss = buffer.pointer;
2516 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2527 static bool __init intel_pstate_has_acpi_ppc(void)
2531 for_each_possible_cpu(i) {
2532 struct acpi_processor *pr = per_cpu(processors, i);
2536 if (acpi_has_method(pr->handle, "_PPC"))
2547 struct hw_vendor_info {
2549 char oem_id[ACPI_OEM_ID_SIZE];
2550 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2554 /* Hardware vendor-specific info that has its own power management modes */
2555 static struct hw_vendor_info vendor_info[] __initdata = {
2556 {1, "HP ", "ProLiant", PSS},
2557 {1, "ORACLE", "X4-2 ", PPC},
2558 {1, "ORACLE", "X4-2L ", PPC},
2559 {1, "ORACLE", "X4-2B ", PPC},
2560 {1, "ORACLE", "X3-2 ", PPC},
2561 {1, "ORACLE", "X3-2L ", PPC},
2562 {1, "ORACLE", "X3-2B ", PPC},
2563 {1, "ORACLE", "X4470M2 ", PPC},
2564 {1, "ORACLE", "X4270M3 ", PPC},
2565 {1, "ORACLE", "X4270M2 ", PPC},
2566 {1, "ORACLE", "X4170M2 ", PPC},
2567 {1, "ORACLE", "X4170 M3", PPC},
2568 {1, "ORACLE", "X4275 M3", PPC},
2569 {1, "ORACLE", "X6-2 ", PPC},
2570 {1, "ORACLE", "Sudbury ", PPC},
2574 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2576 struct acpi_table_header hdr;
2577 struct hw_vendor_info *v_info;
2578 const struct x86_cpu_id *id;
2581 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2583 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2584 if ( misc_pwr & (1 << 8))
2588 if (acpi_disabled ||
2589 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2592 for (v_info = vendor_info; v_info->valid; v_info++) {
2593 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2594 !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2595 ACPI_OEM_TABLE_ID_SIZE))
2596 switch (v_info->oem_pwr_table) {
2598 return intel_pstate_no_acpi_pss();
2600 return intel_pstate_has_acpi_ppc() &&
2608 static void intel_pstate_request_control_from_smm(void)
2611 * It may be unsafe to request P-states control from SMM if _PPC support
2612 * has not been enabled.
2615 acpi_processor_pstate_control();
2617 #else /* CONFIG_ACPI not enabled */
2618 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2619 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2620 static inline void intel_pstate_request_control_from_smm(void) {}
2621 #endif /* CONFIG_ACPI */
2623 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2624 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2628 static int __init intel_pstate_init(void)
2635 if (x86_match_cpu(hwp_support_ids)) {
2636 copy_cpu_funcs(&core_params.funcs);
2638 pstate_funcs.get_target_pstate = get_target_pstate_use_cpu_load;
2641 intel_pstate.attr = hwp_cpufreq_attrs;
2642 goto hwp_cpu_matched;
2645 const struct x86_cpu_id *id;
2646 struct cpu_defaults *cpu_def;
2648 id = x86_match_cpu(intel_pstate_cpu_ids);
2652 cpu_def = (struct cpu_defaults *)id->driver_data;
2654 copy_pid_params(&cpu_def->pid_policy);
2655 copy_cpu_funcs(&cpu_def->funcs);
2658 if (intel_pstate_msrs_not_valid())
2663 * The Intel pstate driver will be ignored if the platform
2664 * firmware has its own power management modes.
2666 if (intel_pstate_platform_pwr_mgmt_exists())
2669 if (!hwp_active && hwp_only)
2672 pr_info("Intel P-state driver initializing\n");
2674 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2678 intel_pstate_request_control_from_smm();
2680 intel_pstate_sysfs_expose_params();
2682 mutex_lock(&intel_pstate_driver_lock);
2683 rc = intel_pstate_register_driver();
2684 mutex_unlock(&intel_pstate_driver_lock);
2689 pr_info("HWP enabled\n");
2693 device_initcall(intel_pstate_init);
2695 static int __init intel_pstate_setup(char *str)
2700 if (!strcmp(str, "disable")) {
2702 } else if (!strcmp(str, "passive")) {
2703 pr_info("Passive mode enabled\n");
2704 intel_pstate_driver = &intel_cpufreq;
2707 if (!strcmp(str, "no_hwp")) {
2708 pr_info("HWP disabled\n");
2711 if (!strcmp(str, "force"))
2713 if (!strcmp(str, "hwp_only"))
2715 if (!strcmp(str, "per_cpu_perf_limits"))
2716 per_cpu_limits = true;
2719 if (!strcmp(str, "support_acpi_ppc"))
2725 early_param("intel_pstate", intel_pstate_setup);
2727 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2728 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2729 MODULE_LICENSE("GPL");