2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * CPU frequency scaling for S5PC110/S5PV210
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/cpufreq.h>
19 #include <linux/reboot.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/suspend.h>
24 #include <mach/regs-clock.h>
26 static struct clk *cpu_clk;
27 static struct clk *dmc0_clk;
28 static struct clk *dmc1_clk;
29 static struct cpufreq_freqs freqs;
30 static DEFINE_MUTEX(set_freq_lock);
32 /* APLL M,P,S values for 1G/800Mhz */
33 #define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
34 #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
36 /* Use 800MHz when entering sleep mode */
37 #define SLEEP_FREQ (800 * 1000)
40 * relation has an additional symantics other than the standard of cpufreq
41 * DISALBE_FURTHER_CPUFREQ: disable further access to target
42 * ENABLE_FURTUER_CPUFREQ: enable access to target
45 DISABLE_FURTHER_CPUFREQ = 0x10,
46 ENABLE_FURTHER_CPUFREQ = 0x20,
49 static bool no_cpufreq_access;
52 * DRAM configurations to calculate refresh counter for changing
53 * frequency of memory.
56 unsigned long freq; /* HZ */
57 unsigned long refresh; /* DRAM refresh counter * 1000 */
60 /* DRAM configuration (DMC0 and DMC1) */
61 static struct dram_conf s5pv210_dram_conf[2];
67 enum s5pv210_mem_type {
73 enum s5pv210_dmc_port {
78 static struct cpufreq_frequency_table s5pv210_freq_table[] = {
84 {0, CPUFREQ_TABLE_END},
87 static struct regulator *arm_regulator;
88 static struct regulator *int_regulator;
90 struct s5pv210_dvs_conf {
91 int arm_volt; /* uV */
92 int int_volt; /* uV */
95 static const int arm_volt_max = 1350000;
96 static const int int_volt_max = 1250000;
98 static struct s5pv210_dvs_conf dvs_conf[] = {
121 static u32 clkdiv_val[5][11] = {
123 * Clock divider value for following
124 * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
125 * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
126 * ONEDRAM, MFC, G3D }
129 /* L0 : [1000/200/100][166/83][133/66][200/200] */
130 {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
132 /* L1 : [800/200/100][166/83][133/66][200/200] */
133 {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
135 /* L2 : [400/200/100][166/83][133/66][200/200] */
136 {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
138 /* L3 : [200/200/100][166/83][133/66][200/200] */
139 {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
141 /* L4 : [100/100/100][83/83][66/66][100/100] */
142 {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
146 * This function set DRAM refresh counter
147 * accoriding to operating frequency of DRAM
148 * ch: DMC port number 0 or 1
149 * freq: Operating frequency of DRAM(KHz)
151 static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
153 unsigned long tmp, tmp1;
154 void __iomem *reg = NULL;
157 reg = (S5P_VA_DMC0 + 0x30);
158 } else if (ch == DMC1) {
159 reg = (S5P_VA_DMC1 + 0x30);
161 printk(KERN_ERR "Cannot find DMC port\n");
165 /* Find current DRAM frequency */
166 tmp = s5pv210_dram_conf[ch].freq;
170 tmp1 = s5pv210_dram_conf[ch].refresh;
174 __raw_writel(tmp1, reg);
177 static unsigned int s5pv210_getspeed(unsigned int cpu)
182 return clk_get_rate(cpu_clk) / 1000;
185 static int s5pv210_target(struct cpufreq_policy *policy,
186 unsigned int target_freq,
187 unsigned int relation)
190 unsigned int index, priv_index;
191 unsigned int pll_changing = 0;
192 unsigned int bus_speed_changing = 0;
193 int arm_volt, int_volt;
196 mutex_lock(&set_freq_lock);
198 if (relation & ENABLE_FURTHER_CPUFREQ)
199 no_cpufreq_access = false;
201 if (no_cpufreq_access) {
202 #ifdef CONFIG_PM_VERBOSE
203 pr_err("%s:%d denied access to %s as it is disabled"
204 "temporarily\n", __FILE__, __LINE__, __func__);
210 if (relation & DISABLE_FURTHER_CPUFREQ)
211 no_cpufreq_access = true;
213 relation &= ~(ENABLE_FURTHER_CPUFREQ | DISABLE_FURTHER_CPUFREQ);
215 freqs.old = s5pv210_getspeed(0);
217 if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
218 target_freq, relation, &index)) {
223 freqs.new = s5pv210_freq_table[index].frequency;
225 if (freqs.new == freqs.old)
228 /* Finding current running level index */
229 if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
230 freqs.old, relation, &priv_index)) {
235 arm_volt = dvs_conf[index].arm_volt;
236 int_volt = dvs_conf[index].int_volt;
238 if (freqs.new > freqs.old) {
239 ret = regulator_set_voltage(arm_regulator,
240 arm_volt, arm_volt_max);
244 ret = regulator_set_voltage(int_regulator,
245 int_volt, int_volt_max);
250 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
252 /* Check if there need to change PLL */
253 if ((index == L0) || (priv_index == L0))
256 /* Check if there need to change System bus clock */
257 if ((index == L4) || (priv_index == L4))
258 bus_speed_changing = 1;
260 if (bus_speed_changing) {
262 * Reconfigure DRAM refresh counter value for minimum
263 * temporary clock while changing divider.
264 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
267 s5pv210_set_refresh(DMC1, 83000);
269 s5pv210_set_refresh(DMC1, 100000);
271 s5pv210_set_refresh(DMC0, 83000);
275 * APLL should be changed in this level
276 * APLL -> MPLL(for stable transition) -> APLL
277 * Some clock source's clock API are not prepared.
278 * Do not use clock API in below code.
282 * 1. Temporary Change divider for MFC and G3D
283 * SCLKA2M(200/1=200)->(200/4=50)Mhz
285 reg = __raw_readl(S5P_CLK_DIV2);
286 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
287 reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
288 (3 << S5P_CLKDIV2_MFC_SHIFT);
289 __raw_writel(reg, S5P_CLK_DIV2);
291 /* For MFC, G3D dividing */
293 reg = __raw_readl(S5P_CLKDIV_STAT0);
294 } while (reg & ((1 << 16) | (1 << 17)));
297 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
298 * (200/4=50)->(667/4=166)Mhz
300 reg = __raw_readl(S5P_CLK_SRC2);
301 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
302 reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
303 (1 << S5P_CLKSRC2_MFC_SHIFT);
304 __raw_writel(reg, S5P_CLK_SRC2);
307 reg = __raw_readl(S5P_CLKMUX_STAT1);
308 } while (reg & ((1 << 7) | (1 << 3)));
311 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
312 * true refresh counter is already programed in upper
315 if (!bus_speed_changing)
316 s5pv210_set_refresh(DMC1, 133000);
318 /* 4. SCLKAPLL -> SCLKMPLL */
319 reg = __raw_readl(S5P_CLK_SRC0);
320 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
321 reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
322 __raw_writel(reg, S5P_CLK_SRC0);
325 reg = __raw_readl(S5P_CLKMUX_STAT0);
326 } while (reg & (0x1 << 18));
331 reg = __raw_readl(S5P_CLK_DIV0);
333 reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
334 S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
335 S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
336 S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
338 reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
339 (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
340 (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
341 (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
342 (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
343 (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
344 (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
345 (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
347 __raw_writel(reg, S5P_CLK_DIV0);
350 reg = __raw_readl(S5P_CLKDIV_STAT0);
351 } while (reg & 0xff);
353 /* ARM MCS value changed */
354 reg = __raw_readl(S5P_ARM_MCS_CON);
361 __raw_writel(reg, S5P_ARM_MCS_CON);
364 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
365 __raw_writel(0x2cf, S5P_APLL_LOCK);
369 * 6-1. Set PMS values
370 * 6-2. Wait untile the PLL is locked
373 __raw_writel(APLL_VAL_1000, S5P_APLL_CON);
375 __raw_writel(APLL_VAL_800, S5P_APLL_CON);
378 reg = __raw_readl(S5P_APLL_CON);
379 } while (!(reg & (0x1 << 29)));
382 * 7. Change souce clock from SCLKMPLL(667Mhz)
383 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
384 * (667/4=166)->(200/4=50)Mhz
386 reg = __raw_readl(S5P_CLK_SRC2);
387 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
388 reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
389 (0 << S5P_CLKSRC2_MFC_SHIFT);
390 __raw_writel(reg, S5P_CLK_SRC2);
393 reg = __raw_readl(S5P_CLKMUX_STAT1);
394 } while (reg & ((1 << 7) | (1 << 3)));
397 * 8. Change divider for MFC and G3D
398 * (200/4=50)->(200/1=200)Mhz
400 reg = __raw_readl(S5P_CLK_DIV2);
401 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
402 reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
403 (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
404 __raw_writel(reg, S5P_CLK_DIV2);
406 /* For MFC, G3D dividing */
408 reg = __raw_readl(S5P_CLKDIV_STAT0);
409 } while (reg & ((1 << 16) | (1 << 17)));
411 /* 9. Change MPLL to APLL in MSYS_MUX */
412 reg = __raw_readl(S5P_CLK_SRC0);
413 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
414 reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
415 __raw_writel(reg, S5P_CLK_SRC0);
418 reg = __raw_readl(S5P_CLKMUX_STAT0);
419 } while (reg & (0x1 << 18));
422 * 10. DMC1 refresh counter
423 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
424 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
426 if (!bus_speed_changing)
427 s5pv210_set_refresh(DMC1, 200000);
431 * L4 level need to change memory bus speed, hence onedram clock divier
432 * and memory refresh parameter should be changed
434 if (bus_speed_changing) {
435 reg = __raw_readl(S5P_CLK_DIV6);
436 reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
437 reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
438 __raw_writel(reg, S5P_CLK_DIV6);
441 reg = __raw_readl(S5P_CLKDIV_STAT1);
442 } while (reg & (1 << 15));
444 /* Reconfigure DRAM refresh counter value */
450 s5pv210_set_refresh(DMC0, 166000);
451 s5pv210_set_refresh(DMC1, 200000);
457 s5pv210_set_refresh(DMC0, 83000);
458 s5pv210_set_refresh(DMC1, 100000);
462 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
464 if (freqs.new < freqs.old) {
465 regulator_set_voltage(int_regulator,
466 int_volt, int_volt_max);
468 regulator_set_voltage(arm_regulator,
469 arm_volt, arm_volt_max);
472 printk(KERN_DEBUG "Perf changed[L%d]\n", index);
475 mutex_unlock(&set_freq_lock);
480 static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy)
485 static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
491 static int check_mem_type(void __iomem *dmc_reg)
495 val = __raw_readl(dmc_reg + 0x4);
496 val = (val & (0xf << 8));
501 static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
503 unsigned long mem_type;
506 cpu_clk = clk_get(NULL, "armclk");
508 return PTR_ERR(cpu_clk);
510 dmc0_clk = clk_get(NULL, "sclk_dmc0");
511 if (IS_ERR(dmc0_clk)) {
512 ret = PTR_ERR(dmc0_clk);
516 dmc1_clk = clk_get(NULL, "hclk_msys");
517 if (IS_ERR(dmc1_clk)) {
518 ret = PTR_ERR(dmc1_clk);
522 if (policy->cpu != 0) {
528 * check_mem_type : This driver only support LPDDR & LPDDR2.
529 * other memory type is not supported.
531 mem_type = check_mem_type(S5P_VA_DMC0);
533 if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
534 printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
539 /* Find current refresh counter and frequency each DMC */
540 s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
541 s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
543 s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
544 s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
546 return cpufreq_generic_init(policy, s5pv210_freq_table, 40000);
555 static int s5pv210_cpufreq_notifier_event(struct notifier_block *this,
556 unsigned long event, void *ptr)
561 case PM_SUSPEND_PREPARE:
562 ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ,
563 DISABLE_FURTHER_CPUFREQ);
568 case PM_POST_RESTORE:
569 case PM_POST_SUSPEND:
570 cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ,
571 ENABLE_FURTHER_CPUFREQ);
579 static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this,
580 unsigned long event, void *ptr)
584 ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ,
585 DISABLE_FURTHER_CPUFREQ);
592 static struct cpufreq_driver s5pv210_driver = {
593 .flags = CPUFREQ_STICKY,
594 .verify = cpufreq_generic_frequency_table_verify,
595 .target = s5pv210_target,
596 .get = s5pv210_getspeed,
597 .init = s5pv210_cpu_init,
600 .suspend = s5pv210_cpufreq_suspend,
601 .resume = s5pv210_cpufreq_resume,
605 static struct notifier_block s5pv210_cpufreq_notifier = {
606 .notifier_call = s5pv210_cpufreq_notifier_event,
609 static struct notifier_block s5pv210_cpufreq_reboot_notifier = {
610 .notifier_call = s5pv210_cpufreq_reboot_notifier_event,
613 static int __init s5pv210_cpufreq_init(void)
615 arm_regulator = regulator_get(NULL, "vddarm");
616 if (IS_ERR(arm_regulator)) {
617 pr_err("failed to get regulator vddarm");
618 return PTR_ERR(arm_regulator);
621 int_regulator = regulator_get(NULL, "vddint");
622 if (IS_ERR(int_regulator)) {
623 pr_err("failed to get regulator vddint");
624 regulator_put(arm_regulator);
625 return PTR_ERR(int_regulator);
628 register_pm_notifier(&s5pv210_cpufreq_notifier);
629 register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier);
631 return cpufreq_register_driver(&s5pv210_driver);
634 late_initcall(s5pv210_cpufreq_init);