4 * Support for ATMEL AES HW acceleration.
6 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
7 * Author: Nicolas Royer <nicolas@eukrea.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
13 * Some ideas are from omap-aes.c driver.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
23 #include <linux/hw_random.h>
24 #include <linux/platform_device.h>
26 #include <linux/device.h>
27 #include <linux/init.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/scatterlist.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/of_device.h>
34 #include <linux/delay.h>
35 #include <linux/crypto.h>
36 #include <crypto/scatterwalk.h>
37 #include <crypto/algapi.h>
38 #include <crypto/aes.h>
39 #include <crypto/xts.h>
40 #include <crypto/internal/aead.h>
41 #include <linux/platform_data/crypto-atmel.h>
42 #include <dt-bindings/dma/at91.h>
43 #include "atmel-aes-regs.h"
45 #define ATMEL_AES_PRIORITY 300
47 #define ATMEL_AES_BUFFER_ORDER 2
48 #define ATMEL_AES_BUFFER_SIZE (PAGE_SIZE << ATMEL_AES_BUFFER_ORDER)
50 #define CFB8_BLOCK_SIZE 1
51 #define CFB16_BLOCK_SIZE 2
52 #define CFB32_BLOCK_SIZE 4
53 #define CFB64_BLOCK_SIZE 8
55 #define SIZE_IN_WORDS(x) ((x) >> 2)
58 /* Reserve bits [18:16] [14:12] [1:0] for mode (same as for AES_MR) */
59 #define AES_FLAGS_ENCRYPT AES_MR_CYPHER_ENC
60 #define AES_FLAGS_GTAGEN AES_MR_GTAGEN
61 #define AES_FLAGS_OPMODE_MASK (AES_MR_OPMOD_MASK | AES_MR_CFBS_MASK)
62 #define AES_FLAGS_ECB AES_MR_OPMOD_ECB
63 #define AES_FLAGS_CBC AES_MR_OPMOD_CBC
64 #define AES_FLAGS_OFB AES_MR_OPMOD_OFB
65 #define AES_FLAGS_CFB128 (AES_MR_OPMOD_CFB | AES_MR_CFBS_128b)
66 #define AES_FLAGS_CFB64 (AES_MR_OPMOD_CFB | AES_MR_CFBS_64b)
67 #define AES_FLAGS_CFB32 (AES_MR_OPMOD_CFB | AES_MR_CFBS_32b)
68 #define AES_FLAGS_CFB16 (AES_MR_OPMOD_CFB | AES_MR_CFBS_16b)
69 #define AES_FLAGS_CFB8 (AES_MR_OPMOD_CFB | AES_MR_CFBS_8b)
70 #define AES_FLAGS_CTR AES_MR_OPMOD_CTR
71 #define AES_FLAGS_GCM AES_MR_OPMOD_GCM
72 #define AES_FLAGS_XTS AES_MR_OPMOD_XTS
74 #define AES_FLAGS_MODE_MASK (AES_FLAGS_OPMODE_MASK | \
78 #define AES_FLAGS_INIT BIT(2)
79 #define AES_FLAGS_BUSY BIT(3)
80 #define AES_FLAGS_DUMP_REG BIT(4)
82 #define AES_FLAGS_PERSISTENT (AES_FLAGS_INIT | AES_FLAGS_BUSY)
84 #define ATMEL_AES_QUEUE_LENGTH 50
86 #define ATMEL_AES_DMA_THRESHOLD 256
89 struct atmel_aes_caps {
101 typedef int (*atmel_aes_fn_t)(struct atmel_aes_dev *);
104 struct atmel_aes_base_ctx {
105 struct atmel_aes_dev *dd;
106 atmel_aes_fn_t start;
108 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
112 struct atmel_aes_ctx {
113 struct atmel_aes_base_ctx base;
116 struct atmel_aes_ctr_ctx {
117 struct atmel_aes_base_ctx base;
119 u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
121 struct scatterlist src[2];
122 struct scatterlist dst[2];
125 struct atmel_aes_gcm_ctx {
126 struct atmel_aes_base_ctx base;
128 struct scatterlist src[2];
129 struct scatterlist dst[2];
131 u32 j0[AES_BLOCK_SIZE / sizeof(u32)];
132 u32 tag[AES_BLOCK_SIZE / sizeof(u32)];
133 u32 ghash[AES_BLOCK_SIZE / sizeof(u32)];
138 atmel_aes_fn_t ghash_resume;
141 struct atmel_aes_xts_ctx {
142 struct atmel_aes_base_ctx base;
144 u32 key2[AES_KEYSIZE_256 / sizeof(u32)];
147 struct atmel_aes_reqctx {
151 struct atmel_aes_dma {
152 struct dma_chan *chan;
153 struct scatterlist *sg;
155 unsigned int remainder;
159 struct atmel_aes_dev {
160 struct list_head list;
161 unsigned long phys_base;
162 void __iomem *io_base;
164 struct crypto_async_request *areq;
165 struct atmel_aes_base_ctx *ctx;
168 atmel_aes_fn_t resume;
169 atmel_aes_fn_t cpu_transfer_complete;
178 struct crypto_queue queue;
180 struct tasklet_struct done_task;
181 struct tasklet_struct queue_task;
187 struct atmel_aes_dma src;
188 struct atmel_aes_dma dst;
192 struct scatterlist aligned_sg;
193 struct scatterlist *real_dst;
195 struct atmel_aes_caps caps;
200 struct atmel_aes_drv {
201 struct list_head dev_list;
205 static struct atmel_aes_drv atmel_aes = {
206 .dev_list = LIST_HEAD_INIT(atmel_aes.dev_list),
207 .lock = __SPIN_LOCK_UNLOCKED(atmel_aes.lock),
211 static const char *atmel_aes_reg_name(u32 offset, char *tmp, size_t sz)
240 snprintf(tmp, sz, "KEYWR[%u]", (offset - AES_KEYWR(0)) >> 2);
247 snprintf(tmp, sz, "IDATAR[%u]", (offset - AES_IDATAR(0)) >> 2);
254 snprintf(tmp, sz, "ODATAR[%u]", (offset - AES_ODATAR(0)) >> 2);
261 snprintf(tmp, sz, "IVR[%u]", (offset - AES_IVR(0)) >> 2);
274 snprintf(tmp, sz, "GHASHR[%u]", (offset - AES_GHASHR(0)) >> 2);
281 snprintf(tmp, sz, "TAGR[%u]", (offset - AES_TAGR(0)) >> 2);
291 snprintf(tmp, sz, "GCMHR[%u]", (offset - AES_GCMHR(0)) >> 2);
298 snprintf(tmp, sz, "TWR[%u]", (offset - AES_TWR(0)) >> 2);
305 snprintf(tmp, sz, "ALPHAR[%u]", (offset - AES_ALPHAR(0)) >> 2);
309 snprintf(tmp, sz, "0x%02x", offset);
315 #endif /* VERBOSE_DEBUG */
317 /* Shared functions */
319 static inline u32 atmel_aes_read(struct atmel_aes_dev *dd, u32 offset)
321 u32 value = readl_relaxed(dd->io_base + offset);
324 if (dd->flags & AES_FLAGS_DUMP_REG) {
327 dev_vdbg(dd->dev, "read 0x%08x from %s\n", value,
328 atmel_aes_reg_name(offset, tmp, sizeof(tmp)));
330 #endif /* VERBOSE_DEBUG */
335 static inline void atmel_aes_write(struct atmel_aes_dev *dd,
336 u32 offset, u32 value)
339 if (dd->flags & AES_FLAGS_DUMP_REG) {
342 dev_vdbg(dd->dev, "write 0x%08x into %s\n", value,
343 atmel_aes_reg_name(offset, tmp, sizeof(tmp)));
345 #endif /* VERBOSE_DEBUG */
347 writel_relaxed(value, dd->io_base + offset);
350 static void atmel_aes_read_n(struct atmel_aes_dev *dd, u32 offset,
351 u32 *value, int count)
353 for (; count--; value++, offset += 4)
354 *value = atmel_aes_read(dd, offset);
357 static void atmel_aes_write_n(struct atmel_aes_dev *dd, u32 offset,
358 const u32 *value, int count)
360 for (; count--; value++, offset += 4)
361 atmel_aes_write(dd, offset, *value);
364 static inline void atmel_aes_read_block(struct atmel_aes_dev *dd, u32 offset,
367 atmel_aes_read_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
370 static inline void atmel_aes_write_block(struct atmel_aes_dev *dd, u32 offset,
373 atmel_aes_write_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
376 static inline int atmel_aes_wait_for_data_ready(struct atmel_aes_dev *dd,
377 atmel_aes_fn_t resume)
379 u32 isr = atmel_aes_read(dd, AES_ISR);
381 if (unlikely(isr & AES_INT_DATARDY))
385 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
389 static inline size_t atmel_aes_padlen(size_t len, size_t block_size)
391 len &= block_size - 1;
392 return len ? block_size - len : 0;
395 static struct atmel_aes_dev *atmel_aes_find_dev(struct atmel_aes_base_ctx *ctx)
397 struct atmel_aes_dev *aes_dd = NULL;
398 struct atmel_aes_dev *tmp;
400 spin_lock_bh(&atmel_aes.lock);
402 list_for_each_entry(tmp, &atmel_aes.dev_list, list) {
411 spin_unlock_bh(&atmel_aes.lock);
416 static int atmel_aes_hw_init(struct atmel_aes_dev *dd)
420 err = clk_enable(dd->iclk);
424 if (!(dd->flags & AES_FLAGS_INIT)) {
425 atmel_aes_write(dd, AES_CR, AES_CR_SWRST);
426 atmel_aes_write(dd, AES_MR, 0xE << AES_MR_CKEY_OFFSET);
427 dd->flags |= AES_FLAGS_INIT;
433 static inline unsigned int atmel_aes_get_version(struct atmel_aes_dev *dd)
435 return atmel_aes_read(dd, AES_HW_VERSION) & 0x00000fff;
438 static int atmel_aes_hw_version_init(struct atmel_aes_dev *dd)
442 err = atmel_aes_hw_init(dd);
446 dd->hw_version = atmel_aes_get_version(dd);
448 dev_info(dd->dev, "version: 0x%x\n", dd->hw_version);
450 clk_disable(dd->iclk);
454 static inline void atmel_aes_set_mode(struct atmel_aes_dev *dd,
455 const struct atmel_aes_reqctx *rctx)
457 /* Clear all but persistent flags and set request flags. */
458 dd->flags = (dd->flags & AES_FLAGS_PERSISTENT) | rctx->mode;
461 static inline bool atmel_aes_is_encrypt(const struct atmel_aes_dev *dd)
463 return (dd->flags & AES_FLAGS_ENCRYPT);
466 static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err)
468 clk_disable(dd->iclk);
469 dd->flags &= ~AES_FLAGS_BUSY;
472 dd->areq->complete(dd->areq, err);
474 tasklet_schedule(&dd->queue_task);
479 static void atmel_aes_write_ctrl_key(struct atmel_aes_dev *dd, bool use_dma,
480 const u32 *iv, const u32 *key, int keylen)
484 /* MR register must be set before IV registers */
485 if (keylen == AES_KEYSIZE_128)
486 valmr |= AES_MR_KEYSIZE_128;
487 else if (keylen == AES_KEYSIZE_192)
488 valmr |= AES_MR_KEYSIZE_192;
490 valmr |= AES_MR_KEYSIZE_256;
492 valmr |= dd->flags & AES_FLAGS_MODE_MASK;
495 valmr |= AES_MR_SMOD_IDATAR0;
496 if (dd->caps.has_dualbuff)
497 valmr |= AES_MR_DUALBUFF;
499 valmr |= AES_MR_SMOD_AUTO;
502 atmel_aes_write(dd, AES_MR, valmr);
504 atmel_aes_write_n(dd, AES_KEYWR(0), key, SIZE_IN_WORDS(keylen));
506 if (iv && (valmr & AES_MR_OPMOD_MASK) != AES_MR_OPMOD_ECB)
507 atmel_aes_write_block(dd, AES_IVR(0), iv);
510 static inline void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
514 atmel_aes_write_ctrl_key(dd, use_dma, iv,
515 dd->ctx->key, dd->ctx->keylen);
520 static int atmel_aes_cpu_transfer(struct atmel_aes_dev *dd)
526 atmel_aes_read_block(dd, AES_ODATAR(0), dd->data);
528 dd->datalen -= AES_BLOCK_SIZE;
530 if (dd->datalen < AES_BLOCK_SIZE)
533 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
535 isr = atmel_aes_read(dd, AES_ISR);
536 if (!(isr & AES_INT_DATARDY)) {
537 dd->resume = atmel_aes_cpu_transfer;
538 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
543 if (!sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
548 return atmel_aes_complete(dd, err);
550 return dd->cpu_transfer_complete(dd);
553 static int atmel_aes_cpu_start(struct atmel_aes_dev *dd,
554 struct scatterlist *src,
555 struct scatterlist *dst,
557 atmel_aes_fn_t resume)
559 size_t padlen = atmel_aes_padlen(len, AES_BLOCK_SIZE);
561 if (unlikely(len == 0))
564 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
568 dd->cpu_transfer_complete = resume;
569 dd->datalen = len + padlen;
570 dd->data = (u32 *)dd->buf;
571 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
572 return atmel_aes_wait_for_data_ready(dd, atmel_aes_cpu_transfer);
578 static void atmel_aes_dma_callback(void *data);
580 static bool atmel_aes_check_aligned(struct atmel_aes_dev *dd,
581 struct scatterlist *sg,
583 struct atmel_aes_dma *dma)
587 if (!IS_ALIGNED(len, dd->ctx->block_size))
590 for (nents = 0; sg; sg = sg_next(sg), ++nents) {
591 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
594 if (len <= sg->length) {
595 if (!IS_ALIGNED(len, dd->ctx->block_size))
598 dma->nents = nents+1;
599 dma->remainder = sg->length - len;
604 if (!IS_ALIGNED(sg->length, dd->ctx->block_size))
613 static inline void atmel_aes_restore_sg(const struct atmel_aes_dma *dma)
615 struct scatterlist *sg = dma->sg;
616 int nents = dma->nents;
621 while (--nents > 0 && sg)
627 sg->length += dma->remainder;
630 static int atmel_aes_map(struct atmel_aes_dev *dd,
631 struct scatterlist *src,
632 struct scatterlist *dst,
635 bool src_aligned, dst_aligned;
643 src_aligned = atmel_aes_check_aligned(dd, src, len, &dd->src);
645 dst_aligned = src_aligned;
647 dst_aligned = atmel_aes_check_aligned(dd, dst, len, &dd->dst);
648 if (!src_aligned || !dst_aligned) {
649 padlen = atmel_aes_padlen(len, dd->ctx->block_size);
651 if (dd->buflen < len + padlen)
655 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
656 dd->src.sg = &dd->aligned_sg;
658 dd->src.remainder = 0;
662 dd->dst.sg = &dd->aligned_sg;
664 dd->dst.remainder = 0;
667 sg_init_table(&dd->aligned_sg, 1);
668 sg_set_buf(&dd->aligned_sg, dd->buf, len + padlen);
671 if (dd->src.sg == dd->dst.sg) {
672 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
674 dd->dst.sg_len = dd->src.sg_len;
678 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
683 dd->dst.sg_len = dma_map_sg(dd->dev, dd->dst.sg, dd->dst.nents,
685 if (!dd->dst.sg_len) {
686 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
695 static void atmel_aes_unmap(struct atmel_aes_dev *dd)
697 if (dd->src.sg == dd->dst.sg) {
698 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
701 if (dd->src.sg != &dd->aligned_sg)
702 atmel_aes_restore_sg(&dd->src);
704 dma_unmap_sg(dd->dev, dd->dst.sg, dd->dst.nents,
707 if (dd->dst.sg != &dd->aligned_sg)
708 atmel_aes_restore_sg(&dd->dst);
710 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
713 if (dd->src.sg != &dd->aligned_sg)
714 atmel_aes_restore_sg(&dd->src);
717 if (dd->dst.sg == &dd->aligned_sg)
718 sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
722 static int atmel_aes_dma_transfer_start(struct atmel_aes_dev *dd,
723 enum dma_slave_buswidth addr_width,
724 enum dma_transfer_direction dir,
727 struct dma_async_tx_descriptor *desc;
728 struct dma_slave_config config;
729 dma_async_tx_callback callback;
730 struct atmel_aes_dma *dma;
733 memset(&config, 0, sizeof(config));
734 config.direction = dir;
735 config.src_addr_width = addr_width;
736 config.dst_addr_width = addr_width;
737 config.src_maxburst = maxburst;
738 config.dst_maxburst = maxburst;
744 config.dst_addr = dd->phys_base + AES_IDATAR(0);
749 callback = atmel_aes_dma_callback;
750 config.src_addr = dd->phys_base + AES_ODATAR(0);
757 err = dmaengine_slave_config(dma->chan, &config);
761 desc = dmaengine_prep_slave_sg(dma->chan, dma->sg, dma->sg_len, dir,
762 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
766 desc->callback = callback;
767 desc->callback_param = dd;
768 dmaengine_submit(desc);
769 dma_async_issue_pending(dma->chan);
774 static void atmel_aes_dma_transfer_stop(struct atmel_aes_dev *dd,
775 enum dma_transfer_direction dir)
777 struct atmel_aes_dma *dma;
792 dmaengine_terminate_all(dma->chan);
795 static int atmel_aes_dma_start(struct atmel_aes_dev *dd,
796 struct scatterlist *src,
797 struct scatterlist *dst,
799 atmel_aes_fn_t resume)
801 enum dma_slave_buswidth addr_width;
805 switch (dd->ctx->block_size) {
806 case CFB8_BLOCK_SIZE:
807 addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
811 case CFB16_BLOCK_SIZE:
812 addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
816 case CFB32_BLOCK_SIZE:
817 case CFB64_BLOCK_SIZE:
818 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
823 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
824 maxburst = dd->caps.max_burst_size;
832 err = atmel_aes_map(dd, src, dst, len);
838 /* Set output DMA transfer first */
839 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_DEV_TO_MEM,
844 /* Then set input DMA transfer */
845 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_MEM_TO_DEV,
848 goto output_transfer_stop;
852 output_transfer_stop:
853 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
857 return atmel_aes_complete(dd, err);
860 static void atmel_aes_dma_stop(struct atmel_aes_dev *dd)
862 atmel_aes_dma_transfer_stop(dd, DMA_MEM_TO_DEV);
863 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
867 static void atmel_aes_dma_callback(void *data)
869 struct atmel_aes_dev *dd = data;
871 atmel_aes_dma_stop(dd);
873 (void)dd->resume(dd);
876 static int atmel_aes_handle_queue(struct atmel_aes_dev *dd,
877 struct crypto_async_request *new_areq)
879 struct crypto_async_request *areq, *backlog;
880 struct atmel_aes_base_ctx *ctx;
884 spin_lock_irqsave(&dd->lock, flags);
886 ret = crypto_enqueue_request(&dd->queue, new_areq);
887 if (dd->flags & AES_FLAGS_BUSY) {
888 spin_unlock_irqrestore(&dd->lock, flags);
891 backlog = crypto_get_backlog(&dd->queue);
892 areq = crypto_dequeue_request(&dd->queue);
894 dd->flags |= AES_FLAGS_BUSY;
895 spin_unlock_irqrestore(&dd->lock, flags);
901 backlog->complete(backlog, -EINPROGRESS);
903 ctx = crypto_tfm_ctx(areq->tfm);
907 dd->is_async = (areq != new_areq);
909 err = ctx->start(dd);
910 return (dd->is_async) ? ret : err;
914 /* AES async block ciphers */
916 static int atmel_aes_transfer_complete(struct atmel_aes_dev *dd)
918 return atmel_aes_complete(dd, 0);
921 static int atmel_aes_start(struct atmel_aes_dev *dd)
923 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
924 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
925 bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD ||
926 dd->ctx->block_size != AES_BLOCK_SIZE);
929 atmel_aes_set_mode(dd, rctx);
931 err = atmel_aes_hw_init(dd);
933 return atmel_aes_complete(dd, err);
935 atmel_aes_write_ctrl(dd, use_dma, req->info);
937 return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
938 atmel_aes_transfer_complete);
940 return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
941 atmel_aes_transfer_complete);
944 static inline struct atmel_aes_ctr_ctx *
945 atmel_aes_ctr_ctx_cast(struct atmel_aes_base_ctx *ctx)
947 return container_of(ctx, struct atmel_aes_ctr_ctx, base);
950 static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
952 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
953 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
954 struct scatterlist *src, *dst;
957 bool use_dma, fragmented = false;
959 /* Check for transfer completion. */
960 ctx->offset += dd->total;
961 if (ctx->offset >= req->nbytes)
962 return atmel_aes_transfer_complete(dd);
964 /* Compute data length. */
965 datalen = req->nbytes - ctx->offset;
966 blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE);
967 ctr = be32_to_cpu(ctx->iv[3]);
968 if (dd->caps.has_ctr32) {
969 /* Check 32bit counter overflow. */
971 u32 end = start + blocks - 1;
975 datalen = AES_BLOCK_SIZE * -start;
979 /* Check 16bit counter overflow. */
980 u16 start = ctr & 0xffff;
981 u16 end = start + (u16)blocks - 1;
983 if (blocks >> 16 || end < start) {
985 datalen = AES_BLOCK_SIZE * (0x10000-start);
989 use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD);
991 /* Jump to offset. */
992 src = scatterwalk_ffwd(ctx->src, req->src, ctx->offset);
993 dst = ((req->src == req->dst) ? src :
994 scatterwalk_ffwd(ctx->dst, req->dst, ctx->offset));
996 /* Configure hardware. */
997 atmel_aes_write_ctrl(dd, use_dma, ctx->iv);
998 if (unlikely(fragmented)) {
1000 * Increment the counter manually to cope with the hardware
1003 ctx->iv[3] = cpu_to_be32(ctr);
1004 crypto_inc((u8 *)ctx->iv, AES_BLOCK_SIZE);
1008 return atmel_aes_dma_start(dd, src, dst, datalen,
1009 atmel_aes_ctr_transfer);
1011 return atmel_aes_cpu_start(dd, src, dst, datalen,
1012 atmel_aes_ctr_transfer);
1015 static int atmel_aes_ctr_start(struct atmel_aes_dev *dd)
1017 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
1018 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1019 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
1022 atmel_aes_set_mode(dd, rctx);
1024 err = atmel_aes_hw_init(dd);
1026 return atmel_aes_complete(dd, err);
1028 memcpy(ctx->iv, req->info, AES_BLOCK_SIZE);
1031 return atmel_aes_ctr_transfer(dd);
1034 static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
1036 struct atmel_aes_base_ctx *ctx;
1037 struct atmel_aes_reqctx *rctx;
1038 struct atmel_aes_dev *dd;
1040 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
1041 switch (mode & AES_FLAGS_OPMODE_MASK) {
1042 case AES_FLAGS_CFB8:
1043 ctx->block_size = CFB8_BLOCK_SIZE;
1046 case AES_FLAGS_CFB16:
1047 ctx->block_size = CFB16_BLOCK_SIZE;
1050 case AES_FLAGS_CFB32:
1051 ctx->block_size = CFB32_BLOCK_SIZE;
1054 case AES_FLAGS_CFB64:
1055 ctx->block_size = CFB64_BLOCK_SIZE;
1059 ctx->block_size = AES_BLOCK_SIZE;
1063 dd = atmel_aes_find_dev(ctx);
1067 rctx = ablkcipher_request_ctx(req);
1070 return atmel_aes_handle_queue(dd, &req->base);
1073 static int atmel_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1074 unsigned int keylen)
1076 struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(tfm);
1078 if (keylen != AES_KEYSIZE_128 &&
1079 keylen != AES_KEYSIZE_192 &&
1080 keylen != AES_KEYSIZE_256) {
1081 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1085 memcpy(ctx->key, key, keylen);
1086 ctx->keylen = keylen;
1091 static int atmel_aes_ecb_encrypt(struct ablkcipher_request *req)
1093 return atmel_aes_crypt(req, AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
1096 static int atmel_aes_ecb_decrypt(struct ablkcipher_request *req)
1098 return atmel_aes_crypt(req, AES_FLAGS_ECB);
1101 static int atmel_aes_cbc_encrypt(struct ablkcipher_request *req)
1103 return atmel_aes_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT);
1106 static int atmel_aes_cbc_decrypt(struct ablkcipher_request *req)
1108 return atmel_aes_crypt(req, AES_FLAGS_CBC);
1111 static int atmel_aes_ofb_encrypt(struct ablkcipher_request *req)
1113 return atmel_aes_crypt(req, AES_FLAGS_OFB | AES_FLAGS_ENCRYPT);
1116 static int atmel_aes_ofb_decrypt(struct ablkcipher_request *req)
1118 return atmel_aes_crypt(req, AES_FLAGS_OFB);
1121 static int atmel_aes_cfb_encrypt(struct ablkcipher_request *req)
1123 return atmel_aes_crypt(req, AES_FLAGS_CFB128 | AES_FLAGS_ENCRYPT);
1126 static int atmel_aes_cfb_decrypt(struct ablkcipher_request *req)
1128 return atmel_aes_crypt(req, AES_FLAGS_CFB128);
1131 static int atmel_aes_cfb64_encrypt(struct ablkcipher_request *req)
1133 return atmel_aes_crypt(req, AES_FLAGS_CFB64 | AES_FLAGS_ENCRYPT);
1136 static int atmel_aes_cfb64_decrypt(struct ablkcipher_request *req)
1138 return atmel_aes_crypt(req, AES_FLAGS_CFB64);
1141 static int atmel_aes_cfb32_encrypt(struct ablkcipher_request *req)
1143 return atmel_aes_crypt(req, AES_FLAGS_CFB32 | AES_FLAGS_ENCRYPT);
1146 static int atmel_aes_cfb32_decrypt(struct ablkcipher_request *req)
1148 return atmel_aes_crypt(req, AES_FLAGS_CFB32);
1151 static int atmel_aes_cfb16_encrypt(struct ablkcipher_request *req)
1153 return atmel_aes_crypt(req, AES_FLAGS_CFB16 | AES_FLAGS_ENCRYPT);
1156 static int atmel_aes_cfb16_decrypt(struct ablkcipher_request *req)
1158 return atmel_aes_crypt(req, AES_FLAGS_CFB16);
1161 static int atmel_aes_cfb8_encrypt(struct ablkcipher_request *req)
1163 return atmel_aes_crypt(req, AES_FLAGS_CFB8 | AES_FLAGS_ENCRYPT);
1166 static int atmel_aes_cfb8_decrypt(struct ablkcipher_request *req)
1168 return atmel_aes_crypt(req, AES_FLAGS_CFB8);
1171 static int atmel_aes_ctr_encrypt(struct ablkcipher_request *req)
1173 return atmel_aes_crypt(req, AES_FLAGS_CTR | AES_FLAGS_ENCRYPT);
1176 static int atmel_aes_ctr_decrypt(struct ablkcipher_request *req)
1178 return atmel_aes_crypt(req, AES_FLAGS_CTR);
1181 static int atmel_aes_cra_init(struct crypto_tfm *tfm)
1183 struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1185 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1186 ctx->base.start = atmel_aes_start;
1191 static int atmel_aes_ctr_cra_init(struct crypto_tfm *tfm)
1193 struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1195 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1196 ctx->base.start = atmel_aes_ctr_start;
1201 static void atmel_aes_cra_exit(struct crypto_tfm *tfm)
1205 static struct crypto_alg aes_algs[] = {
1207 .cra_name = "ecb(aes)",
1208 .cra_driver_name = "atmel-ecb-aes",
1209 .cra_priority = ATMEL_AES_PRIORITY,
1210 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1211 .cra_blocksize = AES_BLOCK_SIZE,
1212 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1213 .cra_alignmask = 0xf,
1214 .cra_type = &crypto_ablkcipher_type,
1215 .cra_module = THIS_MODULE,
1216 .cra_init = atmel_aes_cra_init,
1217 .cra_exit = atmel_aes_cra_exit,
1218 .cra_u.ablkcipher = {
1219 .min_keysize = AES_MIN_KEY_SIZE,
1220 .max_keysize = AES_MAX_KEY_SIZE,
1221 .setkey = atmel_aes_setkey,
1222 .encrypt = atmel_aes_ecb_encrypt,
1223 .decrypt = atmel_aes_ecb_decrypt,
1227 .cra_name = "cbc(aes)",
1228 .cra_driver_name = "atmel-cbc-aes",
1229 .cra_priority = ATMEL_AES_PRIORITY,
1230 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1231 .cra_blocksize = AES_BLOCK_SIZE,
1232 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1233 .cra_alignmask = 0xf,
1234 .cra_type = &crypto_ablkcipher_type,
1235 .cra_module = THIS_MODULE,
1236 .cra_init = atmel_aes_cra_init,
1237 .cra_exit = atmel_aes_cra_exit,
1238 .cra_u.ablkcipher = {
1239 .min_keysize = AES_MIN_KEY_SIZE,
1240 .max_keysize = AES_MAX_KEY_SIZE,
1241 .ivsize = AES_BLOCK_SIZE,
1242 .setkey = atmel_aes_setkey,
1243 .encrypt = atmel_aes_cbc_encrypt,
1244 .decrypt = atmel_aes_cbc_decrypt,
1248 .cra_name = "ofb(aes)",
1249 .cra_driver_name = "atmel-ofb-aes",
1250 .cra_priority = ATMEL_AES_PRIORITY,
1251 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1252 .cra_blocksize = AES_BLOCK_SIZE,
1253 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1254 .cra_alignmask = 0xf,
1255 .cra_type = &crypto_ablkcipher_type,
1256 .cra_module = THIS_MODULE,
1257 .cra_init = atmel_aes_cra_init,
1258 .cra_exit = atmel_aes_cra_exit,
1259 .cra_u.ablkcipher = {
1260 .min_keysize = AES_MIN_KEY_SIZE,
1261 .max_keysize = AES_MAX_KEY_SIZE,
1262 .ivsize = AES_BLOCK_SIZE,
1263 .setkey = atmel_aes_setkey,
1264 .encrypt = atmel_aes_ofb_encrypt,
1265 .decrypt = atmel_aes_ofb_decrypt,
1269 .cra_name = "cfb(aes)",
1270 .cra_driver_name = "atmel-cfb-aes",
1271 .cra_priority = ATMEL_AES_PRIORITY,
1272 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1273 .cra_blocksize = AES_BLOCK_SIZE,
1274 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1275 .cra_alignmask = 0xf,
1276 .cra_type = &crypto_ablkcipher_type,
1277 .cra_module = THIS_MODULE,
1278 .cra_init = atmel_aes_cra_init,
1279 .cra_exit = atmel_aes_cra_exit,
1280 .cra_u.ablkcipher = {
1281 .min_keysize = AES_MIN_KEY_SIZE,
1282 .max_keysize = AES_MAX_KEY_SIZE,
1283 .ivsize = AES_BLOCK_SIZE,
1284 .setkey = atmel_aes_setkey,
1285 .encrypt = atmel_aes_cfb_encrypt,
1286 .decrypt = atmel_aes_cfb_decrypt,
1290 .cra_name = "cfb32(aes)",
1291 .cra_driver_name = "atmel-cfb32-aes",
1292 .cra_priority = ATMEL_AES_PRIORITY,
1293 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1294 .cra_blocksize = CFB32_BLOCK_SIZE,
1295 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1296 .cra_alignmask = 0x3,
1297 .cra_type = &crypto_ablkcipher_type,
1298 .cra_module = THIS_MODULE,
1299 .cra_init = atmel_aes_cra_init,
1300 .cra_exit = atmel_aes_cra_exit,
1301 .cra_u.ablkcipher = {
1302 .min_keysize = AES_MIN_KEY_SIZE,
1303 .max_keysize = AES_MAX_KEY_SIZE,
1304 .ivsize = AES_BLOCK_SIZE,
1305 .setkey = atmel_aes_setkey,
1306 .encrypt = atmel_aes_cfb32_encrypt,
1307 .decrypt = atmel_aes_cfb32_decrypt,
1311 .cra_name = "cfb16(aes)",
1312 .cra_driver_name = "atmel-cfb16-aes",
1313 .cra_priority = ATMEL_AES_PRIORITY,
1314 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1315 .cra_blocksize = CFB16_BLOCK_SIZE,
1316 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1317 .cra_alignmask = 0x1,
1318 .cra_type = &crypto_ablkcipher_type,
1319 .cra_module = THIS_MODULE,
1320 .cra_init = atmel_aes_cra_init,
1321 .cra_exit = atmel_aes_cra_exit,
1322 .cra_u.ablkcipher = {
1323 .min_keysize = AES_MIN_KEY_SIZE,
1324 .max_keysize = AES_MAX_KEY_SIZE,
1325 .ivsize = AES_BLOCK_SIZE,
1326 .setkey = atmel_aes_setkey,
1327 .encrypt = atmel_aes_cfb16_encrypt,
1328 .decrypt = atmel_aes_cfb16_decrypt,
1332 .cra_name = "cfb8(aes)",
1333 .cra_driver_name = "atmel-cfb8-aes",
1334 .cra_priority = ATMEL_AES_PRIORITY,
1335 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1336 .cra_blocksize = CFB8_BLOCK_SIZE,
1337 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1338 .cra_alignmask = 0x0,
1339 .cra_type = &crypto_ablkcipher_type,
1340 .cra_module = THIS_MODULE,
1341 .cra_init = atmel_aes_cra_init,
1342 .cra_exit = atmel_aes_cra_exit,
1343 .cra_u.ablkcipher = {
1344 .min_keysize = AES_MIN_KEY_SIZE,
1345 .max_keysize = AES_MAX_KEY_SIZE,
1346 .ivsize = AES_BLOCK_SIZE,
1347 .setkey = atmel_aes_setkey,
1348 .encrypt = atmel_aes_cfb8_encrypt,
1349 .decrypt = atmel_aes_cfb8_decrypt,
1353 .cra_name = "ctr(aes)",
1354 .cra_driver_name = "atmel-ctr-aes",
1355 .cra_priority = ATMEL_AES_PRIORITY,
1356 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1358 .cra_ctxsize = sizeof(struct atmel_aes_ctr_ctx),
1359 .cra_alignmask = 0xf,
1360 .cra_type = &crypto_ablkcipher_type,
1361 .cra_module = THIS_MODULE,
1362 .cra_init = atmel_aes_ctr_cra_init,
1363 .cra_exit = atmel_aes_cra_exit,
1364 .cra_u.ablkcipher = {
1365 .min_keysize = AES_MIN_KEY_SIZE,
1366 .max_keysize = AES_MAX_KEY_SIZE,
1367 .ivsize = AES_BLOCK_SIZE,
1368 .setkey = atmel_aes_setkey,
1369 .encrypt = atmel_aes_ctr_encrypt,
1370 .decrypt = atmel_aes_ctr_decrypt,
1375 static struct crypto_alg aes_cfb64_alg = {
1376 .cra_name = "cfb64(aes)",
1377 .cra_driver_name = "atmel-cfb64-aes",
1378 .cra_priority = ATMEL_AES_PRIORITY,
1379 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1380 .cra_blocksize = CFB64_BLOCK_SIZE,
1381 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1382 .cra_alignmask = 0x7,
1383 .cra_type = &crypto_ablkcipher_type,
1384 .cra_module = THIS_MODULE,
1385 .cra_init = atmel_aes_cra_init,
1386 .cra_exit = atmel_aes_cra_exit,
1387 .cra_u.ablkcipher = {
1388 .min_keysize = AES_MIN_KEY_SIZE,
1389 .max_keysize = AES_MAX_KEY_SIZE,
1390 .ivsize = AES_BLOCK_SIZE,
1391 .setkey = atmel_aes_setkey,
1392 .encrypt = atmel_aes_cfb64_encrypt,
1393 .decrypt = atmel_aes_cfb64_decrypt,
1398 /* gcm aead functions */
1400 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1401 const u32 *data, size_t datalen,
1402 const u32 *ghash_in, u32 *ghash_out,
1403 atmel_aes_fn_t resume);
1404 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd);
1405 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd);
1407 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd);
1408 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd);
1409 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd);
1410 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd);
1411 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd);
1412 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd);
1413 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd);
1415 static inline struct atmel_aes_gcm_ctx *
1416 atmel_aes_gcm_ctx_cast(struct atmel_aes_base_ctx *ctx)
1418 return container_of(ctx, struct atmel_aes_gcm_ctx, base);
1421 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1422 const u32 *data, size_t datalen,
1423 const u32 *ghash_in, u32 *ghash_out,
1424 atmel_aes_fn_t resume)
1426 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1428 dd->data = (u32 *)data;
1429 dd->datalen = datalen;
1430 ctx->ghash_in = ghash_in;
1431 ctx->ghash_out = ghash_out;
1432 ctx->ghash_resume = resume;
1434 atmel_aes_write_ctrl(dd, false, NULL);
1435 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_ghash_init);
1438 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd)
1440 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1442 /* Set the data length. */
1443 atmel_aes_write(dd, AES_AADLENR, dd->total);
1444 atmel_aes_write(dd, AES_CLENR, 0);
1446 /* If needed, overwrite the GCM Intermediate Hash Word Registers */
1448 atmel_aes_write_block(dd, AES_GHASHR(0), ctx->ghash_in);
1450 return atmel_aes_gcm_ghash_finalize(dd);
1453 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd)
1455 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1458 /* Write data into the Input Data Registers. */
1459 while (dd->datalen > 0) {
1460 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1462 dd->datalen -= AES_BLOCK_SIZE;
1464 isr = atmel_aes_read(dd, AES_ISR);
1465 if (!(isr & AES_INT_DATARDY)) {
1466 dd->resume = atmel_aes_gcm_ghash_finalize;
1467 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1468 return -EINPROGRESS;
1472 /* Read the computed hash from GHASHRx. */
1473 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash_out);
1475 return ctx->ghash_resume(dd);
1479 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd)
1481 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1482 struct aead_request *req = aead_request_cast(dd->areq);
1483 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1484 struct atmel_aes_reqctx *rctx = aead_request_ctx(req);
1485 size_t ivsize = crypto_aead_ivsize(tfm);
1486 size_t datalen, padlen;
1487 const void *iv = req->iv;
1491 atmel_aes_set_mode(dd, rctx);
1493 err = atmel_aes_hw_init(dd);
1495 return atmel_aes_complete(dd, err);
1497 if (likely(ivsize == 12)) {
1498 memcpy(ctx->j0, iv, ivsize);
1499 ctx->j0[3] = cpu_to_be32(1);
1500 return atmel_aes_gcm_process(dd);
1503 padlen = atmel_aes_padlen(ivsize, AES_BLOCK_SIZE);
1504 datalen = ivsize + padlen + AES_BLOCK_SIZE;
1505 if (datalen > dd->buflen)
1506 return atmel_aes_complete(dd, -EINVAL);
1508 memcpy(data, iv, ivsize);
1509 memset(data + ivsize, 0, padlen + sizeof(u64));
1510 ((u64 *)(data + datalen))[-1] = cpu_to_be64(ivsize * 8);
1512 return atmel_aes_gcm_ghash(dd, (const u32 *)data, datalen,
1513 NULL, ctx->j0, atmel_aes_gcm_process);
1516 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd)
1518 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1519 struct aead_request *req = aead_request_cast(dd->areq);
1520 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1521 bool enc = atmel_aes_is_encrypt(dd);
1524 /* Compute text length. */
1525 authsize = crypto_aead_authsize(tfm);
1526 ctx->textlen = req->cryptlen - (enc ? 0 : authsize);
1529 * According to tcrypt test suite, the GCM Automatic Tag Generation
1530 * fails when both the message and its associated data are empty.
1532 if (likely(req->assoclen != 0 || ctx->textlen != 0))
1533 dd->flags |= AES_FLAGS_GTAGEN;
1535 atmel_aes_write_ctrl(dd, false, NULL);
1536 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_length);
1539 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd)
1541 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1542 struct aead_request *req = aead_request_cast(dd->areq);
1543 u32 j0_lsw, *j0 = ctx->j0;
1546 /* Write incr32(J0) into IV. */
1548 j0[3] = cpu_to_be32(be32_to_cpu(j0[3]) + 1);
1549 atmel_aes_write_block(dd, AES_IVR(0), j0);
1552 /* Set aad and text lengths. */
1553 atmel_aes_write(dd, AES_AADLENR, req->assoclen);
1554 atmel_aes_write(dd, AES_CLENR, ctx->textlen);
1556 /* Check whether AAD are present. */
1557 if (unlikely(req->assoclen == 0)) {
1559 return atmel_aes_gcm_data(dd);
1562 /* Copy assoc data and add padding. */
1563 padlen = atmel_aes_padlen(req->assoclen, AES_BLOCK_SIZE);
1564 if (unlikely(req->assoclen + padlen > dd->buflen))
1565 return atmel_aes_complete(dd, -EINVAL);
1566 sg_copy_to_buffer(req->src, sg_nents(req->src), dd->buf, req->assoclen);
1568 /* Write assoc data into the Input Data register. */
1569 dd->data = (u32 *)dd->buf;
1570 dd->datalen = req->assoclen + padlen;
1571 return atmel_aes_gcm_data(dd);
1574 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd)
1576 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1577 struct aead_request *req = aead_request_cast(dd->areq);
1578 bool use_dma = (ctx->textlen >= ATMEL_AES_DMA_THRESHOLD);
1579 struct scatterlist *src, *dst;
1582 /* Write AAD first. */
1583 while (dd->datalen > 0) {
1584 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1586 dd->datalen -= AES_BLOCK_SIZE;
1588 isr = atmel_aes_read(dd, AES_ISR);
1589 if (!(isr & AES_INT_DATARDY)) {
1590 dd->resume = atmel_aes_gcm_data;
1591 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1592 return -EINPROGRESS;
1597 if (unlikely(ctx->textlen == 0))
1598 return atmel_aes_gcm_tag_init(dd);
1600 /* Prepare src and dst scatter lists to transfer cipher/plain texts */
1601 src = scatterwalk_ffwd(ctx->src, req->src, req->assoclen);
1602 dst = ((req->src == req->dst) ? src :
1603 scatterwalk_ffwd(ctx->dst, req->dst, req->assoclen));
1606 /* Update the Mode Register for DMA transfers. */
1607 mr = atmel_aes_read(dd, AES_MR);
1608 mr &= ~(AES_MR_SMOD_MASK | AES_MR_DUALBUFF);
1609 mr |= AES_MR_SMOD_IDATAR0;
1610 if (dd->caps.has_dualbuff)
1611 mr |= AES_MR_DUALBUFF;
1612 atmel_aes_write(dd, AES_MR, mr);
1614 return atmel_aes_dma_start(dd, src, dst, ctx->textlen,
1615 atmel_aes_gcm_tag_init);
1618 return atmel_aes_cpu_start(dd, src, dst, ctx->textlen,
1619 atmel_aes_gcm_tag_init);
1622 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd)
1624 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1625 struct aead_request *req = aead_request_cast(dd->areq);
1626 u64 *data = dd->buf;
1628 if (likely(dd->flags & AES_FLAGS_GTAGEN)) {
1629 if (!(atmel_aes_read(dd, AES_ISR) & AES_INT_TAGRDY)) {
1630 dd->resume = atmel_aes_gcm_tag_init;
1631 atmel_aes_write(dd, AES_IER, AES_INT_TAGRDY);
1632 return -EINPROGRESS;
1635 return atmel_aes_gcm_finalize(dd);
1638 /* Read the GCM Intermediate Hash Word Registers. */
1639 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash);
1641 data[0] = cpu_to_be64(req->assoclen * 8);
1642 data[1] = cpu_to_be64(ctx->textlen * 8);
1644 return atmel_aes_gcm_ghash(dd, (const u32 *)data, AES_BLOCK_SIZE,
1645 ctx->ghash, ctx->ghash, atmel_aes_gcm_tag);
1648 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd)
1650 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1651 unsigned long flags;
1654 * Change mode to CTR to complete the tag generation.
1655 * Use J0 as Initialization Vector.
1658 dd->flags &= ~(AES_FLAGS_OPMODE_MASK | AES_FLAGS_GTAGEN);
1659 dd->flags |= AES_FLAGS_CTR;
1660 atmel_aes_write_ctrl(dd, false, ctx->j0);
1663 atmel_aes_write_block(dd, AES_IDATAR(0), ctx->ghash);
1664 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_finalize);
1667 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd)
1669 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1670 struct aead_request *req = aead_request_cast(dd->areq);
1671 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1672 bool enc = atmel_aes_is_encrypt(dd);
1673 u32 offset, authsize, itag[4], *otag = ctx->tag;
1676 /* Read the computed tag. */
1677 if (likely(dd->flags & AES_FLAGS_GTAGEN))
1678 atmel_aes_read_block(dd, AES_TAGR(0), ctx->tag);
1680 atmel_aes_read_block(dd, AES_ODATAR(0), ctx->tag);
1682 offset = req->assoclen + ctx->textlen;
1683 authsize = crypto_aead_authsize(tfm);
1685 scatterwalk_map_and_copy(otag, req->dst, offset, authsize, 1);
1688 scatterwalk_map_and_copy(itag, req->src, offset, authsize, 0);
1689 err = crypto_memneq(itag, otag, authsize) ? -EBADMSG : 0;
1692 return atmel_aes_complete(dd, err);
1695 static int atmel_aes_gcm_crypt(struct aead_request *req,
1698 struct atmel_aes_base_ctx *ctx;
1699 struct atmel_aes_reqctx *rctx;
1700 struct atmel_aes_dev *dd;
1702 ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
1703 ctx->block_size = AES_BLOCK_SIZE;
1705 dd = atmel_aes_find_dev(ctx);
1709 rctx = aead_request_ctx(req);
1710 rctx->mode = AES_FLAGS_GCM | mode;
1712 return atmel_aes_handle_queue(dd, &req->base);
1715 static int atmel_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
1716 unsigned int keylen)
1718 struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm);
1720 if (keylen != AES_KEYSIZE_256 &&
1721 keylen != AES_KEYSIZE_192 &&
1722 keylen != AES_KEYSIZE_128) {
1723 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1727 memcpy(ctx->key, key, keylen);
1728 ctx->keylen = keylen;
1733 static int atmel_aes_gcm_setauthsize(struct crypto_aead *tfm,
1734 unsigned int authsize)
1736 /* Same as crypto_gcm_authsize() from crypto/gcm.c */
1753 static int atmel_aes_gcm_encrypt(struct aead_request *req)
1755 return atmel_aes_gcm_crypt(req, AES_FLAGS_ENCRYPT);
1758 static int atmel_aes_gcm_decrypt(struct aead_request *req)
1760 return atmel_aes_gcm_crypt(req, 0);
1763 static int atmel_aes_gcm_init(struct crypto_aead *tfm)
1765 struct atmel_aes_gcm_ctx *ctx = crypto_aead_ctx(tfm);
1767 crypto_aead_set_reqsize(tfm, sizeof(struct atmel_aes_reqctx));
1768 ctx->base.start = atmel_aes_gcm_start;
1773 static void atmel_aes_gcm_exit(struct crypto_aead *tfm)
1778 static struct aead_alg aes_gcm_alg = {
1779 .setkey = atmel_aes_gcm_setkey,
1780 .setauthsize = atmel_aes_gcm_setauthsize,
1781 .encrypt = atmel_aes_gcm_encrypt,
1782 .decrypt = atmel_aes_gcm_decrypt,
1783 .init = atmel_aes_gcm_init,
1784 .exit = atmel_aes_gcm_exit,
1786 .maxauthsize = AES_BLOCK_SIZE,
1789 .cra_name = "gcm(aes)",
1790 .cra_driver_name = "atmel-gcm-aes",
1791 .cra_priority = ATMEL_AES_PRIORITY,
1792 .cra_flags = CRYPTO_ALG_ASYNC,
1794 .cra_ctxsize = sizeof(struct atmel_aes_gcm_ctx),
1795 .cra_alignmask = 0xf,
1796 .cra_module = THIS_MODULE,
1803 static inline struct atmel_aes_xts_ctx *
1804 atmel_aes_xts_ctx_cast(struct atmel_aes_base_ctx *ctx)
1806 return container_of(ctx, struct atmel_aes_xts_ctx, base);
1809 static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd);
1811 static int atmel_aes_xts_start(struct atmel_aes_dev *dd)
1813 struct atmel_aes_xts_ctx *ctx = atmel_aes_xts_ctx_cast(dd->ctx);
1814 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1815 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
1816 unsigned long flags;
1819 atmel_aes_set_mode(dd, rctx);
1821 err = atmel_aes_hw_init(dd);
1823 return atmel_aes_complete(dd, err);
1825 /* Compute the tweak value from req->info with ecb(aes). */
1827 dd->flags &= ~AES_FLAGS_MODE_MASK;
1828 dd->flags |= (AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
1829 atmel_aes_write_ctrl_key(dd, false, NULL,
1830 ctx->key2, ctx->base.keylen);
1833 atmel_aes_write_block(dd, AES_IDATAR(0), req->info);
1834 return atmel_aes_wait_for_data_ready(dd, atmel_aes_xts_process_data);
1837 static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd)
1839 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1840 bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD);
1841 u32 tweak[AES_BLOCK_SIZE / sizeof(u32)];
1842 static const u32 one[AES_BLOCK_SIZE / sizeof(u32)] = {cpu_to_le32(1), };
1843 u8 *tweak_bytes = (u8 *)tweak;
1846 /* Read the computed ciphered tweak value. */
1847 atmel_aes_read_block(dd, AES_ODATAR(0), tweak);
1850 * the order of the ciphered tweak bytes need to be reversed before
1851 * writing them into the ODATARx registers.
1853 for (i = 0; i < AES_BLOCK_SIZE/2; ++i) {
1854 u8 tmp = tweak_bytes[AES_BLOCK_SIZE - 1 - i];
1856 tweak_bytes[AES_BLOCK_SIZE - 1 - i] = tweak_bytes[i];
1857 tweak_bytes[i] = tmp;
1860 /* Process the data. */
1861 atmel_aes_write_ctrl(dd, use_dma, NULL);
1862 atmel_aes_write_block(dd, AES_TWR(0), tweak);
1863 atmel_aes_write_block(dd, AES_ALPHAR(0), one);
1865 return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
1866 atmel_aes_transfer_complete);
1868 return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
1869 atmel_aes_transfer_complete);
1872 static int atmel_aes_xts_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1873 unsigned int keylen)
1875 struct atmel_aes_xts_ctx *ctx = crypto_ablkcipher_ctx(tfm);
1878 err = xts_check_key(crypto_ablkcipher_tfm(tfm), key, keylen);
1882 memcpy(ctx->base.key, key, keylen/2);
1883 memcpy(ctx->key2, key + keylen/2, keylen/2);
1884 ctx->base.keylen = keylen/2;
1889 static int atmel_aes_xts_encrypt(struct ablkcipher_request *req)
1891 return atmel_aes_crypt(req, AES_FLAGS_XTS | AES_FLAGS_ENCRYPT);
1894 static int atmel_aes_xts_decrypt(struct ablkcipher_request *req)
1896 return atmel_aes_crypt(req, AES_FLAGS_XTS);
1899 static int atmel_aes_xts_cra_init(struct crypto_tfm *tfm)
1901 struct atmel_aes_xts_ctx *ctx = crypto_tfm_ctx(tfm);
1903 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1904 ctx->base.start = atmel_aes_xts_start;
1909 static struct crypto_alg aes_xts_alg = {
1910 .cra_name = "xts(aes)",
1911 .cra_driver_name = "atmel-xts-aes",
1912 .cra_priority = ATMEL_AES_PRIORITY,
1913 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1914 .cra_blocksize = AES_BLOCK_SIZE,
1915 .cra_ctxsize = sizeof(struct atmel_aes_xts_ctx),
1916 .cra_alignmask = 0xf,
1917 .cra_type = &crypto_ablkcipher_type,
1918 .cra_module = THIS_MODULE,
1919 .cra_init = atmel_aes_xts_cra_init,
1920 .cra_exit = atmel_aes_cra_exit,
1921 .cra_u.ablkcipher = {
1922 .min_keysize = 2 * AES_MIN_KEY_SIZE,
1923 .max_keysize = 2 * AES_MAX_KEY_SIZE,
1924 .ivsize = AES_BLOCK_SIZE,
1925 .setkey = atmel_aes_xts_setkey,
1926 .encrypt = atmel_aes_xts_encrypt,
1927 .decrypt = atmel_aes_xts_decrypt,
1932 /* Probe functions */
1934 static int atmel_aes_buff_init(struct atmel_aes_dev *dd)
1936 dd->buf = (void *)__get_free_pages(GFP_KERNEL, ATMEL_AES_BUFFER_ORDER);
1937 dd->buflen = ATMEL_AES_BUFFER_SIZE;
1938 dd->buflen &= ~(AES_BLOCK_SIZE - 1);
1941 dev_err(dd->dev, "unable to alloc pages.\n");
1948 static void atmel_aes_buff_cleanup(struct atmel_aes_dev *dd)
1950 free_page((unsigned long)dd->buf);
1953 static bool atmel_aes_filter(struct dma_chan *chan, void *slave)
1955 struct at_dma_slave *sl = slave;
1957 if (sl && sl->dma_dev == chan->device->dev) {
1965 static int atmel_aes_dma_init(struct atmel_aes_dev *dd,
1966 struct crypto_platform_data *pdata)
1968 struct at_dma_slave *slave;
1970 dma_cap_mask_t mask;
1973 dma_cap_set(DMA_SLAVE, mask);
1975 /* Try to grab 2 DMA channels */
1976 slave = &pdata->dma_slave->rxdata;
1977 dd->src.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
1978 slave, dd->dev, "tx");
1982 slave = &pdata->dma_slave->txdata;
1983 dd->dst.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
1984 slave, dd->dev, "rx");
1991 dma_release_channel(dd->src.chan);
1993 dev_warn(dd->dev, "no DMA channel available\n");
1997 static void atmel_aes_dma_cleanup(struct atmel_aes_dev *dd)
1999 dma_release_channel(dd->dst.chan);
2000 dma_release_channel(dd->src.chan);
2003 static void atmel_aes_queue_task(unsigned long data)
2005 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
2007 atmel_aes_handle_queue(dd, NULL);
2010 static void atmel_aes_done_task(unsigned long data)
2012 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
2014 dd->is_async = true;
2015 (void)dd->resume(dd);
2018 static irqreturn_t atmel_aes_irq(int irq, void *dev_id)
2020 struct atmel_aes_dev *aes_dd = dev_id;
2023 reg = atmel_aes_read(aes_dd, AES_ISR);
2024 if (reg & atmel_aes_read(aes_dd, AES_IMR)) {
2025 atmel_aes_write(aes_dd, AES_IDR, reg);
2026 if (AES_FLAGS_BUSY & aes_dd->flags)
2027 tasklet_schedule(&aes_dd->done_task);
2029 dev_warn(aes_dd->dev, "AES interrupt when no active requests.\n");
2036 static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd)
2040 if (dd->caps.has_xts)
2041 crypto_unregister_alg(&aes_xts_alg);
2043 if (dd->caps.has_gcm)
2044 crypto_unregister_aead(&aes_gcm_alg);
2046 if (dd->caps.has_cfb64)
2047 crypto_unregister_alg(&aes_cfb64_alg);
2049 for (i = 0; i < ARRAY_SIZE(aes_algs); i++)
2050 crypto_unregister_alg(&aes_algs[i]);
2053 static int atmel_aes_register_algs(struct atmel_aes_dev *dd)
2057 for (i = 0; i < ARRAY_SIZE(aes_algs); i++) {
2058 err = crypto_register_alg(&aes_algs[i]);
2063 if (dd->caps.has_cfb64) {
2064 err = crypto_register_alg(&aes_cfb64_alg);
2066 goto err_aes_cfb64_alg;
2069 if (dd->caps.has_gcm) {
2070 err = crypto_register_aead(&aes_gcm_alg);
2072 goto err_aes_gcm_alg;
2075 if (dd->caps.has_xts) {
2076 err = crypto_register_alg(&aes_xts_alg);
2078 goto err_aes_xts_alg;
2084 crypto_unregister_aead(&aes_gcm_alg);
2086 crypto_unregister_alg(&aes_cfb64_alg);
2088 i = ARRAY_SIZE(aes_algs);
2090 for (j = 0; j < i; j++)
2091 crypto_unregister_alg(&aes_algs[j]);
2096 static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
2098 dd->caps.has_dualbuff = 0;
2099 dd->caps.has_cfb64 = 0;
2100 dd->caps.has_ctr32 = 0;
2101 dd->caps.has_gcm = 0;
2102 dd->caps.has_xts = 0;
2103 dd->caps.max_burst_size = 1;
2105 /* keep only major version number */
2106 switch (dd->hw_version & 0xff0) {
2108 dd->caps.has_dualbuff = 1;
2109 dd->caps.has_cfb64 = 1;
2110 dd->caps.has_ctr32 = 1;
2111 dd->caps.has_gcm = 1;
2112 dd->caps.has_xts = 1;
2113 dd->caps.max_burst_size = 4;
2116 dd->caps.has_dualbuff = 1;
2117 dd->caps.has_cfb64 = 1;
2118 dd->caps.has_ctr32 = 1;
2119 dd->caps.has_gcm = 1;
2120 dd->caps.max_burst_size = 4;
2123 dd->caps.has_dualbuff = 1;
2124 dd->caps.has_cfb64 = 1;
2125 dd->caps.max_burst_size = 4;
2131 "Unmanaged aes version, set minimum capabilities\n");
2136 #if defined(CONFIG_OF)
2137 static const struct of_device_id atmel_aes_dt_ids[] = {
2138 { .compatible = "atmel,at91sam9g46-aes" },
2141 MODULE_DEVICE_TABLE(of, atmel_aes_dt_ids);
2143 static struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
2145 struct device_node *np = pdev->dev.of_node;
2146 struct crypto_platform_data *pdata;
2149 dev_err(&pdev->dev, "device node not found\n");
2150 return ERR_PTR(-EINVAL);
2153 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
2155 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
2156 return ERR_PTR(-ENOMEM);
2159 pdata->dma_slave = devm_kzalloc(&pdev->dev,
2160 sizeof(*(pdata->dma_slave)),
2162 if (!pdata->dma_slave) {
2163 dev_err(&pdev->dev, "could not allocate memory for dma_slave\n");
2164 devm_kfree(&pdev->dev, pdata);
2165 return ERR_PTR(-ENOMEM);
2171 static inline struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
2173 return ERR_PTR(-EINVAL);
2177 static int atmel_aes_probe(struct platform_device *pdev)
2179 struct atmel_aes_dev *aes_dd;
2180 struct crypto_platform_data *pdata;
2181 struct device *dev = &pdev->dev;
2182 struct resource *aes_res;
2185 pdata = pdev->dev.platform_data;
2187 pdata = atmel_aes_of_init(pdev);
2188 if (IS_ERR(pdata)) {
2189 err = PTR_ERR(pdata);
2194 if (!pdata->dma_slave) {
2199 aes_dd = devm_kzalloc(&pdev->dev, sizeof(*aes_dd), GFP_KERNEL);
2200 if (aes_dd == NULL) {
2201 dev_err(dev, "unable to alloc data struct.\n");
2208 platform_set_drvdata(pdev, aes_dd);
2210 INIT_LIST_HEAD(&aes_dd->list);
2211 spin_lock_init(&aes_dd->lock);
2213 tasklet_init(&aes_dd->done_task, atmel_aes_done_task,
2214 (unsigned long)aes_dd);
2215 tasklet_init(&aes_dd->queue_task, atmel_aes_queue_task,
2216 (unsigned long)aes_dd);
2218 crypto_init_queue(&aes_dd->queue, ATMEL_AES_QUEUE_LENGTH);
2222 /* Get the base address */
2223 aes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2225 dev_err(dev, "no MEM resource info\n");
2229 aes_dd->phys_base = aes_res->start;
2232 aes_dd->irq = platform_get_irq(pdev, 0);
2233 if (aes_dd->irq < 0) {
2234 dev_err(dev, "no IRQ resource info\n");
2239 err = devm_request_irq(&pdev->dev, aes_dd->irq, atmel_aes_irq,
2240 IRQF_SHARED, "atmel-aes", aes_dd);
2242 dev_err(dev, "unable to request aes irq.\n");
2246 /* Initializing the clock */
2247 aes_dd->iclk = devm_clk_get(&pdev->dev, "aes_clk");
2248 if (IS_ERR(aes_dd->iclk)) {
2249 dev_err(dev, "clock initialization failed.\n");
2250 err = PTR_ERR(aes_dd->iclk);
2254 aes_dd->io_base = devm_ioremap_resource(&pdev->dev, aes_res);
2255 if (IS_ERR(aes_dd->io_base)) {
2256 dev_err(dev, "can't ioremap\n");
2257 err = PTR_ERR(aes_dd->io_base);
2261 err = clk_prepare(aes_dd->iclk);
2265 err = atmel_aes_hw_version_init(aes_dd);
2267 goto iclk_unprepare;
2269 atmel_aes_get_cap(aes_dd);
2271 err = atmel_aes_buff_init(aes_dd);
2275 err = atmel_aes_dma_init(aes_dd, pdata);
2279 spin_lock(&atmel_aes.lock);
2280 list_add_tail(&aes_dd->list, &atmel_aes.dev_list);
2281 spin_unlock(&atmel_aes.lock);
2283 err = atmel_aes_register_algs(aes_dd);
2287 dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n",
2288 dma_chan_name(aes_dd->src.chan),
2289 dma_chan_name(aes_dd->dst.chan));
2294 spin_lock(&atmel_aes.lock);
2295 list_del(&aes_dd->list);
2296 spin_unlock(&atmel_aes.lock);
2297 atmel_aes_dma_cleanup(aes_dd);
2299 atmel_aes_buff_cleanup(aes_dd);
2302 clk_unprepare(aes_dd->iclk);
2304 tasklet_kill(&aes_dd->done_task);
2305 tasklet_kill(&aes_dd->queue_task);
2307 dev_err(dev, "initialization failed.\n");
2312 static int atmel_aes_remove(struct platform_device *pdev)
2314 struct atmel_aes_dev *aes_dd;
2316 aes_dd = platform_get_drvdata(pdev);
2319 spin_lock(&atmel_aes.lock);
2320 list_del(&aes_dd->list);
2321 spin_unlock(&atmel_aes.lock);
2323 atmel_aes_unregister_algs(aes_dd);
2325 tasklet_kill(&aes_dd->done_task);
2326 tasklet_kill(&aes_dd->queue_task);
2328 atmel_aes_dma_cleanup(aes_dd);
2329 atmel_aes_buff_cleanup(aes_dd);
2331 clk_unprepare(aes_dd->iclk);
2336 static struct platform_driver atmel_aes_driver = {
2337 .probe = atmel_aes_probe,
2338 .remove = atmel_aes_remove,
2340 .name = "atmel_aes",
2341 .of_match_table = of_match_ptr(atmel_aes_dt_ids),
2345 module_platform_driver(atmel_aes_driver);
2347 MODULE_DESCRIPTION("Atmel AES hw acceleration support.");
2348 MODULE_LICENSE("GPL v2");
2349 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");