4 * Support for ATMEL AES HW acceleration.
6 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
7 * Author: Nicolas Royer <nicolas@eukrea.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
13 * Some ideas are from omap-aes.c driver.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
23 #include <linux/hw_random.h>
24 #include <linux/platform_device.h>
26 #include <linux/device.h>
27 #include <linux/init.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/scatterlist.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/of_device.h>
34 #include <linux/delay.h>
35 #include <linux/crypto.h>
36 #include <crypto/scatterwalk.h>
37 #include <crypto/algapi.h>
38 #include <crypto/aes.h>
39 #include <crypto/internal/aead.h>
40 #include <linux/platform_data/crypto-atmel.h>
41 #include <dt-bindings/dma/at91.h>
42 #include "atmel-aes-regs.h"
44 #define ATMEL_AES_PRIORITY 300
46 #define ATMEL_AES_BUFFER_ORDER 2
47 #define ATMEL_AES_BUFFER_SIZE (PAGE_SIZE << ATMEL_AES_BUFFER_ORDER)
49 #define CFB8_BLOCK_SIZE 1
50 #define CFB16_BLOCK_SIZE 2
51 #define CFB32_BLOCK_SIZE 4
52 #define CFB64_BLOCK_SIZE 8
54 #define SIZE_IN_WORDS(x) ((x) >> 2)
57 /* Reserve bits [18:16] [14:12] [1:0] for mode (same as for AES_MR) */
58 #define AES_FLAGS_ENCRYPT AES_MR_CYPHER_ENC
59 #define AES_FLAGS_GTAGEN AES_MR_GTAGEN
60 #define AES_FLAGS_OPMODE_MASK (AES_MR_OPMOD_MASK | AES_MR_CFBS_MASK)
61 #define AES_FLAGS_ECB AES_MR_OPMOD_ECB
62 #define AES_FLAGS_CBC AES_MR_OPMOD_CBC
63 #define AES_FLAGS_OFB AES_MR_OPMOD_OFB
64 #define AES_FLAGS_CFB128 (AES_MR_OPMOD_CFB | AES_MR_CFBS_128b)
65 #define AES_FLAGS_CFB64 (AES_MR_OPMOD_CFB | AES_MR_CFBS_64b)
66 #define AES_FLAGS_CFB32 (AES_MR_OPMOD_CFB | AES_MR_CFBS_32b)
67 #define AES_FLAGS_CFB16 (AES_MR_OPMOD_CFB | AES_MR_CFBS_16b)
68 #define AES_FLAGS_CFB8 (AES_MR_OPMOD_CFB | AES_MR_CFBS_8b)
69 #define AES_FLAGS_CTR AES_MR_OPMOD_CTR
70 #define AES_FLAGS_GCM AES_MR_OPMOD_GCM
72 #define AES_FLAGS_MODE_MASK (AES_FLAGS_OPMODE_MASK | \
76 #define AES_FLAGS_INIT BIT(2)
77 #define AES_FLAGS_BUSY BIT(3)
78 #define AES_FLAGS_DUMP_REG BIT(4)
80 #define AES_FLAGS_PERSISTENT (AES_FLAGS_INIT | AES_FLAGS_BUSY)
82 #define ATMEL_AES_QUEUE_LENGTH 50
84 #define ATMEL_AES_DMA_THRESHOLD 256
87 struct atmel_aes_caps {
98 typedef int (*atmel_aes_fn_t)(struct atmel_aes_dev *);
101 struct atmel_aes_base_ctx {
102 struct atmel_aes_dev *dd;
103 atmel_aes_fn_t start;
105 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
109 struct atmel_aes_ctx {
110 struct atmel_aes_base_ctx base;
113 struct atmel_aes_ctr_ctx {
114 struct atmel_aes_base_ctx base;
116 u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
118 struct scatterlist src[2];
119 struct scatterlist dst[2];
122 struct atmel_aes_gcm_ctx {
123 struct atmel_aes_base_ctx base;
125 struct scatterlist src[2];
126 struct scatterlist dst[2];
128 u32 j0[AES_BLOCK_SIZE / sizeof(u32)];
129 u32 tag[AES_BLOCK_SIZE / sizeof(u32)];
130 u32 ghash[AES_BLOCK_SIZE / sizeof(u32)];
135 atmel_aes_fn_t ghash_resume;
138 struct atmel_aes_reqctx {
142 struct atmel_aes_dma {
143 struct dma_chan *chan;
144 struct scatterlist *sg;
146 unsigned int remainder;
150 struct atmel_aes_dev {
151 struct list_head list;
152 unsigned long phys_base;
153 void __iomem *io_base;
155 struct crypto_async_request *areq;
156 struct atmel_aes_base_ctx *ctx;
159 atmel_aes_fn_t resume;
160 atmel_aes_fn_t cpu_transfer_complete;
169 struct crypto_queue queue;
171 struct tasklet_struct done_task;
172 struct tasklet_struct queue_task;
178 struct atmel_aes_dma src;
179 struct atmel_aes_dma dst;
183 struct scatterlist aligned_sg;
184 struct scatterlist *real_dst;
186 struct atmel_aes_caps caps;
191 struct atmel_aes_drv {
192 struct list_head dev_list;
196 static struct atmel_aes_drv atmel_aes = {
197 .dev_list = LIST_HEAD_INIT(atmel_aes.dev_list),
198 .lock = __SPIN_LOCK_UNLOCKED(atmel_aes.lock),
202 static const char *atmel_aes_reg_name(u32 offset, char *tmp, size_t sz)
231 snprintf(tmp, sz, "KEYWR[%u]", (offset - AES_KEYWR(0)) >> 2);
238 snprintf(tmp, sz, "IDATAR[%u]", (offset - AES_IDATAR(0)) >> 2);
245 snprintf(tmp, sz, "ODATAR[%u]", (offset - AES_ODATAR(0)) >> 2);
252 snprintf(tmp, sz, "IVR[%u]", (offset - AES_IVR(0)) >> 2);
265 snprintf(tmp, sz, "GHASHR[%u]", (offset - AES_GHASHR(0)) >> 2);
272 snprintf(tmp, sz, "TAGR[%u]", (offset - AES_TAGR(0)) >> 2);
282 snprintf(tmp, sz, "GCMHR[%u]", (offset - AES_GCMHR(0)) >> 2);
285 snprintf(tmp, sz, "0x%02x", offset);
291 #endif /* VERBOSE_DEBUG */
293 /* Shared functions */
295 static inline u32 atmel_aes_read(struct atmel_aes_dev *dd, u32 offset)
297 u32 value = readl_relaxed(dd->io_base + offset);
300 if (dd->flags & AES_FLAGS_DUMP_REG) {
303 dev_vdbg(dd->dev, "read 0x%08x from %s\n", value,
304 atmel_aes_reg_name(offset, tmp, sizeof(tmp)));
306 #endif /* VERBOSE_DEBUG */
311 static inline void atmel_aes_write(struct atmel_aes_dev *dd,
312 u32 offset, u32 value)
315 if (dd->flags & AES_FLAGS_DUMP_REG) {
318 dev_vdbg(dd->dev, "write 0x%08x into %s\n", value,
319 atmel_aes_reg_name(offset, tmp));
321 #endif /* VERBOSE_DEBUG */
323 writel_relaxed(value, dd->io_base + offset);
326 static void atmel_aes_read_n(struct atmel_aes_dev *dd, u32 offset,
327 u32 *value, int count)
329 for (; count--; value++, offset += 4)
330 *value = atmel_aes_read(dd, offset);
333 static void atmel_aes_write_n(struct atmel_aes_dev *dd, u32 offset,
334 const u32 *value, int count)
336 for (; count--; value++, offset += 4)
337 atmel_aes_write(dd, offset, *value);
340 static inline void atmel_aes_read_block(struct atmel_aes_dev *dd, u32 offset,
343 atmel_aes_read_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
346 static inline void atmel_aes_write_block(struct atmel_aes_dev *dd, u32 offset,
349 atmel_aes_write_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
352 static inline int atmel_aes_wait_for_data_ready(struct atmel_aes_dev *dd,
353 atmel_aes_fn_t resume)
355 u32 isr = atmel_aes_read(dd, AES_ISR);
357 if (unlikely(isr & AES_INT_DATARDY))
361 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
365 static inline size_t atmel_aes_padlen(size_t len, size_t block_size)
367 len &= block_size - 1;
368 return len ? block_size - len : 0;
371 static inline struct aead_request *
372 aead_request_cast(struct crypto_async_request *req)
374 return container_of(req, struct aead_request, base);
377 static struct atmel_aes_dev *atmel_aes_find_dev(struct atmel_aes_base_ctx *ctx)
379 struct atmel_aes_dev *aes_dd = NULL;
380 struct atmel_aes_dev *tmp;
382 spin_lock_bh(&atmel_aes.lock);
384 list_for_each_entry(tmp, &atmel_aes.dev_list, list) {
393 spin_unlock_bh(&atmel_aes.lock);
398 static int atmel_aes_hw_init(struct atmel_aes_dev *dd)
402 err = clk_prepare_enable(dd->iclk);
406 if (!(dd->flags & AES_FLAGS_INIT)) {
407 atmel_aes_write(dd, AES_CR, AES_CR_SWRST);
408 atmel_aes_write(dd, AES_MR, 0xE << AES_MR_CKEY_OFFSET);
409 dd->flags |= AES_FLAGS_INIT;
415 static inline unsigned int atmel_aes_get_version(struct atmel_aes_dev *dd)
417 return atmel_aes_read(dd, AES_HW_VERSION) & 0x00000fff;
420 static int atmel_aes_hw_version_init(struct atmel_aes_dev *dd)
424 err = atmel_aes_hw_init(dd);
428 dd->hw_version = atmel_aes_get_version(dd);
430 dev_info(dd->dev, "version: 0x%x\n", dd->hw_version);
432 clk_disable_unprepare(dd->iclk);
436 static inline void atmel_aes_set_mode(struct atmel_aes_dev *dd,
437 const struct atmel_aes_reqctx *rctx)
439 /* Clear all but persistent flags and set request flags. */
440 dd->flags = (dd->flags & AES_FLAGS_PERSISTENT) | rctx->mode;
443 static inline bool atmel_aes_is_encrypt(const struct atmel_aes_dev *dd)
445 return (dd->flags & AES_FLAGS_ENCRYPT);
448 static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err)
450 clk_disable_unprepare(dd->iclk);
451 dd->flags &= ~AES_FLAGS_BUSY;
454 dd->areq->complete(dd->areq, err);
456 tasklet_schedule(&dd->queue_task);
461 static void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
466 /* MR register must be set before IV registers */
467 if (dd->ctx->keylen == AES_KEYSIZE_128)
468 valmr |= AES_MR_KEYSIZE_128;
469 else if (dd->ctx->keylen == AES_KEYSIZE_192)
470 valmr |= AES_MR_KEYSIZE_192;
472 valmr |= AES_MR_KEYSIZE_256;
474 valmr |= dd->flags & AES_FLAGS_MODE_MASK;
477 valmr |= AES_MR_SMOD_IDATAR0;
478 if (dd->caps.has_dualbuff)
479 valmr |= AES_MR_DUALBUFF;
481 valmr |= AES_MR_SMOD_AUTO;
484 atmel_aes_write(dd, AES_MR, valmr);
486 atmel_aes_write_n(dd, AES_KEYWR(0), dd->ctx->key,
487 SIZE_IN_WORDS(dd->ctx->keylen));
489 if (iv && (valmr & AES_MR_OPMOD_MASK) != AES_MR_OPMOD_ECB)
490 atmel_aes_write_block(dd, AES_IVR(0), iv);
496 static int atmel_aes_cpu_transfer(struct atmel_aes_dev *dd)
502 atmel_aes_read_block(dd, AES_ODATAR(0), dd->data);
504 dd->datalen -= AES_BLOCK_SIZE;
506 if (dd->datalen < AES_BLOCK_SIZE)
509 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
511 isr = atmel_aes_read(dd, AES_ISR);
512 if (!(isr & AES_INT_DATARDY)) {
513 dd->resume = atmel_aes_cpu_transfer;
514 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
519 if (!sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
524 return atmel_aes_complete(dd, err);
526 return dd->cpu_transfer_complete(dd);
529 static int atmel_aes_cpu_start(struct atmel_aes_dev *dd,
530 struct scatterlist *src,
531 struct scatterlist *dst,
533 atmel_aes_fn_t resume)
535 size_t padlen = atmel_aes_padlen(len, AES_BLOCK_SIZE);
537 if (unlikely(len == 0))
540 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
544 dd->cpu_transfer_complete = resume;
545 dd->datalen = len + padlen;
546 dd->data = (u32 *)dd->buf;
547 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
548 return atmel_aes_wait_for_data_ready(dd, atmel_aes_cpu_transfer);
554 static void atmel_aes_dma_callback(void *data);
556 static bool atmel_aes_check_aligned(struct atmel_aes_dev *dd,
557 struct scatterlist *sg,
559 struct atmel_aes_dma *dma)
563 if (!IS_ALIGNED(len, dd->ctx->block_size))
566 for (nents = 0; sg; sg = sg_next(sg), ++nents) {
567 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
570 if (len <= sg->length) {
571 if (!IS_ALIGNED(len, dd->ctx->block_size))
574 dma->nents = nents+1;
575 dma->remainder = sg->length - len;
580 if (!IS_ALIGNED(sg->length, dd->ctx->block_size))
589 static inline void atmel_aes_restore_sg(const struct atmel_aes_dma *dma)
591 struct scatterlist *sg = dma->sg;
592 int nents = dma->nents;
597 while (--nents > 0 && sg)
603 sg->length += dma->remainder;
606 static int atmel_aes_map(struct atmel_aes_dev *dd,
607 struct scatterlist *src,
608 struct scatterlist *dst,
611 bool src_aligned, dst_aligned;
619 src_aligned = atmel_aes_check_aligned(dd, src, len, &dd->src);
621 dst_aligned = src_aligned;
623 dst_aligned = atmel_aes_check_aligned(dd, dst, len, &dd->dst);
624 if (!src_aligned || !dst_aligned) {
625 padlen = atmel_aes_padlen(len, dd->ctx->block_size);
627 if (dd->buflen < len + padlen)
631 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
632 dd->src.sg = &dd->aligned_sg;
634 dd->src.remainder = 0;
638 dd->dst.sg = &dd->aligned_sg;
640 dd->dst.remainder = 0;
643 sg_init_table(&dd->aligned_sg, 1);
644 sg_set_buf(&dd->aligned_sg, dd->buf, len + padlen);
647 if (dd->src.sg == dd->dst.sg) {
648 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
650 dd->dst.sg_len = dd->src.sg_len;
654 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
659 dd->dst.sg_len = dma_map_sg(dd->dev, dd->dst.sg, dd->dst.nents,
661 if (!dd->dst.sg_len) {
662 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
671 static void atmel_aes_unmap(struct atmel_aes_dev *dd)
673 if (dd->src.sg == dd->dst.sg) {
674 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
677 if (dd->src.sg != &dd->aligned_sg)
678 atmel_aes_restore_sg(&dd->src);
680 dma_unmap_sg(dd->dev, dd->dst.sg, dd->dst.nents,
683 if (dd->dst.sg != &dd->aligned_sg)
684 atmel_aes_restore_sg(&dd->dst);
686 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
689 if (dd->src.sg != &dd->aligned_sg)
690 atmel_aes_restore_sg(&dd->src);
693 if (dd->dst.sg == &dd->aligned_sg)
694 sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
698 static int atmel_aes_dma_transfer_start(struct atmel_aes_dev *dd,
699 enum dma_slave_buswidth addr_width,
700 enum dma_transfer_direction dir,
703 struct dma_async_tx_descriptor *desc;
704 struct dma_slave_config config;
705 dma_async_tx_callback callback;
706 struct atmel_aes_dma *dma;
709 memset(&config, 0, sizeof(config));
710 config.direction = dir;
711 config.src_addr_width = addr_width;
712 config.dst_addr_width = addr_width;
713 config.src_maxburst = maxburst;
714 config.dst_maxburst = maxburst;
720 config.dst_addr = dd->phys_base + AES_IDATAR(0);
725 callback = atmel_aes_dma_callback;
726 config.src_addr = dd->phys_base + AES_ODATAR(0);
733 err = dmaengine_slave_config(dma->chan, &config);
737 desc = dmaengine_prep_slave_sg(dma->chan, dma->sg, dma->sg_len, dir,
738 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
742 desc->callback = callback;
743 desc->callback_param = dd;
744 dmaengine_submit(desc);
745 dma_async_issue_pending(dma->chan);
750 static void atmel_aes_dma_transfer_stop(struct atmel_aes_dev *dd,
751 enum dma_transfer_direction dir)
753 struct atmel_aes_dma *dma;
768 dmaengine_terminate_all(dma->chan);
771 static int atmel_aes_dma_start(struct atmel_aes_dev *dd,
772 struct scatterlist *src,
773 struct scatterlist *dst,
775 atmel_aes_fn_t resume)
777 enum dma_slave_buswidth addr_width;
781 switch (dd->ctx->block_size) {
782 case CFB8_BLOCK_SIZE:
783 addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
787 case CFB16_BLOCK_SIZE:
788 addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
792 case CFB32_BLOCK_SIZE:
793 case CFB64_BLOCK_SIZE:
794 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
799 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
800 maxburst = dd->caps.max_burst_size;
808 err = atmel_aes_map(dd, src, dst, len);
814 /* Set output DMA transfer first */
815 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_DEV_TO_MEM,
820 /* Then set input DMA transfer */
821 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_MEM_TO_DEV,
824 goto output_transfer_stop;
828 output_transfer_stop:
829 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
833 return atmel_aes_complete(dd, err);
836 static void atmel_aes_dma_stop(struct atmel_aes_dev *dd)
838 atmel_aes_dma_transfer_stop(dd, DMA_MEM_TO_DEV);
839 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
843 static void atmel_aes_dma_callback(void *data)
845 struct atmel_aes_dev *dd = data;
847 atmel_aes_dma_stop(dd);
849 (void)dd->resume(dd);
852 static int atmel_aes_handle_queue(struct atmel_aes_dev *dd,
853 struct crypto_async_request *new_areq)
855 struct crypto_async_request *areq, *backlog;
856 struct atmel_aes_base_ctx *ctx;
860 spin_lock_irqsave(&dd->lock, flags);
862 ret = crypto_enqueue_request(&dd->queue, new_areq);
863 if (dd->flags & AES_FLAGS_BUSY) {
864 spin_unlock_irqrestore(&dd->lock, flags);
867 backlog = crypto_get_backlog(&dd->queue);
868 areq = crypto_dequeue_request(&dd->queue);
870 dd->flags |= AES_FLAGS_BUSY;
871 spin_unlock_irqrestore(&dd->lock, flags);
877 backlog->complete(backlog, -EINPROGRESS);
879 ctx = crypto_tfm_ctx(areq->tfm);
883 dd->is_async = (areq != new_areq);
885 err = ctx->start(dd);
886 return (dd->is_async) ? ret : err;
890 /* AES async block ciphers */
892 static int atmel_aes_transfer_complete(struct atmel_aes_dev *dd)
894 return atmel_aes_complete(dd, 0);
897 static int atmel_aes_start(struct atmel_aes_dev *dd)
899 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
900 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
901 bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD ||
902 dd->ctx->block_size != AES_BLOCK_SIZE);
905 atmel_aes_set_mode(dd, rctx);
907 err = atmel_aes_hw_init(dd);
909 return atmel_aes_complete(dd, err);
911 atmel_aes_write_ctrl(dd, use_dma, req->info);
913 return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
914 atmel_aes_transfer_complete);
916 return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
917 atmel_aes_transfer_complete);
920 static inline struct atmel_aes_ctr_ctx *
921 atmel_aes_ctr_ctx_cast(struct atmel_aes_base_ctx *ctx)
923 return container_of(ctx, struct atmel_aes_ctr_ctx, base);
926 static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
928 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
929 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
930 struct scatterlist *src, *dst;
933 bool use_dma, fragmented = false;
935 /* Check for transfer completion. */
936 ctx->offset += dd->total;
937 if (ctx->offset >= req->nbytes)
938 return atmel_aes_transfer_complete(dd);
940 /* Compute data length. */
941 datalen = req->nbytes - ctx->offset;
942 blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE);
943 ctr = be32_to_cpu(ctx->iv[3]);
944 if (dd->caps.has_ctr32) {
945 /* Check 32bit counter overflow. */
947 u32 end = start + blocks - 1;
951 datalen = AES_BLOCK_SIZE * -start;
955 /* Check 16bit counter overflow. */
956 u16 start = ctr & 0xffff;
957 u16 end = start + (u16)blocks - 1;
959 if (blocks >> 16 || end < start) {
961 datalen = AES_BLOCK_SIZE * (0x10000-start);
965 use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD);
967 /* Jump to offset. */
968 src = scatterwalk_ffwd(ctx->src, req->src, ctx->offset);
969 dst = ((req->src == req->dst) ? src :
970 scatterwalk_ffwd(ctx->dst, req->dst, ctx->offset));
972 /* Configure hardware. */
973 atmel_aes_write_ctrl(dd, use_dma, ctx->iv);
974 if (unlikely(fragmented)) {
976 * Increment the counter manually to cope with the hardware
979 ctx->iv[3] = cpu_to_be32(ctr);
980 crypto_inc((u8 *)ctx->iv, AES_BLOCK_SIZE);
984 return atmel_aes_dma_start(dd, src, dst, datalen,
985 atmel_aes_ctr_transfer);
987 return atmel_aes_cpu_start(dd, src, dst, datalen,
988 atmel_aes_ctr_transfer);
991 static int atmel_aes_ctr_start(struct atmel_aes_dev *dd)
993 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
994 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
995 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
998 atmel_aes_set_mode(dd, rctx);
1000 err = atmel_aes_hw_init(dd);
1002 return atmel_aes_complete(dd, err);
1004 memcpy(ctx->iv, req->info, AES_BLOCK_SIZE);
1007 return atmel_aes_ctr_transfer(dd);
1010 static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
1012 struct atmel_aes_base_ctx *ctx;
1013 struct atmel_aes_reqctx *rctx;
1014 struct atmel_aes_dev *dd;
1016 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
1017 switch (mode & AES_FLAGS_OPMODE_MASK) {
1018 case AES_FLAGS_CFB8:
1019 ctx->block_size = CFB8_BLOCK_SIZE;
1022 case AES_FLAGS_CFB16:
1023 ctx->block_size = CFB16_BLOCK_SIZE;
1026 case AES_FLAGS_CFB32:
1027 ctx->block_size = CFB32_BLOCK_SIZE;
1030 case AES_FLAGS_CFB64:
1031 ctx->block_size = CFB64_BLOCK_SIZE;
1035 ctx->block_size = AES_BLOCK_SIZE;
1039 dd = atmel_aes_find_dev(ctx);
1043 rctx = ablkcipher_request_ctx(req);
1046 return atmel_aes_handle_queue(dd, &req->base);
1049 static int atmel_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1050 unsigned int keylen)
1052 struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(tfm);
1054 if (keylen != AES_KEYSIZE_128 &&
1055 keylen != AES_KEYSIZE_192 &&
1056 keylen != AES_KEYSIZE_256) {
1057 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1061 memcpy(ctx->key, key, keylen);
1062 ctx->keylen = keylen;
1067 static int atmel_aes_ecb_encrypt(struct ablkcipher_request *req)
1069 return atmel_aes_crypt(req, AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
1072 static int atmel_aes_ecb_decrypt(struct ablkcipher_request *req)
1074 return atmel_aes_crypt(req, AES_FLAGS_ECB);
1077 static int atmel_aes_cbc_encrypt(struct ablkcipher_request *req)
1079 return atmel_aes_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT);
1082 static int atmel_aes_cbc_decrypt(struct ablkcipher_request *req)
1084 return atmel_aes_crypt(req, AES_FLAGS_CBC);
1087 static int atmel_aes_ofb_encrypt(struct ablkcipher_request *req)
1089 return atmel_aes_crypt(req, AES_FLAGS_OFB | AES_FLAGS_ENCRYPT);
1092 static int atmel_aes_ofb_decrypt(struct ablkcipher_request *req)
1094 return atmel_aes_crypt(req, AES_FLAGS_OFB);
1097 static int atmel_aes_cfb_encrypt(struct ablkcipher_request *req)
1099 return atmel_aes_crypt(req, AES_FLAGS_CFB128 | AES_FLAGS_ENCRYPT);
1102 static int atmel_aes_cfb_decrypt(struct ablkcipher_request *req)
1104 return atmel_aes_crypt(req, AES_FLAGS_CFB128);
1107 static int atmel_aes_cfb64_encrypt(struct ablkcipher_request *req)
1109 return atmel_aes_crypt(req, AES_FLAGS_CFB64 | AES_FLAGS_ENCRYPT);
1112 static int atmel_aes_cfb64_decrypt(struct ablkcipher_request *req)
1114 return atmel_aes_crypt(req, AES_FLAGS_CFB64);
1117 static int atmel_aes_cfb32_encrypt(struct ablkcipher_request *req)
1119 return atmel_aes_crypt(req, AES_FLAGS_CFB32 | AES_FLAGS_ENCRYPT);
1122 static int atmel_aes_cfb32_decrypt(struct ablkcipher_request *req)
1124 return atmel_aes_crypt(req, AES_FLAGS_CFB32);
1127 static int atmel_aes_cfb16_encrypt(struct ablkcipher_request *req)
1129 return atmel_aes_crypt(req, AES_FLAGS_CFB16 | AES_FLAGS_ENCRYPT);
1132 static int atmel_aes_cfb16_decrypt(struct ablkcipher_request *req)
1134 return atmel_aes_crypt(req, AES_FLAGS_CFB16);
1137 static int atmel_aes_cfb8_encrypt(struct ablkcipher_request *req)
1139 return atmel_aes_crypt(req, AES_FLAGS_CFB8 | AES_FLAGS_ENCRYPT);
1142 static int atmel_aes_cfb8_decrypt(struct ablkcipher_request *req)
1144 return atmel_aes_crypt(req, AES_FLAGS_CFB8);
1147 static int atmel_aes_ctr_encrypt(struct ablkcipher_request *req)
1149 return atmel_aes_crypt(req, AES_FLAGS_CTR | AES_FLAGS_ENCRYPT);
1152 static int atmel_aes_ctr_decrypt(struct ablkcipher_request *req)
1154 return atmel_aes_crypt(req, AES_FLAGS_CTR);
1157 static int atmel_aes_cra_init(struct crypto_tfm *tfm)
1159 struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1161 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1162 ctx->base.start = atmel_aes_start;
1167 static int atmel_aes_ctr_cra_init(struct crypto_tfm *tfm)
1169 struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1171 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1172 ctx->base.start = atmel_aes_ctr_start;
1177 static void atmel_aes_cra_exit(struct crypto_tfm *tfm)
1181 static struct crypto_alg aes_algs[] = {
1183 .cra_name = "ecb(aes)",
1184 .cra_driver_name = "atmel-ecb-aes",
1185 .cra_priority = ATMEL_AES_PRIORITY,
1186 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1187 .cra_blocksize = AES_BLOCK_SIZE,
1188 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1189 .cra_alignmask = 0xf,
1190 .cra_type = &crypto_ablkcipher_type,
1191 .cra_module = THIS_MODULE,
1192 .cra_init = atmel_aes_cra_init,
1193 .cra_exit = atmel_aes_cra_exit,
1194 .cra_u.ablkcipher = {
1195 .min_keysize = AES_MIN_KEY_SIZE,
1196 .max_keysize = AES_MAX_KEY_SIZE,
1197 .setkey = atmel_aes_setkey,
1198 .encrypt = atmel_aes_ecb_encrypt,
1199 .decrypt = atmel_aes_ecb_decrypt,
1203 .cra_name = "cbc(aes)",
1204 .cra_driver_name = "atmel-cbc-aes",
1205 .cra_priority = ATMEL_AES_PRIORITY,
1206 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1207 .cra_blocksize = AES_BLOCK_SIZE,
1208 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1209 .cra_alignmask = 0xf,
1210 .cra_type = &crypto_ablkcipher_type,
1211 .cra_module = THIS_MODULE,
1212 .cra_init = atmel_aes_cra_init,
1213 .cra_exit = atmel_aes_cra_exit,
1214 .cra_u.ablkcipher = {
1215 .min_keysize = AES_MIN_KEY_SIZE,
1216 .max_keysize = AES_MAX_KEY_SIZE,
1217 .ivsize = AES_BLOCK_SIZE,
1218 .setkey = atmel_aes_setkey,
1219 .encrypt = atmel_aes_cbc_encrypt,
1220 .decrypt = atmel_aes_cbc_decrypt,
1224 .cra_name = "ofb(aes)",
1225 .cra_driver_name = "atmel-ofb-aes",
1226 .cra_priority = ATMEL_AES_PRIORITY,
1227 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1228 .cra_blocksize = AES_BLOCK_SIZE,
1229 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1230 .cra_alignmask = 0xf,
1231 .cra_type = &crypto_ablkcipher_type,
1232 .cra_module = THIS_MODULE,
1233 .cra_init = atmel_aes_cra_init,
1234 .cra_exit = atmel_aes_cra_exit,
1235 .cra_u.ablkcipher = {
1236 .min_keysize = AES_MIN_KEY_SIZE,
1237 .max_keysize = AES_MAX_KEY_SIZE,
1238 .ivsize = AES_BLOCK_SIZE,
1239 .setkey = atmel_aes_setkey,
1240 .encrypt = atmel_aes_ofb_encrypt,
1241 .decrypt = atmel_aes_ofb_decrypt,
1245 .cra_name = "cfb(aes)",
1246 .cra_driver_name = "atmel-cfb-aes",
1247 .cra_priority = ATMEL_AES_PRIORITY,
1248 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1249 .cra_blocksize = AES_BLOCK_SIZE,
1250 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1251 .cra_alignmask = 0xf,
1252 .cra_type = &crypto_ablkcipher_type,
1253 .cra_module = THIS_MODULE,
1254 .cra_init = atmel_aes_cra_init,
1255 .cra_exit = atmel_aes_cra_exit,
1256 .cra_u.ablkcipher = {
1257 .min_keysize = AES_MIN_KEY_SIZE,
1258 .max_keysize = AES_MAX_KEY_SIZE,
1259 .ivsize = AES_BLOCK_SIZE,
1260 .setkey = atmel_aes_setkey,
1261 .encrypt = atmel_aes_cfb_encrypt,
1262 .decrypt = atmel_aes_cfb_decrypt,
1266 .cra_name = "cfb32(aes)",
1267 .cra_driver_name = "atmel-cfb32-aes",
1268 .cra_priority = ATMEL_AES_PRIORITY,
1269 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1270 .cra_blocksize = CFB32_BLOCK_SIZE,
1271 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1272 .cra_alignmask = 0x3,
1273 .cra_type = &crypto_ablkcipher_type,
1274 .cra_module = THIS_MODULE,
1275 .cra_init = atmel_aes_cra_init,
1276 .cra_exit = atmel_aes_cra_exit,
1277 .cra_u.ablkcipher = {
1278 .min_keysize = AES_MIN_KEY_SIZE,
1279 .max_keysize = AES_MAX_KEY_SIZE,
1280 .ivsize = AES_BLOCK_SIZE,
1281 .setkey = atmel_aes_setkey,
1282 .encrypt = atmel_aes_cfb32_encrypt,
1283 .decrypt = atmel_aes_cfb32_decrypt,
1287 .cra_name = "cfb16(aes)",
1288 .cra_driver_name = "atmel-cfb16-aes",
1289 .cra_priority = ATMEL_AES_PRIORITY,
1290 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1291 .cra_blocksize = CFB16_BLOCK_SIZE,
1292 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1293 .cra_alignmask = 0x1,
1294 .cra_type = &crypto_ablkcipher_type,
1295 .cra_module = THIS_MODULE,
1296 .cra_init = atmel_aes_cra_init,
1297 .cra_exit = atmel_aes_cra_exit,
1298 .cra_u.ablkcipher = {
1299 .min_keysize = AES_MIN_KEY_SIZE,
1300 .max_keysize = AES_MAX_KEY_SIZE,
1301 .ivsize = AES_BLOCK_SIZE,
1302 .setkey = atmel_aes_setkey,
1303 .encrypt = atmel_aes_cfb16_encrypt,
1304 .decrypt = atmel_aes_cfb16_decrypt,
1308 .cra_name = "cfb8(aes)",
1309 .cra_driver_name = "atmel-cfb8-aes",
1310 .cra_priority = ATMEL_AES_PRIORITY,
1311 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1312 .cra_blocksize = CFB8_BLOCK_SIZE,
1313 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1314 .cra_alignmask = 0x0,
1315 .cra_type = &crypto_ablkcipher_type,
1316 .cra_module = THIS_MODULE,
1317 .cra_init = atmel_aes_cra_init,
1318 .cra_exit = atmel_aes_cra_exit,
1319 .cra_u.ablkcipher = {
1320 .min_keysize = AES_MIN_KEY_SIZE,
1321 .max_keysize = AES_MAX_KEY_SIZE,
1322 .ivsize = AES_BLOCK_SIZE,
1323 .setkey = atmel_aes_setkey,
1324 .encrypt = atmel_aes_cfb8_encrypt,
1325 .decrypt = atmel_aes_cfb8_decrypt,
1329 .cra_name = "ctr(aes)",
1330 .cra_driver_name = "atmel-ctr-aes",
1331 .cra_priority = ATMEL_AES_PRIORITY,
1332 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1334 .cra_ctxsize = sizeof(struct atmel_aes_ctr_ctx),
1335 .cra_alignmask = 0xf,
1336 .cra_type = &crypto_ablkcipher_type,
1337 .cra_module = THIS_MODULE,
1338 .cra_init = atmel_aes_ctr_cra_init,
1339 .cra_exit = atmel_aes_cra_exit,
1340 .cra_u.ablkcipher = {
1341 .min_keysize = AES_MIN_KEY_SIZE,
1342 .max_keysize = AES_MAX_KEY_SIZE,
1343 .ivsize = AES_BLOCK_SIZE,
1344 .setkey = atmel_aes_setkey,
1345 .encrypt = atmel_aes_ctr_encrypt,
1346 .decrypt = atmel_aes_ctr_decrypt,
1351 static struct crypto_alg aes_cfb64_alg = {
1352 .cra_name = "cfb64(aes)",
1353 .cra_driver_name = "atmel-cfb64-aes",
1354 .cra_priority = ATMEL_AES_PRIORITY,
1355 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1356 .cra_blocksize = CFB64_BLOCK_SIZE,
1357 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1358 .cra_alignmask = 0x7,
1359 .cra_type = &crypto_ablkcipher_type,
1360 .cra_module = THIS_MODULE,
1361 .cra_init = atmel_aes_cra_init,
1362 .cra_exit = atmel_aes_cra_exit,
1363 .cra_u.ablkcipher = {
1364 .min_keysize = AES_MIN_KEY_SIZE,
1365 .max_keysize = AES_MAX_KEY_SIZE,
1366 .ivsize = AES_BLOCK_SIZE,
1367 .setkey = atmel_aes_setkey,
1368 .encrypt = atmel_aes_cfb64_encrypt,
1369 .decrypt = atmel_aes_cfb64_decrypt,
1374 /* gcm aead functions */
1376 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1377 const u32 *data, size_t datalen,
1378 const u32 *ghash_in, u32 *ghash_out,
1379 atmel_aes_fn_t resume);
1380 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd);
1381 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd);
1383 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd);
1384 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd);
1385 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd);
1386 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd);
1387 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd);
1388 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd);
1389 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd);
1391 static inline struct atmel_aes_gcm_ctx *
1392 atmel_aes_gcm_ctx_cast(struct atmel_aes_base_ctx *ctx)
1394 return container_of(ctx, struct atmel_aes_gcm_ctx, base);
1397 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1398 const u32 *data, size_t datalen,
1399 const u32 *ghash_in, u32 *ghash_out,
1400 atmel_aes_fn_t resume)
1402 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1404 dd->data = (u32 *)data;
1405 dd->datalen = datalen;
1406 ctx->ghash_in = ghash_in;
1407 ctx->ghash_out = ghash_out;
1408 ctx->ghash_resume = resume;
1410 atmel_aes_write_ctrl(dd, false, NULL);
1411 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_ghash_init);
1414 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd)
1416 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1418 /* Set the data length. */
1419 atmel_aes_write(dd, AES_AADLENR, dd->total);
1420 atmel_aes_write(dd, AES_CLENR, 0);
1422 /* If needed, overwrite the GCM Intermediate Hash Word Registers */
1424 atmel_aes_write_block(dd, AES_GHASHR(0), ctx->ghash_in);
1426 return atmel_aes_gcm_ghash_finalize(dd);
1429 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd)
1431 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1434 /* Write data into the Input Data Registers. */
1435 while (dd->datalen > 0) {
1436 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1438 dd->datalen -= AES_BLOCK_SIZE;
1440 isr = atmel_aes_read(dd, AES_ISR);
1441 if (!(isr & AES_INT_DATARDY)) {
1442 dd->resume = atmel_aes_gcm_ghash_finalize;
1443 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1444 return -EINPROGRESS;
1448 /* Read the computed hash from GHASHRx. */
1449 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash_out);
1451 return ctx->ghash_resume(dd);
1455 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd)
1457 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1458 struct aead_request *req = aead_request_cast(dd->areq);
1459 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1460 struct atmel_aes_reqctx *rctx = aead_request_ctx(req);
1461 size_t ivsize = crypto_aead_ivsize(tfm);
1462 size_t datalen, padlen;
1463 const void *iv = req->iv;
1467 atmel_aes_set_mode(dd, rctx);
1469 err = atmel_aes_hw_init(dd);
1471 return atmel_aes_complete(dd, err);
1473 if (likely(ivsize == 12)) {
1474 memcpy(ctx->j0, iv, ivsize);
1475 ctx->j0[3] = cpu_to_be32(1);
1476 return atmel_aes_gcm_process(dd);
1479 padlen = atmel_aes_padlen(ivsize, AES_BLOCK_SIZE);
1480 datalen = ivsize + padlen + AES_BLOCK_SIZE;
1481 if (datalen > dd->buflen)
1482 return atmel_aes_complete(dd, -EINVAL);
1484 memcpy(data, iv, ivsize);
1485 memset(data + ivsize, 0, padlen + sizeof(u64));
1486 ((u64 *)(data + datalen))[-1] = cpu_to_be64(ivsize * 8);
1488 return atmel_aes_gcm_ghash(dd, (const u32 *)data, datalen,
1489 NULL, ctx->j0, atmel_aes_gcm_process);
1492 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd)
1494 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1495 struct aead_request *req = aead_request_cast(dd->areq);
1496 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1497 bool enc = atmel_aes_is_encrypt(dd);
1500 /* Compute text length. */
1501 authsize = crypto_aead_authsize(tfm);
1502 ctx->textlen = req->cryptlen - (enc ? 0 : authsize);
1505 * According to tcrypt test suite, the GCM Automatic Tag Generation
1506 * fails when both the message and its associated data are empty.
1508 if (likely(req->assoclen != 0 || ctx->textlen != 0))
1509 dd->flags |= AES_FLAGS_GTAGEN;
1511 atmel_aes_write_ctrl(dd, false, NULL);
1512 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_length);
1515 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd)
1517 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1518 struct aead_request *req = aead_request_cast(dd->areq);
1519 u32 j0_lsw, *j0 = ctx->j0;
1522 /* Write incr32(J0) into IV. */
1524 j0[3] = cpu_to_be32(be32_to_cpu(j0[3]) + 1);
1525 atmel_aes_write_block(dd, AES_IVR(0), j0);
1528 /* Set aad and text lengths. */
1529 atmel_aes_write(dd, AES_AADLENR, req->assoclen);
1530 atmel_aes_write(dd, AES_CLENR, ctx->textlen);
1532 /* Check whether AAD are present. */
1533 if (unlikely(req->assoclen == 0)) {
1535 return atmel_aes_gcm_data(dd);
1538 /* Copy assoc data and add padding. */
1539 padlen = atmel_aes_padlen(req->assoclen, AES_BLOCK_SIZE);
1540 if (unlikely(req->assoclen + padlen > dd->buflen))
1541 return atmel_aes_complete(dd, -EINVAL);
1542 sg_copy_to_buffer(req->src, sg_nents(req->src), dd->buf, req->assoclen);
1544 /* Write assoc data into the Input Data register. */
1545 dd->data = (u32 *)dd->buf;
1546 dd->datalen = req->assoclen + padlen;
1547 return atmel_aes_gcm_data(dd);
1550 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd)
1552 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1553 struct aead_request *req = aead_request_cast(dd->areq);
1554 bool use_dma = (ctx->textlen >= ATMEL_AES_DMA_THRESHOLD);
1555 struct scatterlist *src, *dst;
1558 /* Write AAD first. */
1559 while (dd->datalen > 0) {
1560 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1562 dd->datalen -= AES_BLOCK_SIZE;
1564 isr = atmel_aes_read(dd, AES_ISR);
1565 if (!(isr & AES_INT_DATARDY)) {
1566 dd->resume = atmel_aes_gcm_data;
1567 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1568 return -EINPROGRESS;
1573 if (unlikely(ctx->textlen == 0))
1574 return atmel_aes_gcm_tag_init(dd);
1576 /* Prepare src and dst scatter lists to transfer cipher/plain texts */
1577 src = scatterwalk_ffwd(ctx->src, req->src, req->assoclen);
1578 dst = ((req->src == req->dst) ? src :
1579 scatterwalk_ffwd(ctx->dst, req->dst, req->assoclen));
1582 /* Update the Mode Register for DMA transfers. */
1583 mr = atmel_aes_read(dd, AES_MR);
1584 mr &= ~(AES_MR_SMOD_MASK | AES_MR_DUALBUFF);
1585 mr |= AES_MR_SMOD_IDATAR0;
1586 if (dd->caps.has_dualbuff)
1587 mr |= AES_MR_DUALBUFF;
1588 atmel_aes_write(dd, AES_MR, mr);
1590 return atmel_aes_dma_start(dd, src, dst, ctx->textlen,
1591 atmel_aes_gcm_tag_init);
1594 return atmel_aes_cpu_start(dd, src, dst, ctx->textlen,
1595 atmel_aes_gcm_tag_init);
1598 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd)
1600 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1601 struct aead_request *req = aead_request_cast(dd->areq);
1602 u64 *data = dd->buf;
1604 if (likely(dd->flags & AES_FLAGS_GTAGEN)) {
1605 if (!(atmel_aes_read(dd, AES_ISR) & AES_INT_TAGRDY)) {
1606 dd->resume = atmel_aes_gcm_tag_init;
1607 atmel_aes_write(dd, AES_IER, AES_INT_TAGRDY);
1608 return -EINPROGRESS;
1611 return atmel_aes_gcm_finalize(dd);
1614 /* Read the GCM Intermediate Hash Word Registers. */
1615 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash);
1617 data[0] = cpu_to_be64(req->assoclen * 8);
1618 data[1] = cpu_to_be64(ctx->textlen * 8);
1620 return atmel_aes_gcm_ghash(dd, (const u32 *)data, AES_BLOCK_SIZE,
1621 ctx->ghash, ctx->ghash, atmel_aes_gcm_tag);
1624 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd)
1626 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1627 unsigned long flags;
1630 * Change mode to CTR to complete the tag generation.
1631 * Use J0 as Initialization Vector.
1634 dd->flags &= ~(AES_FLAGS_OPMODE_MASK | AES_FLAGS_GTAGEN);
1635 dd->flags |= AES_FLAGS_CTR;
1636 atmel_aes_write_ctrl(dd, false, ctx->j0);
1639 atmel_aes_write_block(dd, AES_IDATAR(0), ctx->ghash);
1640 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_finalize);
1643 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd)
1645 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1646 struct aead_request *req = aead_request_cast(dd->areq);
1647 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1648 bool enc = atmel_aes_is_encrypt(dd);
1649 u32 offset, authsize, itag[4], *otag = ctx->tag;
1652 /* Read the computed tag. */
1653 if (likely(dd->flags & AES_FLAGS_GTAGEN))
1654 atmel_aes_read_block(dd, AES_TAGR(0), ctx->tag);
1656 atmel_aes_read_block(dd, AES_ODATAR(0), ctx->tag);
1658 offset = req->assoclen + ctx->textlen;
1659 authsize = crypto_aead_authsize(tfm);
1661 scatterwalk_map_and_copy(otag, req->dst, offset, authsize, 1);
1664 scatterwalk_map_and_copy(itag, req->src, offset, authsize, 0);
1665 err = crypto_memneq(itag, otag, authsize) ? -EBADMSG : 0;
1668 return atmel_aes_complete(dd, err);
1671 static int atmel_aes_gcm_crypt(struct aead_request *req,
1674 struct atmel_aes_base_ctx *ctx;
1675 struct atmel_aes_reqctx *rctx;
1676 struct atmel_aes_dev *dd;
1678 ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
1679 ctx->block_size = AES_BLOCK_SIZE;
1681 dd = atmel_aes_find_dev(ctx);
1685 rctx = aead_request_ctx(req);
1686 rctx->mode = AES_FLAGS_GCM | mode;
1688 return atmel_aes_handle_queue(dd, &req->base);
1691 static int atmel_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
1692 unsigned int keylen)
1694 struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm);
1696 if (keylen != AES_KEYSIZE_256 &&
1697 keylen != AES_KEYSIZE_192 &&
1698 keylen != AES_KEYSIZE_128) {
1699 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1703 memcpy(ctx->key, key, keylen);
1704 ctx->keylen = keylen;
1709 static int atmel_aes_gcm_setauthsize(struct crypto_aead *tfm,
1710 unsigned int authsize)
1712 /* Same as crypto_gcm_authsize() from crypto/gcm.c */
1729 static int atmel_aes_gcm_encrypt(struct aead_request *req)
1731 return atmel_aes_gcm_crypt(req, AES_FLAGS_ENCRYPT);
1734 static int atmel_aes_gcm_decrypt(struct aead_request *req)
1736 return atmel_aes_gcm_crypt(req, 0);
1739 static int atmel_aes_gcm_init(struct crypto_aead *tfm)
1741 struct atmel_aes_gcm_ctx *ctx = crypto_aead_ctx(tfm);
1743 crypto_aead_set_reqsize(tfm, sizeof(struct atmel_aes_reqctx));
1744 ctx->base.start = atmel_aes_gcm_start;
1749 static void atmel_aes_gcm_exit(struct crypto_aead *tfm)
1754 static struct aead_alg aes_gcm_alg = {
1755 .setkey = atmel_aes_gcm_setkey,
1756 .setauthsize = atmel_aes_gcm_setauthsize,
1757 .encrypt = atmel_aes_gcm_encrypt,
1758 .decrypt = atmel_aes_gcm_decrypt,
1759 .init = atmel_aes_gcm_init,
1760 .exit = atmel_aes_gcm_exit,
1762 .maxauthsize = AES_BLOCK_SIZE,
1765 .cra_name = "gcm(aes)",
1766 .cra_driver_name = "atmel-gcm-aes",
1767 .cra_priority = ATMEL_AES_PRIORITY,
1768 .cra_flags = CRYPTO_ALG_ASYNC,
1770 .cra_ctxsize = sizeof(struct atmel_aes_gcm_ctx),
1771 .cra_alignmask = 0xf,
1772 .cra_module = THIS_MODULE,
1777 /* Probe functions */
1779 static int atmel_aes_buff_init(struct atmel_aes_dev *dd)
1781 dd->buf = (void *)__get_free_pages(GFP_KERNEL, ATMEL_AES_BUFFER_ORDER);
1782 dd->buflen = ATMEL_AES_BUFFER_SIZE;
1783 dd->buflen &= ~(AES_BLOCK_SIZE - 1);
1786 dev_err(dd->dev, "unable to alloc pages.\n");
1793 static void atmel_aes_buff_cleanup(struct atmel_aes_dev *dd)
1795 free_page((unsigned long)dd->buf);
1798 static bool atmel_aes_filter(struct dma_chan *chan, void *slave)
1800 struct at_dma_slave *sl = slave;
1802 if (sl && sl->dma_dev == chan->device->dev) {
1810 static int atmel_aes_dma_init(struct atmel_aes_dev *dd,
1811 struct crypto_platform_data *pdata)
1813 struct at_dma_slave *slave;
1815 dma_cap_mask_t mask;
1818 dma_cap_set(DMA_SLAVE, mask);
1820 /* Try to grab 2 DMA channels */
1821 slave = &pdata->dma_slave->rxdata;
1822 dd->src.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
1823 slave, dd->dev, "tx");
1827 slave = &pdata->dma_slave->txdata;
1828 dd->dst.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
1829 slave, dd->dev, "rx");
1836 dma_release_channel(dd->src.chan);
1838 dev_warn(dd->dev, "no DMA channel available\n");
1842 static void atmel_aes_dma_cleanup(struct atmel_aes_dev *dd)
1844 dma_release_channel(dd->dst.chan);
1845 dma_release_channel(dd->src.chan);
1848 static void atmel_aes_queue_task(unsigned long data)
1850 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
1852 atmel_aes_handle_queue(dd, NULL);
1855 static void atmel_aes_done_task(unsigned long data)
1857 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
1859 dd->is_async = true;
1860 (void)dd->resume(dd);
1863 static irqreturn_t atmel_aes_irq(int irq, void *dev_id)
1865 struct atmel_aes_dev *aes_dd = dev_id;
1868 reg = atmel_aes_read(aes_dd, AES_ISR);
1869 if (reg & atmel_aes_read(aes_dd, AES_IMR)) {
1870 atmel_aes_write(aes_dd, AES_IDR, reg);
1871 if (AES_FLAGS_BUSY & aes_dd->flags)
1872 tasklet_schedule(&aes_dd->done_task);
1874 dev_warn(aes_dd->dev, "AES interrupt when no active requests.\n");
1881 static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd)
1885 if (dd->caps.has_gcm)
1886 crypto_unregister_aead(&aes_gcm_alg);
1888 if (dd->caps.has_cfb64)
1889 crypto_unregister_alg(&aes_cfb64_alg);
1891 for (i = 0; i < ARRAY_SIZE(aes_algs); i++)
1892 crypto_unregister_alg(&aes_algs[i]);
1895 static int atmel_aes_register_algs(struct atmel_aes_dev *dd)
1899 for (i = 0; i < ARRAY_SIZE(aes_algs); i++) {
1900 err = crypto_register_alg(&aes_algs[i]);
1905 if (dd->caps.has_cfb64) {
1906 err = crypto_register_alg(&aes_cfb64_alg);
1908 goto err_aes_cfb64_alg;
1911 if (dd->caps.has_gcm) {
1912 err = crypto_register_aead(&aes_gcm_alg);
1914 goto err_aes_gcm_alg;
1920 crypto_unregister_alg(&aes_cfb64_alg);
1922 i = ARRAY_SIZE(aes_algs);
1924 for (j = 0; j < i; j++)
1925 crypto_unregister_alg(&aes_algs[j]);
1930 static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
1932 dd->caps.has_dualbuff = 0;
1933 dd->caps.has_cfb64 = 0;
1934 dd->caps.has_ctr32 = 0;
1935 dd->caps.has_gcm = 0;
1936 dd->caps.max_burst_size = 1;
1938 /* keep only major version number */
1939 switch (dd->hw_version & 0xff0) {
1941 dd->caps.has_dualbuff = 1;
1942 dd->caps.has_cfb64 = 1;
1943 dd->caps.has_ctr32 = 1;
1944 dd->caps.has_gcm = 1;
1945 dd->caps.max_burst_size = 4;
1948 dd->caps.has_dualbuff = 1;
1949 dd->caps.has_cfb64 = 1;
1950 dd->caps.has_ctr32 = 1;
1951 dd->caps.has_gcm = 1;
1952 dd->caps.max_burst_size = 4;
1955 dd->caps.has_dualbuff = 1;
1956 dd->caps.has_cfb64 = 1;
1957 dd->caps.max_burst_size = 4;
1963 "Unmanaged aes version, set minimum capabilities\n");
1968 #if defined(CONFIG_OF)
1969 static const struct of_device_id atmel_aes_dt_ids[] = {
1970 { .compatible = "atmel,at91sam9g46-aes" },
1973 MODULE_DEVICE_TABLE(of, atmel_aes_dt_ids);
1975 static struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
1977 struct device_node *np = pdev->dev.of_node;
1978 struct crypto_platform_data *pdata;
1981 dev_err(&pdev->dev, "device node not found\n");
1982 return ERR_PTR(-EINVAL);
1985 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1987 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
1988 return ERR_PTR(-ENOMEM);
1991 pdata->dma_slave = devm_kzalloc(&pdev->dev,
1992 sizeof(*(pdata->dma_slave)),
1994 if (!pdata->dma_slave) {
1995 dev_err(&pdev->dev, "could not allocate memory for dma_slave\n");
1996 devm_kfree(&pdev->dev, pdata);
1997 return ERR_PTR(-ENOMEM);
2003 static inline struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
2005 return ERR_PTR(-EINVAL);
2009 static int atmel_aes_probe(struct platform_device *pdev)
2011 struct atmel_aes_dev *aes_dd;
2012 struct crypto_platform_data *pdata;
2013 struct device *dev = &pdev->dev;
2014 struct resource *aes_res;
2017 pdata = pdev->dev.platform_data;
2019 pdata = atmel_aes_of_init(pdev);
2020 if (IS_ERR(pdata)) {
2021 err = PTR_ERR(pdata);
2026 if (!pdata->dma_slave) {
2031 aes_dd = devm_kzalloc(&pdev->dev, sizeof(*aes_dd), GFP_KERNEL);
2032 if (aes_dd == NULL) {
2033 dev_err(dev, "unable to alloc data struct.\n");
2040 platform_set_drvdata(pdev, aes_dd);
2042 INIT_LIST_HEAD(&aes_dd->list);
2043 spin_lock_init(&aes_dd->lock);
2045 tasklet_init(&aes_dd->done_task, atmel_aes_done_task,
2046 (unsigned long)aes_dd);
2047 tasklet_init(&aes_dd->queue_task, atmel_aes_queue_task,
2048 (unsigned long)aes_dd);
2050 crypto_init_queue(&aes_dd->queue, ATMEL_AES_QUEUE_LENGTH);
2054 /* Get the base address */
2055 aes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2057 dev_err(dev, "no MEM resource info\n");
2061 aes_dd->phys_base = aes_res->start;
2064 aes_dd->irq = platform_get_irq(pdev, 0);
2065 if (aes_dd->irq < 0) {
2066 dev_err(dev, "no IRQ resource info\n");
2071 err = devm_request_irq(&pdev->dev, aes_dd->irq, atmel_aes_irq,
2072 IRQF_SHARED, "atmel-aes", aes_dd);
2074 dev_err(dev, "unable to request aes irq.\n");
2078 /* Initializing the clock */
2079 aes_dd->iclk = devm_clk_get(&pdev->dev, "aes_clk");
2080 if (IS_ERR(aes_dd->iclk)) {
2081 dev_err(dev, "clock initialization failed.\n");
2082 err = PTR_ERR(aes_dd->iclk);
2086 aes_dd->io_base = devm_ioremap_resource(&pdev->dev, aes_res);
2087 if (!aes_dd->io_base) {
2088 dev_err(dev, "can't ioremap\n");
2093 err = atmel_aes_hw_version_init(aes_dd);
2097 atmel_aes_get_cap(aes_dd);
2099 err = atmel_aes_buff_init(aes_dd);
2103 err = atmel_aes_dma_init(aes_dd, pdata);
2107 spin_lock(&atmel_aes.lock);
2108 list_add_tail(&aes_dd->list, &atmel_aes.dev_list);
2109 spin_unlock(&atmel_aes.lock);
2111 err = atmel_aes_register_algs(aes_dd);
2115 dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n",
2116 dma_chan_name(aes_dd->src.chan),
2117 dma_chan_name(aes_dd->dst.chan));
2122 spin_lock(&atmel_aes.lock);
2123 list_del(&aes_dd->list);
2124 spin_unlock(&atmel_aes.lock);
2125 atmel_aes_dma_cleanup(aes_dd);
2127 atmel_aes_buff_cleanup(aes_dd);
2130 tasklet_kill(&aes_dd->done_task);
2131 tasklet_kill(&aes_dd->queue_task);
2133 dev_err(dev, "initialization failed.\n");
2138 static int atmel_aes_remove(struct platform_device *pdev)
2140 static struct atmel_aes_dev *aes_dd;
2142 aes_dd = platform_get_drvdata(pdev);
2145 spin_lock(&atmel_aes.lock);
2146 list_del(&aes_dd->list);
2147 spin_unlock(&atmel_aes.lock);
2149 atmel_aes_unregister_algs(aes_dd);
2151 tasklet_kill(&aes_dd->done_task);
2152 tasklet_kill(&aes_dd->queue_task);
2154 atmel_aes_dma_cleanup(aes_dd);
2155 atmel_aes_buff_cleanup(aes_dd);
2160 static struct platform_driver atmel_aes_driver = {
2161 .probe = atmel_aes_probe,
2162 .remove = atmel_aes_remove,
2164 .name = "atmel_aes",
2165 .of_match_table = of_match_ptr(atmel_aes_dt_ids),
2169 module_platform_driver(atmel_aes_driver);
2171 MODULE_DESCRIPTION("Atmel AES hw acceleration support.");
2172 MODULE_LICENSE("GPL v2");
2173 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");