2 * AMD Cryptographic Coprocessor (CCP) driver
4 * Copyright (C) 2013 Advanced Micro Devices, Inc.
6 * Author: Tom Lendacky <thomas.lendacky@amd.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
16 #include <linux/device.h>
17 #include <linux/pci.h>
18 #include <linux/spinlock.h>
19 #include <linux/mutex.h>
20 #include <linux/list.h>
21 #include <linux/wait.h>
22 #include <linux/dmapool.h>
23 #include <linux/hw_random.h>
26 #define MAX_DMAPOOL_NAME_LEN 32
28 #define MAX_HW_QUEUES 5
29 #define MAX_CMD_QLEN 100
31 #define TRNG_RETRIES 10
33 #define CACHE_NONE 0x00
34 #define CACHE_WB_NO_ALLOC 0xb7
37 /****** Register Mappings ******/
38 #define Q_MASK_REG 0x000
39 #define TRNG_OUT_REG 0x00c
40 #define IRQ_MASK_REG 0x040
41 #define IRQ_STATUS_REG 0x200
43 #define DEL_CMD_Q_JOB 0x124
44 #define DEL_Q_ACTIVE 0x00000200
45 #define DEL_Q_ID_SHIFT 6
47 #define CMD_REQ0 0x180
48 #define CMD_REQ_INCR 0x04
50 #define CMD_Q_STATUS_BASE 0x210
51 #define CMD_Q_INT_STATUS_BASE 0x214
52 #define CMD_Q_STATUS_INCR 0x20
54 #define CMD_Q_CACHE_BASE 0x228
55 #define CMD_Q_CACHE_INC 0x20
57 #define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f);
58 #define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f);
60 /****** REQ0 Related Values ******/
61 #define REQ0_WAIT_FOR_WRITE 0x00000004
62 #define REQ0_INT_ON_COMPLETE 0x00000002
63 #define REQ0_STOP_ON_COMPLETE 0x00000001
65 #define REQ0_CMD_Q_SHIFT 9
66 #define REQ0_JOBID_SHIFT 3
68 /****** REQ1 Related Values ******/
69 #define REQ1_PROTECT_SHIFT 27
70 #define REQ1_ENGINE_SHIFT 23
71 #define REQ1_KEY_KSB_SHIFT 2
73 #define REQ1_EOM 0x00000002
74 #define REQ1_INIT 0x00000001
76 /* AES Related Values */
77 #define REQ1_AES_TYPE_SHIFT 21
78 #define REQ1_AES_MODE_SHIFT 18
79 #define REQ1_AES_ACTION_SHIFT 17
80 #define REQ1_AES_CFB_SIZE_SHIFT 10
82 /* XTS-AES Related Values */
83 #define REQ1_XTS_AES_SIZE_SHIFT 10
85 /* SHA Related Values */
86 #define REQ1_SHA_TYPE_SHIFT 21
88 /* RSA Related Values */
89 #define REQ1_RSA_MOD_SIZE_SHIFT 10
91 /* Pass-Through Related Values */
92 #define REQ1_PT_BW_SHIFT 12
93 #define REQ1_PT_BS_SHIFT 10
95 /* ECC Related Values */
96 #define REQ1_ECC_AFFINE_CONVERT 0x00200000
97 #define REQ1_ECC_FUNCTION_SHIFT 18
99 /****** REQ4 Related Values ******/
100 #define REQ4_KSB_SHIFT 18
101 #define REQ4_MEMTYPE_SHIFT 16
103 /****** REQ6 Related Values ******/
104 #define REQ6_MEMTYPE_SHIFT 16
107 /****** Key Storage Block ******/
110 #define KSB_COUNT (KSB_END - KSB_START + 1)
111 #define CCP_KSB_BITS 256
112 #define CCP_KSB_BYTES 32
114 #define CCP_JOBID_MASK 0x0000003f
116 #define CCP_DMAPOOL_MAX_SIZE 64
117 #define CCP_DMAPOOL_ALIGN (1 << 5)
119 #define CCP_REVERSE_BUF_SIZE 64
121 #define CCP_AES_KEY_KSB_COUNT 1
122 #define CCP_AES_CTX_KSB_COUNT 1
124 #define CCP_XTS_AES_KEY_KSB_COUNT 1
125 #define CCP_XTS_AES_CTX_KSB_COUNT 1
127 #define CCP_SHA_KSB_COUNT 1
129 #define CCP_RSA_MAX_WIDTH 4096
131 #define CCP_PASSTHRU_BLOCKSIZE 256
132 #define CCP_PASSTHRU_MASKSIZE 32
133 #define CCP_PASSTHRU_KSB_COUNT 1
135 #define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */
136 #define CCP_ECC_MAX_OPERANDS 6
137 #define CCP_ECC_MAX_OUTPUTS 3
138 #define CCP_ECC_SRC_BUF_SIZE 448
139 #define CCP_ECC_DST_BUF_SIZE 192
140 #define CCP_ECC_OPERAND_SIZE 64
141 #define CCP_ECC_OUTPUT_SIZE 64
142 #define CCP_ECC_RESULT_OFFSET 60
143 #define CCP_ECC_RESULT_SUCCESS 0x0001
149 struct ccp_cmd_queue {
150 struct ccp_device *ccp;
152 /* Queue identifier */
156 struct dma_pool *dma_pool;
158 /* Queue reserved KSB regions */
162 /* Queue processing thread */
163 struct task_struct *kthread;
165 unsigned int suspended;
167 /* Number of free command slots available */
168 unsigned int free_slots;
170 /* Interrupt masks */
174 /* Register addresses for queue */
175 void __iomem *reg_status;
176 void __iomem *reg_int_status;
178 /* Status values from job */
184 /* Interrupt wait queue */
185 wait_queue_head_t int_queue;
186 unsigned int int_rcvd;
187 } ____cacheline_aligned;
193 * Bus specific device information
196 int (*get_irq)(struct ccp_device *ccp);
197 void (*free_irq)(struct ccp_device *ccp);
201 * I/O area used for device communication. The register mapping
202 * starts at an offset into the mapped bar.
203 * The CMD_REQx registers and the Delete_Cmd_Queue_Job register
204 * need to be protected while a command queue thread is accessing
207 struct mutex req_mutex ____cacheline_aligned;
208 void __iomem *io_map;
209 void __iomem *io_regs;
212 * Master lists that all cmds are queued on. Because there can be
213 * more than one CCP command queue that can process a cmd a separate
214 * backlog list is neeeded so that the backlog completion call
215 * completes before the cmd is available for execution.
217 spinlock_t cmd_lock ____cacheline_aligned;
218 unsigned int cmd_count;
219 struct list_head cmd;
220 struct list_head backlog;
223 * The command queues. These represent the queues available on the
224 * CCP that are available for processing cmds
226 struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
227 unsigned int cmd_q_count;
230 * Support for the CCP True RNG
233 unsigned int hwrng_retries;
236 * A counter used to generate job-ids for cmds submitted to the CCP
238 atomic_t current_id ____cacheline_aligned;
241 * The CCP uses key storage blocks (KSB) to maintain context for certain
242 * operations. To prevent multiple cmds from using the same KSB range
243 * a command queue reserves a KSB range for the duration of the cmd.
244 * Each queue, will however, reserve 2 KSB blocks for operations that
245 * only require single KSB entries (eg. AES context/iv and key) in order
246 * to avoid allocation contention. This will reserve at most 10 KSB
247 * entries, leaving 40 KSB entries available for dynamic allocation.
249 struct mutex ksb_mutex ____cacheline_aligned;
250 DECLARE_BITMAP(ksb, KSB_COUNT);
251 wait_queue_head_t ksb_queue;
252 unsigned int ksb_avail;
253 unsigned int ksb_count;
256 /* Suspend support */
257 unsigned int suspending;
258 wait_queue_head_t suspend_queue;
260 /* DMA caching attribute support */
261 unsigned int axcache;
265 int ccp_pci_init(void);
266 void ccp_pci_exit(void);
268 int ccp_platform_init(void);
269 void ccp_platform_exit(void);
271 struct ccp_device *ccp_alloc_struct(struct device *dev);
272 int ccp_init(struct ccp_device *ccp);
273 void ccp_destroy(struct ccp_device *ccp);
274 bool ccp_queues_suspended(struct ccp_device *ccp);
276 irqreturn_t ccp_irq_handler(int irq, void *data);
278 int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);