drivers/crypto/hifn_795x.c

   1 /*
   2  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/mod_devicetable.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/crypto.h>
  31
  32 #include <crypto/algapi.h>
  33 #include <crypto/des.h>
  34
  35 #include <asm/kmap_types.h>
  36
  37 #undef dprintk
  38
  39 #define HIFN_TEST
  40 //#define HIFN_DEBUG
  41
  42 #ifdef HIFN_DEBUG
  43 #define dprintk(f, a...)        printk(f, ##a)
  44 #else
  45 #define dprintk(f, a...)        do {} while (0)
  46 #endif
  47
  48 static atomic_t hifn_dev_number;
  49
  50 #define ACRYPTO_OP_DECRYPT      0
  51 #define ACRYPTO_OP_ENCRYPT      1
  52 #define ACRYPTO_OP_HMAC         2
  53 #define ACRYPTO_OP_RNG          3
  54
  55 #define ACRYPTO_MODE_ECB                0
  56 #define ACRYPTO_MODE_CBC                1
  57 #define ACRYPTO_MODE_CFB                2
  58 #define ACRYPTO_MODE_OFB                3
  59
  60 #define ACRYPTO_TYPE_AES_128    0
  61 #define ACRYPTO_TYPE_AES_192    1
  62 #define ACRYPTO_TYPE_AES_256    2
  63 #define ACRYPTO_TYPE_3DES       3
  64 #define ACRYPTO_TYPE_DES        4
  65
  66 #define PCI_VENDOR_ID_HIFN              0x13A3
  67 #define PCI_DEVICE_ID_HIFN_7955         0x0020
  68 #define PCI_DEVICE_ID_HIFN_7956         0x001d
  69
  70 /* I/O region sizes */
  71
  72 #define HIFN_BAR0_SIZE                  0x1000
  73 #define HIFN_BAR1_SIZE                  0x2000
  74 #define HIFN_BAR2_SIZE                  0x8000
  75
  76 /* DMA registres */
  77
  78 #define HIFN_DMA_CRA                    0x0C    /* DMA Command Ring Address */
  79 #define HIFN_DMA_SDRA                   0x1C    /* DMA Source Data Ring Address */
  80 #define HIFN_DMA_RRA                    0x2C    /* DMA Result Ring Address */
  81 #define HIFN_DMA_DDRA                   0x3C    /* DMA Destination Data Ring Address */
  82 #define HIFN_DMA_STCTL                  0x40    /* DMA Status and Control */
  83 #define HIFN_DMA_INTREN                 0x44    /* DMA Interrupt Enable */
  84 #define HIFN_DMA_CFG1                   0x48    /* DMA Configuration #1 */
  85 #define HIFN_DMA_CFG2                   0x6C    /* DMA Configuration #2 */
  86 #define HIFN_CHIP_ID                    0x98    /* Chip ID */
  87
  88 /*
  89  * Processing Unit Registers (offset from BASEREG0)
  90  */
  91 #define HIFN_0_PUDATA           0x00    /* Processing Unit Data */
  92 #define HIFN_0_PUCTRL           0x04    /* Processing Unit Control */
  93 #define HIFN_0_PUISR            0x08    /* Processing Unit Interrupt Status */
  94 #define HIFN_0_PUCNFG           0x0c    /* Processing Unit Configuration */
  95 #define HIFN_0_PUIER            0x10    /* Processing Unit Interrupt Enable */
  96 #define HIFN_0_PUSTAT           0x14    /* Processing Unit Status/Chip ID */
  97 #define HIFN_0_FIFOSTAT         0x18    /* FIFO Status */
  98 #define HIFN_0_FIFOCNFG         0x1c    /* FIFO Configuration */
  99 #define HIFN_0_SPACESIZE        0x20    /* Register space size */
 100
 101 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
 102 #define HIFN_PUCTRL_CLRSRCFIFO  0x0010  /* clear source fifo */
 103 #define HIFN_PUCTRL_STOP        0x0008  /* stop pu */
 104 #define HIFN_PUCTRL_LOCKRAM     0x0004  /* lock ram */
 105 #define HIFN_PUCTRL_DMAENA      0x0002  /* enable dma */
 106 #define HIFN_PUCTRL_RESET       0x0001  /* Reset processing unit */
 107
 108 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
 109 #define HIFN_PUISR_CMDINVAL     0x8000  /* Invalid command interrupt */
 110 #define HIFN_PUISR_DATAERR      0x4000  /* Data error interrupt */
 111 #define HIFN_PUISR_SRCFIFO      0x2000  /* Source FIFO ready interrupt */
 112 #define HIFN_PUISR_DSTFIFO      0x1000  /* Destination FIFO ready interrupt */
 113 #define HIFN_PUISR_DSTOVER      0x0200  /* Destination overrun interrupt */
 114 #define HIFN_PUISR_SRCCMD       0x0080  /* Source command interrupt */
 115 #define HIFN_PUISR_SRCCTX       0x0040  /* Source context interrupt */
 116 #define HIFN_PUISR_SRCDATA      0x0020  /* Source data interrupt */
 117 #define HIFN_PUISR_DSTDATA      0x0010  /* Destination data interrupt */
 118 #define HIFN_PUISR_DSTRESULT    0x0004  /* Destination result interrupt */
 119
 120 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
 121 #define HIFN_PUCNFG_DRAMMASK    0xe000  /* DRAM size mask */
 122 #define HIFN_PUCNFG_DSZ_256K    0x0000  /* 256k dram */
 123 #define HIFN_PUCNFG_DSZ_512K    0x2000  /* 512k dram */
 124 #define HIFN_PUCNFG_DSZ_1M      0x4000  /* 1m dram */
 125 #define HIFN_PUCNFG_DSZ_2M      0x6000  /* 2m dram */
 126 #define HIFN_PUCNFG_DSZ_4M      0x8000  /* 4m dram */
 127 #define HIFN_PUCNFG_DSZ_8M      0xa000  /* 8m dram */
 128 #define HIFN_PUNCFG_DSZ_16M     0xc000  /* 16m dram */
 129 #define HIFN_PUCNFG_DSZ_32M     0xe000  /* 32m dram */
 130 #define HIFN_PUCNFG_DRAMREFRESH 0x1800  /* DRAM refresh rate mask */
 131 #define HIFN_PUCNFG_DRFR_512    0x0000  /* 512 divisor of ECLK */
 132 #define HIFN_PUCNFG_DRFR_256    0x0800  /* 256 divisor of ECLK */
 133 #define HIFN_PUCNFG_DRFR_128    0x1000  /* 128 divisor of ECLK */
 134 #define HIFN_PUCNFG_TCALLPHASES 0x0200  /* your guess is as good as mine... */
 135 #define HIFN_PUCNFG_TCDRVTOTEM  0x0100  /* your guess is as good as mine... */
 136 #define HIFN_PUCNFG_BIGENDIAN   0x0080  /* DMA big endian mode */
 137 #define HIFN_PUCNFG_BUS32       0x0040  /* Bus width 32bits */
 138 #define HIFN_PUCNFG_BUS16       0x0000  /* Bus width 16 bits */
 139 #define HIFN_PUCNFG_CHIPID      0x0020  /* Allow chipid from PUSTAT */
 140 #define HIFN_PUCNFG_DRAM        0x0010  /* Context RAM is DRAM */
 141 #define HIFN_PUCNFG_SRAM        0x0000  /* Context RAM is SRAM */
 142 #define HIFN_PUCNFG_COMPSING    0x0004  /* Enable single compression context */
 143 #define HIFN_PUCNFG_ENCCNFG     0x0002  /* Encryption configuration */
 144
 145 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
 146 #define HIFN_PUIER_CMDINVAL     0x8000  /* Invalid command interrupt */
 147 #define HIFN_PUIER_DATAERR      0x4000  /* Data error interrupt */
 148 #define HIFN_PUIER_SRCFIFO      0x2000  /* Source FIFO ready interrupt */
 149 #define HIFN_PUIER_DSTFIFO      0x1000  /* Destination FIFO ready interrupt */
 150 #define HIFN_PUIER_DSTOVER      0x0200  /* Destination overrun interrupt */
 151 #define HIFN_PUIER_SRCCMD       0x0080  /* Source command interrupt */
 152 #define HIFN_PUIER_SRCCTX       0x0040  /* Source context interrupt */
 153 #define HIFN_PUIER_SRCDATA      0x0020  /* Source data interrupt */
 154 #define HIFN_PUIER_DSTDATA      0x0010  /* Destination data interrupt */
 155 #define HIFN_PUIER_DSTRESULT    0x0004  /* Destination result interrupt */
 156
 157 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
 158 #define HIFN_PUSTAT_CMDINVAL    0x8000  /* Invalid command interrupt */
 159 #define HIFN_PUSTAT_DATAERR     0x4000  /* Data error interrupt */
 160 #define HIFN_PUSTAT_SRCFIFO     0x2000  /* Source FIFO ready interrupt */
 161 #define HIFN_PUSTAT_DSTFIFO     0x1000  /* Destination FIFO ready interrupt */
 162 #define HIFN_PUSTAT_DSTOVER     0x0200  /* Destination overrun interrupt */
 163 #define HIFN_PUSTAT_SRCCMD      0x0080  /* Source command interrupt */
 164 #define HIFN_PUSTAT_SRCCTX      0x0040  /* Source context interrupt */
 165 #define HIFN_PUSTAT_SRCDATA     0x0020  /* Source data interrupt */
 166 #define HIFN_PUSTAT_DSTDATA     0x0010  /* Destination data interrupt */
 167 #define HIFN_PUSTAT_DSTRESULT   0x0004  /* Destination result interrupt */
 168 #define HIFN_PUSTAT_CHIPREV     0x00ff  /* Chip revision mask */
 169 #define HIFN_PUSTAT_CHIPENA     0xff00  /* Chip enabled mask */
 170 #define HIFN_PUSTAT_ENA_2       0x1100  /* Level 2 enabled */
 171 #define HIFN_PUSTAT_ENA_1       0x1000  /* Level 1 enabled */
 172 #define HIFN_PUSTAT_ENA_0       0x3000  /* Level 0 enabled */
 173 #define HIFN_PUSTAT_REV_2       0x0020  /* 7751 PT6/2 */
 174 #define HIFN_PUSTAT_REV_3       0x0030  /* 7751 PT6/3 */
 175
 176 /* FIFO Status Register (HIFN_0_FIFOSTAT) */
 177 #define HIFN_FIFOSTAT_SRC       0x7f00  /* Source FIFO available */
 178 #define HIFN_FIFOSTAT_DST       0x007f  /* Destination FIFO available */
 179
 180 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
 181 #define HIFN_FIFOCNFG_THRESHOLD 0x0400  /* must be written as 1 */
 182
 183 /*
 184  * DMA Interface Registers (offset from BASEREG1)
 185  */
 186 #define HIFN_1_DMA_CRAR         0x0c    /* DMA Command Ring Address */
 187 #define HIFN_1_DMA_SRAR         0x1c    /* DMA Source Ring Address */
 188 #define HIFN_1_DMA_RRAR         0x2c    /* DMA Result Ring Address */
 189 #define HIFN_1_DMA_DRAR         0x3c    /* DMA Destination Ring Address */
 190 #define HIFN_1_DMA_CSR          0x40    /* DMA Status and Control */
 191 #define HIFN_1_DMA_IER          0x44    /* DMA Interrupt Enable */
 192 #define HIFN_1_DMA_CNFG         0x48    /* DMA Configuration */
 193 #define HIFN_1_PLL              0x4c    /* 795x: PLL config */
 194 #define HIFN_1_7811_RNGENA      0x60    /* 7811: rng enable */
 195 #define HIFN_1_7811_RNGCFG      0x64    /* 7811: rng config */
 196 #define HIFN_1_7811_RNGDAT      0x68    /* 7811: rng data */
 197 #define HIFN_1_7811_RNGSTS      0x6c    /* 7811: rng status */
 198 #define HIFN_1_7811_MIPSRST     0x94    /* 7811: MIPS reset */
 199 #define HIFN_1_REVID            0x98    /* Revision ID */
 200 #define HIFN_1_UNLOCK_SECRET1   0xf4
 201 #define HIFN_1_UNLOCK_SECRET2   0xfc
 202 #define HIFN_1_PUB_RESET        0x204   /* Public/RNG Reset */
 203 #define HIFN_1_PUB_BASE         0x300   /* Public Base Address */
 204 #define HIFN_1_PUB_OPLEN        0x304   /* Public Operand Length */
 205 #define HIFN_1_PUB_OP           0x308   /* Public Operand */
 206 #define HIFN_1_PUB_STATUS       0x30c   /* Public Status */
 207 #define HIFN_1_PUB_IEN          0x310   /* Public Interrupt enable */
 208 #define HIFN_1_RNG_CONFIG       0x314   /* RNG config */
 209 #define HIFN_1_RNG_DATA         0x318   /* RNG data */
 210 #define HIFN_1_PUB_MEM          0x400   /* start of Public key memory */
 211 #define HIFN_1_PUB_MEMEND       0xbff   /* end of Public key memory */
 212
 213 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
 214 #define HIFN_DMACSR_D_CTRLMASK  0xc0000000      /* Destinition Ring Control */
 215 #define HIFN_DMACSR_D_CTRL_NOP  0x00000000      /* Dest. Control: no-op */
 216 #define HIFN_DMACSR_D_CTRL_DIS  0x40000000      /* Dest. Control: disable */
 217 #define HIFN_DMACSR_D_CTRL_ENA  0x80000000      /* Dest. Control: enable */
 218 #define HIFN_DMACSR_D_ABORT     0x20000000      /* Destinition Ring PCIAbort */
 219 #define HIFN_DMACSR_D_DONE      0x10000000      /* Destinition Ring Done */
 220 #define HIFN_DMACSR_D_LAST      0x08000000      /* Destinition Ring Last */
 221 #define HIFN_DMACSR_D_WAIT      0x04000000      /* Destinition Ring Waiting */
 222 #define HIFN_DMACSR_D_OVER      0x02000000      /* Destinition Ring Overflow */
 223 #define HIFN_DMACSR_R_CTRL      0x00c00000      /* Result Ring Control */
 224 #define HIFN_DMACSR_R_CTRL_NOP  0x00000000      /* Result Control: no-op */
 225 #define HIFN_DMACSR_R_CTRL_DIS  0x00400000      /* Result Control: disable */
 226 #define HIFN_DMACSR_R_CTRL_ENA  0x00800000      /* Result Control: enable */
 227 #define HIFN_DMACSR_R_ABORT     0x00200000      /* Result Ring PCI Abort */
 228 #define HIFN_DMACSR_R_DONE      0x00100000      /* Result Ring Done */
 229 #define HIFN_DMACSR_R_LAST      0x00080000      /* Result Ring Last */
 230 #define HIFN_DMACSR_R_WAIT      0x00040000      /* Result Ring Waiting */
 231 #define HIFN_DMACSR_R_OVER      0x00020000      /* Result Ring Overflow */
 232 #define HIFN_DMACSR_S_CTRL      0x0000c000      /* Source Ring Control */
 233 #define HIFN_DMACSR_S_CTRL_NOP  0x00000000      /* Source Control: no-op */
 234 #define HIFN_DMACSR_S_CTRL_DIS  0x00004000      /* Source Control: disable */
 235 #define HIFN_DMACSR_S_CTRL_ENA  0x00008000      /* Source Control: enable */
 236 #define HIFN_DMACSR_S_ABORT     0x00002000      /* Source Ring PCI Abort */
 237 #define HIFN_DMACSR_S_DONE      0x00001000      /* Source Ring Done */
 238 #define HIFN_DMACSR_S_LAST      0x00000800      /* Source Ring Last */
 239 #define HIFN_DMACSR_S_WAIT      0x00000400      /* Source Ring Waiting */
 240 #define HIFN_DMACSR_ILLW        0x00000200      /* Illegal write (7811 only) */
 241 #define HIFN_DMACSR_ILLR        0x00000100      /* Illegal read (7811 only) */
 242 #define HIFN_DMACSR_C_CTRL      0x000000c0      /* Command Ring Control */
 243 #define HIFN_DMACSR_C_CTRL_NOP  0x00000000      /* Command Control: no-op */
 244 #define HIFN_DMACSR_C_CTRL_DIS  0x00000040      /* Command Control: disable */
 245 #define HIFN_DMACSR_C_CTRL_ENA  0x00000080      /* Command Control: enable */
 246 #define HIFN_DMACSR_C_ABORT     0x00000020      /* Command Ring PCI Abort */
 247 #define HIFN_DMACSR_C_DONE      0x00000010      /* Command Ring Done */
 248 #define HIFN_DMACSR_C_LAST      0x00000008      /* Command Ring Last */
 249 #define HIFN_DMACSR_C_WAIT      0x00000004      /* Command Ring Waiting */
 250 #define HIFN_DMACSR_PUBDONE     0x00000002      /* Public op done (7951 only) */
 251 #define HIFN_DMACSR_ENGINE      0x00000001      /* Command Ring Engine IRQ */
 252
 253 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
 254 #define HIFN_DMAIER_D_ABORT     0x20000000      /* Destination Ring PCIAbort */
 255 #define HIFN_DMAIER_D_DONE      0x10000000      /* Destination Ring Done */
 256 #define HIFN_DMAIER_D_LAST      0x08000000      /* Destination Ring Last */
 257 #define HIFN_DMAIER_D_WAIT      0x04000000      /* Destination Ring Waiting */
 258 #define HIFN_DMAIER_D_OVER      0x02000000      /* Destination Ring Overflow */
 259 #define HIFN_DMAIER_R_ABORT     0x00200000      /* Result Ring PCI Abort */
 260 #define HIFN_DMAIER_R_DONE      0x00100000      /* Result Ring Done */
 261 #define HIFN_DMAIER_R_LAST      0x00080000      /* Result Ring Last */
 262 #define HIFN_DMAIER_R_WAIT      0x00040000      /* Result Ring Waiting */
 263 #define HIFN_DMAIER_R_OVER      0x00020000      /* Result Ring Overflow */
 264 #define HIFN_DMAIER_S_ABORT     0x00002000      /* Source Ring PCI Abort */
 265 #define HIFN_DMAIER_S_DONE      0x00001000      /* Source Ring Done */
 266 #define HIFN_DMAIER_S_LAST      0x00000800      /* Source Ring Last */
 267 #define HIFN_DMAIER_S_WAIT      0x00000400      /* Source Ring Waiting */
 268 #define HIFN_DMAIER_ILLW        0x00000200      /* Illegal write (7811 only) */
 269 #define HIFN_DMAIER_ILLR        0x00000100      /* Illegal read (7811 only) */
 270 #define HIFN_DMAIER_C_ABORT     0x00000020      /* Command Ring PCI Abort */
 271 #define HIFN_DMAIER_C_DONE      0x00000010      /* Command Ring Done */
 272 #define HIFN_DMAIER_C_LAST      0x00000008      /* Command Ring Last */
 273 #define HIFN_DMAIER_C_WAIT      0x00000004      /* Command Ring Waiting */
 274 #define HIFN_DMAIER_PUBDONE     0x00000002      /* public op done (7951 only) */
 275 #define HIFN_DMAIER_ENGINE      0x00000001      /* Engine IRQ */
 276
 277 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
 278 #define HIFN_DMACNFG_BIGENDIAN  0x10000000      /* big endian mode */
 279 #define HIFN_DMACNFG_POLLFREQ   0x00ff0000      /* Poll frequency mask */
 280 #define HIFN_DMACNFG_UNLOCK     0x00000800
 281 #define HIFN_DMACNFG_POLLINVAL  0x00000700      /* Invalid Poll Scalar */
 282 #define HIFN_DMACNFG_LAST       0x00000010      /* Host control LAST bit */
 283 #define HIFN_DMACNFG_MODE       0x00000004      /* DMA mode */
 284 #define HIFN_DMACNFG_DMARESET   0x00000002      /* DMA Reset # */
 285 #define HIFN_DMACNFG_MSTRESET   0x00000001      /* Master Reset # */
 286
 287 #define HIFN_PLL_7956           0x00001d18      /* 7956 PLL config value */
 288
 289 /* Public key reset register (HIFN_1_PUB_RESET) */
 290 #define HIFN_PUBRST_RESET       0x00000001      /* reset public/rng unit */
 291
 292 /* Public base address register (HIFN_1_PUB_BASE) */
 293 #define HIFN_PUBBASE_ADDR       0x00003fff      /* base address */
 294
 295 /* Public operand length register (HIFN_1_PUB_OPLEN) */
 296 #define HIFN_PUBOPLEN_MOD_M     0x0000007f      /* modulus length mask */
 297 #define HIFN_PUBOPLEN_MOD_S     0               /* modulus length shift */
 298 #define HIFN_PUBOPLEN_EXP_M     0x0003ff80      /* exponent length mask */
 299 #define HIFN_PUBOPLEN_EXP_S     7               /* exponent lenght shift */
 300 #define HIFN_PUBOPLEN_RED_M     0x003c0000      /* reducend length mask */
 301 #define HIFN_PUBOPLEN_RED_S     18              /* reducend length shift */
 302
 303 /* Public operation register (HIFN_1_PUB_OP) */
 304 #define HIFN_PUBOP_AOFFSET_M    0x0000007f      /* A offset mask */
 305 #define HIFN_PUBOP_AOFFSET_S    0               /* A offset shift */
 306 #define HIFN_PUBOP_BOFFSET_M    0x00000f80      /* B offset mask */
 307 #define HIFN_PUBOP_BOFFSET_S    7               /* B offset shift */
 308 #define HIFN_PUBOP_MOFFSET_M    0x0003f000      /* M offset mask */
 309 #define HIFN_PUBOP_MOFFSET_S    12              /* M offset shift */
 310 #define HIFN_PUBOP_OP_MASK      0x003c0000      /* Opcode: */
 311 #define HIFN_PUBOP_OP_NOP       0x00000000      /*  NOP */
 312 #define HIFN_PUBOP_OP_ADD       0x00040000      /*  ADD */
 313 #define HIFN_PUBOP_OP_ADDC      0x00080000      /*  ADD w/carry */
 314 #define HIFN_PUBOP_OP_SUB       0x000c0000      /*  SUB */
 315 #define HIFN_PUBOP_OP_SUBC      0x00100000      /*  SUB w/carry */
 316 #define HIFN_PUBOP_OP_MODADD    0x00140000      /*  Modular ADD */
 317 #define HIFN_PUBOP_OP_MODSUB    0x00180000      /*  Modular SUB */
 318 #define HIFN_PUBOP_OP_INCA      0x001c0000      /*  INC A */
 319 #define HIFN_PUBOP_OP_DECA      0x00200000      /*  DEC A */
 320 #define HIFN_PUBOP_OP_MULT      0x00240000      /*  MULT */
 321 #define HIFN_PUBOP_OP_MODMULT   0x00280000      /*  Modular MULT */
 322 #define HIFN_PUBOP_OP_MODRED    0x002c0000      /*  Modular RED */
 323 #define HIFN_PUBOP_OP_MODEXP    0x00300000      /*  Modular EXP */
 324
 325 /* Public status register (HIFN_1_PUB_STATUS) */
 326 #define HIFN_PUBSTS_DONE        0x00000001      /* operation done */
 327 #define HIFN_PUBSTS_CARRY       0x00000002      /* carry */
 328
 329 /* Public interrupt enable register (HIFN_1_PUB_IEN) */
 330 #define HIFN_PUBIEN_DONE        0x00000001      /* operation done interrupt */
 331
 332 /* Random number generator config register (HIFN_1_RNG_CONFIG) */
 333 #define HIFN_RNGCFG_ENA         0x00000001      /* enable rng */
 334
 335 #define HIFN_NAMESIZE                   32
 336 #define HIFN_MAX_RESULT_ORDER           5
 337
 338 #define HIFN_D_CMD_RSIZE                24*4
 339 #define HIFN_D_SRC_RSIZE                80*4
 340 #define HIFN_D_DST_RSIZE                80*4
 341 #define HIFN_D_RES_RSIZE                24*4
 342
 343 #define HIFN_QUEUE_LENGTH               HIFN_D_CMD_RSIZE-5
 344
 345 #define AES_MIN_KEY_SIZE                16
 346 #define AES_MAX_KEY_SIZE                32
 347
 348 #define HIFN_DES_KEY_LENGTH             8
 349 #define HIFN_3DES_KEY_LENGTH            24
 350 #define HIFN_MAX_CRYPT_KEY_LENGTH       AES_MAX_KEY_SIZE
 351 #define HIFN_IV_LENGTH                  8
 352 #define HIFN_AES_IV_LENGTH              16
 353 #define HIFN_MAX_IV_LENGTH              HIFN_AES_IV_LENGTH
 354
 355 #define HIFN_MAC_KEY_LENGTH             64
 356 #define HIFN_MD5_LENGTH                 16
 357 #define HIFN_SHA1_LENGTH                20
 358 #define HIFN_MAC_TRUNC_LENGTH           12
 359
 360 #define HIFN_MAX_COMMAND                (8 + 8 + 8 + 64 + 260)
 361 #define HIFN_MAX_RESULT                 (8 + 4 + 4 + 20 + 4)
 362 #define HIFN_USED_RESULT                12
 363
 364 struct hifn_desc
 365 {
 366         volatile u32            l;
 367         volatile u32            p;
 368 };
 369
 370 struct hifn_dma {
 371         struct hifn_desc        cmdr[HIFN_D_CMD_RSIZE+1];
 372         struct hifn_desc        srcr[HIFN_D_SRC_RSIZE+1];
 373         struct hifn_desc        dstr[HIFN_D_DST_RSIZE+1];
 374         struct hifn_desc        resr[HIFN_D_RES_RSIZE+1];
 375
 376         u8                      command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
 377         u8                      result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
 378
 379         u64                     test_src, test_dst;
 380
 381         /*
 382          *  Our current positions for insertion and removal from the descriptor
 383          *  rings.
 384          */
 385         volatile int            cmdi, srci, dsti, resi;
 386         volatile int            cmdu, srcu, dstu, resu;
 387         int                     cmdk, srck, dstk, resk;
 388 };
 389
 390 #define HIFN_FLAG_CMD_BUSY      (1<<0)
 391 #define HIFN_FLAG_SRC_BUSY      (1<<1)
 392 #define HIFN_FLAG_DST_BUSY      (1<<2)
 393 #define HIFN_FLAG_RES_BUSY      (1<<3)
 394 #define HIFN_FLAG_OLD_KEY       (1<<4)
 395
 396 #define HIFN_DEFAULT_ACTIVE_NUM 5
 397
 398 struct hifn_device
 399 {
 400         char                    name[HIFN_NAMESIZE];
 401
 402         int                     irq;
 403
 404         struct pci_dev          *pdev;
 405         void __iomem            *bar[3];
 406
 407         unsigned long           result_mem;
 408         dma_addr_t              dst;
 409
 410         void                    *desc_virt;
 411         dma_addr_t              desc_dma;
 412
 413         u32                     dmareg;
 414
 415         void                    *sa[HIFN_D_RES_RSIZE];
 416
 417         spinlock_t              lock;
 418
 419         void                    *priv;
 420
 421         u32                     flags;
 422         int                     active, started;
 423         struct delayed_work     work;
 424         unsigned long           reset;
 425         unsigned long           success;
 426         unsigned long           prev_success;
 427
 428         u8                      snum;
 429
 430         struct tasklet_struct   tasklet;
 431
 432         struct crypto_queue     queue;
 433         struct list_head        alg_list;
 434 };
 435
 436 #define HIFN_D_LENGTH                   0x0000ffff
 437 #define HIFN_D_NOINVALID                0x01000000
 438 #define HIFN_D_MASKDONEIRQ              0x02000000
 439 #define HIFN_D_DESTOVER                 0x04000000
 440 #define HIFN_D_OVER                     0x08000000
 441 #define HIFN_D_LAST                     0x20000000
 442 #define HIFN_D_JUMP                     0x40000000
 443 #define HIFN_D_VALID                    0x80000000
 444
 445 struct hifn_base_command
 446 {
 447         volatile u16            masks;
 448         volatile u16            session_num;
 449         volatile u16            total_source_count;
 450         volatile u16            total_dest_count;
 451 };
 452
 453 #define HIFN_BASE_CMD_COMP              0x0100  /* enable compression engine */
 454 #define HIFN_BASE_CMD_PAD               0x0200  /* enable padding engine */
 455 #define HIFN_BASE_CMD_MAC               0x0400  /* enable MAC engine */
 456 #define HIFN_BASE_CMD_CRYPT             0x0800  /* enable crypt engine */
 457 #define HIFN_BASE_CMD_DECODE            0x2000
 458 #define HIFN_BASE_CMD_SRCLEN_M          0xc000
 459 #define HIFN_BASE_CMD_SRCLEN_S          14
 460 #define HIFN_BASE_CMD_DSTLEN_M          0x3000
 461 #define HIFN_BASE_CMD_DSTLEN_S          12
 462 #define HIFN_BASE_CMD_LENMASK_HI        0x30000
 463 #define HIFN_BASE_CMD_LENMASK_LO        0x0ffff
 464
 465 /*
 466  * Structure to help build up the command data structure.
 467  */
 468 struct hifn_crypt_command
 469 {
 470         volatile u16            masks;
 471         volatile u16            header_skip;
 472         volatile u16            source_count;
 473         volatile u16            reserved;
 474 };
 475
 476 #define HIFN_CRYPT_CMD_ALG_MASK         0x0003          /* algorithm: */
 477 #define HIFN_CRYPT_CMD_ALG_DES          0x0000          /*   DES */
 478 #define HIFN_CRYPT_CMD_ALG_3DES         0x0001          /*   3DES */
 479 #define HIFN_CRYPT_CMD_ALG_RC4          0x0002          /*   RC4 */
 480 #define HIFN_CRYPT_CMD_ALG_AES          0x0003          /*   AES */
 481 #define HIFN_CRYPT_CMD_MODE_MASK        0x0018          /* Encrypt mode: */
 482 #define HIFN_CRYPT_CMD_MODE_ECB         0x0000          /*   ECB */
 483 #define HIFN_CRYPT_CMD_MODE_CBC         0x0008          /*   CBC */
 484 #define HIFN_CRYPT_CMD_MODE_CFB         0x0010          /*   CFB */
 485 #define HIFN_CRYPT_CMD_MODE_OFB         0x0018          /*   OFB */
 486 #define HIFN_CRYPT_CMD_CLR_CTX          0x0040          /* clear context */
 487 #define HIFN_CRYPT_CMD_KSZ_MASK         0x0600          /* AES key size: */
 488 #define HIFN_CRYPT_CMD_KSZ_128          0x0000          /*  128 bit */
 489 #define HIFN_CRYPT_CMD_KSZ_192          0x0200          /*  192 bit */
 490 #define HIFN_CRYPT_CMD_KSZ_256          0x0400          /*  256 bit */
 491 #define HIFN_CRYPT_CMD_NEW_KEY          0x0800          /* expect new key */
 492 #define HIFN_CRYPT_CMD_NEW_IV           0x1000          /* expect new iv */
 493 #define HIFN_CRYPT_CMD_SRCLEN_M         0xc000
 494 #define HIFN_CRYPT_CMD_SRCLEN_S         14
 495
 496 /*
 497  * Structure to help build up the command data structure.
 498  */
 499 struct hifn_mac_command
 500 {
 501         volatile u16            masks;
 502         volatile u16            header_skip;
 503         volatile u16            source_count;
 504         volatile u16            reserved;
 505 };
 506
 507 #define HIFN_MAC_CMD_ALG_MASK           0x0001
 508 #define HIFN_MAC_CMD_ALG_SHA1           0x0000
 509 #define HIFN_MAC_CMD_ALG_MD5            0x0001
 510 #define HIFN_MAC_CMD_MODE_MASK          0x000c
 511 #define HIFN_MAC_CMD_MODE_HMAC          0x0000
 512 #define HIFN_MAC_CMD_MODE_SSL_MAC       0x0004
 513 #define HIFN_MAC_CMD_MODE_HASH          0x0008
 514 #define HIFN_MAC_CMD_MODE_FULL          0x0004
 515 #define HIFN_MAC_CMD_TRUNC              0x0010
 516 #define HIFN_MAC_CMD_RESULT             0x0020
 517 #define HIFN_MAC_CMD_APPEND             0x0040
 518 #define HIFN_MAC_CMD_SRCLEN_M           0xc000
 519 #define HIFN_MAC_CMD_SRCLEN_S           14
 520
 521 /*
 522  * MAC POS IPsec initiates authentication after encryption on encodes
 523  * and before decryption on decodes.
 524  */
 525 #define HIFN_MAC_CMD_POS_IPSEC          0x0200
 526 #define HIFN_MAC_CMD_NEW_KEY            0x0800
 527
 528 struct hifn_comp_command
 529 {
 530         volatile u16            masks;
 531         volatile u16            header_skip;
 532         volatile u16            source_count;
 533         volatile u16            reserved;
 534 };
 535
 536 #define HIFN_COMP_CMD_SRCLEN_M          0xc000
 537 #define HIFN_COMP_CMD_SRCLEN_S          14
 538 #define HIFN_COMP_CMD_ONE               0x0100  /* must be one */
 539 #define HIFN_COMP_CMD_CLEARHIST         0x0010  /* clear history */
 540 #define HIFN_COMP_CMD_UPDATEHIST        0x0008  /* update history */
 541 #define HIFN_COMP_CMD_LZS_STRIP0        0x0004  /* LZS: strip zero */
 542 #define HIFN_COMP_CMD_MPPC_RESTART      0x0004  /* MPPC: restart */
 543 #define HIFN_COMP_CMD_ALG_MASK          0x0001  /* compression mode: */
 544 #define HIFN_COMP_CMD_ALG_MPPC          0x0001  /*   MPPC */
 545 #define HIFN_COMP_CMD_ALG_LZS           0x0000  /*   LZS */
 546
 547 struct hifn_base_result
 548 {
 549         volatile u16            flags;
 550         volatile u16            session;
 551         volatile u16            src_cnt;                /* 15:0 of source count */
 552         volatile u16            dst_cnt;                /* 15:0 of dest count */
 553 };
 554
 555 #define HIFN_BASE_RES_DSTOVERRUN        0x0200  /* destination overrun */
 556 #define HIFN_BASE_RES_SRCLEN_M          0xc000  /* 17:16 of source count */
 557 #define HIFN_BASE_RES_SRCLEN_S          14
 558 #define HIFN_BASE_RES_DSTLEN_M          0x3000  /* 17:16 of dest count */
 559 #define HIFN_BASE_RES_DSTLEN_S          12
 560
 561 struct hifn_comp_result
 562 {
 563         volatile u16            flags;
 564         volatile u16            crc;
 565 };
 566
 567 #define HIFN_COMP_RES_LCB_M             0xff00  /* longitudinal check byte */
 568 #define HIFN_COMP_RES_LCB_S             8
 569 #define HIFN_COMP_RES_RESTART           0x0004  /* MPPC: restart */
 570 #define HIFN_COMP_RES_ENDMARKER         0x0002  /* LZS: end marker seen */
 571 #define HIFN_COMP_RES_SRC_NOTZERO       0x0001  /* source expired */
 572
 573 struct hifn_mac_result
 574 {
 575         volatile u16            flags;
 576         volatile u16            reserved;
 577         /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
 578 };
 579
 580 #define HIFN_MAC_RES_MISCOMPARE         0x0002  /* compare failed */
 581 #define HIFN_MAC_RES_SRC_NOTZERO        0x0001  /* source expired */
 582
 583 struct hifn_crypt_result
 584 {
 585         volatile u16            flags;
 586         volatile u16            reserved;
 587 };
 588
 589 #define HIFN_CRYPT_RES_SRC_NOTZERO      0x0001  /* source expired */
 590
 591 #ifndef HIFN_POLL_FREQUENCY
 592 #define HIFN_POLL_FREQUENCY     0x1
 593 #endif
 594
 595 #ifndef HIFN_POLL_SCALAR
 596 #define HIFN_POLL_SCALAR        0x0
 597 #endif
 598
 599 #define HIFN_MAX_SEGLEN         0xffff          /* maximum dma segment len */
 600 #define HIFN_MAX_DMALEN         0x3ffff         /* maximum dma length */
 601
 602 struct hifn_crypto_alg
 603 {
 604         struct list_head        entry;
 605         struct crypto_alg       alg;
 606         struct hifn_device      *dev;
 607 };
 608
 609 #define ASYNC_SCATTERLIST_CACHE 16
 610
 611 #define ASYNC_FLAGS_MISALIGNED  (1<<0)
 612
 613 struct ablkcipher_walk
 614 {
 615         struct scatterlist      cache[ASYNC_SCATTERLIST_CACHE];
 616         u32                     flags;
 617         int                     num;
 618 };
 619
 620 struct hifn_context
 621 {
 622         u8                      key[HIFN_MAX_CRYPT_KEY_LENGTH], *iv;
 623         struct hifn_device      *dev;
 624         unsigned int            keysize, ivsize;
 625         u8                      op, type, mode, unused;
 626         struct ablkcipher_walk  walk;
 627         atomic_t                sg_num;
 628 };
 629
 630 #define crypto_alg_to_hifn(alg) container_of(alg, struct hifn_crypto_alg, alg)
 631
 632 static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg)
 633 {
 634         u32 ret;
 635
 636         ret = readl((char *)(dev->bar[0]) + reg);
 637
 638         return ret;
 639 }
 640
 641 static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg)
 642 {
 643         u32 ret;
 644
 645         ret = readl((char *)(dev->bar[1]) + reg);
 646
 647         return ret;
 648 }
 649
 650 static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val)
 651 {
 652         writel(val, (char *)(dev->bar[0]) + reg);
 653 }
 654
 655 static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)
 656 {
 657         writel(val, (char *)(dev->bar[1]) + reg);
 658 }
 659
 660 static void hifn_wait_puc(struct hifn_device *dev)
 661 {
 662         int i;
 663         u32 ret;
 664
 665         for (i=10000; i > 0; --i) {
 666                 ret = hifn_read_0(dev, HIFN_0_PUCTRL);
 667                 if (!(ret & HIFN_PUCTRL_RESET))
 668                         break;
 669
 670                 udelay(1);
 671         }
 672
 673         if (!i)
 674                 dprintk("%s: Failed to reset PUC unit.\n", dev->name);
 675 }
 676
 677 static void hifn_reset_puc(struct hifn_device *dev)
 678 {
 679         hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
 680         hifn_wait_puc(dev);
 681 }
 682
 683 static void hifn_stop_device(struct hifn_device *dev)
 684 {
 685         hifn_write_1(dev, HIFN_1_DMA_CSR,
 686                 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
 687                 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS);
 688         hifn_write_0(dev, HIFN_0_PUIER, 0);
 689         hifn_write_1(dev, HIFN_1_DMA_IER, 0);
 690 }
 691
 692 static void hifn_reset_dma(struct hifn_device *dev, int full)
 693 {
 694         hifn_stop_device(dev);
 695
 696         /*
 697          * Setting poll frequency and others to 0.
 698          */
 699         hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 700                         HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 701         mdelay(1);
 702
 703         /*
 704          * Reset DMA.
 705          */
 706         if (full) {
 707                 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
 708                 mdelay(1);
 709         } else {
 710                 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |
 711                                 HIFN_DMACNFG_MSTRESET);
 712                 hifn_reset_puc(dev);
 713         }
 714
 715         hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 716                         HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 717
 718         hifn_reset_puc(dev);
 719 }
 720
 721 static u32 hifn_next_signature(u_int32_t a, u_int cnt)
 722 {
 723         int i;
 724         u32 v;
 725
 726         for (i = 0; i < cnt; i++) {
 727
 728                 /* get the parity */
 729                 v = a & 0x80080125;
 730                 v ^= v >> 16;
 731                 v ^= v >> 8;
 732                 v ^= v >> 4;
 733                 v ^= v >> 2;
 734                 v ^= v >> 1;
 735
 736                 a = (v & 1) ^ (a << 1);
 737         }
 738
 739         return a;
 740 }
 741
 742 static struct pci2id {
 743         u_short         pci_vendor;
 744         u_short         pci_prod;
 745         char            card_id[13];
 746 } pci2id[] = {
 747         {
 748                 PCI_VENDOR_ID_HIFN,
 749                 PCI_DEVICE_ID_HIFN_7955,
 750                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 751                   0x00, 0x00, 0x00, 0x00, 0x00 }
 752         },
 753         {
 754                 PCI_VENDOR_ID_HIFN,
 755                 PCI_DEVICE_ID_HIFN_7956,
 756                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 757                   0x00, 0x00, 0x00, 0x00, 0x00 }
 758         }
 759 };
 760
 761 static int hifn_init_pubrng(struct hifn_device *dev)
 762 {
 763         int i;
 764
 765         hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
 766                         HIFN_PUBRST_RESET);
 767
 768         for (i=100; i > 0; --i) {
 769                 mdelay(1);
 770
 771                 if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0)
 772                         break;
 773         }
 774
 775         if (!i)
 776                 dprintk("Chip %s: Failed to initialise public key engine.\n",
 777                                 dev->name);
 778         else {
 779                 hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
 780                 dev->dmareg |= HIFN_DMAIER_PUBDONE;
 781                 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
 782
 783                 dprintk("Chip %s: Public key engine has been sucessfully "
 784                                 "initialised.\n", dev->name);
 785         }
 786
 787         /*
 788          * Enable RNG engine.
 789          */
 790
 791         hifn_write_1(dev, HIFN_1_RNG_CONFIG,
 792                         hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA);
 793         dprintk("Chip %s: RNG engine has been successfully initialised.\n",
 794                         dev->name);
 795
 796         return 0;
 797 }
 798
 799 static int hifn_enable_crypto(struct hifn_device *dev)
 800 {
 801         u32 dmacfg, addr;
 802         char *offtbl = NULL;
 803         int i;
 804
 805         for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) {
 806                 if (pci2id[i].pci_vendor == dev->pdev->vendor &&
 807                                 pci2id[i].pci_prod == dev->pdev->device) {
 808                         offtbl = pci2id[i].card_id;
 809                         break;
 810                 }
 811         }
 812
 813         if (offtbl == NULL) {
 814                 dprintk("Chip %s: Unknown card!\n", dev->name);
 815                 return -ENODEV;
 816         }
 817
 818         dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG);
 819
 820         hifn_write_1(dev, HIFN_1_DMA_CNFG,
 821                         HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET |
 822                         HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 823         mdelay(1);
 824         addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1);
 825         mdelay(1);
 826         hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
 827         mdelay(1);
 828
 829         for (i=0; i<12; ++i) {
 830                 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
 831                 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
 832
 833                 mdelay(1);
 834         }
 835         hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
 836
 837         dprintk("Chip %s: %s.\n", dev->name, pci_name(dev->pdev));
 838
 839         return 0;
 840 }
 841
 842 static void hifn_init_dma(struct hifn_device *dev)
 843 {
 844         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
 845         u32 dptr = dev->desc_dma;
 846         int i;
 847
 848         for (i=0; i<HIFN_D_CMD_RSIZE; ++i)
 849                 dma->cmdr[i].p = __cpu_to_le32(dptr +
 850                                 offsetof(struct hifn_dma, command_bufs[i][0]));
 851         for (i=0; i<HIFN_D_RES_RSIZE; ++i)
 852                 dma->resr[i].p = __cpu_to_le32(dptr +
 853                                 offsetof(struct hifn_dma, result_bufs[i][0]));
 854
 855         /*
 856          * Setup LAST descriptors.
 857          */
 858         dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr +
 859                         offsetof(struct hifn_dma, cmdr[0]));
 860         dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr +
 861                         offsetof(struct hifn_dma, srcr[0]));
 862         dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr +
 863                         offsetof(struct hifn_dma, dstr[0]));
 864         dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr +
 865                         offsetof(struct hifn_dma, resr[0]));
 866
 867         dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
 868         dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
 869         dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
 870 }
 871
 872 static void hifn_init_registers(struct hifn_device *dev)
 873 {
 874         u32 dptr = dev->desc_dma;
 875
 876         /* Initialization magic... */
 877         hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
 878         hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
 879         hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
 880
 881         /* write all 4 ring address registers */
 882         hifn_write_1(dev, HIFN_1_DMA_CRAR, __cpu_to_le32(dptr +
 883                                 offsetof(struct hifn_dma, cmdr[0])));
 884         hifn_write_1(dev, HIFN_1_DMA_SRAR, __cpu_to_le32(dptr +
 885                                 offsetof(struct hifn_dma, srcr[0])));
 886         hifn_write_1(dev, HIFN_1_DMA_DRAR, __cpu_to_le32(dptr +
 887                                 offsetof(struct hifn_dma, dstr[0])));
 888         hifn_write_1(dev, HIFN_1_DMA_RRAR, __cpu_to_le32(dptr +
 889                                 offsetof(struct hifn_dma, resr[0])));
 890
 891         mdelay(2);
 892 #if 0
 893         hifn_write_1(dev, HIFN_1_DMA_CSR,
 894             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
 895             HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
 896             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
 897             HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
 898             HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
 899             HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
 900             HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
 901             HIFN_DMACSR_S_WAIT |
 902             HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
 903             HIFN_DMACSR_C_WAIT |
 904             HIFN_DMACSR_ENGINE |
 905             HIFN_DMACSR_PUBDONE);
 906 #else
 907         hifn_write_1(dev, HIFN_1_DMA_CSR,
 908             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
 909             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA |
 910             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
 911             HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
 912             HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
 913             HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
 914             HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
 915             HIFN_DMACSR_S_WAIT |
 916             HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
 917             HIFN_DMACSR_C_WAIT |
 918             HIFN_DMACSR_ENGINE |
 919             HIFN_DMACSR_PUBDONE);
 920 #endif
 921         hifn_read_1(dev, HIFN_1_DMA_CSR);
 922
 923         dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
 924             HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
 925             HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
 926             HIFN_DMAIER_ENGINE;
 927         dev->dmareg &= ~HIFN_DMAIER_C_WAIT;
 928
 929         hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
 930         hifn_read_1(dev, HIFN_1_DMA_IER);
 931 #if 0
 932         hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG |
 933                     HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
 934                     HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
 935                     HIFN_PUCNFG_DRAM);
 936 #else
 937         hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342);
 938 #endif
 939         hifn_write_1(dev, HIFN_1_PLL, HIFN_PLL_7956);
 940
 941         hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
 942         hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 943             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
 944             ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
 945             ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
 946 }
 947
 948 static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf,
 949                 unsigned dlen, unsigned slen, u16 mask, u8 snum)
 950 {
 951         struct hifn_base_command *base_cmd;
 952         u8 *buf_pos = buf;
 953
 954         base_cmd = (struct hifn_base_command *)buf_pos;
 955         base_cmd->masks = __cpu_to_le16(mask);
 956         base_cmd->total_source_count =
 957                 __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO);
 958         base_cmd->total_dest_count =
 959                 __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO);
 960
 961         dlen >>= 16;
 962         slen >>= 16;
 963         base_cmd->session_num = __cpu_to_le16(snum |
 964             ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
 965             ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
 966
 967         return sizeof(struct hifn_base_command);
 968 }
 969
 970 static int hifn_setup_crypto_command(struct hifn_device *dev,
 971                 u8 *buf, unsigned dlen, unsigned slen,
 972                 u8 *key, int keylen, u8 *iv, int ivsize, u16 mode)
 973 {
 974         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
 975         struct hifn_crypt_command *cry_cmd;
 976         u8 *buf_pos = buf;
 977         u16 cmd_len;
 978
 979         cry_cmd = (struct hifn_crypt_command *)buf_pos;
 980
 981         cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff);
 982         dlen >>= 16;
 983         cry_cmd->masks = __cpu_to_le16(mode |
 984                         ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) &
 985                          HIFN_CRYPT_CMD_SRCLEN_M));
 986         cry_cmd->header_skip = 0;
 987         cry_cmd->reserved = 0;
 988
 989         buf_pos += sizeof(struct hifn_crypt_command);
 990
 991         dma->cmdu++;
 992         if (dma->cmdu > 1) {
 993                 dev->dmareg |= HIFN_DMAIER_C_WAIT;
 994                 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
 995         }
 996
 997         if (keylen) {
 998                 memcpy(buf_pos, key, keylen);
 999                 buf_pos += keylen;
1000         }
1001         if (ivsize) {
1002                 memcpy(buf_pos, iv, ivsize);
1003                 buf_pos += ivsize;
1004         }
1005
1006         cmd_len = buf_pos - buf;
1007
1008         return cmd_len;
1009 }
1010
1011 static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page,
1012                 unsigned int offset, unsigned int size)
1013 {
1014         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1015         int idx;
1016         dma_addr_t addr;
1017
1018         addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE);
1019
1020         idx = dma->srci;
1021
1022         dma->srcr[idx].p = __cpu_to_le32(addr);
1023         dma->srcr[idx].l = __cpu_to_le32(size) | HIFN_D_VALID |
1024                         HIFN_D_MASKDONEIRQ | HIFN_D_NOINVALID | HIFN_D_LAST;
1025
1026         if (++idx == HIFN_D_SRC_RSIZE) {
1027                 dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1028                                 HIFN_D_JUMP |
1029                                 HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
1030                 idx = 0;
1031         }
1032
1033         dma->srci = idx;
1034         dma->srcu++;
1035
1036         if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) {
1037                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1038                 dev->flags |= HIFN_FLAG_SRC_BUSY;
1039         }
1040
1041         return size;
1042 }
1043
1044 static void hifn_setup_res_desc(struct hifn_device *dev)
1045 {
1046         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1047
1048         dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT |
1049                         HIFN_D_VALID | HIFN_D_LAST);
1050         /*
1051          * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID |
1052          *                                      HIFN_D_LAST | HIFN_D_NOINVALID);
1053          */
1054
1055         if (++dma->resi == HIFN_D_RES_RSIZE) {
1056                 dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID |
1057                                 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
1058                 dma->resi = 0;
1059         }
1060
1061         dma->resu++;
1062
1063         if (!(dev->flags & HIFN_FLAG_RES_BUSY)) {
1064                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
1065                 dev->flags |= HIFN_FLAG_RES_BUSY;
1066         }
1067 }
1068
1069 static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page,
1070                 unsigned offset, unsigned size)
1071 {
1072         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1073         int idx;
1074         dma_addr_t addr;
1075
1076         addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE);
1077
1078         idx = dma->dsti;
1079         dma->dstr[idx].p = __cpu_to_le32(addr);
1080         dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
1081                         HIFN_D_MASKDONEIRQ | HIFN_D_NOINVALID | HIFN_D_LAST);
1082
1083         if (++idx == HIFN_D_DST_RSIZE) {
1084                 dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1085                                 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
1086                                 HIFN_D_LAST | HIFN_D_NOINVALID);
1087                 idx = 0;
1088         }
1089         dma->dsti = idx;
1090         dma->dstu++;
1091
1092         if (!(dev->flags & HIFN_FLAG_DST_BUSY)) {
1093                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
1094                 dev->flags |= HIFN_FLAG_DST_BUSY;
1095         }
1096 }
1097
1098 static int hifn_setup_dma(struct hifn_device *dev, struct page *spage, unsigned int soff,
1099                 struct page *dpage, unsigned int doff, unsigned int nbytes, void *priv,
1100                 struct hifn_context *ctx)
1101 {
1102         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1103         int cmd_len, sa_idx;
1104         u8 *buf, *buf_pos;
1105         u16 mask;
1106
1107         dprintk("%s: spage: %p, soffset: %u, dpage: %p, doffset: %u, nbytes: %u, priv: %p, ctx: %p.\n",
1108                         dev->name, spage, soff, dpage, doff, nbytes, priv, ctx);
1109
1110         sa_idx = dma->resi;
1111
1112         hifn_setup_src_desc(dev, spage, soff, nbytes);
1113
1114         buf_pos = buf = dma->command_bufs[dma->cmdi];
1115
1116         mask = 0;
1117         switch (ctx->op) {
1118                 case ACRYPTO_OP_DECRYPT:
1119                         mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE;
1120                         break;
1121                 case ACRYPTO_OP_ENCRYPT:
1122                         mask = HIFN_BASE_CMD_CRYPT;
1123                         break;
1124                 case ACRYPTO_OP_HMAC:
1125                         mask = HIFN_BASE_CMD_MAC;
1126                         break;
1127                 default:
1128                         goto err_out;
1129         }
1130
1131         buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes,
1132                         nbytes, mask, dev->snum);
1133
1134         if (ctx->op == ACRYPTO_OP_ENCRYPT || ctx->op == ACRYPTO_OP_DECRYPT) {
1135                 u16 md = 0;
1136
1137                 if (ctx->keysize)
1138                         md |= HIFN_CRYPT_CMD_NEW_KEY;
1139                 if (ctx->iv && ctx->mode != ACRYPTO_MODE_ECB)
1140                         md |= HIFN_CRYPT_CMD_NEW_IV;
1141
1142                 switch (ctx->mode) {
1143                         case ACRYPTO_MODE_ECB:
1144                                 md |= HIFN_CRYPT_CMD_MODE_ECB;
1145                                 break;
1146                         case ACRYPTO_MODE_CBC:
1147                                 md |= HIFN_CRYPT_CMD_MODE_CBC;
1148                                 break;
1149                         case ACRYPTO_MODE_CFB:
1150                                 md |= HIFN_CRYPT_CMD_MODE_CFB;
1151                                 break;
1152                         case ACRYPTO_MODE_OFB:
1153                                 md |= HIFN_CRYPT_CMD_MODE_OFB;
1154                                 break;
1155                         default:
1156                                 goto err_out;
1157                 }
1158
1159                 switch (ctx->type) {
1160                         case ACRYPTO_TYPE_AES_128:
1161                                 if (ctx->keysize != 16)
1162                                         goto err_out;
1163                                 md |= HIFN_CRYPT_CMD_KSZ_128 |
1164                                         HIFN_CRYPT_CMD_ALG_AES;
1165                                 break;
1166                         case ACRYPTO_TYPE_AES_192:
1167                                 if (ctx->keysize != 24)
1168                                         goto err_out;
1169                                 md |= HIFN_CRYPT_CMD_KSZ_192 |
1170                                         HIFN_CRYPT_CMD_ALG_AES;
1171                                 break;
1172                         case ACRYPTO_TYPE_AES_256:
1173                                 if (ctx->keysize != 32)
1174                                         goto err_out;
1175                                 md |= HIFN_CRYPT_CMD_KSZ_256 |
1176                                         HIFN_CRYPT_CMD_ALG_AES;
1177                                 break;
1178                         case ACRYPTO_TYPE_3DES:
1179                                 if (ctx->keysize != 24)
1180                                         goto err_out;
1181                                 md |= HIFN_CRYPT_CMD_ALG_3DES;
1182                                 break;
1183                         case ACRYPTO_TYPE_DES:
1184                                 if (ctx->keysize != 8)
1185                                         goto err_out;
1186                                 md |= HIFN_CRYPT_CMD_ALG_DES;
1187                                 break;
1188                         default:
1189                                 goto err_out;
1190                 }
1191
1192                 buf_pos += hifn_setup_crypto_command(dev, buf_pos,
1193                                 nbytes, nbytes, ctx->key, ctx->keysize,
1194                                 ctx->iv, ctx->ivsize, md);
1195         }
1196
1197         dev->sa[sa_idx] = priv;
1198
1199         cmd_len = buf_pos - buf;
1200         dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID |
1201                         HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
1202
1203         if (++dma->cmdi == HIFN_D_CMD_RSIZE) {
1204                 dma->cmdr[dma->cmdi].l = __cpu_to_le32(HIFN_MAX_COMMAND |
1205                         HIFN_D_VALID | HIFN_D_LAST |
1206                         HIFN_D_MASKDONEIRQ | HIFN_D_JUMP);
1207                 dma->cmdi = 0;
1208         } else
1209                 dma->cmdr[dma->cmdi-1].l |= __cpu_to_le32(HIFN_D_VALID);
1210
1211         if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) {
1212                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1213                 dev->flags |= HIFN_FLAG_CMD_BUSY;
1214         }
1215
1216         hifn_setup_dst_desc(dev, dpage, doff, nbytes);
1217         hifn_setup_res_desc(dev);
1218
1219         return 0;
1220
1221 err_out:
1222         return -EINVAL;
1223 }
1224
1225 static int ablkcipher_walk_init(struct ablkcipher_walk *w,
1226                 int num, gfp_t gfp_flags)
1227 {
1228         int i;
1229
1230         num = min(ASYNC_SCATTERLIST_CACHE, num);
1231         sg_init_table(w->cache, num);
1232
1233         w->num = 0;
1234         for (i=0; i<num; ++i) {
1235                 struct page *page = alloc_page(gfp_flags);
1236                 struct scatterlist *s;
1237
1238                 if (!page)
1239                         break;
1240
1241                 s = &w->cache[i];
1242
1243                 sg_set_page(s, page, PAGE_SIZE, 0);
1244                 w->num++;
1245         }
1246
1247         return i;
1248 }
1249
1250 static void ablkcipher_walk_exit(struct ablkcipher_walk *w)
1251 {
1252         int i;
1253
1254         for (i=0; i<w->num; ++i) {
1255                 struct scatterlist *s = &w->cache[i];
1256
1257                 __free_page(sg_page(s));
1258
1259                 s->length = 0;
1260         }
1261
1262         w->num = 0;
1263 }
1264
1265 static int ablkcipher_add(void *daddr, unsigned int *drestp, struct scatterlist *src,
1266                 unsigned int size, unsigned int *nbytesp)
1267 {
1268         unsigned int copy, drest = *drestp, nbytes = *nbytesp;
1269         int idx = 0;
1270         void *saddr;
1271
1272         if (drest < size || size > nbytes)
1273                 return -EINVAL;
1274
1275         while (size) {
1276                 copy = min(drest, src->length);
1277
1278                 saddr = kmap_atomic(sg_page(src), KM_SOFTIRQ1);
1279                 memcpy(daddr, saddr + src->offset, copy);
1280                 kunmap_atomic(saddr, KM_SOFTIRQ1);
1281
1282                 size -= copy;
1283                 drest -= copy;
1284                 nbytes -= copy;
1285                 daddr += copy;
1286
1287                 dprintk("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
1288                                 __func__, copy, size, drest, nbytes);
1289
1290                 src++;
1291                 idx++;
1292         }
1293
1294         *nbytesp = nbytes;
1295         *drestp = drest;
1296
1297         return idx;
1298 }
1299
1300 static int ablkcipher_walk(struct ablkcipher_request *req,
1301                 struct ablkcipher_walk *w)
1302 {
1303         unsigned blocksize =
1304                 crypto_ablkcipher_blocksize(crypto_ablkcipher_reqtfm(req));
1305         unsigned alignmask =
1306                 crypto_ablkcipher_alignmask(crypto_ablkcipher_reqtfm(req));
1307         struct scatterlist *src, *dst, *t;
1308         void *daddr;
1309         unsigned int nbytes = req->nbytes, offset, copy, diff;
1310         int idx, tidx, err;
1311
1312         tidx = idx = 0;
1313         offset = 0;
1314         while (nbytes) {
1315                 if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED))
1316                         return -EINVAL;
1317
1318                 src = &req->src[idx];
1319                 dst = &req->dst[idx];
1320
1321                 dprintk("\n%s: slen: %u, dlen: %u, soff: %u, doff: %u, offset: %u, "
1322                                 "blocksize: %u, nbytes: %u.\n",
1323                                 __func__, src->length, dst->length, src->offset,
1324                                 dst->offset, offset, blocksize, nbytes);
1325
1326                 if (src->length & (blocksize - 1) ||
1327                                 src->offset & (alignmask - 1) ||
1328                                 dst->length & (blocksize - 1) ||
1329                                 dst->offset & (alignmask - 1) ||
1330                                 offset) {
1331                         unsigned slen = src->length - offset;
1332                         unsigned dlen = PAGE_SIZE;
1333
1334                         t = &w->cache[idx];
1335
1336                         daddr = kmap_atomic(sg_page(t), KM_SOFTIRQ0);
1337                         err = ablkcipher_add(daddr, &dlen, src, slen, &nbytes);
1338                         if (err < 0)
1339                                 goto err_out_unmap;
1340
1341                         idx += err;
1342
1343                         copy = slen & ~(blocksize - 1);
1344                         diff = slen & (blocksize - 1);
1345
1346                         if (dlen < nbytes) {
1347                                 /*
1348                                  * Destination page does not have enough space
1349                                  * to put there additional blocksized chunk,
1350                                  * so we mark that page as containing only
1351                                  * blocksize aligned chunks:
1352                                  *      t->length = (slen & ~(blocksize - 1));
1353                                  * and increase number of bytes to be processed
1354                                  * in next chunk:
1355                                  *      nbytes += diff;
1356                                  */
1357                                 nbytes += diff;
1358
1359                                 /*
1360                                  * Temporary of course...
1361                                  * Kick author if you will catch this one.
1362                                  */
1363                                 printk(KERN_ERR "%s: dlen: %u, nbytes: %u,"
1364                                         "slen: %u, offset: %u.\n",
1365                                         __func__, dlen, nbytes, slen, offset);
1366                                 printk(KERN_ERR "%s: please contact author to fix this "
1367                                         "issue, generally you should not catch "
1368                                         "this path under any condition but who "
1369                                         "knows how did you use crypto code.\n"
1370                                         "Thank you.\n", __func__);
1371                                 BUG();
1372                         } else {
1373                                 copy += diff + nbytes;
1374
1375                                 src = &req->src[idx];
1376
1377                                 err = ablkcipher_add(daddr + slen, &dlen, src, nbytes, &nbytes);
1378                                 if (err < 0)
1379                                         goto err_out_unmap;
1380
1381                                 idx += err;
1382                         }
1383
1384                         t->length = copy;
1385                         t->offset = offset;
1386
1387                         kunmap_atomic(daddr, KM_SOFTIRQ0);
1388                 } else {
1389                         nbytes -= src->length;
1390                         idx++;
1391                 }
1392
1393                 tidx++;
1394         }
1395
1396         return tidx;
1397
1398 err_out_unmap:
1399         kunmap_atomic(daddr, KM_SOFTIRQ0);
1400         return err;
1401 }
1402
1403 static int hifn_setup_session(struct ablkcipher_request *req)
1404 {
1405         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1406         struct hifn_device *dev = ctx->dev;
1407         struct page *spage, *dpage;
1408         unsigned long soff, doff, flags;
1409         unsigned int nbytes = req->nbytes, idx = 0, len;
1410         int err = -EINVAL, sg_num;
1411         struct scatterlist *src, *dst, *t;
1412         unsigned blocksize =
1413                 crypto_ablkcipher_blocksize(crypto_ablkcipher_reqtfm(req));
1414         unsigned alignmask =
1415                 crypto_ablkcipher_alignmask(crypto_ablkcipher_reqtfm(req));
1416
1417         if (ctx->iv && !ctx->ivsize && ctx->mode != ACRYPTO_MODE_ECB)
1418                 goto err_out_exit;
1419
1420         ctx->walk.flags = 0;
1421
1422         while (nbytes) {
1423                 src = &req->src[idx];
1424                 dst = &req->dst[idx];
1425
1426                 if (src->length & (blocksize - 1) ||
1427                                 src->offset & (alignmask - 1) ||
1428                                 dst->length & (blocksize - 1) ||
1429                                 dst->offset & (alignmask - 1)) {
1430                         ctx->walk.flags |= ASYNC_FLAGS_MISALIGNED;
1431                 }
1432
1433                 nbytes -= src->length;
1434                 idx++;
1435         }
1436
1437         if (ctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1438                 err = ablkcipher_walk_init(&ctx->walk, idx, GFP_ATOMIC);
1439                 if (err < 0)
1440                         return err;
1441         }
1442
1443         nbytes = req->nbytes;
1444         idx = 0;
1445
1446         sg_num = ablkcipher_walk(req, &ctx->walk);
1447
1448         atomic_set(&ctx->sg_num, sg_num);
1449
1450         spin_lock_irqsave(&dev->lock, flags);
1451         if (dev->started + sg_num > HIFN_QUEUE_LENGTH) {
1452                 err = -EAGAIN;
1453                 goto err_out;
1454         }
1455
1456         dev->snum++;
1457         dev->started += sg_num;
1458
1459         while (nbytes) {
1460                 src = &req->src[idx];
1461                 dst = &req->dst[idx];
1462                 t = &ctx->walk.cache[idx];
1463
1464                 if (t->length) {
1465                         spage = dpage = sg_page(t);
1466                         soff = doff = 0;
1467                         len = t->length;
1468                 } else {
1469                         spage = sg_page(src);
1470                         soff = src->offset;
1471
1472                         dpage = sg_page(dst);
1473                         doff = dst->offset;
1474
1475                         len = dst->length;
1476                 }
1477
1478                 idx++;
1479
1480                 err = hifn_setup_dma(dev, spage, soff, dpage, doff, nbytes,
1481                                 req, ctx);
1482                 if (err)
1483                         goto err_out;
1484
1485                 nbytes -= len;
1486         }
1487
1488         dev->active = HIFN_DEFAULT_ACTIVE_NUM;
1489         spin_unlock_irqrestore(&dev->lock, flags);
1490
1491         return 0;
1492
1493 err_out:
1494         spin_unlock_irqrestore(&dev->lock, flags);
1495 err_out_exit:
1496         if (err && printk_ratelimit())
1497                 dprintk("%s: iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
1498                                 "type: %u, err: %d.\n",
1499                         dev->name, ctx->iv, ctx->ivsize,
1500                         ctx->key, ctx->keysize,
1501                         ctx->mode, ctx->op, ctx->type, err);
1502
1503         return err;
1504 }
1505
1506 static int hifn_test(struct hifn_device *dev, int encdec, u8 snum)
1507 {
1508         int n, err;
1509         u8 src[16];
1510         struct hifn_context ctx;
1511         u8 fips_aes_ecb_from_zero[16] = {
1512                 0x66, 0xE9, 0x4B, 0xD4,
1513                 0xEF, 0x8A, 0x2C, 0x3B,
1514                 0x88, 0x4C, 0xFA, 0x59,
1515                 0xCA, 0x34, 0x2B, 0x2E};
1516
1517         memset(src, 0, sizeof(src));
1518         memset(ctx.key, 0, sizeof(ctx.key));
1519
1520         ctx.dev = dev;
1521         ctx.keysize = 16;
1522         ctx.ivsize = 0;
1523         ctx.iv = NULL;
1524         ctx.op = (encdec)?ACRYPTO_OP_ENCRYPT:ACRYPTO_OP_DECRYPT;
1525         ctx.mode = ACRYPTO_MODE_ECB;
1526         ctx.type = ACRYPTO_TYPE_AES_128;
1527         atomic_set(&ctx.sg_num, 1);
1528
1529         err = hifn_setup_dma(dev,
1530                         virt_to_page(src), offset_in_page(src),
1531                         virt_to_page(src), offset_in_page(src),
1532                         sizeof(src), NULL, &ctx);
1533         if (err)
1534                 goto err_out;
1535
1536         msleep(200);
1537
1538         dprintk("%s: decoded: ", dev->name);
1539         for (n=0; n<sizeof(src); ++n)
1540                 dprintk("%02x ", src[n]);
1541         dprintk("\n");
1542         dprintk("%s: FIPS   : ", dev->name);
1543         for (n=0; n<sizeof(fips_aes_ecb_from_zero); ++n)
1544                 dprintk("%02x ", fips_aes_ecb_from_zero[n]);
1545         dprintk("\n");
1546
1547         if (!memcmp(src, fips_aes_ecb_from_zero, sizeof(fips_aes_ecb_from_zero))) {
1548                 printk(KERN_INFO "%s: AES 128 ECB test has been successfully "
1549                                 "passed.\n", dev->name);
1550                 return 0;
1551         }
1552
1553 err_out:
1554         printk(KERN_INFO "%s: AES 128 ECB test has been failed.\n", dev->name);
1555         return -1;
1556 }
1557
1558 static int hifn_start_device(struct hifn_device *dev)
1559 {
1560         int err;
1561
1562         hifn_reset_dma(dev, 1);
1563
1564         err = hifn_enable_crypto(dev);
1565         if (err)
1566                 return err;
1567
1568         hifn_reset_puc(dev);
1569
1570         hifn_init_dma(dev);
1571
1572         hifn_init_registers(dev);
1573
1574         hifn_init_pubrng(dev);
1575
1576         return 0;
1577 }
1578
1579 static int ablkcipher_get(void *saddr, unsigned int *srestp, unsigned int offset,
1580                 struct scatterlist *dst, unsigned int size, unsigned int *nbytesp)
1581 {
1582         unsigned int srest = *srestp, nbytes = *nbytesp, copy;
1583         void *daddr;
1584         int idx = 0;
1585
1586         if (srest < size || size > nbytes)
1587                 return -EINVAL;
1588
1589         while (size) {
1590
1591                 copy = min(dst->length, srest);
1592
1593                 daddr = kmap_atomic(sg_page(dst), KM_IRQ0);
1594                 memcpy(daddr + dst->offset + offset, saddr, copy);
1595                 kunmap_atomic(daddr, KM_IRQ0);
1596
1597                 nbytes -= copy;
1598                 size -= copy;
1599                 srest -= copy;
1600                 saddr += copy;
1601                 offset = 0;
1602
1603                 dprintk("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n",
1604                                 __func__, copy, size, srest, nbytes);
1605
1606                 dst++;
1607                 idx++;
1608         }
1609
1610         *nbytesp = nbytes;
1611         *srestp = srest;
1612
1613         return idx;
1614 }
1615
1616 static void hifn_process_ready(struct ablkcipher_request *req, int error)
1617 {
1618         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1619         struct hifn_device *dev;
1620
1621         dprintk("%s: req: %p, ctx: %p.\n", __func__, req, ctx);
1622
1623         dev = ctx->dev;
1624         dprintk("%s: req: %p, started: %d, sg_num: %d.\n",
1625                 __func__, req, dev->started, atomic_read(&ctx->sg_num));
1626
1627         if (--dev->started < 0)
1628                 BUG();
1629
1630         if (atomic_dec_and_test(&ctx->sg_num)) {
1631                 unsigned int nbytes = req->nbytes;
1632                 int idx = 0, err;
1633                 struct scatterlist *dst, *t;
1634                 void *saddr;
1635
1636                 if (ctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1637                         while (nbytes) {
1638                                 t = &ctx->walk.cache[idx];
1639                                 dst = &req->dst[idx];
1640
1641                                 dprintk("\n%s: sg_page(t): %p, t->length: %u, "
1642                                         "sg_page(dst): %p, dst->length: %u, "
1643                                         "nbytes: %u.\n",
1644                                         __func__, sg_page(t), t->length,
1645                                         sg_page(dst), dst->length, nbytes);
1646
1647                                 if (!t->length) {
1648                                         nbytes -= dst->length;
1649                                         idx++;
1650                                         continue;
1651                                 }
1652
1653                                 saddr = kmap_atomic(sg_page(t), KM_IRQ1);
1654
1655                                 err = ablkcipher_get(saddr, &t->length, t->offset,
1656                                                 dst, nbytes, &nbytes);
1657                                 if (err < 0) {
1658                                         kunmap_atomic(saddr, KM_IRQ1);
1659                                         break;
1660                                 }
1661
1662                                 idx += err;
1663                                 kunmap_atomic(saddr, KM_IRQ1);
1664                         }
1665
1666                         ablkcipher_walk_exit(&ctx->walk);
1667                 }
1668
1669                 req->base.complete(&req->base, error);
1670         }
1671 }
1672
1673 static void hifn_check_for_completion(struct hifn_device *dev, int error)
1674 {
1675         int i;
1676         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1677
1678         for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
1679                 struct hifn_desc *d = &dma->resr[i];
1680
1681                 if (!(d->l & __cpu_to_le32(HIFN_D_VALID)) && dev->sa[i]) {
1682                         dev->success++;
1683                         dev->reset = 0;
1684                         hifn_process_ready(dev->sa[i], error);
1685                         dev->sa[i] = NULL;
1686                 }
1687
1688                 if (d->l & __cpu_to_le32(HIFN_D_DESTOVER | HIFN_D_OVER))
1689                         if (printk_ratelimit())
1690                                 printk("%s: overflow detected [d: %u, o: %u] "
1691                                                 "at %d resr: l: %08x, p: %08x.\n",
1692                                         dev->name,
1693                                         !!(d->l & __cpu_to_le32(HIFN_D_DESTOVER)),
1694                                         !!(d->l & __cpu_to_le32(HIFN_D_OVER)),
1695                                         i, d->l, d->p);
1696         }
1697 }
1698
1699 static void hifn_clear_rings(struct hifn_device *dev)
1700 {
1701         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1702         int i, u;
1703
1704         dprintk("%s: ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1705                         "k: %d.%d.%d.%d.\n",
1706                         dev->name,
1707                         dma->cmdi, dma->srci, dma->dsti, dma->resi,
1708                         dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1709                         dma->cmdk, dma->srck, dma->dstk, dma->resk);
1710
1711         i = dma->resk; u = dma->resu;
1712         while (u != 0) {
1713                 if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID))
1714                         break;
1715
1716                 if (i != HIFN_D_RES_RSIZE)
1717                         u--;
1718
1719                 if (++i == (HIFN_D_RES_RSIZE + 1))
1720                         i = 0;
1721         }
1722         dma->resk = i; dma->resu = u;
1723
1724         i = dma->srck; u = dma->srcu;
1725         while (u != 0) {
1726                 if (i == HIFN_D_SRC_RSIZE)
1727                         i = 0;
1728                 if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID))
1729                         break;
1730                 i++, u--;
1731         }
1732         dma->srck = i; dma->srcu = u;
1733
1734         i = dma->cmdk; u = dma->cmdu;
1735         while (u != 0) {
1736                 if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID))
1737                         break;
1738                 if (i != HIFN_D_CMD_RSIZE)
1739                         u--;
1740                 if (++i == (HIFN_D_CMD_RSIZE + 1))
1741                         i = 0;
1742         }
1743         dma->cmdk = i; dma->cmdu = u;
1744
1745         i = dma->dstk; u = dma->dstu;
1746         while (u != 0) {
1747                 if (i == HIFN_D_DST_RSIZE)
1748                         i = 0;
1749                 if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID))
1750                         break;
1751                 i++, u--;
1752         }
1753         dma->dstk = i; dma->dstu = u;
1754
1755         dprintk("%s: ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1756                         "k: %d.%d.%d.%d.\n",
1757                         dev->name,
1758                         dma->cmdi, dma->srci, dma->dsti, dma->resi,
1759                         dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1760                         dma->cmdk, dma->srck, dma->dstk, dma->resk);
1761 }
1762
1763 static void hifn_work(struct work_struct *work)
1764 {
1765         struct delayed_work *dw = container_of(work, struct delayed_work, work);
1766         struct hifn_device *dev = container_of(dw, struct hifn_device, work);
1767         unsigned long flags;
1768         int reset = 0;
1769         u32 r = 0;
1770
1771         spin_lock_irqsave(&dev->lock, flags);
1772         if (dev->active == 0) {
1773                 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1774
1775                 if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) {
1776                         dev->flags &= ~HIFN_FLAG_CMD_BUSY;
1777                         r |= HIFN_DMACSR_C_CTRL_DIS;
1778                 }
1779                 if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) {
1780                         dev->flags &= ~HIFN_FLAG_SRC_BUSY;
1781                         r |= HIFN_DMACSR_S_CTRL_DIS;
1782                 }
1783                 if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) {
1784                         dev->flags &= ~HIFN_FLAG_DST_BUSY;
1785                         r |= HIFN_DMACSR_D_CTRL_DIS;
1786                 }
1787                 if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) {
1788                         dev->flags &= ~HIFN_FLAG_RES_BUSY;
1789                         r |= HIFN_DMACSR_R_CTRL_DIS;
1790                 }
1791                 if (r)
1792                         hifn_write_1(dev, HIFN_1_DMA_CSR, r);
1793         } else
1794                 dev->active--;
1795
1796         if (dev->prev_success == dev->success && dev->started)
1797                 reset = 1;
1798         dev->prev_success = dev->success;
1799         spin_unlock_irqrestore(&dev->lock, flags);
1800
1801         if (reset) {
1802                 dprintk("%s: r: %08x, active: %d, started: %d, "
1803                                 "success: %lu: reset: %d.\n",
1804                         dev->name, r, dev->active, dev->started,
1805                         dev->success, reset);
1806
1807                 if (++dev->reset >= 5) {
1808                         dprintk("%s: really hard reset.\n", dev->name);
1809                         hifn_reset_dma(dev, 1);
1810                         hifn_stop_device(dev);
1811                         hifn_start_device(dev);
1812                         dev->reset = 0;
1813                 }
1814
1815                 spin_lock_irqsave(&dev->lock, flags);
1816                 hifn_check_for_completion(dev, -EBUSY);
1817                 hifn_clear_rings(dev);
1818                 dev->started = 0;
1819                 spin_unlock_irqrestore(&dev->lock, flags);
1820         }
1821
1822         schedule_delayed_work(&dev->work, HZ);
1823 }
1824
1825 static irqreturn_t hifn_interrupt(int irq, void *data)
1826 {
1827         struct hifn_device *dev = (struct hifn_device *)data;
1828         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1829         u32 dmacsr, restart;
1830
1831         dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR);
1832
1833         dprintk("%s: 1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], "
1834                         "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n",
1835                 dev->name, dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi,
1836                 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1837                 dma->cmdi, dma->srci, dma->dsti, dma->resi);
1838
1839         if ((dmacsr & dev->dmareg) == 0)
1840                 return IRQ_NONE;
1841
1842         hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);
1843
1844         if (dmacsr & HIFN_DMACSR_ENGINE)
1845                 hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR));
1846         if (dmacsr & HIFN_DMACSR_PUBDONE)
1847                 hifn_write_1(dev, HIFN_1_PUB_STATUS,
1848                         hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
1849
1850         restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER);
1851         if (restart) {
1852                 u32 puisr = hifn_read_0(dev, HIFN_0_PUISR);
1853
1854                 if (printk_ratelimit())
1855                         printk("%s: overflow: r: %d, d: %d, puisr: %08x, d: %u.\n",
1856                                 dev->name, !!(dmacsr & HIFN_DMACSR_R_OVER),
1857                                 !!(dmacsr & HIFN_DMACSR_D_OVER),
1858                                 puisr, !!(puisr & HIFN_PUISR_DSTOVER));
1859                 if (!!(puisr & HIFN_PUISR_DSTOVER))
1860                         hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1861                 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |
1862                                         HIFN_DMACSR_D_OVER));
1863         }
1864
1865         restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
1866                         HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
1867         if (restart) {
1868                 if (printk_ratelimit())
1869                         printk("%s: abort: c: %d, s: %d, d: %d, r: %d.\n",
1870                                 dev->name, !!(dmacsr & HIFN_DMACSR_C_ABORT),
1871                                 !!(dmacsr & HIFN_DMACSR_S_ABORT),
1872                                 !!(dmacsr & HIFN_DMACSR_D_ABORT),
1873                                 !!(dmacsr & HIFN_DMACSR_R_ABORT));
1874                 hifn_reset_dma(dev, 1);
1875                 hifn_init_dma(dev);
1876                 hifn_init_registers(dev);
1877         }
1878
1879         if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
1880                 dprintk("%s: wait on command.\n", dev->name);
1881                 dev->dmareg &= ~(HIFN_DMAIER_C_WAIT);
1882                 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1883         }
1884
1885         tasklet_schedule(&dev->tasklet);
1886         hifn_clear_rings(dev);
1887
1888         return IRQ_HANDLED;
1889 }
1890
1891 static void hifn_flush(struct hifn_device *dev)
1892 {
1893         unsigned long flags;
1894         struct crypto_async_request *async_req;
1895         struct hifn_context *ctx;
1896         struct ablkcipher_request *req;
1897         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1898         int i;
1899
1900         spin_lock_irqsave(&dev->lock, flags);
1901         for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
1902                 struct hifn_desc *d = &dma->resr[i];
1903
1904                 if (dev->sa[i]) {
1905                         hifn_process_ready(dev->sa[i],
1906                                 (d->l & __cpu_to_le32(HIFN_D_VALID))?-ENODEV:0);
1907                 }
1908         }
1909
1910         while ((async_req = crypto_dequeue_request(&dev->queue))) {
1911                 ctx = crypto_tfm_ctx(async_req->tfm);
1912                 req = container_of(async_req, struct ablkcipher_request, base);
1913
1914                 hifn_process_ready(req, -ENODEV);
1915         }
1916         spin_unlock_irqrestore(&dev->lock, flags);
1917 }
1918
1919 static int hifn_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
1920                 unsigned int len)
1921 {
1922         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
1923         struct hifn_context *ctx = crypto_tfm_ctx(tfm);
1924         struct hifn_device *dev = ctx->dev;
1925
1926         if (len > HIFN_MAX_CRYPT_KEY_LENGTH) {
1927                 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1928                 return -1;
1929         }
1930
1931         if (len == HIFN_DES_KEY_LENGTH) {
1932                 u32 tmp[DES_EXPKEY_WORDS];
1933                 int ret = des_ekey(tmp, key);
1934
1935                 if (unlikely(ret == 0) && (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
1936                         tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
1937                         return -EINVAL;
1938                 }
1939         }
1940
1941         dev->flags &= ~HIFN_FLAG_OLD_KEY;
1942
1943         memcpy(ctx->key, key, len);
1944         ctx->keysize = len;
1945
1946         return 0;
1947 }
1948
1949 static int hifn_handle_req(struct ablkcipher_request *req)
1950 {
1951         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1952         struct hifn_device *dev = ctx->dev;
1953         int err = -EAGAIN;
1954
1955         if (dev->started + DIV_ROUND_UP(req->nbytes, PAGE_SIZE) <= HIFN_QUEUE_LENGTH)
1956                 err = hifn_setup_session(req);
1957
1958         if (err == -EAGAIN) {
1959                 unsigned long flags;
1960
1961                 spin_lock_irqsave(&dev->lock, flags);
1962                 err = ablkcipher_enqueue_request(&dev->queue, req);
1963                 spin_unlock_irqrestore(&dev->lock, flags);
1964         }
1965
1966         return err;
1967 }
1968
1969 static int hifn_setup_crypto_req(struct ablkcipher_request *req, u8 op,
1970                 u8 type, u8 mode)
1971 {
1972         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1973         unsigned ivsize;
1974
1975         ivsize = crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req));
1976
1977         if (req->info && mode != ACRYPTO_MODE_ECB) {
1978                 if (type == ACRYPTO_TYPE_AES_128)
1979                         ivsize = HIFN_AES_IV_LENGTH;
1980                 else if (type == ACRYPTO_TYPE_DES)
1981                         ivsize = HIFN_DES_KEY_LENGTH;
1982                 else if (type == ACRYPTO_TYPE_3DES)
1983                         ivsize = HIFN_3DES_KEY_LENGTH;
1984         }
1985
1986         if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) {
1987                 if (ctx->keysize == 24)
1988                         type = ACRYPTO_TYPE_AES_192;
1989                 else if (ctx->keysize == 32)
1990                         type = ACRYPTO_TYPE_AES_256;
1991         }
1992
1993         ctx->op = op;
1994         ctx->mode = mode;
1995         ctx->type = type;
1996         ctx->iv = req->info;
1997         ctx->ivsize = ivsize;
1998
1999         /*
2000          * HEAVY TODO: needs to kick Herbert XU to write documentation.
2001          * HEAVY TODO: needs to kick Herbert XU to write documentation.
2002          * HEAVY TODO: needs to kick Herbert XU to write documentation.
2003          */
2004
2005         return hifn_handle_req(req);
2006 }
2007
2008 static int hifn_process_queue(struct hifn_device *dev)
2009 {
2010         struct crypto_async_request *async_req;
2011         struct hifn_context *ctx;
2012         struct ablkcipher_request *req;
2013         unsigned long flags;
2014         int err = 0;
2015
2016         while (dev->started < HIFN_QUEUE_LENGTH) {
2017                 spin_lock_irqsave(&dev->lock, flags);
2018                 async_req = crypto_dequeue_request(&dev->queue);
2019                 spin_unlock_irqrestore(&dev->lock, flags);
2020
2021                 if (!async_req)
2022                         break;
2023
2024                 ctx = crypto_tfm_ctx(async_req->tfm);
2025                 req = container_of(async_req, struct ablkcipher_request, base);
2026
2027                 err = hifn_handle_req(req);
2028                 if (err)
2029                         break;
2030         }
2031
2032         return err;
2033 }
2034
2035 static int hifn_setup_crypto(struct ablkcipher_request *req, u8 op,
2036                 u8 type, u8 mode)
2037 {
2038         int err;
2039         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2040         struct hifn_device *dev = ctx->dev;
2041
2042         err = hifn_setup_crypto_req(req, op, type, mode);
2043         if (err)
2044                 return err;
2045
2046         if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
2047                 err = hifn_process_queue(dev);
2048
2049         return err;
2050 }
2051
2052 /*
2053  * AES ecryption functions.
2054  */
2055 static inline int hifn_encrypt_aes_ecb(struct ablkcipher_request *req)
2056 {
2057         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2058                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2059 }
2060 static inline int hifn_encrypt_aes_cbc(struct ablkcipher_request *req)
2061 {
2062         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2063                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2064 }
2065 static inline int hifn_encrypt_aes_cfb(struct ablkcipher_request *req)
2066 {
2067         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2068                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2069 }
2070 static inline int hifn_encrypt_aes_ofb(struct ablkcipher_request *req)
2071 {
2072         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2073                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2074 }
2075
2076 /*
2077  * AES decryption functions.
2078  */
2079 static inline int hifn_decrypt_aes_ecb(struct ablkcipher_request *req)
2080 {
2081         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2082                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2083 }
2084 static inline int hifn_decrypt_aes_cbc(struct ablkcipher_request *req)
2085 {
2086         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2087                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2088 }
2089 static inline int hifn_decrypt_aes_cfb(struct ablkcipher_request *req)
2090 {
2091         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2092                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2093 }
2094 static inline int hifn_decrypt_aes_ofb(struct ablkcipher_request *req)
2095 {
2096         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2097                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2098 }
2099
2100 /*
2101  * DES ecryption functions.
2102  */
2103 static inline int hifn_encrypt_des_ecb(struct ablkcipher_request *req)
2104 {
2105         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2106                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2107 }
2108 static inline int hifn_encrypt_des_cbc(struct ablkcipher_request *req)
2109 {
2110         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2111                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2112 }
2113 static inline int hifn_encrypt_des_cfb(struct ablkcipher_request *req)
2114 {
2115         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2116                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2117 }
2118 static inline int hifn_encrypt_des_ofb(struct ablkcipher_request *req)
2119 {
2120         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2121                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2122 }
2123
2124 /*
2125  * DES decryption functions.
2126  */
2127 static inline int hifn_decrypt_des_ecb(struct ablkcipher_request *req)
2128 {
2129         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2130                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2131 }
2132 static inline int hifn_decrypt_des_cbc(struct ablkcipher_request *req)
2133 {
2134         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2135                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2136 }
2137 static inline int hifn_decrypt_des_cfb(struct ablkcipher_request *req)
2138 {
2139         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2140                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2141 }
2142 static inline int hifn_decrypt_des_ofb(struct ablkcipher_request *req)
2143 {
2144         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2145                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2146 }
2147
2148 /*
2149  * 3DES ecryption functions.
2150  */
2151 static inline int hifn_encrypt_3des_ecb(struct ablkcipher_request *req)
2152 {
2153         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2154                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2155 }
2156 static inline int hifn_encrypt_3des_cbc(struct ablkcipher_request *req)
2157 {
2158         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2159                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2160 }
2161 static inline int hifn_encrypt_3des_cfb(struct ablkcipher_request *req)
2162 {
2163         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2164                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2165 }
2166 static inline int hifn_encrypt_3des_ofb(struct ablkcipher_request *req)
2167 {
2168         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2169                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2170 }
2171
2172 /*
2173  * 3DES decryption functions.
2174  */
2175 static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request *req)
2176 {
2177         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2178                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2179 }
2180 static inline int hifn_decrypt_3des_cbc(struct ablkcipher_request *req)
2181 {
2182         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2183                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2184 }
2185 static inline int hifn_decrypt_3des_cfb(struct ablkcipher_request *req)
2186 {
2187         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2188                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2189 }
2190 static inline int hifn_decrypt_3des_ofb(struct ablkcipher_request *req)
2191 {
2192         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2193                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2194 }
2195
2196 struct hifn_alg_template
2197 {
2198         char name[CRYPTO_MAX_ALG_NAME];
2199         char drv_name[CRYPTO_MAX_ALG_NAME];
2200         unsigned int bsize;
2201         struct ablkcipher_alg ablkcipher;
2202 };
2203
2204 static struct hifn_alg_template hifn_alg_templates[] = {
2205         /*
2206          * 3DES ECB, CBC, CFB and OFB modes.
2207          */
2208         {
2209                 .name = "cfb(des3_ede)", .drv_name = "hifn-3des", .bsize = 8,
2210                 .ablkcipher = {
2211                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2212                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2213                         .setkey         =       hifn_setkey,
2214                         .encrypt        =       hifn_encrypt_3des_cfb,
2215                         .decrypt        =       hifn_decrypt_3des_cfb,
2216                 },
2217         },
2218         {
2219                 .name = "ofb(des3_ede)", .drv_name = "hifn-3des", .bsize = 8,
2220                 .ablkcipher = {
2221                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2222                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2223                         .setkey         =       hifn_setkey,
2224                         .encrypt        =       hifn_encrypt_3des_ofb,
2225                         .decrypt        =       hifn_decrypt_3des_ofb,
2226                 },
2227         },
2228         {
2229                 .name = "cbc(des3_ede)", .drv_name = "hifn-3des", .bsize = 8,
2230                 .ablkcipher = {
2231                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2232                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2233                         .setkey         =       hifn_setkey,
2234                         .encrypt        =       hifn_encrypt_3des_cbc,
2235                         .decrypt        =       hifn_decrypt_3des_cbc,
2236                 },
2237         },
2238         {
2239                 .name = "ecb(des3_ede)", .drv_name = "hifn-3des", .bsize = 8,
2240                 .ablkcipher = {
2241                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2242                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2243                         .setkey         =       hifn_setkey,
2244                         .encrypt        =       hifn_encrypt_3des_ecb,
2245                         .decrypt        =       hifn_decrypt_3des_ecb,
2246                 },
2247         },
2248
2249         /*
2250          * DES ECB, CBC, CFB and OFB modes.
2251          */
2252         {
2253                 .name = "cfb(des)", .drv_name = "hifn-des", .bsize = 8,
2254                 .ablkcipher = {
2255                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2256                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2257                         .setkey         =       hifn_setkey,
2258                         .encrypt        =       hifn_encrypt_des_cfb,
2259                         .decrypt        =       hifn_decrypt_des_cfb,
2260                 },
2261         },
2262         {
2263                 .name = "ofb(des)", .drv_name = "hifn-des", .bsize = 8,
2264                 .ablkcipher = {
2265                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2266                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2267                         .setkey         =       hifn_setkey,
2268                         .encrypt        =       hifn_encrypt_des_ofb,
2269                         .decrypt        =       hifn_decrypt_des_ofb,
2270                 },
2271         },
2272         {
2273                 .name = "cbc(des)", .drv_name = "hifn-des", .bsize = 8,
2274                 .ablkcipher = {
2275                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2276                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2277                         .setkey         =       hifn_setkey,
2278                         .encrypt        =       hifn_encrypt_des_cbc,
2279                         .decrypt        =       hifn_decrypt_des_cbc,
2280                 },
2281         },
2282         {
2283                 .name = "ecb(des)", .drv_name = "hifn-des", .bsize = 8,
2284                 .ablkcipher = {
2285                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2286                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2287                         .setkey         =       hifn_setkey,
2288                         .encrypt        =       hifn_encrypt_des_ecb,
2289                         .decrypt        =       hifn_decrypt_des_ecb,
2290                 },
2291         },
2292
2293         /*
2294          * AES ECB, CBC, CFB and OFB modes.
2295          */
2296         {
2297                 .name = "ecb(aes)", .drv_name = "hifn-aes", .bsize = 16,
2298                 .ablkcipher = {
2299                         .min_keysize    =       AES_MIN_KEY_SIZE,
2300                         .max_keysize    =       AES_MAX_KEY_SIZE,
2301                         .setkey         =       hifn_setkey,
2302                         .encrypt        =       hifn_encrypt_aes_ecb,
2303                         .decrypt        =       hifn_decrypt_aes_ecb,
2304                 },
2305         },
2306         {
2307                 .name = "cbc(aes)", .drv_name = "hifn-aes", .bsize = 16,
2308                 .ablkcipher = {
2309                         .min_keysize    =       AES_MIN_KEY_SIZE,
2310                         .max_keysize    =       AES_MAX_KEY_SIZE,
2311                         .setkey         =       hifn_setkey,
2312                         .encrypt        =       hifn_encrypt_aes_cbc,
2313                         .decrypt        =       hifn_decrypt_aes_cbc,
2314                 },
2315         },
2316         {
2317                 .name = "cfb(aes)", .drv_name = "hifn-aes", .bsize = 16,
2318                 .ablkcipher = {
2319                         .min_keysize    =       AES_MIN_KEY_SIZE,
2320                         .max_keysize    =       AES_MAX_KEY_SIZE,
2321                         .setkey         =       hifn_setkey,
2322                         .encrypt        =       hifn_encrypt_aes_cfb,
2323                         .decrypt        =       hifn_decrypt_aes_cfb,
2324                 },
2325         },
2326         {
2327                 .name = "ofb(aes)", .drv_name = "hifn-aes", .bsize = 16,
2328                 .ablkcipher = {
2329                         .min_keysize    =       AES_MIN_KEY_SIZE,
2330                         .max_keysize    =       AES_MAX_KEY_SIZE,
2331                         .setkey         =       hifn_setkey,
2332                         .encrypt        =       hifn_encrypt_aes_ofb,
2333                         .decrypt        =       hifn_decrypt_aes_ofb,
2334                 },
2335         },
2336 };
2337
2338 static int hifn_cra_init(struct crypto_tfm *tfm)
2339 {
2340         struct crypto_alg *alg = tfm->__crt_alg;
2341         struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg);
2342         struct hifn_context *ctx = crypto_tfm_ctx(tfm);
2343
2344         ctx->dev = ha->dev;
2345
2346         return 0;
2347 }
2348
2349 static int hifn_alg_alloc(struct hifn_device *dev, struct hifn_alg_template *t)
2350 {
2351         struct hifn_crypto_alg *alg;
2352         int err;
2353
2354         alg = kzalloc(sizeof(struct hifn_crypto_alg), GFP_KERNEL);
2355         if (!alg)
2356                 return -ENOMEM;
2357
2358         snprintf(alg->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name);
2359         snprintf(alg->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", t->drv_name);
2360
2361         alg->alg.cra_priority = 300;
2362         alg->alg.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | CRYPTO_ALG_ASYNC;
2363         alg->alg.cra_blocksize = t->bsize;
2364         alg->alg.cra_ctxsize = sizeof(struct hifn_context);
2365         alg->alg.cra_alignmask = 15;
2366         if (t->bsize == 8)
2367                 alg->alg.cra_alignmask = 3;
2368         alg->alg.cra_type = &crypto_ablkcipher_type;
2369         alg->alg.cra_module = THIS_MODULE;
2370         alg->alg.cra_u.ablkcipher = t->ablkcipher;
2371         alg->alg.cra_init = hifn_cra_init;
2372
2373         alg->dev = dev;
2374
2375         list_add_tail(&alg->entry, &dev->alg_list);
2376
2377         err = crypto_register_alg(&alg->alg);
2378         if (err) {
2379                 list_del(&alg->entry);
2380                 kfree(alg);
2381         }
2382
2383         return err;
2384 }
2385
2386 static void hifn_unregister_alg(struct hifn_device *dev)
2387 {
2388         struct hifn_crypto_alg *a, *n;
2389
2390         list_for_each_entry_safe(a, n, &dev->alg_list, entry) {
2391                 list_del(&a->entry);
2392                 crypto_unregister_alg(&a->alg);
2393                 kfree(a);
2394         }
2395 }
2396
2397 static int hifn_register_alg(struct hifn_device *dev)
2398 {
2399         int i, err;
2400
2401         for (i=0; i<ARRAY_SIZE(hifn_alg_templates); ++i) {
2402                 err = hifn_alg_alloc(dev, &hifn_alg_templates[i]);
2403                 if (err)
2404                         goto err_out_exit;
2405         }
2406
2407         return 0;
2408
2409 err_out_exit:
2410         hifn_unregister_alg(dev);
2411         return err;
2412 }
2413
2414 static void hifn_tasklet_callback(unsigned long data)
2415 {
2416         struct hifn_device *dev = (struct hifn_device *)data;
2417
2418         /*
2419          * This is ok to call this without lock being held,
2420          * althogh it modifies some parameters used in parallel,
2421          * (like dev->success), but they are used in process
2422          * context or update is atomic (like setting dev->sa[i] to NULL).
2423          */
2424         hifn_check_for_completion(dev, 0);
2425 }
2426
2427 static int hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2428 {
2429         int err, i;
2430         struct hifn_device *dev;
2431         char name[8];
2432
2433         err = pci_enable_device(pdev);
2434         if (err)
2435                 return err;
2436         pci_set_master(pdev);
2437
2438         err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2439         if (err)
2440                 goto err_out_disable_pci_device;
2441
2442         snprintf(name, sizeof(name), "hifn%d",
2443                         atomic_inc_return(&hifn_dev_number)-1);
2444
2445         err = pci_request_regions(pdev, name);
2446         if (err)
2447                 goto err_out_disable_pci_device;
2448
2449         if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE ||
2450             pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE ||
2451             pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) {
2452                 dprintk("%s: Broken hardware - I/O regions are too small.\n",
2453                                 pci_name(pdev));
2454                 err = -ENODEV;
2455                 goto err_out_free_regions;
2456         }
2457
2458         dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg),
2459                         GFP_KERNEL);
2460         if (!dev) {
2461                 err = -ENOMEM;
2462                 goto err_out_free_regions;
2463         }
2464
2465         INIT_LIST_HEAD(&dev->alg_list);
2466
2467         snprintf(dev->name, sizeof(dev->name), "%s", name);
2468         spin_lock_init(&dev->lock);
2469
2470         for (i=0; i<3; ++i) {
2471                 unsigned long addr, size;
2472
2473                 addr = pci_resource_start(pdev, i);
2474                 size = pci_resource_len(pdev, i);
2475
2476                 dev->bar[i] = ioremap_nocache(addr, size);
2477                 if (!dev->bar[i])
2478                         goto err_out_unmap_bars;
2479         }
2480
2481         dev->result_mem = __get_free_pages(GFP_KERNEL, HIFN_MAX_RESULT_ORDER);
2482         if (!dev->result_mem) {
2483                 dprintk("Failed to allocate %d pages for result_mem.\n",
2484                                 HIFN_MAX_RESULT_ORDER);
2485                 goto err_out_unmap_bars;
2486         }
2487         memset((void *)dev->result_mem, 0, PAGE_SIZE*(1<<HIFN_MAX_RESULT_ORDER));
2488
2489         dev->dst = pci_map_single(pdev, (void *)dev->result_mem,
2490                         PAGE_SIZE << HIFN_MAX_RESULT_ORDER, PCI_DMA_FROMDEVICE);
2491
2492         dev->desc_virt = pci_alloc_consistent(pdev, sizeof(struct hifn_dma),
2493                         &dev->desc_dma);
2494         if (!dev->desc_virt) {
2495                 dprintk("Failed to allocate descriptor rings.\n");
2496                 goto err_out_free_result_pages;
2497         }
2498         memset(dev->desc_virt, 0, sizeof(struct hifn_dma));
2499
2500         dev->pdev = pdev;
2501         dev->irq = pdev->irq;
2502
2503         for (i=0; i<HIFN_D_RES_RSIZE; ++i)
2504                 dev->sa[i] = NULL;
2505
2506         pci_set_drvdata(pdev, dev);
2507
2508         tasklet_init(&dev->tasklet, hifn_tasklet_callback, (unsigned long)dev);
2509
2510         crypto_init_queue(&dev->queue, 1);
2511
2512         err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev);
2513         if (err) {
2514                 dprintk("Failed to request IRQ%d: err: %d.\n", dev->irq, err);
2515                 dev->irq = 0;
2516                 goto err_out_free_desc;
2517         }
2518
2519         err = hifn_start_device(dev);
2520         if (err)
2521                 goto err_out_free_irq;
2522
2523         err = hifn_test(dev, 1, 0);
2524         if (err)
2525                 goto err_out_stop_device;
2526
2527         err = hifn_register_alg(dev);
2528         if (err)
2529                 goto err_out_stop_device;
2530
2531         INIT_DELAYED_WORK(&dev->work, hifn_work);
2532         schedule_delayed_work(&dev->work, HZ);
2533
2534         dprintk("HIFN crypto accelerator card at %s has been "
2535                         "successfully registered as %s.\n",
2536                         pci_name(pdev), dev->name);
2537
2538         return 0;
2539
2540 err_out_stop_device:
2541         hifn_reset_dma(dev, 1);
2542         hifn_stop_device(dev);
2543 err_out_free_irq:
2544         free_irq(dev->irq, dev->name);
2545         tasklet_kill(&dev->tasklet);
2546 err_out_free_desc:
2547         pci_free_consistent(pdev, sizeof(struct hifn_dma),
2548                         dev->desc_virt, dev->desc_dma);
2549
2550 err_out_free_result_pages:
2551         pci_unmap_single(pdev, dev->dst, PAGE_SIZE << HIFN_MAX_RESULT_ORDER,
2552                         PCI_DMA_FROMDEVICE);
2553         free_pages(dev->result_mem, HIFN_MAX_RESULT_ORDER);
2554
2555 err_out_unmap_bars:
2556         for (i=0; i<3; ++i)
2557                 if (dev->bar[i])
2558                         iounmap(dev->bar[i]);
2559
2560 err_out_free_regions:
2561         pci_release_regions(pdev);
2562
2563 err_out_disable_pci_device:
2564         pci_disable_device(pdev);
2565
2566         return err;
2567 }
2568
2569 static void hifn_remove(struct pci_dev *pdev)
2570 {
2571         int i;
2572         struct hifn_device *dev;
2573
2574         dev = pci_get_drvdata(pdev);
2575
2576         if (dev) {
2577                 cancel_delayed_work(&dev->work);
2578                 flush_scheduled_work();
2579
2580                 hifn_unregister_alg(dev);
2581                 hifn_reset_dma(dev, 1);
2582                 hifn_stop_device(dev);
2583
2584                 free_irq(dev->irq, dev->name);
2585                 tasklet_kill(&dev->tasklet);
2586
2587                 hifn_flush(dev);
2588
2589                 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2590                                 dev->desc_virt, dev->desc_dma);
2591                 pci_unmap_single(pdev, dev->dst,
2592                                 PAGE_SIZE << HIFN_MAX_RESULT_ORDER,
2593                                 PCI_DMA_FROMDEVICE);
2594                 free_pages(dev->result_mem, HIFN_MAX_RESULT_ORDER);
2595                 for (i=0; i<3; ++i)
2596                         if (dev->bar[i])
2597                                 iounmap(dev->bar[i]);
2598
2599                 kfree(dev);
2600         }
2601
2602         pci_release_regions(pdev);
2603         pci_disable_device(pdev);
2604 }
2605
2606 static struct pci_device_id hifn_pci_tbl[] = {
2607         { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) },
2608         { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) },
2609         { 0 }
2610 };
2611 MODULE_DEVICE_TABLE(pci, hifn_pci_tbl);
2612
2613 static struct pci_driver hifn_pci_driver = {
2614         .name     = "hifn795x",
2615         .id_table = hifn_pci_tbl,
2616         .probe    = hifn_probe,
2617         .remove   = __devexit_p(hifn_remove),
2618 };
2619
2620 static int __devinit hifn_init(void)
2621 {
2622         int err;
2623
2624         err = pci_register_driver(&hifn_pci_driver);
2625         if (err < 0) {
2626                 dprintk("Failed to register PCI driver for %s device.\n",
2627                                 hifn_pci_driver.name);
2628                 return -ENODEV;
2629         }
2630
2631         printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip "
2632                         "has been successfully registered.\n");
2633
2634         return 0;
2635 }
2636
2637 static void __devexit hifn_fini(void)
2638 {
2639         pci_unregister_driver(&hifn_pci_driver);
2640
2641         printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip "
2642                         "has been successfully unregistered.\n");
2643 }
2644
2645 module_init(hifn_init);
2646 module_exit(hifn_fini);
2647
2648 MODULE_LICENSE("GPL");
2649 MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
2650 MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip.");