drivers/crypto/hifn_795x.c

   1 /*
   2  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/pci.h>
  26 #include <linux/slab.h>
  27 #include <linux/delay.h>
  28 #include <linux/mm.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/scatterlist.h>
  31 #include <linux/highmem.h>
  32 #include <linux/crypto.h>
  33 #include <linux/hw_random.h>
  34 #include <linux/ktime.h>
  35
  36 #include <crypto/algapi.h>
  37 #include <crypto/des.h>
  38
  39 static char hifn_pll_ref[sizeof("extNNN")] = "ext";
  40 module_param_string(hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444);
  41 MODULE_PARM_DESC(hifn_pll_ref,
  42                  "PLL reference clock (pci[freq] or ext[freq], default ext)");
  43
  44 static atomic_t hifn_dev_number;
  45
  46 #define ACRYPTO_OP_DECRYPT      0
  47 #define ACRYPTO_OP_ENCRYPT      1
  48 #define ACRYPTO_OP_HMAC         2
  49 #define ACRYPTO_OP_RNG          3
  50
  51 #define ACRYPTO_MODE_ECB                0
  52 #define ACRYPTO_MODE_CBC                1
  53 #define ACRYPTO_MODE_CFB                2
  54 #define ACRYPTO_MODE_OFB                3
  55
  56 #define ACRYPTO_TYPE_AES_128    0
  57 #define ACRYPTO_TYPE_AES_192    1
  58 #define ACRYPTO_TYPE_AES_256    2
  59 #define ACRYPTO_TYPE_3DES       3
  60 #define ACRYPTO_TYPE_DES        4
  61
  62 #define PCI_VENDOR_ID_HIFN              0x13A3
  63 #define PCI_DEVICE_ID_HIFN_7955         0x0020
  64 #define PCI_DEVICE_ID_HIFN_7956         0x001d
  65
  66 /* I/O region sizes */
  67
  68 #define HIFN_BAR0_SIZE                  0x1000
  69 #define HIFN_BAR1_SIZE                  0x2000
  70 #define HIFN_BAR2_SIZE                  0x8000
  71
  72 /* DMA registres */
  73
  74 #define HIFN_DMA_CRA                    0x0C    /* DMA Command Ring Address */
  75 #define HIFN_DMA_SDRA                   0x1C    /* DMA Source Data Ring Address */
  76 #define HIFN_DMA_RRA                    0x2C    /* DMA Result Ring Address */
  77 #define HIFN_DMA_DDRA                   0x3C    /* DMA Destination Data Ring Address */
  78 #define HIFN_DMA_STCTL                  0x40    /* DMA Status and Control */
  79 #define HIFN_DMA_INTREN                 0x44    /* DMA Interrupt Enable */
  80 #define HIFN_DMA_CFG1                   0x48    /* DMA Configuration #1 */
  81 #define HIFN_DMA_CFG2                   0x6C    /* DMA Configuration #2 */
  82 #define HIFN_CHIP_ID                    0x98    /* Chip ID */
  83
  84 /*
  85  * Processing Unit Registers (offset from BASEREG0)
  86  */
  87 #define HIFN_0_PUDATA           0x00    /* Processing Unit Data */
  88 #define HIFN_0_PUCTRL           0x04    /* Processing Unit Control */
  89 #define HIFN_0_PUISR            0x08    /* Processing Unit Interrupt Status */
  90 #define HIFN_0_PUCNFG           0x0c    /* Processing Unit Configuration */
  91 #define HIFN_0_PUIER            0x10    /* Processing Unit Interrupt Enable */
  92 #define HIFN_0_PUSTAT           0x14    /* Processing Unit Status/Chip ID */
  93 #define HIFN_0_FIFOSTAT         0x18    /* FIFO Status */
  94 #define HIFN_0_FIFOCNFG         0x1c    /* FIFO Configuration */
  95 #define HIFN_0_SPACESIZE        0x20    /* Register space size */
  96
  97 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
  98 #define HIFN_PUCTRL_CLRSRCFIFO  0x0010  /* clear source fifo */
  99 #define HIFN_PUCTRL_STOP        0x0008  /* stop pu */
 100 #define HIFN_PUCTRL_LOCKRAM     0x0004  /* lock ram */
 101 #define HIFN_PUCTRL_DMAENA      0x0002  /* enable dma */
 102 #define HIFN_PUCTRL_RESET       0x0001  /* Reset processing unit */
 103
 104 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
 105 #define HIFN_PUISR_CMDINVAL     0x8000  /* Invalid command interrupt */
 106 #define HIFN_PUISR_DATAERR      0x4000  /* Data error interrupt */
 107 #define HIFN_PUISR_SRCFIFO      0x2000  /* Source FIFO ready interrupt */
 108 #define HIFN_PUISR_DSTFIFO      0x1000  /* Destination FIFO ready interrupt */
 109 #define HIFN_PUISR_DSTOVER      0x0200  /* Destination overrun interrupt */
 110 #define HIFN_PUISR_SRCCMD       0x0080  /* Source command interrupt */
 111 #define HIFN_PUISR_SRCCTX       0x0040  /* Source context interrupt */
 112 #define HIFN_PUISR_SRCDATA      0x0020  /* Source data interrupt */
 113 #define HIFN_PUISR_DSTDATA      0x0010  /* Destination data interrupt */
 114 #define HIFN_PUISR_DSTRESULT    0x0004  /* Destination result interrupt */
 115
 116 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
 117 #define HIFN_PUCNFG_DRAMMASK    0xe000  /* DRAM size mask */
 118 #define HIFN_PUCNFG_DSZ_256K    0x0000  /* 256k dram */
 119 #define HIFN_PUCNFG_DSZ_512K    0x2000  /* 512k dram */
 120 #define HIFN_PUCNFG_DSZ_1M      0x4000  /* 1m dram */
 121 #define HIFN_PUCNFG_DSZ_2M      0x6000  /* 2m dram */
 122 #define HIFN_PUCNFG_DSZ_4M      0x8000  /* 4m dram */
 123 #define HIFN_PUCNFG_DSZ_8M      0xa000  /* 8m dram */
 124 #define HIFN_PUNCFG_DSZ_16M     0xc000  /* 16m dram */
 125 #define HIFN_PUCNFG_DSZ_32M     0xe000  /* 32m dram */
 126 #define HIFN_PUCNFG_DRAMREFRESH 0x1800  /* DRAM refresh rate mask */
 127 #define HIFN_PUCNFG_DRFR_512    0x0000  /* 512 divisor of ECLK */
 128 #define HIFN_PUCNFG_DRFR_256    0x0800  /* 256 divisor of ECLK */
 129 #define HIFN_PUCNFG_DRFR_128    0x1000  /* 128 divisor of ECLK */
 130 #define HIFN_PUCNFG_TCALLPHASES 0x0200  /* your guess is as good as mine... */
 131 #define HIFN_PUCNFG_TCDRVTOTEM  0x0100  /* your guess is as good as mine... */
 132 #define HIFN_PUCNFG_BIGENDIAN   0x0080  /* DMA big endian mode */
 133 #define HIFN_PUCNFG_BUS32       0x0040  /* Bus width 32bits */
 134 #define HIFN_PUCNFG_BUS16       0x0000  /* Bus width 16 bits */
 135 #define HIFN_PUCNFG_CHIPID      0x0020  /* Allow chipid from PUSTAT */
 136 #define HIFN_PUCNFG_DRAM        0x0010  /* Context RAM is DRAM */
 137 #define HIFN_PUCNFG_SRAM        0x0000  /* Context RAM is SRAM */
 138 #define HIFN_PUCNFG_COMPSING    0x0004  /* Enable single compression context */
 139 #define HIFN_PUCNFG_ENCCNFG     0x0002  /* Encryption configuration */
 140
 141 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
 142 #define HIFN_PUIER_CMDINVAL     0x8000  /* Invalid command interrupt */
 143 #define HIFN_PUIER_DATAERR      0x4000  /* Data error interrupt */
 144 #define HIFN_PUIER_SRCFIFO      0x2000  /* Source FIFO ready interrupt */
 145 #define HIFN_PUIER_DSTFIFO      0x1000  /* Destination FIFO ready interrupt */
 146 #define HIFN_PUIER_DSTOVER      0x0200  /* Destination overrun interrupt */
 147 #define HIFN_PUIER_SRCCMD       0x0080  /* Source command interrupt */
 148 #define HIFN_PUIER_SRCCTX       0x0040  /* Source context interrupt */
 149 #define HIFN_PUIER_SRCDATA      0x0020  /* Source data interrupt */
 150 #define HIFN_PUIER_DSTDATA      0x0010  /* Destination data interrupt */
 151 #define HIFN_PUIER_DSTRESULT    0x0004  /* Destination result interrupt */
 152
 153 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
 154 #define HIFN_PUSTAT_CMDINVAL    0x8000  /* Invalid command interrupt */
 155 #define HIFN_PUSTAT_DATAERR     0x4000  /* Data error interrupt */
 156 #define HIFN_PUSTAT_SRCFIFO     0x2000  /* Source FIFO ready interrupt */
 157 #define HIFN_PUSTAT_DSTFIFO     0x1000  /* Destination FIFO ready interrupt */
 158 #define HIFN_PUSTAT_DSTOVER     0x0200  /* Destination overrun interrupt */
 159 #define HIFN_PUSTAT_SRCCMD      0x0080  /* Source command interrupt */
 160 #define HIFN_PUSTAT_SRCCTX      0x0040  /* Source context interrupt */
 161 #define HIFN_PUSTAT_SRCDATA     0x0020  /* Source data interrupt */
 162 #define HIFN_PUSTAT_DSTDATA     0x0010  /* Destination data interrupt */
 163 #define HIFN_PUSTAT_DSTRESULT   0x0004  /* Destination result interrupt */
 164 #define HIFN_PUSTAT_CHIPREV     0x00ff  /* Chip revision mask */
 165 #define HIFN_PUSTAT_CHIPENA     0xff00  /* Chip enabled mask */
 166 #define HIFN_PUSTAT_ENA_2       0x1100  /* Level 2 enabled */
 167 #define HIFN_PUSTAT_ENA_1       0x1000  /* Level 1 enabled */
 168 #define HIFN_PUSTAT_ENA_0       0x3000  /* Level 0 enabled */
 169 #define HIFN_PUSTAT_REV_2       0x0020  /* 7751 PT6/2 */
 170 #define HIFN_PUSTAT_REV_3       0x0030  /* 7751 PT6/3 */
 171
 172 /* FIFO Status Register (HIFN_0_FIFOSTAT) */
 173 #define HIFN_FIFOSTAT_SRC       0x7f00  /* Source FIFO available */
 174 #define HIFN_FIFOSTAT_DST       0x007f  /* Destination FIFO available */
 175
 176 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
 177 #define HIFN_FIFOCNFG_THRESHOLD 0x0400  /* must be written as 1 */
 178
 179 /*
 180  * DMA Interface Registers (offset from BASEREG1)
 181  */
 182 #define HIFN_1_DMA_CRAR         0x0c    /* DMA Command Ring Address */
 183 #define HIFN_1_DMA_SRAR         0x1c    /* DMA Source Ring Address */
 184 #define HIFN_1_DMA_RRAR         0x2c    /* DMA Result Ring Address */
 185 #define HIFN_1_DMA_DRAR         0x3c    /* DMA Destination Ring Address */
 186 #define HIFN_1_DMA_CSR          0x40    /* DMA Status and Control */
 187 #define HIFN_1_DMA_IER          0x44    /* DMA Interrupt Enable */
 188 #define HIFN_1_DMA_CNFG         0x48    /* DMA Configuration */
 189 #define HIFN_1_PLL              0x4c    /* 795x: PLL config */
 190 #define HIFN_1_7811_RNGENA      0x60    /* 7811: rng enable */
 191 #define HIFN_1_7811_RNGCFG      0x64    /* 7811: rng config */
 192 #define HIFN_1_7811_RNGDAT      0x68    /* 7811: rng data */
 193 #define HIFN_1_7811_RNGSTS      0x6c    /* 7811: rng status */
 194 #define HIFN_1_7811_MIPSRST     0x94    /* 7811: MIPS reset */
 195 #define HIFN_1_REVID            0x98    /* Revision ID */
 196 #define HIFN_1_UNLOCK_SECRET1   0xf4
 197 #define HIFN_1_UNLOCK_SECRET2   0xfc
 198 #define HIFN_1_PUB_RESET        0x204   /* Public/RNG Reset */
 199 #define HIFN_1_PUB_BASE         0x300   /* Public Base Address */
 200 #define HIFN_1_PUB_OPLEN        0x304   /* Public Operand Length */
 201 #define HIFN_1_PUB_OP           0x308   /* Public Operand */
 202 #define HIFN_1_PUB_STATUS       0x30c   /* Public Status */
 203 #define HIFN_1_PUB_IEN          0x310   /* Public Interrupt enable */
 204 #define HIFN_1_RNG_CONFIG       0x314   /* RNG config */
 205 #define HIFN_1_RNG_DATA         0x318   /* RNG data */
 206 #define HIFN_1_PUB_MEM          0x400   /* start of Public key memory */
 207 #define HIFN_1_PUB_MEMEND       0xbff   /* end of Public key memory */
 208
 209 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
 210 #define HIFN_DMACSR_D_CTRLMASK  0xc0000000      /* Destinition Ring Control */
 211 #define HIFN_DMACSR_D_CTRL_NOP  0x00000000      /* Dest. Control: no-op */
 212 #define HIFN_DMACSR_D_CTRL_DIS  0x40000000      /* Dest. Control: disable */
 213 #define HIFN_DMACSR_D_CTRL_ENA  0x80000000      /* Dest. Control: enable */
 214 #define HIFN_DMACSR_D_ABORT     0x20000000      /* Destinition Ring PCIAbort */
 215 #define HIFN_DMACSR_D_DONE      0x10000000      /* Destinition Ring Done */
 216 #define HIFN_DMACSR_D_LAST      0x08000000      /* Destinition Ring Last */
 217 #define HIFN_DMACSR_D_WAIT      0x04000000      /* Destinition Ring Waiting */
 218 #define HIFN_DMACSR_D_OVER      0x02000000      /* Destinition Ring Overflow */
 219 #define HIFN_DMACSR_R_CTRL      0x00c00000      /* Result Ring Control */
 220 #define HIFN_DMACSR_R_CTRL_NOP  0x00000000      /* Result Control: no-op */
 221 #define HIFN_DMACSR_R_CTRL_DIS  0x00400000      /* Result Control: disable */
 222 #define HIFN_DMACSR_R_CTRL_ENA  0x00800000      /* Result Control: enable */
 223 #define HIFN_DMACSR_R_ABORT     0x00200000      /* Result Ring PCI Abort */
 224 #define HIFN_DMACSR_R_DONE      0x00100000      /* Result Ring Done */
 225 #define HIFN_DMACSR_R_LAST      0x00080000      /* Result Ring Last */
 226 #define HIFN_DMACSR_R_WAIT      0x00040000      /* Result Ring Waiting */
 227 #define HIFN_DMACSR_R_OVER      0x00020000      /* Result Ring Overflow */
 228 #define HIFN_DMACSR_S_CTRL      0x0000c000      /* Source Ring Control */
 229 #define HIFN_DMACSR_S_CTRL_NOP  0x00000000      /* Source Control: no-op */
 230 #define HIFN_DMACSR_S_CTRL_DIS  0x00004000      /* Source Control: disable */
 231 #define HIFN_DMACSR_S_CTRL_ENA  0x00008000      /* Source Control: enable */
 232 #define HIFN_DMACSR_S_ABORT     0x00002000      /* Source Ring PCI Abort */
 233 #define HIFN_DMACSR_S_DONE      0x00001000      /* Source Ring Done */
 234 #define HIFN_DMACSR_S_LAST      0x00000800      /* Source Ring Last */
 235 #define HIFN_DMACSR_S_WAIT      0x00000400      /* Source Ring Waiting */
 236 #define HIFN_DMACSR_ILLW        0x00000200      /* Illegal write (7811 only) */
 237 #define HIFN_DMACSR_ILLR        0x00000100      /* Illegal read (7811 only) */
 238 #define HIFN_DMACSR_C_CTRL      0x000000c0      /* Command Ring Control */
 239 #define HIFN_DMACSR_C_CTRL_NOP  0x00000000      /* Command Control: no-op */
 240 #define HIFN_DMACSR_C_CTRL_DIS  0x00000040      /* Command Control: disable */
 241 #define HIFN_DMACSR_C_CTRL_ENA  0x00000080      /* Command Control: enable */
 242 #define HIFN_DMACSR_C_ABORT     0x00000020      /* Command Ring PCI Abort */
 243 #define HIFN_DMACSR_C_DONE      0x00000010      /* Command Ring Done */
 244 #define HIFN_DMACSR_C_LAST      0x00000008      /* Command Ring Last */
 245 #define HIFN_DMACSR_C_WAIT      0x00000004      /* Command Ring Waiting */
 246 #define HIFN_DMACSR_PUBDONE     0x00000002      /* Public op done (7951 only) */
 247 #define HIFN_DMACSR_ENGINE      0x00000001      /* Command Ring Engine IRQ */
 248
 249 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
 250 #define HIFN_DMAIER_D_ABORT     0x20000000      /* Destination Ring PCIAbort */
 251 #define HIFN_DMAIER_D_DONE      0x10000000      /* Destination Ring Done */
 252 #define HIFN_DMAIER_D_LAST      0x08000000      /* Destination Ring Last */
 253 #define HIFN_DMAIER_D_WAIT      0x04000000      /* Destination Ring Waiting */
 254 #define HIFN_DMAIER_D_OVER      0x02000000      /* Destination Ring Overflow */
 255 #define HIFN_DMAIER_R_ABORT     0x00200000      /* Result Ring PCI Abort */
 256 #define HIFN_DMAIER_R_DONE      0x00100000      /* Result Ring Done */
 257 #define HIFN_DMAIER_R_LAST      0x00080000      /* Result Ring Last */
 258 #define HIFN_DMAIER_R_WAIT      0x00040000      /* Result Ring Waiting */
 259 #define HIFN_DMAIER_R_OVER      0x00020000      /* Result Ring Overflow */
 260 #define HIFN_DMAIER_S_ABORT     0x00002000      /* Source Ring PCI Abort */
 261 #define HIFN_DMAIER_S_DONE      0x00001000      /* Source Ring Done */
 262 #define HIFN_DMAIER_S_LAST      0x00000800      /* Source Ring Last */
 263 #define HIFN_DMAIER_S_WAIT      0x00000400      /* Source Ring Waiting */
 264 #define HIFN_DMAIER_ILLW        0x00000200      /* Illegal write (7811 only) */
 265 #define HIFN_DMAIER_ILLR        0x00000100      /* Illegal read (7811 only) */
 266 #define HIFN_DMAIER_C_ABORT     0x00000020      /* Command Ring PCI Abort */
 267 #define HIFN_DMAIER_C_DONE      0x00000010      /* Command Ring Done */
 268 #define HIFN_DMAIER_C_LAST      0x00000008      /* Command Ring Last */
 269 #define HIFN_DMAIER_C_WAIT      0x00000004      /* Command Ring Waiting */
 270 #define HIFN_DMAIER_PUBDONE     0x00000002      /* public op done (7951 only) */
 271 #define HIFN_DMAIER_ENGINE      0x00000001      /* Engine IRQ */
 272
 273 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
 274 #define HIFN_DMACNFG_BIGENDIAN  0x10000000      /* big endian mode */
 275 #define HIFN_DMACNFG_POLLFREQ   0x00ff0000      /* Poll frequency mask */
 276 #define HIFN_DMACNFG_UNLOCK     0x00000800
 277 #define HIFN_DMACNFG_POLLINVAL  0x00000700      /* Invalid Poll Scalar */
 278 #define HIFN_DMACNFG_LAST       0x00000010      /* Host control LAST bit */
 279 #define HIFN_DMACNFG_MODE       0x00000004      /* DMA mode */
 280 #define HIFN_DMACNFG_DMARESET   0x00000002      /* DMA Reset # */
 281 #define HIFN_DMACNFG_MSTRESET   0x00000001      /* Master Reset # */
 282
 283 /* PLL configuration register */
 284 #define HIFN_PLL_REF_CLK_HBI    0x00000000      /* HBI reference clock */
 285 #define HIFN_PLL_REF_CLK_PLL    0x00000001      /* PLL reference clock */
 286 #define HIFN_PLL_BP             0x00000002      /* Reference clock bypass */
 287 #define HIFN_PLL_PK_CLK_HBI     0x00000000      /* PK engine HBI clock */
 288 #define HIFN_PLL_PK_CLK_PLL     0x00000008      /* PK engine PLL clock */
 289 #define HIFN_PLL_PE_CLK_HBI     0x00000000      /* PE engine HBI clock */
 290 #define HIFN_PLL_PE_CLK_PLL     0x00000010      /* PE engine PLL clock */
 291 #define HIFN_PLL_RESERVED_1     0x00000400      /* Reserved bit, must be 1 */
 292 #define HIFN_PLL_ND_SHIFT       11              /* Clock multiplier shift */
 293 #define HIFN_PLL_ND_MULT_2      0x00000000      /* PLL clock multiplier 2 */
 294 #define HIFN_PLL_ND_MULT_4      0x00000800      /* PLL clock multiplier 4 */
 295 #define HIFN_PLL_ND_MULT_6      0x00001000      /* PLL clock multiplier 6 */
 296 #define HIFN_PLL_ND_MULT_8      0x00001800      /* PLL clock multiplier 8 */
 297 #define HIFN_PLL_ND_MULT_10     0x00002000      /* PLL clock multiplier 10 */
 298 #define HIFN_PLL_ND_MULT_12     0x00002800      /* PLL clock multiplier 12 */
 299 #define HIFN_PLL_IS_1_8         0x00000000      /* charge pump (mult. 1-8) */
 300 #define HIFN_PLL_IS_9_12        0x00010000      /* charge pump (mult. 9-12) */
 301
 302 #define HIFN_PLL_FCK_MAX        266             /* Maximum PLL frequency */
 303
 304 /* Public key reset register (HIFN_1_PUB_RESET) */
 305 #define HIFN_PUBRST_RESET       0x00000001      /* reset public/rng unit */
 306
 307 /* Public base address register (HIFN_1_PUB_BASE) */
 308 #define HIFN_PUBBASE_ADDR       0x00003fff      /* base address */
 309
 310 /* Public operand length register (HIFN_1_PUB_OPLEN) */
 311 #define HIFN_PUBOPLEN_MOD_M     0x0000007f      /* modulus length mask */
 312 #define HIFN_PUBOPLEN_MOD_S     0               /* modulus length shift */
 313 #define HIFN_PUBOPLEN_EXP_M     0x0003ff80      /* exponent length mask */
 314 #define HIFN_PUBOPLEN_EXP_S     7               /* exponent length shift */
 315 #define HIFN_PUBOPLEN_RED_M     0x003c0000      /* reducend length mask */
 316 #define HIFN_PUBOPLEN_RED_S     18              /* reducend length shift */
 317
 318 /* Public operation register (HIFN_1_PUB_OP) */
 319 #define HIFN_PUBOP_AOFFSET_M    0x0000007f      /* A offset mask */
 320 #define HIFN_PUBOP_AOFFSET_S    0               /* A offset shift */
 321 #define HIFN_PUBOP_BOFFSET_M    0x00000f80      /* B offset mask */
 322 #define HIFN_PUBOP_BOFFSET_S    7               /* B offset shift */
 323 #define HIFN_PUBOP_MOFFSET_M    0x0003f000      /* M offset mask */
 324 #define HIFN_PUBOP_MOFFSET_S    12              /* M offset shift */
 325 #define HIFN_PUBOP_OP_MASK      0x003c0000      /* Opcode: */
 326 #define HIFN_PUBOP_OP_NOP       0x00000000      /*  NOP */
 327 #define HIFN_PUBOP_OP_ADD       0x00040000      /*  ADD */
 328 #define HIFN_PUBOP_OP_ADDC      0x00080000      /*  ADD w/carry */
 329 #define HIFN_PUBOP_OP_SUB       0x000c0000      /*  SUB */
 330 #define HIFN_PUBOP_OP_SUBC      0x00100000      /*  SUB w/carry */
 331 #define HIFN_PUBOP_OP_MODADD    0x00140000      /*  Modular ADD */
 332 #define HIFN_PUBOP_OP_MODSUB    0x00180000      /*  Modular SUB */
 333 #define HIFN_PUBOP_OP_INCA      0x001c0000      /*  INC A */
 334 #define HIFN_PUBOP_OP_DECA      0x00200000      /*  DEC A */
 335 #define HIFN_PUBOP_OP_MULT      0x00240000      /*  MULT */
 336 #define HIFN_PUBOP_OP_MODMULT   0x00280000      /*  Modular MULT */
 337 #define HIFN_PUBOP_OP_MODRED    0x002c0000      /*  Modular RED */
 338 #define HIFN_PUBOP_OP_MODEXP    0x00300000      /*  Modular EXP */
 339
 340 /* Public status register (HIFN_1_PUB_STATUS) */
 341 #define HIFN_PUBSTS_DONE        0x00000001      /* operation done */
 342 #define HIFN_PUBSTS_CARRY       0x00000002      /* carry */
 343
 344 /* Public interrupt enable register (HIFN_1_PUB_IEN) */
 345 #define HIFN_PUBIEN_DONE        0x00000001      /* operation done interrupt */
 346
 347 /* Random number generator config register (HIFN_1_RNG_CONFIG) */
 348 #define HIFN_RNGCFG_ENA         0x00000001      /* enable rng */
 349
 350 #define HIFN_NAMESIZE                   32
 351 #define HIFN_MAX_RESULT_ORDER           5
 352
 353 #define HIFN_D_CMD_RSIZE                24*1
 354 #define HIFN_D_SRC_RSIZE                80*1
 355 #define HIFN_D_DST_RSIZE                80*1
 356 #define HIFN_D_RES_RSIZE                24*1
 357
 358 #define HIFN_D_DST_DALIGN               4
 359
 360 #define HIFN_QUEUE_LENGTH               (HIFN_D_CMD_RSIZE - 1)
 361
 362 #define AES_MIN_KEY_SIZE                16
 363 #define AES_MAX_KEY_SIZE                32
 364
 365 #define HIFN_DES_KEY_LENGTH             8
 366 #define HIFN_3DES_KEY_LENGTH            24
 367 #define HIFN_MAX_CRYPT_KEY_LENGTH       AES_MAX_KEY_SIZE
 368 #define HIFN_IV_LENGTH                  8
 369 #define HIFN_AES_IV_LENGTH              16
 370 #define HIFN_MAX_IV_LENGTH              HIFN_AES_IV_LENGTH
 371
 372 #define HIFN_MAC_KEY_LENGTH             64
 373 #define HIFN_MD5_LENGTH                 16
 374 #define HIFN_SHA1_LENGTH                20
 375 #define HIFN_MAC_TRUNC_LENGTH           12
 376
 377 #define HIFN_MAX_COMMAND                (8 + 8 + 8 + 64 + 260)
 378 #define HIFN_MAX_RESULT                 (8 + 4 + 4 + 20 + 4)
 379 #define HIFN_USED_RESULT                12
 380
 381 struct hifn_desc
 382 {
 383         volatile __le32         l;
 384         volatile __le32         p;
 385 };
 386
 387 struct hifn_dma {
 388         struct hifn_desc        cmdr[HIFN_D_CMD_RSIZE+1];
 389         struct hifn_desc        srcr[HIFN_D_SRC_RSIZE+1];
 390         struct hifn_desc        dstr[HIFN_D_DST_RSIZE+1];
 391         struct hifn_desc        resr[HIFN_D_RES_RSIZE+1];
 392
 393         u8                      command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
 394         u8                      result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
 395
 396         /*
 397          *  Our current positions for insertion and removal from the descriptor
 398          *  rings.
 399          */
 400         volatile int            cmdi, srci, dsti, resi;
 401         volatile int            cmdu, srcu, dstu, resu;
 402         int                     cmdk, srck, dstk, resk;
 403 };
 404
 405 #define HIFN_FLAG_CMD_BUSY      (1<<0)
 406 #define HIFN_FLAG_SRC_BUSY      (1<<1)
 407 #define HIFN_FLAG_DST_BUSY      (1<<2)
 408 #define HIFN_FLAG_RES_BUSY      (1<<3)
 409 #define HIFN_FLAG_OLD_KEY       (1<<4)
 410
 411 #define HIFN_DEFAULT_ACTIVE_NUM 5
 412
 413 struct hifn_device
 414 {
 415         char                    name[HIFN_NAMESIZE];
 416
 417         int                     irq;
 418
 419         struct pci_dev          *pdev;
 420         void __iomem            *bar[3];
 421
 422         void                    *desc_virt;
 423         dma_addr_t              desc_dma;
 424
 425         u32                     dmareg;
 426
 427         void                    *sa[HIFN_D_RES_RSIZE];
 428
 429         spinlock_t              lock;
 430
 431         u32                     flags;
 432         int                     active, started;
 433         struct delayed_work     work;
 434         unsigned long           reset;
 435         unsigned long           success;
 436         unsigned long           prev_success;
 437
 438         u8                      snum;
 439
 440         struct tasklet_struct   tasklet;
 441
 442         struct crypto_queue     queue;
 443         struct list_head        alg_list;
 444
 445         unsigned int            pk_clk_freq;
 446
 447 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
 448         unsigned int            rng_wait_time;
 449         ktime_t                 rngtime;
 450         struct hwrng            rng;
 451 #endif
 452 };
 453
 454 #define HIFN_D_LENGTH                   0x0000ffff
 455 #define HIFN_D_NOINVALID                0x01000000
 456 #define HIFN_D_MASKDONEIRQ              0x02000000
 457 #define HIFN_D_DESTOVER                 0x04000000
 458 #define HIFN_D_OVER                     0x08000000
 459 #define HIFN_D_LAST                     0x20000000
 460 #define HIFN_D_JUMP                     0x40000000
 461 #define HIFN_D_VALID                    0x80000000
 462
 463 struct hifn_base_command
 464 {
 465         volatile __le16         masks;
 466         volatile __le16         session_num;
 467         volatile __le16         total_source_count;
 468         volatile __le16         total_dest_count;
 469 };
 470
 471 #define HIFN_BASE_CMD_COMP              0x0100  /* enable compression engine */
 472 #define HIFN_BASE_CMD_PAD               0x0200  /* enable padding engine */
 473 #define HIFN_BASE_CMD_MAC               0x0400  /* enable MAC engine */
 474 #define HIFN_BASE_CMD_CRYPT             0x0800  /* enable crypt engine */
 475 #define HIFN_BASE_CMD_DECODE            0x2000
 476 #define HIFN_BASE_CMD_SRCLEN_M          0xc000
 477 #define HIFN_BASE_CMD_SRCLEN_S          14
 478 #define HIFN_BASE_CMD_DSTLEN_M          0x3000
 479 #define HIFN_BASE_CMD_DSTLEN_S          12
 480 #define HIFN_BASE_CMD_LENMASK_HI        0x30000
 481 #define HIFN_BASE_CMD_LENMASK_LO        0x0ffff
 482
 483 /*
 484  * Structure to help build up the command data structure.
 485  */
 486 struct hifn_crypt_command
 487 {
 488         volatile __le16                 masks;
 489         volatile __le16                 header_skip;
 490         volatile __le16                 source_count;
 491         volatile __le16                 reserved;
 492 };
 493
 494 #define HIFN_CRYPT_CMD_ALG_MASK         0x0003          /* algorithm: */
 495 #define HIFN_CRYPT_CMD_ALG_DES          0x0000          /*   DES */
 496 #define HIFN_CRYPT_CMD_ALG_3DES         0x0001          /*   3DES */
 497 #define HIFN_CRYPT_CMD_ALG_RC4          0x0002          /*   RC4 */
 498 #define HIFN_CRYPT_CMD_ALG_AES          0x0003          /*   AES */
 499 #define HIFN_CRYPT_CMD_MODE_MASK        0x0018          /* Encrypt mode: */
 500 #define HIFN_CRYPT_CMD_MODE_ECB         0x0000          /*   ECB */
 501 #define HIFN_CRYPT_CMD_MODE_CBC         0x0008          /*   CBC */
 502 #define HIFN_CRYPT_CMD_MODE_CFB         0x0010          /*   CFB */
 503 #define HIFN_CRYPT_CMD_MODE_OFB         0x0018          /*   OFB */
 504 #define HIFN_CRYPT_CMD_CLR_CTX          0x0040          /* clear context */
 505 #define HIFN_CRYPT_CMD_KSZ_MASK         0x0600          /* AES key size: */
 506 #define HIFN_CRYPT_CMD_KSZ_128          0x0000          /*  128 bit */
 507 #define HIFN_CRYPT_CMD_KSZ_192          0x0200          /*  192 bit */
 508 #define HIFN_CRYPT_CMD_KSZ_256          0x0400          /*  256 bit */
 509 #define HIFN_CRYPT_CMD_NEW_KEY          0x0800          /* expect new key */
 510 #define HIFN_CRYPT_CMD_NEW_IV           0x1000          /* expect new iv */
 511 #define HIFN_CRYPT_CMD_SRCLEN_M         0xc000
 512 #define HIFN_CRYPT_CMD_SRCLEN_S         14
 513
 514 /*
 515  * Structure to help build up the command data structure.
 516  */
 517 struct hifn_mac_command
 518 {
 519         volatile __le16         masks;
 520         volatile __le16         header_skip;
 521         volatile __le16         source_count;
 522         volatile __le16         reserved;
 523 };
 524
 525 #define HIFN_MAC_CMD_ALG_MASK           0x0001
 526 #define HIFN_MAC_CMD_ALG_SHA1           0x0000
 527 #define HIFN_MAC_CMD_ALG_MD5            0x0001
 528 #define HIFN_MAC_CMD_MODE_MASK          0x000c
 529 #define HIFN_MAC_CMD_MODE_HMAC          0x0000
 530 #define HIFN_MAC_CMD_MODE_SSL_MAC       0x0004
 531 #define HIFN_MAC_CMD_MODE_HASH          0x0008
 532 #define HIFN_MAC_CMD_MODE_FULL          0x0004
 533 #define HIFN_MAC_CMD_TRUNC              0x0010
 534 #define HIFN_MAC_CMD_RESULT             0x0020
 535 #define HIFN_MAC_CMD_APPEND             0x0040
 536 #define HIFN_MAC_CMD_SRCLEN_M           0xc000
 537 #define HIFN_MAC_CMD_SRCLEN_S           14
 538
 539 /*
 540  * MAC POS IPsec initiates authentication after encryption on encodes
 541  * and before decryption on decodes.
 542  */
 543 #define HIFN_MAC_CMD_POS_IPSEC          0x0200
 544 #define HIFN_MAC_CMD_NEW_KEY            0x0800
 545
 546 struct hifn_comp_command
 547 {
 548         volatile __le16         masks;
 549         volatile __le16         header_skip;
 550         volatile __le16         source_count;
 551         volatile __le16         reserved;
 552 };
 553
 554 #define HIFN_COMP_CMD_SRCLEN_M          0xc000
 555 #define HIFN_COMP_CMD_SRCLEN_S          14
 556 #define HIFN_COMP_CMD_ONE               0x0100  /* must be one */
 557 #define HIFN_COMP_CMD_CLEARHIST         0x0010  /* clear history */
 558 #define HIFN_COMP_CMD_UPDATEHIST        0x0008  /* update history */
 559 #define HIFN_COMP_CMD_LZS_STRIP0        0x0004  /* LZS: strip zero */
 560 #define HIFN_COMP_CMD_MPPC_RESTART      0x0004  /* MPPC: restart */
 561 #define HIFN_COMP_CMD_ALG_MASK          0x0001  /* compression mode: */
 562 #define HIFN_COMP_CMD_ALG_MPPC          0x0001  /*   MPPC */
 563 #define HIFN_COMP_CMD_ALG_LZS           0x0000  /*   LZS */
 564
 565 struct hifn_base_result
 566 {
 567         volatile __le16         flags;
 568         volatile __le16         session;
 569         volatile __le16         src_cnt;                /* 15:0 of source count */
 570         volatile __le16         dst_cnt;                /* 15:0 of dest count */
 571 };
 572
 573 #define HIFN_BASE_RES_DSTOVERRUN        0x0200  /* destination overrun */
 574 #define HIFN_BASE_RES_SRCLEN_M          0xc000  /* 17:16 of source count */
 575 #define HIFN_BASE_RES_SRCLEN_S          14
 576 #define HIFN_BASE_RES_DSTLEN_M          0x3000  /* 17:16 of dest count */
 577 #define HIFN_BASE_RES_DSTLEN_S          12
 578
 579 struct hifn_comp_result
 580 {
 581         volatile __le16         flags;
 582         volatile __le16         crc;
 583 };
 584
 585 #define HIFN_COMP_RES_LCB_M             0xff00  /* longitudinal check byte */
 586 #define HIFN_COMP_RES_LCB_S             8
 587 #define HIFN_COMP_RES_RESTART           0x0004  /* MPPC: restart */
 588 #define HIFN_COMP_RES_ENDMARKER         0x0002  /* LZS: end marker seen */
 589 #define HIFN_COMP_RES_SRC_NOTZERO       0x0001  /* source expired */
 590
 591 struct hifn_mac_result
 592 {
 593         volatile __le16         flags;
 594         volatile __le16         reserved;
 595         /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
 596 };
 597
 598 #define HIFN_MAC_RES_MISCOMPARE         0x0002  /* compare failed */
 599 #define HIFN_MAC_RES_SRC_NOTZERO        0x0001  /* source expired */
 600
 601 struct hifn_crypt_result
 602 {
 603         volatile __le16         flags;
 604         volatile __le16         reserved;
 605 };
 606
 607 #define HIFN_CRYPT_RES_SRC_NOTZERO      0x0001  /* source expired */
 608
 609 #ifndef HIFN_POLL_FREQUENCY
 610 #define HIFN_POLL_FREQUENCY     0x1
 611 #endif
 612
 613 #ifndef HIFN_POLL_SCALAR
 614 #define HIFN_POLL_SCALAR        0x0
 615 #endif
 616
 617 #define HIFN_MAX_SEGLEN         0xffff          /* maximum dma segment len */
 618 #define HIFN_MAX_DMALEN         0x3ffff         /* maximum dma length */
 619
 620 struct hifn_crypto_alg
 621 {
 622         struct list_head        entry;
 623         struct crypto_alg       alg;
 624         struct hifn_device      *dev;
 625 };
 626
 627 #define ASYNC_SCATTERLIST_CACHE 16
 628
 629 #define ASYNC_FLAGS_MISALIGNED  (1<<0)
 630
 631 struct hifn_cipher_walk
 632 {
 633         struct scatterlist      cache[ASYNC_SCATTERLIST_CACHE];
 634         u32                     flags;
 635         int                     num;
 636 };
 637
 638 struct hifn_context
 639 {
 640         u8                      key[HIFN_MAX_CRYPT_KEY_LENGTH];
 641         struct hifn_device      *dev;
 642         unsigned int            keysize;
 643 };
 644
 645 struct hifn_request_context
 646 {
 647         u8                      *iv;
 648         unsigned int            ivsize;
 649         u8                      op, type, mode, unused;
 650         struct hifn_cipher_walk walk;
 651 };
 652
 653 #define crypto_alg_to_hifn(a)   container_of(a, struct hifn_crypto_alg, alg)
 654
 655 static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg)
 656 {
 657         u32 ret;
 658
 659         ret = readl(dev->bar[0] + reg);
 660
 661         return ret;
 662 }
 663
 664 static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg)
 665 {
 666         u32 ret;
 667
 668         ret = readl(dev->bar[1] + reg);
 669
 670         return ret;
 671 }
 672
 673 static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val)
 674 {
 675         writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg);
 676 }
 677
 678 static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)
 679 {
 680         writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg);
 681 }
 682
 683 static void hifn_wait_puc(struct hifn_device *dev)
 684 {
 685         int i;
 686         u32 ret;
 687
 688         for (i=10000; i > 0; --i) {
 689                 ret = hifn_read_0(dev, HIFN_0_PUCTRL);
 690                 if (!(ret & HIFN_PUCTRL_RESET))
 691                         break;
 692
 693                 udelay(1);
 694         }
 695
 696         if (!i)
 697                 dev_err(&dev->pdev->dev, "Failed to reset PUC unit.\n");
 698 }
 699
 700 static void hifn_reset_puc(struct hifn_device *dev)
 701 {
 702         hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
 703         hifn_wait_puc(dev);
 704 }
 705
 706 static void hifn_stop_device(struct hifn_device *dev)
 707 {
 708         hifn_write_1(dev, HIFN_1_DMA_CSR,
 709                 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
 710                 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS);
 711         hifn_write_0(dev, HIFN_0_PUIER, 0);
 712         hifn_write_1(dev, HIFN_1_DMA_IER, 0);
 713 }
 714
 715 static void hifn_reset_dma(struct hifn_device *dev, int full)
 716 {
 717         hifn_stop_device(dev);
 718
 719         /*
 720          * Setting poll frequency and others to 0.
 721          */
 722         hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 723                         HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 724         mdelay(1);
 725
 726         /*
 727          * Reset DMA.
 728          */
 729         if (full) {
 730                 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
 731                 mdelay(1);
 732         } else {
 733                 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |
 734                                 HIFN_DMACNFG_MSTRESET);
 735                 hifn_reset_puc(dev);
 736         }
 737
 738         hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 739                         HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 740
 741         hifn_reset_puc(dev);
 742 }
 743
 744 static u32 hifn_next_signature(u_int32_t a, u_int cnt)
 745 {
 746         int i;
 747         u32 v;
 748
 749         for (i = 0; i < cnt; i++) {
 750
 751                 /* get the parity */
 752                 v = a & 0x80080125;
 753                 v ^= v >> 16;
 754                 v ^= v >> 8;
 755                 v ^= v >> 4;
 756                 v ^= v >> 2;
 757                 v ^= v >> 1;
 758
 759                 a = (v & 1) ^ (a << 1);
 760         }
 761
 762         return a;
 763 }
 764
 765 static struct pci2id {
 766         u_short         pci_vendor;
 767         u_short         pci_prod;
 768         char            card_id[13];
 769 } pci2id[] = {
 770         {
 771                 PCI_VENDOR_ID_HIFN,
 772                 PCI_DEVICE_ID_HIFN_7955,
 773                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 774                   0x00, 0x00, 0x00, 0x00, 0x00 }
 775         },
 776         {
 777                 PCI_VENDOR_ID_HIFN,
 778                 PCI_DEVICE_ID_HIFN_7956,
 779                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 780                   0x00, 0x00, 0x00, 0x00, 0x00 }
 781         }
 782 };
 783
 784 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
 785 static int hifn_rng_data_present(struct hwrng *rng, int wait)
 786 {
 787         struct hifn_device *dev = (struct hifn_device *)rng->priv;
 788         s64 nsec;
 789
 790         nsec = ktime_to_ns(ktime_sub(ktime_get(), dev->rngtime));
 791         nsec -= dev->rng_wait_time;
 792         if (nsec <= 0)
 793                 return 1;
 794         if (!wait)
 795                 return 0;
 796         ndelay(nsec);
 797         return 1;
 798 }
 799
 800 static int hifn_rng_data_read(struct hwrng *rng, u32 *data)
 801 {
 802         struct hifn_device *dev = (struct hifn_device *)rng->priv;
 803
 804         *data = hifn_read_1(dev, HIFN_1_RNG_DATA);
 805         dev->rngtime = ktime_get();
 806         return 4;
 807 }
 808
 809 static int hifn_register_rng(struct hifn_device *dev)
 810 {
 811         /*
 812          * We must wait at least 256 Pk_clk cycles between two reads of the rng.
 813          */
 814         dev->rng_wait_time      = DIV_ROUND_UP_ULL(NSEC_PER_SEC,
 815                                                    dev->pk_clk_freq) * 256;
 816
 817         dev->rng.name           = dev->name;
 818         dev->rng.data_present   = hifn_rng_data_present,
 819         dev->rng.data_read      = hifn_rng_data_read,
 820         dev->rng.priv           = (unsigned long)dev;
 821
 822         return hwrng_register(&dev->rng);
 823 }
 824
 825 static void hifn_unregister_rng(struct hifn_device *dev)
 826 {
 827         hwrng_unregister(&dev->rng);
 828 }
 829 #else
 830 #define hifn_register_rng(dev)          0
 831 #define hifn_unregister_rng(dev)
 832 #endif
 833
 834 static int hifn_init_pubrng(struct hifn_device *dev)
 835 {
 836         int i;
 837
 838         hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
 839                         HIFN_PUBRST_RESET);
 840
 841         for (i=100; i > 0; --i) {
 842                 mdelay(1);
 843
 844                 if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0)
 845                         break;
 846         }
 847
 848         if (!i)
 849                 dev_err(&dev->pdev->dev, "Failed to initialise public key engine.\n");
 850         else {
 851                 hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
 852                 dev->dmareg |= HIFN_DMAIER_PUBDONE;
 853                 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
 854
 855                 dev_dbg(&dev->pdev->dev, "Public key engine has been successfully initialised.\n");
 856         }
 857
 858         /*
 859          * Enable RNG engine.
 860          */
 861
 862         hifn_write_1(dev, HIFN_1_RNG_CONFIG,
 863                         hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA);
 864         dev_dbg(&dev->pdev->dev, "RNG engine has been successfully initialised.\n");
 865
 866 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
 867         /* First value must be discarded */
 868         hifn_read_1(dev, HIFN_1_RNG_DATA);
 869         dev->rngtime = ktime_get();
 870 #endif
 871         return 0;
 872 }
 873
 874 static int hifn_enable_crypto(struct hifn_device *dev)
 875 {
 876         u32 dmacfg, addr;
 877         char *offtbl = NULL;
 878         int i;
 879
 880         for (i = 0; i < ARRAY_SIZE(pci2id); i++) {
 881                 if (pci2id[i].pci_vendor == dev->pdev->vendor &&
 882                                 pci2id[i].pci_prod == dev->pdev->device) {
 883                         offtbl = pci2id[i].card_id;
 884                         break;
 885                 }
 886         }
 887
 888         if (offtbl == NULL) {
 889                 dev_err(&dev->pdev->dev, "Unknown card!\n");
 890                 return -ENODEV;
 891         }
 892
 893         dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG);
 894
 895         hifn_write_1(dev, HIFN_1_DMA_CNFG,
 896                         HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET |
 897                         HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 898         mdelay(1);
 899         addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1);
 900         mdelay(1);
 901         hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
 902         mdelay(1);
 903
 904         for (i=0; i<12; ++i) {
 905                 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
 906                 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
 907
 908                 mdelay(1);
 909         }
 910         hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
 911
 912         dev_dbg(&dev->pdev->dev, "%s %s.\n", dev->name, pci_name(dev->pdev));
 913
 914         return 0;
 915 }
 916
 917 static void hifn_init_dma(struct hifn_device *dev)
 918 {
 919         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
 920         u32 dptr = dev->desc_dma;
 921         int i;
 922
 923         for (i=0; i<HIFN_D_CMD_RSIZE; ++i)
 924                 dma->cmdr[i].p = __cpu_to_le32(dptr +
 925                                 offsetof(struct hifn_dma, command_bufs[i][0]));
 926         for (i=0; i<HIFN_D_RES_RSIZE; ++i)
 927                 dma->resr[i].p = __cpu_to_le32(dptr +
 928                                 offsetof(struct hifn_dma, result_bufs[i][0]));
 929
 930         /*
 931          * Setup LAST descriptors.
 932          */
 933         dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr +
 934                         offsetof(struct hifn_dma, cmdr[0]));
 935         dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr +
 936                         offsetof(struct hifn_dma, srcr[0]));
 937         dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr +
 938                         offsetof(struct hifn_dma, dstr[0]));
 939         dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr +
 940                         offsetof(struct hifn_dma, resr[0]));
 941
 942         dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
 943         dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
 944         dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
 945 }
 946
 947 /*
 948  * Initialize the PLL. We need to know the frequency of the reference clock
 949  * to calculate the optimal multiplier. For PCI we assume 66MHz, since that
 950  * allows us to operate without the risk of overclocking the chip. If it
 951  * actually uses 33MHz, the chip will operate at half the speed, this can be
 952  * overriden by specifying the frequency as module parameter (pci33).
 953  *
 954  * Unfortunately the PCI clock is not very suitable since the HIFN needs a
 955  * stable clock and the PCI clock frequency may vary, so the default is the
 956  * external clock. There is no way to find out its frequency, we default to
 957  * 66MHz since according to Mike Ham of HiFn, almost every board in existence
 958  * has an external crystal populated at 66MHz.
 959  */
 960 static void hifn_init_pll(struct hifn_device *dev)
 961 {
 962         unsigned int freq, m;
 963         u32 pllcfg;
 964
 965         pllcfg = HIFN_1_PLL | HIFN_PLL_RESERVED_1;
 966
 967         if (strncmp(hifn_pll_ref, "ext", 3) == 0)
 968                 pllcfg |= HIFN_PLL_REF_CLK_PLL;
 969         else
 970                 pllcfg |= HIFN_PLL_REF_CLK_HBI;
 971
 972         if (hifn_pll_ref[3] != '\0')
 973                 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
 974         else {
 975                 freq = 66;
 976                 dev_info(&dev->pdev->dev, "assuming %uMHz clock speed, override with hifn_pll_ref=%.3s<frequency>\n",
 977                          freq, hifn_pll_ref);
 978         }
 979
 980         m = HIFN_PLL_FCK_MAX / freq;
 981
 982         pllcfg |= (m / 2 - 1) << HIFN_PLL_ND_SHIFT;
 983         if (m <= 8)
 984                 pllcfg |= HIFN_PLL_IS_1_8;
 985         else
 986                 pllcfg |= HIFN_PLL_IS_9_12;
 987
 988         /* Select clock source and enable clock bypass */
 989         hifn_write_1(dev, HIFN_1_PLL, pllcfg |
 990                      HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI | HIFN_PLL_BP);
 991
 992         /* Let the chip lock to the input clock */
 993         mdelay(10);
 994
 995         /* Disable clock bypass */
 996         hifn_write_1(dev, HIFN_1_PLL, pllcfg |
 997                      HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI);
 998
 999         /* Switch the engines to the PLL */
1000         hifn_write_1(dev, HIFN_1_PLL, pllcfg |
1001                      HIFN_PLL_PK_CLK_PLL | HIFN_PLL_PE_CLK_PLL);
1002
1003         /*
1004          * The Fpk_clk runs at half the total speed. Its frequency is needed to
1005          * calculate the minimum time between two reads of the rng. Since 33MHz
1006          * is actually 33.333... we overestimate the frequency here, resulting
1007          * in slightly larger intervals.
1008          */
1009         dev->pk_clk_freq = 1000000 * (freq + 1) * m / 2;
1010 }
1011
1012 static void hifn_init_registers(struct hifn_device *dev)
1013 {
1014         u32 dptr = dev->desc_dma;
1015
1016         /* Initialization magic... */
1017         hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1018         hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1019         hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1020
1021         /* write all 4 ring address registers */
1022         hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr +
1023                                 offsetof(struct hifn_dma, cmdr[0]));
1024         hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr +
1025                                 offsetof(struct hifn_dma, srcr[0]));
1026         hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr +
1027                                 offsetof(struct hifn_dma, dstr[0]));
1028         hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr +
1029                                 offsetof(struct hifn_dma, resr[0]));
1030
1031         mdelay(2);
1032 #if 0
1033         hifn_write_1(dev, HIFN_1_DMA_CSR,
1034             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1035             HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1036             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1037             HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1038             HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1039             HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1040             HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1041             HIFN_DMACSR_S_WAIT |
1042             HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1043             HIFN_DMACSR_C_WAIT |
1044             HIFN_DMACSR_ENGINE |
1045             HIFN_DMACSR_PUBDONE);
1046 #else
1047         hifn_write_1(dev, HIFN_1_DMA_CSR,
1048             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1049             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA |
1050             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1051             HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1052             HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1053             HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1054             HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1055             HIFN_DMACSR_S_WAIT |
1056             HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1057             HIFN_DMACSR_C_WAIT |
1058             HIFN_DMACSR_ENGINE |
1059             HIFN_DMACSR_PUBDONE);
1060 #endif
1061         hifn_read_1(dev, HIFN_1_DMA_CSR);
1062
1063         dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1064             HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1065             HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1066             HIFN_DMAIER_ENGINE;
1067         dev->dmareg &= ~HIFN_DMAIER_C_WAIT;
1068
1069         hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1070         hifn_read_1(dev, HIFN_1_DMA_IER);
1071 #if 0
1072         hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG |
1073                     HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1074                     HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1075                     HIFN_PUCNFG_DRAM);
1076 #else
1077         hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342);
1078 #endif
1079         hifn_init_pll(dev);
1080
1081         hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1082         hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1083             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1084             ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1085             ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1086 }
1087
1088 static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf,
1089                 unsigned dlen, unsigned slen, u16 mask, u8 snum)
1090 {
1091         struct hifn_base_command *base_cmd;
1092         u8 *buf_pos = buf;
1093
1094         base_cmd = (struct hifn_base_command *)buf_pos;
1095         base_cmd->masks = __cpu_to_le16(mask);
1096         base_cmd->total_source_count =
1097                 __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO);
1098         base_cmd->total_dest_count =
1099                 __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1100
1101         dlen >>= 16;
1102         slen >>= 16;
1103         base_cmd->session_num = __cpu_to_le16(snum |
1104             ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1105             ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1106
1107         return sizeof(struct hifn_base_command);
1108 }
1109
1110 static int hifn_setup_crypto_command(struct hifn_device *dev,
1111                 u8 *buf, unsigned dlen, unsigned slen,
1112                 u8 *key, int keylen, u8 *iv, int ivsize, u16 mode)
1113 {
1114         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1115         struct hifn_crypt_command *cry_cmd;
1116         u8 *buf_pos = buf;
1117         u16 cmd_len;
1118
1119         cry_cmd = (struct hifn_crypt_command *)buf_pos;
1120
1121         cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff);
1122         dlen >>= 16;
1123         cry_cmd->masks = __cpu_to_le16(mode |
1124                         ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) &
1125                          HIFN_CRYPT_CMD_SRCLEN_M));
1126         cry_cmd->header_skip = 0;
1127         cry_cmd->reserved = 0;
1128
1129         buf_pos += sizeof(struct hifn_crypt_command);
1130
1131         dma->cmdu++;
1132         if (dma->cmdu > 1) {
1133                 dev->dmareg |= HIFN_DMAIER_C_WAIT;
1134                 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1135         }
1136
1137         if (keylen) {
1138                 memcpy(buf_pos, key, keylen);
1139                 buf_pos += keylen;
1140         }
1141         if (ivsize) {
1142                 memcpy(buf_pos, iv, ivsize);
1143                 buf_pos += ivsize;
1144         }
1145
1146         cmd_len = buf_pos - buf;
1147
1148         return cmd_len;
1149 }
1150
1151 static int hifn_setup_cmd_desc(struct hifn_device *dev,
1152                 struct hifn_context *ctx, struct hifn_request_context *rctx,
1153                 void *priv, unsigned int nbytes)
1154 {
1155         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1156         int cmd_len, sa_idx;
1157         u8 *buf, *buf_pos;
1158         u16 mask;
1159
1160         sa_idx = dma->cmdi;
1161         buf_pos = buf = dma->command_bufs[dma->cmdi];
1162
1163         mask = 0;
1164         switch (rctx->op) {
1165                 case ACRYPTO_OP_DECRYPT:
1166                         mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE;
1167                         break;
1168                 case ACRYPTO_OP_ENCRYPT:
1169                         mask = HIFN_BASE_CMD_CRYPT;
1170                         break;
1171                 case ACRYPTO_OP_HMAC:
1172                         mask = HIFN_BASE_CMD_MAC;
1173                         break;
1174                 default:
1175                         goto err_out;
1176         }
1177
1178         buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes,
1179                         nbytes, mask, dev->snum);
1180
1181         if (rctx->op == ACRYPTO_OP_ENCRYPT || rctx->op == ACRYPTO_OP_DECRYPT) {
1182                 u16 md = 0;
1183
1184                 if (ctx->keysize)
1185                         md |= HIFN_CRYPT_CMD_NEW_KEY;
1186                 if (rctx->iv && rctx->mode != ACRYPTO_MODE_ECB)
1187                         md |= HIFN_CRYPT_CMD_NEW_IV;
1188
1189                 switch (rctx->mode) {
1190                         case ACRYPTO_MODE_ECB:
1191                                 md |= HIFN_CRYPT_CMD_MODE_ECB;
1192                                 break;
1193                         case ACRYPTO_MODE_CBC:
1194                                 md |= HIFN_CRYPT_CMD_MODE_CBC;
1195                                 break;
1196                         case ACRYPTO_MODE_CFB:
1197                                 md |= HIFN_CRYPT_CMD_MODE_CFB;
1198                                 break;
1199                         case ACRYPTO_MODE_OFB:
1200                                 md |= HIFN_CRYPT_CMD_MODE_OFB;
1201                                 break;
1202                         default:
1203                                 goto err_out;
1204                 }
1205
1206                 switch (rctx->type) {
1207                         case ACRYPTO_TYPE_AES_128:
1208                                 if (ctx->keysize != 16)
1209                                         goto err_out;
1210                                 md |= HIFN_CRYPT_CMD_KSZ_128 |
1211                                         HIFN_CRYPT_CMD_ALG_AES;
1212                                 break;
1213                         case ACRYPTO_TYPE_AES_192:
1214                                 if (ctx->keysize != 24)
1215                                         goto err_out;
1216                                 md |= HIFN_CRYPT_CMD_KSZ_192 |
1217                                         HIFN_CRYPT_CMD_ALG_AES;
1218                                 break;
1219                         case ACRYPTO_TYPE_AES_256:
1220                                 if (ctx->keysize != 32)
1221                                         goto err_out;
1222                                 md |= HIFN_CRYPT_CMD_KSZ_256 |
1223                                         HIFN_CRYPT_CMD_ALG_AES;
1224                                 break;
1225                         case ACRYPTO_TYPE_3DES:
1226                                 if (ctx->keysize != 24)
1227                                         goto err_out;
1228                                 md |= HIFN_CRYPT_CMD_ALG_3DES;
1229                                 break;
1230                         case ACRYPTO_TYPE_DES:
1231                                 if (ctx->keysize != 8)
1232                                         goto err_out;
1233                                 md |= HIFN_CRYPT_CMD_ALG_DES;
1234                                 break;
1235                         default:
1236                                 goto err_out;
1237                 }
1238
1239                 buf_pos += hifn_setup_crypto_command(dev, buf_pos,
1240                                 nbytes, nbytes, ctx->key, ctx->keysize,
1241                                 rctx->iv, rctx->ivsize, md);
1242         }
1243
1244         dev->sa[sa_idx] = priv;
1245         dev->started++;
1246
1247         cmd_len = buf_pos - buf;
1248         dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID |
1249                         HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
1250
1251         if (++dma->cmdi == HIFN_D_CMD_RSIZE) {
1252                 dma->cmdr[dma->cmdi].l = __cpu_to_le32(
1253                         HIFN_D_VALID | HIFN_D_LAST |
1254                         HIFN_D_MASKDONEIRQ | HIFN_D_JUMP);
1255                 dma->cmdi = 0;
1256         } else
1257                 dma->cmdr[dma->cmdi-1].l |= __cpu_to_le32(HIFN_D_VALID);
1258
1259         if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) {
1260                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1261                 dev->flags |= HIFN_FLAG_CMD_BUSY;
1262         }
1263         return 0;
1264
1265 err_out:
1266         return -EINVAL;
1267 }
1268
1269 static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page,
1270                 unsigned int offset, unsigned int size, int last)
1271 {
1272         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1273         int idx;
1274         dma_addr_t addr;
1275
1276         addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE);
1277
1278         idx = dma->srci;
1279
1280         dma->srcr[idx].p = __cpu_to_le32(addr);
1281         dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
1282                         HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
1283
1284         if (++idx == HIFN_D_SRC_RSIZE) {
1285                 dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1286                                 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
1287                                 (last ? HIFN_D_LAST : 0));
1288                 idx = 0;
1289         }
1290
1291         dma->srci = idx;
1292         dma->srcu++;
1293
1294         if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) {
1295                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1296                 dev->flags |= HIFN_FLAG_SRC_BUSY;
1297         }
1298
1299         return size;
1300 }
1301
1302 static void hifn_setup_res_desc(struct hifn_device *dev)
1303 {
1304         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1305
1306         dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT |
1307                         HIFN_D_VALID | HIFN_D_LAST);
1308         /*
1309          * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID |
1310          *                                      HIFN_D_LAST);
1311          */
1312
1313         if (++dma->resi == HIFN_D_RES_RSIZE) {
1314                 dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID |
1315                                 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
1316                 dma->resi = 0;
1317         }
1318
1319         dma->resu++;
1320
1321         if (!(dev->flags & HIFN_FLAG_RES_BUSY)) {
1322                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
1323                 dev->flags |= HIFN_FLAG_RES_BUSY;
1324         }
1325 }
1326
1327 static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page,
1328                 unsigned offset, unsigned size, int last)
1329 {
1330         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1331         int idx;
1332         dma_addr_t addr;
1333
1334         addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE);
1335
1336         idx = dma->dsti;
1337         dma->dstr[idx].p = __cpu_to_le32(addr);
1338         dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
1339                         HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
1340
1341         if (++idx == HIFN_D_DST_RSIZE) {
1342                 dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1343                                 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
1344                                 (last ? HIFN_D_LAST : 0));
1345                 idx = 0;
1346         }
1347         dma->dsti = idx;
1348         dma->dstu++;
1349
1350         if (!(dev->flags & HIFN_FLAG_DST_BUSY)) {
1351                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
1352                 dev->flags |= HIFN_FLAG_DST_BUSY;
1353         }
1354 }
1355
1356 static int hifn_setup_dma(struct hifn_device *dev,
1357                 struct hifn_context *ctx, struct hifn_request_context *rctx,
1358                 struct scatterlist *src, struct scatterlist *dst,
1359                 unsigned int nbytes, void *priv)
1360 {
1361         struct scatterlist *t;
1362         struct page *spage, *dpage;
1363         unsigned int soff, doff;
1364         unsigned int n, len;
1365
1366         n = nbytes;
1367         while (n) {
1368                 spage = sg_page(src);
1369                 soff = src->offset;
1370                 len = min(src->length, n);
1371
1372                 hifn_setup_src_desc(dev, spage, soff, len, n - len == 0);
1373
1374                 src++;
1375                 n -= len;
1376         }
1377
1378         t = &rctx->walk.cache[0];
1379         n = nbytes;
1380         while (n) {
1381                 if (t->length && rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1382                         BUG_ON(!sg_page(t));
1383                         dpage = sg_page(t);
1384                         doff = 0;
1385                         len = t->length;
1386                 } else {
1387                         BUG_ON(!sg_page(dst));
1388                         dpage = sg_page(dst);
1389                         doff = dst->offset;
1390                         len = dst->length;
1391                 }
1392                 len = min(len, n);
1393
1394                 hifn_setup_dst_desc(dev, dpage, doff, len, n - len == 0);
1395
1396                 dst++;
1397                 t++;
1398                 n -= len;
1399         }
1400
1401         hifn_setup_cmd_desc(dev, ctx, rctx, priv, nbytes);
1402         hifn_setup_res_desc(dev);
1403         return 0;
1404 }
1405
1406 static int hifn_cipher_walk_init(struct hifn_cipher_walk *w,
1407                 int num, gfp_t gfp_flags)
1408 {
1409         int i;
1410
1411         num = min(ASYNC_SCATTERLIST_CACHE, num);
1412         sg_init_table(w->cache, num);
1413
1414         w->num = 0;
1415         for (i=0; i<num; ++i) {
1416                 struct page *page = alloc_page(gfp_flags);
1417                 struct scatterlist *s;
1418
1419                 if (!page)
1420                         break;
1421
1422                 s = &w->cache[i];
1423
1424                 sg_set_page(s, page, PAGE_SIZE, 0);
1425                 w->num++;
1426         }
1427
1428         return i;
1429 }
1430
1431 static void hifn_cipher_walk_exit(struct hifn_cipher_walk *w)
1432 {
1433         int i;
1434
1435         for (i=0; i<w->num; ++i) {
1436                 struct scatterlist *s = &w->cache[i];
1437
1438                 __free_page(sg_page(s));
1439
1440                 s->length = 0;
1441         }
1442
1443         w->num = 0;
1444 }
1445
1446 static int ablkcipher_add(unsigned int *drestp, struct scatterlist *dst,
1447                 unsigned int size, unsigned int *nbytesp)
1448 {
1449         unsigned int copy, drest = *drestp, nbytes = *nbytesp;
1450         int idx = 0;
1451
1452         if (drest < size || size > nbytes)
1453                 return -EINVAL;
1454
1455         while (size) {
1456                 copy = min3(drest, size, dst->length);
1457
1458                 size -= copy;
1459                 drest -= copy;
1460                 nbytes -= copy;
1461
1462                 pr_debug("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
1463                          __func__, copy, size, drest, nbytes);
1464
1465                 dst++;
1466                 idx++;
1467         }
1468
1469         *nbytesp = nbytes;
1470         *drestp = drest;
1471
1472         return idx;
1473 }
1474
1475 static int hifn_cipher_walk(struct ablkcipher_request *req,
1476                 struct hifn_cipher_walk *w)
1477 {
1478         struct scatterlist *dst, *t;
1479         unsigned int nbytes = req->nbytes, offset, copy, diff;
1480         int idx, tidx, err;
1481
1482         tidx = idx = 0;
1483         offset = 0;
1484         while (nbytes) {
1485                 if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED))
1486                         return -EINVAL;
1487
1488                 dst = &req->dst[idx];
1489
1490                 pr_debug("\n%s: dlen: %u, doff: %u, offset: %u, nbytes: %u.\n",
1491                          __func__, dst->length, dst->offset, offset, nbytes);
1492
1493                 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
1494                     !IS_ALIGNED(dst->length, HIFN_D_DST_DALIGN) ||
1495                     offset) {
1496                         unsigned slen = min(dst->length - offset, nbytes);
1497                         unsigned dlen = PAGE_SIZE;
1498
1499                         t = &w->cache[idx];
1500
1501                         err = ablkcipher_add(&dlen, dst, slen, &nbytes);
1502                         if (err < 0)
1503                                 return err;
1504
1505                         idx += err;
1506
1507                         copy = slen & ~(HIFN_D_DST_DALIGN - 1);
1508                         diff = slen & (HIFN_D_DST_DALIGN - 1);
1509
1510                         if (dlen < nbytes) {
1511                                 /*
1512                                  * Destination page does not have enough space
1513                                  * to put there additional blocksized chunk,
1514                                  * so we mark that page as containing only
1515                                  * blocksize aligned chunks:
1516                                  *      t->length = (slen & ~(HIFN_D_DST_DALIGN - 1));
1517                                  * and increase number of bytes to be processed
1518                                  * in next chunk:
1519                                  *      nbytes += diff;
1520                                  */
1521                                 nbytes += diff;
1522
1523                                 /*
1524                                  * Temporary of course...
1525                                  * Kick author if you will catch this one.
1526                                  */
1527                                 pr_err("%s: dlen: %u, nbytes: %u, slen: %u, offset: %u.\n",
1528                                        __func__, dlen, nbytes, slen, offset);
1529                                 pr_err("%s: please contact author to fix this "
1530                                        "issue, generally you should not catch "
1531                                        "this path under any condition but who "
1532                                        "knows how did you use crypto code.\n"
1533                                        "Thank you.\n",  __func__);
1534                                 BUG();
1535                         } else {
1536                                 copy += diff + nbytes;
1537
1538                                 dst = &req->dst[idx];
1539
1540                                 err = ablkcipher_add(&dlen, dst, nbytes, &nbytes);
1541                                 if (err < 0)
1542                                         return err;
1543
1544                                 idx += err;
1545                         }
1546
1547                         t->length = copy;
1548                         t->offset = offset;
1549                 } else {
1550                         nbytes -= min(dst->length, nbytes);
1551                         idx++;
1552                 }
1553
1554                 tidx++;
1555         }
1556
1557         return tidx;
1558 }
1559
1560 static int hifn_setup_session(struct ablkcipher_request *req)
1561 {
1562         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1563         struct hifn_request_context *rctx = ablkcipher_request_ctx(req);
1564         struct hifn_device *dev = ctx->dev;
1565         unsigned long dlen, flags;
1566         unsigned int nbytes = req->nbytes, idx = 0;
1567         int err = -EINVAL, sg_num;
1568         struct scatterlist *dst;
1569
1570         if (rctx->iv && !rctx->ivsize && rctx->mode != ACRYPTO_MODE_ECB)
1571                 goto err_out_exit;
1572
1573         rctx->walk.flags = 0;
1574
1575         while (nbytes) {
1576                 dst = &req->dst[idx];
1577                 dlen = min(dst->length, nbytes);
1578
1579                 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
1580                     !IS_ALIGNED(dlen, HIFN_D_DST_DALIGN))
1581                         rctx->walk.flags |= ASYNC_FLAGS_MISALIGNED;
1582
1583                 nbytes -= dlen;
1584                 idx++;
1585         }
1586
1587         if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1588                 err = hifn_cipher_walk_init(&rctx->walk, idx, GFP_ATOMIC);
1589                 if (err < 0)
1590                         return err;
1591         }
1592
1593         sg_num = hifn_cipher_walk(req, &rctx->walk);
1594         if (sg_num < 0) {
1595                 err = sg_num;
1596                 goto err_out_exit;
1597         }
1598
1599         spin_lock_irqsave(&dev->lock, flags);
1600         if (dev->started + sg_num > HIFN_QUEUE_LENGTH) {
1601                 err = -EAGAIN;
1602                 goto err_out;
1603         }
1604
1605         err = hifn_setup_dma(dev, ctx, rctx, req->src, req->dst, req->nbytes, req);
1606         if (err)
1607                 goto err_out;
1608
1609         dev->snum++;
1610
1611         dev->active = HIFN_DEFAULT_ACTIVE_NUM;
1612         spin_unlock_irqrestore(&dev->lock, flags);
1613
1614         return 0;
1615
1616 err_out:
1617         spin_unlock_irqrestore(&dev->lock, flags);
1618 err_out_exit:
1619         if (err) {
1620                 dev_info(&dev->pdev->dev, "iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
1621                          "type: %u, err: %d.\n",
1622                          rctx->iv, rctx->ivsize,
1623                          ctx->key, ctx->keysize,
1624                          rctx->mode, rctx->op, rctx->type, err);
1625         }
1626
1627         return err;
1628 }
1629
1630 static int hifn_start_device(struct hifn_device *dev)
1631 {
1632         int err;
1633
1634         dev->started = dev->active = 0;
1635         hifn_reset_dma(dev, 1);
1636
1637         err = hifn_enable_crypto(dev);
1638         if (err)
1639                 return err;
1640
1641         hifn_reset_puc(dev);
1642
1643         hifn_init_dma(dev);
1644
1645         hifn_init_registers(dev);
1646
1647         hifn_init_pubrng(dev);
1648
1649         return 0;
1650 }
1651
1652 static int ablkcipher_get(void *saddr, unsigned int *srestp, unsigned int offset,
1653                 struct scatterlist *dst, unsigned int size, unsigned int *nbytesp)
1654 {
1655         unsigned int srest = *srestp, nbytes = *nbytesp, copy;
1656         void *daddr;
1657         int idx = 0;
1658
1659         if (srest < size || size > nbytes)
1660                 return -EINVAL;
1661
1662         while (size) {
1663                 copy = min3(srest, dst->length, size);
1664
1665                 daddr = kmap_atomic(sg_page(dst));
1666                 memcpy(daddr + dst->offset + offset, saddr, copy);
1667                 kunmap_atomic(daddr);
1668
1669                 nbytes -= copy;
1670                 size -= copy;
1671                 srest -= copy;
1672                 saddr += copy;
1673                 offset = 0;
1674
1675                 pr_debug("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n",
1676                          __func__, copy, size, srest, nbytes);
1677
1678                 dst++;
1679                 idx++;
1680         }
1681
1682         *nbytesp = nbytes;
1683         *srestp = srest;
1684
1685         return idx;
1686 }
1687
1688 static inline void hifn_complete_sa(struct hifn_device *dev, int i)
1689 {
1690         unsigned long flags;
1691
1692         spin_lock_irqsave(&dev->lock, flags);
1693         dev->sa[i] = NULL;
1694         dev->started--;
1695         if (dev->started < 0)
1696                 dev_info(&dev->pdev->dev, "%s: started: %d.\n", __func__,
1697                          dev->started);
1698         spin_unlock_irqrestore(&dev->lock, flags);
1699         BUG_ON(dev->started < 0);
1700 }
1701
1702 static void hifn_process_ready(struct ablkcipher_request *req, int error)
1703 {
1704         struct hifn_request_context *rctx = ablkcipher_request_ctx(req);
1705
1706         if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1707                 unsigned int nbytes = req->nbytes;
1708                 int idx = 0, err;
1709                 struct scatterlist *dst, *t;
1710                 void *saddr;
1711
1712                 while (nbytes) {
1713                         t = &rctx->walk.cache[idx];
1714                         dst = &req->dst[idx];
1715
1716                         pr_debug("\n%s: sg_page(t): %p, t->length: %u, "
1717                                 "sg_page(dst): %p, dst->length: %u, "
1718                                 "nbytes: %u.\n",
1719                                 __func__, sg_page(t), t->length,
1720                                 sg_page(dst), dst->length, nbytes);
1721
1722                         if (!t->length) {
1723                                 nbytes -= min(dst->length, nbytes);
1724                                 idx++;
1725                                 continue;
1726                         }
1727
1728                         saddr = kmap_atomic(sg_page(t));
1729
1730                         err = ablkcipher_get(saddr, &t->length, t->offset,
1731                                         dst, nbytes, &nbytes);
1732                         if (err < 0) {
1733                                 kunmap_atomic(saddr);
1734                                 break;
1735                         }
1736
1737                         idx += err;
1738                         kunmap_atomic(saddr);
1739                 }
1740
1741                 hifn_cipher_walk_exit(&rctx->walk);
1742         }
1743
1744         req->base.complete(&req->base, error);
1745 }
1746
1747 static void hifn_clear_rings(struct hifn_device *dev, int error)
1748 {
1749         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1750         int i, u;
1751
1752         dev_dbg(&dev->pdev->dev, "ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1753                         "k: %d.%d.%d.%d.\n",
1754                         dma->cmdi, dma->srci, dma->dsti, dma->resi,
1755                         dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1756                         dma->cmdk, dma->srck, dma->dstk, dma->resk);
1757
1758         i = dma->resk; u = dma->resu;
1759         while (u != 0) {
1760                 if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID))
1761                         break;
1762
1763                 if (dev->sa[i]) {
1764                         dev->success++;
1765                         dev->reset = 0;
1766                         hifn_process_ready(dev->sa[i], error);
1767                         hifn_complete_sa(dev, i);
1768                 }
1769
1770                 if (++i == HIFN_D_RES_RSIZE)
1771                         i = 0;
1772                 u--;
1773         }
1774         dma->resk = i; dma->resu = u;
1775
1776         i = dma->srck; u = dma->srcu;
1777         while (u != 0) {
1778                 if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID))
1779                         break;
1780                 if (++i == HIFN_D_SRC_RSIZE)
1781                         i = 0;
1782                 u--;
1783         }
1784         dma->srck = i; dma->srcu = u;
1785
1786         i = dma->cmdk; u = dma->cmdu;
1787         while (u != 0) {
1788                 if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID))
1789                         break;
1790                 if (++i == HIFN_D_CMD_RSIZE)
1791                         i = 0;
1792                 u--;
1793         }
1794         dma->cmdk = i; dma->cmdu = u;
1795
1796         i = dma->dstk; u = dma->dstu;
1797         while (u != 0) {
1798                 if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID))
1799                         break;
1800                 if (++i == HIFN_D_DST_RSIZE)
1801                         i = 0;
1802                 u--;
1803         }
1804         dma->dstk = i; dma->dstu = u;
1805
1806         dev_dbg(&dev->pdev->dev, "ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1807                         "k: %d.%d.%d.%d.\n",
1808                         dma->cmdi, dma->srci, dma->dsti, dma->resi,
1809                         dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1810                         dma->cmdk, dma->srck, dma->dstk, dma->resk);
1811 }
1812
1813 static void hifn_work(struct work_struct *work)
1814 {
1815         struct delayed_work *dw = to_delayed_work(work);
1816         struct hifn_device *dev = container_of(dw, struct hifn_device, work);
1817         unsigned long flags;
1818         int reset = 0;
1819         u32 r = 0;
1820
1821         spin_lock_irqsave(&dev->lock, flags);
1822         if (dev->active == 0) {
1823                 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1824
1825                 if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) {
1826                         dev->flags &= ~HIFN_FLAG_CMD_BUSY;
1827                         r |= HIFN_DMACSR_C_CTRL_DIS;
1828                 }
1829                 if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) {
1830                         dev->flags &= ~HIFN_FLAG_SRC_BUSY;
1831                         r |= HIFN_DMACSR_S_CTRL_DIS;
1832                 }
1833                 if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) {
1834                         dev->flags &= ~HIFN_FLAG_DST_BUSY;
1835                         r |= HIFN_DMACSR_D_CTRL_DIS;
1836                 }
1837                 if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) {
1838                         dev->flags &= ~HIFN_FLAG_RES_BUSY;
1839                         r |= HIFN_DMACSR_R_CTRL_DIS;
1840                 }
1841                 if (r)
1842                         hifn_write_1(dev, HIFN_1_DMA_CSR, r);
1843         } else
1844                 dev->active--;
1845
1846         if ((dev->prev_success == dev->success) && dev->started)
1847                 reset = 1;
1848         dev->prev_success = dev->success;
1849         spin_unlock_irqrestore(&dev->lock, flags);
1850
1851         if (reset) {
1852                 if (++dev->reset >= 5) {
1853                         int i;
1854                         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1855
1856                         dev_info(&dev->pdev->dev,
1857                                  "r: %08x, active: %d, started: %d, "
1858                                  "success: %lu: qlen: %u/%u, reset: %d.\n",
1859                                  r, dev->active, dev->started,
1860                                  dev->success, dev->queue.qlen, dev->queue.max_qlen,
1861                                  reset);
1862
1863                         dev_info(&dev->pdev->dev, "%s: res: ", __func__);
1864                         for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
1865                                 pr_info("%x.%p ", dma->resr[i].l, dev->sa[i]);
1866                                 if (dev->sa[i]) {
1867                                         hifn_process_ready(dev->sa[i], -ENODEV);
1868                                         hifn_complete_sa(dev, i);
1869                                 }
1870                         }
1871                         pr_info("\n");
1872
1873                         hifn_reset_dma(dev, 1);
1874                         hifn_stop_device(dev);
1875                         hifn_start_device(dev);
1876                         dev->reset = 0;
1877                 }
1878
1879                 tasklet_schedule(&dev->tasklet);
1880         }
1881
1882         schedule_delayed_work(&dev->work, HZ);
1883 }
1884
1885 static irqreturn_t hifn_interrupt(int irq, void *data)
1886 {
1887         struct hifn_device *dev = (struct hifn_device *)data;
1888         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1889         u32 dmacsr, restart;
1890
1891         dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR);
1892
1893         dev_dbg(&dev->pdev->dev, "1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], "
1894                         "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n",
1895                 dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi,
1896                 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1897                 dma->cmdu, dma->srcu, dma->dstu, dma->resu);
1898
1899         if ((dmacsr & dev->dmareg) == 0)
1900                 return IRQ_NONE;
1901
1902         hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);
1903
1904         if (dmacsr & HIFN_DMACSR_ENGINE)
1905                 hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR));
1906         if (dmacsr & HIFN_DMACSR_PUBDONE)
1907                 hifn_write_1(dev, HIFN_1_PUB_STATUS,
1908                         hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
1909
1910         restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER);
1911         if (restart) {
1912                 u32 puisr = hifn_read_0(dev, HIFN_0_PUISR);
1913
1914                 dev_warn(&dev->pdev->dev, "overflow: r: %d, d: %d, puisr: %08x, d: %u.\n",
1915                          !!(dmacsr & HIFN_DMACSR_R_OVER),
1916                          !!(dmacsr & HIFN_DMACSR_D_OVER),
1917                         puisr, !!(puisr & HIFN_PUISR_DSTOVER));
1918                 if (!!(puisr & HIFN_PUISR_DSTOVER))
1919                         hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1920                 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |
1921                                         HIFN_DMACSR_D_OVER));
1922         }
1923
1924         restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
1925                         HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
1926         if (restart) {
1927                 dev_warn(&dev->pdev->dev, "abort: c: %d, s: %d, d: %d, r: %d.\n",
1928                          !!(dmacsr & HIFN_DMACSR_C_ABORT),
1929                          !!(dmacsr & HIFN_DMACSR_S_ABORT),
1930                          !!(dmacsr & HIFN_DMACSR_D_ABORT),
1931                          !!(dmacsr & HIFN_DMACSR_R_ABORT));
1932                 hifn_reset_dma(dev, 1);
1933                 hifn_init_dma(dev);
1934                 hifn_init_registers(dev);
1935         }
1936
1937         if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
1938                 dev_dbg(&dev->pdev->dev, "wait on command.\n");
1939                 dev->dmareg &= ~(HIFN_DMAIER_C_WAIT);
1940                 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1941         }
1942
1943         tasklet_schedule(&dev->tasklet);
1944
1945         return IRQ_HANDLED;
1946 }
1947
1948 static void hifn_flush(struct hifn_device *dev)
1949 {
1950         unsigned long flags;
1951         struct crypto_async_request *async_req;
1952         struct ablkcipher_request *req;
1953         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1954         int i;
1955
1956         for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
1957                 struct hifn_desc *d = &dma->resr[i];
1958
1959                 if (dev->sa[i]) {
1960                         hifn_process_ready(dev->sa[i],
1961                                 (d->l & __cpu_to_le32(HIFN_D_VALID))?-ENODEV:0);
1962                         hifn_complete_sa(dev, i);
1963                 }
1964         }
1965
1966         spin_lock_irqsave(&dev->lock, flags);
1967         while ((async_req = crypto_dequeue_request(&dev->queue))) {
1968                 req = container_of(async_req, struct ablkcipher_request, base);
1969                 spin_unlock_irqrestore(&dev->lock, flags);
1970
1971                 hifn_process_ready(req, -ENODEV);
1972
1973                 spin_lock_irqsave(&dev->lock, flags);
1974         }
1975         spin_unlock_irqrestore(&dev->lock, flags);
1976 }
1977
1978 static int hifn_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
1979                 unsigned int len)
1980 {
1981         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
1982         struct hifn_context *ctx = crypto_tfm_ctx(tfm);
1983         struct hifn_device *dev = ctx->dev;
1984
1985         if (len > HIFN_MAX_CRYPT_KEY_LENGTH) {
1986                 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1987                 return -1;
1988         }
1989
1990         if (len == HIFN_DES_KEY_LENGTH) {
1991                 u32 tmp[DES_EXPKEY_WORDS];
1992                 int ret = des_ekey(tmp, key);
1993
1994                 if (unlikely(ret == 0) && (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
1995                         tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
1996                         return -EINVAL;
1997                 }
1998         }
1999
2000         dev->flags &= ~HIFN_FLAG_OLD_KEY;
2001
2002         memcpy(ctx->key, key, len);
2003         ctx->keysize = len;
2004
2005         return 0;
2006 }
2007
2008 static int hifn_handle_req(struct ablkcipher_request *req)
2009 {
2010         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2011         struct hifn_device *dev = ctx->dev;
2012         int err = -EAGAIN;
2013
2014         if (dev->started + DIV_ROUND_UP(req->nbytes, PAGE_SIZE) <= HIFN_QUEUE_LENGTH)
2015                 err = hifn_setup_session(req);
2016
2017         if (err == -EAGAIN) {
2018                 unsigned long flags;
2019
2020                 spin_lock_irqsave(&dev->lock, flags);
2021                 err = ablkcipher_enqueue_request(&dev->queue, req);
2022                 spin_unlock_irqrestore(&dev->lock, flags);
2023         }
2024
2025         return err;
2026 }
2027
2028 static int hifn_setup_crypto_req(struct ablkcipher_request *req, u8 op,
2029                 u8 type, u8 mode)
2030 {
2031         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2032         struct hifn_request_context *rctx = ablkcipher_request_ctx(req);
2033         unsigned ivsize;
2034
2035         ivsize = crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req));
2036
2037         if (req->info && mode != ACRYPTO_MODE_ECB) {
2038                 if (type == ACRYPTO_TYPE_AES_128)
2039                         ivsize = HIFN_AES_IV_LENGTH;
2040                 else if (type == ACRYPTO_TYPE_DES)
2041                         ivsize = HIFN_DES_KEY_LENGTH;
2042                 else if (type == ACRYPTO_TYPE_3DES)
2043                         ivsize = HIFN_3DES_KEY_LENGTH;
2044         }
2045
2046         if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) {
2047                 if (ctx->keysize == 24)
2048                         type = ACRYPTO_TYPE_AES_192;
2049                 else if (ctx->keysize == 32)
2050                         type = ACRYPTO_TYPE_AES_256;
2051         }
2052
2053         rctx->op = op;
2054         rctx->mode = mode;
2055         rctx->type = type;
2056         rctx->iv = req->info;
2057         rctx->ivsize = ivsize;
2058
2059         /*
2060          * HEAVY TODO: needs to kick Herbert XU to write documentation.
2061          * HEAVY TODO: needs to kick Herbert XU to write documentation.
2062          * HEAVY TODO: needs to kick Herbert XU to write documentation.
2063          */
2064
2065         return hifn_handle_req(req);
2066 }
2067
2068 static int hifn_process_queue(struct hifn_device *dev)
2069 {
2070         struct crypto_async_request *async_req, *backlog;
2071         struct ablkcipher_request *req;
2072         unsigned long flags;
2073         int err = 0;
2074
2075         while (dev->started < HIFN_QUEUE_LENGTH) {
2076                 spin_lock_irqsave(&dev->lock, flags);
2077                 backlog = crypto_get_backlog(&dev->queue);
2078                 async_req = crypto_dequeue_request(&dev->queue);
2079                 spin_unlock_irqrestore(&dev->lock, flags);
2080
2081                 if (!async_req)
2082                         break;
2083
2084                 if (backlog)
2085                         backlog->complete(backlog, -EINPROGRESS);
2086
2087                 req = container_of(async_req, struct ablkcipher_request, base);
2088
2089                 err = hifn_handle_req(req);
2090                 if (err)
2091                         break;
2092         }
2093
2094         return err;
2095 }
2096
2097 static int hifn_setup_crypto(struct ablkcipher_request *req, u8 op,
2098                 u8 type, u8 mode)
2099 {
2100         int err;
2101         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2102         struct hifn_device *dev = ctx->dev;
2103
2104         err = hifn_setup_crypto_req(req, op, type, mode);
2105         if (err)
2106                 return err;
2107
2108         if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
2109                 hifn_process_queue(dev);
2110
2111         return -EINPROGRESS;
2112 }
2113
2114 /*
2115  * AES ecryption functions.
2116  */
2117 static inline int hifn_encrypt_aes_ecb(struct ablkcipher_request *req)
2118 {
2119         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2120                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2121 }
2122 static inline int hifn_encrypt_aes_cbc(struct ablkcipher_request *req)
2123 {
2124         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2125                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2126 }
2127 static inline int hifn_encrypt_aes_cfb(struct ablkcipher_request *req)
2128 {
2129         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2130                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2131 }
2132 static inline int hifn_encrypt_aes_ofb(struct ablkcipher_request *req)
2133 {
2134         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2135                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2136 }
2137
2138 /*
2139  * AES decryption functions.
2140  */
2141 static inline int hifn_decrypt_aes_ecb(struct ablkcipher_request *req)
2142 {
2143         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2144                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2145 }
2146 static inline int hifn_decrypt_aes_cbc(struct ablkcipher_request *req)
2147 {
2148         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2149                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2150 }
2151 static inline int hifn_decrypt_aes_cfb(struct ablkcipher_request *req)
2152 {
2153         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2154                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2155 }
2156 static inline int hifn_decrypt_aes_ofb(struct ablkcipher_request *req)
2157 {
2158         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2159                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2160 }
2161
2162 /*
2163  * DES ecryption functions.
2164  */
2165 static inline int hifn_encrypt_des_ecb(struct ablkcipher_request *req)
2166 {
2167         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2168                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2169 }
2170 static inline int hifn_encrypt_des_cbc(struct ablkcipher_request *req)
2171 {
2172         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2173                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2174 }
2175 static inline int hifn_encrypt_des_cfb(struct ablkcipher_request *req)
2176 {
2177         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2178                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2179 }
2180 static inline int hifn_encrypt_des_ofb(struct ablkcipher_request *req)
2181 {
2182         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2183                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2184 }
2185
2186 /*
2187  * DES decryption functions.
2188  */
2189 static inline int hifn_decrypt_des_ecb(struct ablkcipher_request *req)
2190 {
2191         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2192                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2193 }
2194 static inline int hifn_decrypt_des_cbc(struct ablkcipher_request *req)
2195 {
2196         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2197                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2198 }
2199 static inline int hifn_decrypt_des_cfb(struct ablkcipher_request *req)
2200 {
2201         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2202                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2203 }
2204 static inline int hifn_decrypt_des_ofb(struct ablkcipher_request *req)
2205 {
2206         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2207                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2208 }
2209
2210 /*
2211  * 3DES ecryption functions.
2212  */
2213 static inline int hifn_encrypt_3des_ecb(struct ablkcipher_request *req)
2214 {
2215         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2216                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2217 }
2218 static inline int hifn_encrypt_3des_cbc(struct ablkcipher_request *req)
2219 {
2220         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2221                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2222 }
2223 static inline int hifn_encrypt_3des_cfb(struct ablkcipher_request *req)
2224 {
2225         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2226                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2227 }
2228 static inline int hifn_encrypt_3des_ofb(struct ablkcipher_request *req)
2229 {
2230         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2231                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2232 }
2233
2234 /*
2235  * 3DES decryption functions.
2236  */
2237 static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request *req)
2238 {
2239         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2240                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2241 }
2242 static inline int hifn_decrypt_3des_cbc(struct ablkcipher_request *req)
2243 {
2244         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2245                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2246 }
2247 static inline int hifn_decrypt_3des_cfb(struct ablkcipher_request *req)
2248 {
2249         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2250                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2251 }
2252 static inline int hifn_decrypt_3des_ofb(struct ablkcipher_request *req)
2253 {
2254         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2255                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2256 }
2257
2258 struct hifn_alg_template
2259 {
2260         char name[CRYPTO_MAX_ALG_NAME];
2261         char drv_name[CRYPTO_MAX_ALG_NAME];
2262         unsigned int bsize;
2263         struct ablkcipher_alg ablkcipher;
2264 };
2265
2266 static struct hifn_alg_template hifn_alg_templates[] = {
2267         /*
2268          * 3DES ECB, CBC, CFB and OFB modes.
2269          */
2270         {
2271                 .name = "cfb(des3_ede)", .drv_name = "cfb-3des", .bsize = 8,
2272                 .ablkcipher = {
2273                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2274                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2275                         .setkey         =       hifn_setkey,
2276                         .encrypt        =       hifn_encrypt_3des_cfb,
2277                         .decrypt        =       hifn_decrypt_3des_cfb,
2278                 },
2279         },
2280         {
2281                 .name = "ofb(des3_ede)", .drv_name = "ofb-3des", .bsize = 8,
2282                 .ablkcipher = {
2283                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2284                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2285                         .setkey         =       hifn_setkey,
2286                         .encrypt        =       hifn_encrypt_3des_ofb,
2287                         .decrypt        =       hifn_decrypt_3des_ofb,
2288                 },
2289         },
2290         {
2291                 .name = "cbc(des3_ede)", .drv_name = "cbc-3des", .bsize = 8,
2292                 .ablkcipher = {
2293                         .ivsize         =       HIFN_IV_LENGTH,
2294                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2295                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2296                         .setkey         =       hifn_setkey,
2297                         .encrypt        =       hifn_encrypt_3des_cbc,
2298                         .decrypt        =       hifn_decrypt_3des_cbc,
2299                 },
2300         },
2301         {
2302                 .name = "ecb(des3_ede)", .drv_name = "ecb-3des", .bsize = 8,
2303                 .ablkcipher = {
2304                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2305                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2306                         .setkey         =       hifn_setkey,
2307                         .encrypt        =       hifn_encrypt_3des_ecb,
2308                         .decrypt        =       hifn_decrypt_3des_ecb,
2309                 },
2310         },
2311
2312         /*
2313          * DES ECB, CBC, CFB and OFB modes.
2314          */
2315         {
2316                 .name = "cfb(des)", .drv_name = "cfb-des", .bsize = 8,
2317                 .ablkcipher = {
2318                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2319                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2320                         .setkey         =       hifn_setkey,
2321                         .encrypt        =       hifn_encrypt_des_cfb,
2322                         .decrypt        =       hifn_decrypt_des_cfb,
2323                 },
2324         },
2325         {
2326                 .name = "ofb(des)", .drv_name = "ofb-des", .bsize = 8,
2327                 .ablkcipher = {
2328                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2329                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2330                         .setkey         =       hifn_setkey,
2331                         .encrypt        =       hifn_encrypt_des_ofb,
2332                         .decrypt        =       hifn_decrypt_des_ofb,
2333                 },
2334         },
2335         {
2336                 .name = "cbc(des)", .drv_name = "cbc-des", .bsize = 8,
2337                 .ablkcipher = {
2338                         .ivsize         =       HIFN_IV_LENGTH,
2339                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2340                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2341                         .setkey         =       hifn_setkey,
2342                         .encrypt        =       hifn_encrypt_des_cbc,
2343                         .decrypt        =       hifn_decrypt_des_cbc,
2344                 },
2345         },
2346         {
2347                 .name = "ecb(des)", .drv_name = "ecb-des", .bsize = 8,
2348                 .ablkcipher = {
2349                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2350                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2351                         .setkey         =       hifn_setkey,
2352                         .encrypt        =       hifn_encrypt_des_ecb,
2353                         .decrypt        =       hifn_decrypt_des_ecb,
2354                 },
2355         },
2356
2357         /*
2358          * AES ECB, CBC, CFB and OFB modes.
2359          */
2360         {
2361                 .name = "ecb(aes)", .drv_name = "ecb-aes", .bsize = 16,
2362                 .ablkcipher = {
2363                         .min_keysize    =       AES_MIN_KEY_SIZE,
2364                         .max_keysize    =       AES_MAX_KEY_SIZE,
2365                         .setkey         =       hifn_setkey,
2366                         .encrypt        =       hifn_encrypt_aes_ecb,
2367                         .decrypt        =       hifn_decrypt_aes_ecb,
2368                 },
2369         },
2370         {
2371                 .name = "cbc(aes)", .drv_name = "cbc-aes", .bsize = 16,
2372                 .ablkcipher = {
2373                         .ivsize         =       HIFN_AES_IV_LENGTH,
2374                         .min_keysize    =       AES_MIN_KEY_SIZE,
2375                         .max_keysize    =       AES_MAX_KEY_SIZE,
2376                         .setkey         =       hifn_setkey,
2377                         .encrypt        =       hifn_encrypt_aes_cbc,
2378                         .decrypt        =       hifn_decrypt_aes_cbc,
2379                 },
2380         },
2381         {
2382                 .name = "cfb(aes)", .drv_name = "cfb-aes", .bsize = 16,
2383                 .ablkcipher = {
2384                         .min_keysize    =       AES_MIN_KEY_SIZE,
2385                         .max_keysize    =       AES_MAX_KEY_SIZE,
2386                         .setkey         =       hifn_setkey,
2387                         .encrypt        =       hifn_encrypt_aes_cfb,
2388                         .decrypt        =       hifn_decrypt_aes_cfb,
2389                 },
2390         },
2391         {
2392                 .name = "ofb(aes)", .drv_name = "ofb-aes", .bsize = 16,
2393                 .ablkcipher = {
2394                         .min_keysize    =       AES_MIN_KEY_SIZE,
2395                         .max_keysize    =       AES_MAX_KEY_SIZE,
2396                         .setkey         =       hifn_setkey,
2397                         .encrypt        =       hifn_encrypt_aes_ofb,
2398                         .decrypt        =       hifn_decrypt_aes_ofb,
2399                 },
2400         },
2401 };
2402
2403 static int hifn_cra_init(struct crypto_tfm *tfm)
2404 {
2405         struct crypto_alg *alg = tfm->__crt_alg;
2406         struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg);
2407         struct hifn_context *ctx = crypto_tfm_ctx(tfm);
2408
2409         ctx->dev = ha->dev;
2410         tfm->crt_ablkcipher.reqsize = sizeof(struct hifn_request_context);
2411         return 0;
2412 }
2413
2414 static int hifn_alg_alloc(struct hifn_device *dev, struct hifn_alg_template *t)
2415 {
2416         struct hifn_crypto_alg *alg;
2417         int err;
2418
2419         alg = kzalloc(sizeof(struct hifn_crypto_alg), GFP_KERNEL);
2420         if (!alg)
2421                 return -ENOMEM;
2422
2423         snprintf(alg->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name);
2424         snprintf(alg->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-%s",
2425                  t->drv_name, dev->name);
2426
2427         alg->alg.cra_priority = 300;
2428         alg->alg.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2429                                 CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC;
2430         alg->alg.cra_blocksize = t->bsize;
2431         alg->alg.cra_ctxsize = sizeof(struct hifn_context);
2432         alg->alg.cra_alignmask = 0;
2433         alg->alg.cra_type = &crypto_ablkcipher_type;
2434         alg->alg.cra_module = THIS_MODULE;
2435         alg->alg.cra_u.ablkcipher = t->ablkcipher;
2436         alg->alg.cra_init = hifn_cra_init;
2437
2438         alg->dev = dev;
2439
2440         list_add_tail(&alg->entry, &dev->alg_list);
2441
2442         err = crypto_register_alg(&alg->alg);
2443         if (err) {
2444                 list_del(&alg->entry);
2445                 kfree(alg);
2446         }
2447
2448         return err;
2449 }
2450
2451 static void hifn_unregister_alg(struct hifn_device *dev)
2452 {
2453         struct hifn_crypto_alg *a, *n;
2454
2455         list_for_each_entry_safe(a, n, &dev->alg_list, entry) {
2456                 list_del(&a->entry);
2457                 crypto_unregister_alg(&a->alg);
2458                 kfree(a);
2459         }
2460 }
2461
2462 static int hifn_register_alg(struct hifn_device *dev)
2463 {
2464         int i, err;
2465
2466         for (i=0; i<ARRAY_SIZE(hifn_alg_templates); ++i) {
2467                 err = hifn_alg_alloc(dev, &hifn_alg_templates[i]);
2468                 if (err)
2469                         goto err_out_exit;
2470         }
2471
2472         return 0;
2473
2474 err_out_exit:
2475         hifn_unregister_alg(dev);
2476         return err;
2477 }
2478
2479 static void hifn_tasklet_callback(unsigned long data)
2480 {
2481         struct hifn_device *dev = (struct hifn_device *)data;
2482
2483         /*
2484          * This is ok to call this without lock being held,
2485          * althogh it modifies some parameters used in parallel,
2486          * (like dev->success), but they are used in process
2487          * context or update is atomic (like setting dev->sa[i] to NULL).
2488          */
2489         hifn_clear_rings(dev, 0);
2490
2491         if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
2492                 hifn_process_queue(dev);
2493 }
2494
2495 static int hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2496 {
2497         int err, i;
2498         struct hifn_device *dev;
2499         char name[8];
2500
2501         err = pci_enable_device(pdev);
2502         if (err)
2503                 return err;
2504         pci_set_master(pdev);
2505
2506         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2507         if (err)
2508                 goto err_out_disable_pci_device;
2509
2510         snprintf(name, sizeof(name), "hifn%d",
2511                         atomic_inc_return(&hifn_dev_number)-1);
2512
2513         err = pci_request_regions(pdev, name);
2514         if (err)
2515                 goto err_out_disable_pci_device;
2516
2517         if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE ||
2518             pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE ||
2519             pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) {
2520                 dev_err(&pdev->dev, "Broken hardware - I/O regions are too small.\n");
2521                 err = -ENODEV;
2522                 goto err_out_free_regions;
2523         }
2524
2525         dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg),
2526                         GFP_KERNEL);
2527         if (!dev) {
2528                 err = -ENOMEM;
2529                 goto err_out_free_regions;
2530         }
2531
2532         INIT_LIST_HEAD(&dev->alg_list);
2533
2534         snprintf(dev->name, sizeof(dev->name), "%s", name);
2535         spin_lock_init(&dev->lock);
2536
2537         for (i=0; i<3; ++i) {
2538                 unsigned long addr, size;
2539
2540                 addr = pci_resource_start(pdev, i);
2541                 size = pci_resource_len(pdev, i);
2542
2543                 dev->bar[i] = ioremap_nocache(addr, size);
2544                 if (!dev->bar[i]) {
2545                         err = -ENOMEM;
2546                         goto err_out_unmap_bars;
2547                 }
2548         }
2549
2550         dev->desc_virt = pci_zalloc_consistent(pdev, sizeof(struct hifn_dma),
2551                                                &dev->desc_dma);
2552         if (!dev->desc_virt) {
2553                 dev_err(&pdev->dev, "Failed to allocate descriptor rings.\n");
2554                 err = -ENOMEM;
2555                 goto err_out_unmap_bars;
2556         }
2557
2558         dev->pdev = pdev;
2559         dev->irq = pdev->irq;
2560
2561         for (i=0; i<HIFN_D_RES_RSIZE; ++i)
2562                 dev->sa[i] = NULL;
2563
2564         pci_set_drvdata(pdev, dev);
2565
2566         tasklet_init(&dev->tasklet, hifn_tasklet_callback, (unsigned long)dev);
2567
2568         crypto_init_queue(&dev->queue, 1);
2569
2570         err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev);
2571         if (err) {
2572                 dev_err(&pdev->dev, "Failed to request IRQ%d: err: %d.\n",
2573                         dev->irq, err);
2574                 dev->irq = 0;
2575                 goto err_out_free_desc;
2576         }
2577
2578         err = hifn_start_device(dev);
2579         if (err)
2580                 goto err_out_free_irq;
2581
2582         err = hifn_register_rng(dev);
2583         if (err)
2584                 goto err_out_stop_device;
2585
2586         err = hifn_register_alg(dev);
2587         if (err)
2588                 goto err_out_unregister_rng;
2589
2590         INIT_DELAYED_WORK(&dev->work, hifn_work);
2591         schedule_delayed_work(&dev->work, HZ);
2592
2593         dev_dbg(&pdev->dev, "HIFN crypto accelerator card at %s has been "
2594                 "successfully registered as %s.\n",
2595                 pci_name(pdev), dev->name);
2596
2597         return 0;
2598
2599 err_out_unregister_rng:
2600         hifn_unregister_rng(dev);
2601 err_out_stop_device:
2602         hifn_reset_dma(dev, 1);
2603         hifn_stop_device(dev);
2604 err_out_free_irq:
2605         free_irq(dev->irq, dev);
2606         tasklet_kill(&dev->tasklet);
2607 err_out_free_desc:
2608         pci_free_consistent(pdev, sizeof(struct hifn_dma),
2609                         dev->desc_virt, dev->desc_dma);
2610
2611 err_out_unmap_bars:
2612         for (i=0; i<3; ++i)
2613                 if (dev->bar[i])
2614                         iounmap(dev->bar[i]);
2615
2616 err_out_free_regions:
2617         pci_release_regions(pdev);
2618
2619 err_out_disable_pci_device:
2620         pci_disable_device(pdev);
2621
2622         return err;
2623 }
2624
2625 static void hifn_remove(struct pci_dev *pdev)
2626 {
2627         int i;
2628         struct hifn_device *dev;
2629
2630         dev = pci_get_drvdata(pdev);
2631
2632         if (dev) {
2633                 cancel_delayed_work_sync(&dev->work);
2634
2635                 hifn_unregister_rng(dev);
2636                 hifn_unregister_alg(dev);
2637                 hifn_reset_dma(dev, 1);
2638                 hifn_stop_device(dev);
2639
2640                 free_irq(dev->irq, dev);
2641                 tasklet_kill(&dev->tasklet);
2642
2643                 hifn_flush(dev);
2644
2645                 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2646                                 dev->desc_virt, dev->desc_dma);
2647                 for (i=0; i<3; ++i)
2648                         if (dev->bar[i])
2649                                 iounmap(dev->bar[i]);
2650
2651                 kfree(dev);
2652         }
2653
2654         pci_release_regions(pdev);
2655         pci_disable_device(pdev);
2656 }
2657
2658 static struct pci_device_id hifn_pci_tbl[] = {
2659         { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) },
2660         { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) },
2661         { 0 }
2662 };
2663 MODULE_DEVICE_TABLE(pci, hifn_pci_tbl);
2664
2665 static struct pci_driver hifn_pci_driver = {
2666         .name     = "hifn795x",
2667         .id_table = hifn_pci_tbl,
2668         .probe    = hifn_probe,
2669         .remove   = hifn_remove,
2670 };
2671
2672 static int __init hifn_init(void)
2673 {
2674         unsigned int freq;
2675         int err;
2676
2677         /* HIFN supports only 32-bit addresses */
2678         BUILD_BUG_ON(sizeof(dma_addr_t) != 4);
2679
2680         if (strncmp(hifn_pll_ref, "ext", 3) &&
2681             strncmp(hifn_pll_ref, "pci", 3)) {
2682                 pr_err("hifn795x: invalid hifn_pll_ref clock, must be pci or ext");
2683                 return -EINVAL;
2684         }
2685
2686         /*
2687          * For the 7955/7956 the reference clock frequency must be in the
2688          * range of 20MHz-100MHz. For the 7954 the upper bound is 66.67MHz,
2689          * but this chip is currently not supported.
2690          */
2691         if (hifn_pll_ref[3] != '\0') {
2692                 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
2693                 if (freq < 20 || freq > 100) {
2694                         pr_err("hifn795x: invalid hifn_pll_ref frequency, must"
2695                                "be in the range of 20-100");
2696                         return -EINVAL;
2697                 }
2698         }
2699
2700         err = pci_register_driver(&hifn_pci_driver);
2701         if (err < 0) {
2702                 pr_err("Failed to register PCI driver for %s device.\n",
2703                        hifn_pci_driver.name);
2704                 return -ENODEV;
2705         }
2706
2707         pr_info("Driver for HIFN 795x crypto accelerator chip "
2708                 "has been successfully registered.\n");
2709
2710         return 0;
2711 }
2712
2713 static void __exit hifn_fini(void)
2714 {
2715         pci_unregister_driver(&hifn_pci_driver);
2716
2717         pr_info("Driver for HIFN 795x crypto accelerator chip "
2718                 "has been successfully unregistered.\n");
2719 }
2720
2721 module_init(hifn_init);
2722 module_exit(hifn_fini);
2723
2724 MODULE_LICENSE("GPL");
2725 MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
2726 MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip.");