2 * Hash algorithms supported by the CESA: MD5, SHA1 and SHA256.
4 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
5 * Author: Arnaud Ebalard <arno@natisbad.org>
7 * This work is based on an initial version written by
8 * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
15 #include <crypto/md5.h>
16 #include <crypto/sha.h>
20 struct mv_cesa_ahash_dma_iter {
21 struct mv_cesa_dma_iter base;
22 struct mv_cesa_sg_dma_iter src;
26 mv_cesa_ahash_req_iter_init(struct mv_cesa_ahash_dma_iter *iter,
27 struct ahash_request *req)
29 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
30 unsigned int len = req->nbytes + creq->cache_ptr;
33 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
35 mv_cesa_req_dma_iter_init(&iter->base, len);
36 mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE);
37 iter->src.op_offset = creq->cache_ptr;
41 mv_cesa_ahash_req_iter_next_op(struct mv_cesa_ahash_dma_iter *iter)
43 iter->src.op_offset = 0;
45 return mv_cesa_req_dma_iter_next_op(&iter->base);
49 mv_cesa_ahash_dma_alloc_cache(struct mv_cesa_ahash_dma_req *req, gfp_t flags)
51 req->cache = dma_pool_alloc(cesa_dev->dma->cache_pool, flags,
60 mv_cesa_ahash_dma_free_cache(struct mv_cesa_ahash_dma_req *req)
65 dma_pool_free(cesa_dev->dma->cache_pool, req->cache,
69 static int mv_cesa_ahash_dma_alloc_padding(struct mv_cesa_ahash_dma_req *req,
75 req->padding = dma_pool_alloc(cesa_dev->dma->padding_pool, flags,
83 static void mv_cesa_ahash_dma_free_padding(struct mv_cesa_ahash_dma_req *req)
88 dma_pool_free(cesa_dev->dma->padding_pool, req->padding,
93 static inline void mv_cesa_ahash_dma_last_cleanup(struct ahash_request *req)
95 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
97 mv_cesa_ahash_dma_free_padding(&creq->req.dma);
100 static inline void mv_cesa_ahash_dma_cleanup(struct ahash_request *req)
102 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
104 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
105 mv_cesa_ahash_dma_free_cache(&creq->req.dma);
106 mv_cesa_dma_cleanup(&creq->base);
109 static inline void mv_cesa_ahash_cleanup(struct ahash_request *req)
111 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
113 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
114 mv_cesa_ahash_dma_cleanup(req);
117 static void mv_cesa_ahash_last_cleanup(struct ahash_request *req)
119 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
121 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
122 mv_cesa_ahash_dma_last_cleanup(req);
125 static int mv_cesa_ahash_pad_len(struct mv_cesa_ahash_req *creq)
127 unsigned int index, padlen;
129 index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
130 padlen = (index < 56) ? (56 - index) : (64 + 56 - index);
135 static int mv_cesa_ahash_pad_req(struct mv_cesa_ahash_req *creq, u8 *buf)
137 unsigned int index, padlen;
140 /* Pad out to 56 mod 64 */
141 index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
142 padlen = mv_cesa_ahash_pad_len(creq);
143 memset(buf + 1, 0, padlen - 1);
146 __le64 bits = cpu_to_le64(creq->len << 3);
147 memcpy(buf + padlen, &bits, sizeof(bits));
149 __be64 bits = cpu_to_be64(creq->len << 3);
150 memcpy(buf + padlen, &bits, sizeof(bits));
156 static void mv_cesa_ahash_std_step(struct ahash_request *req)
158 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
159 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
160 struct mv_cesa_engine *engine = creq->base.engine;
161 struct mv_cesa_op_ctx *op;
162 unsigned int new_cache_ptr = 0;
165 unsigned int digsize;
168 mv_cesa_adjust_op(engine, &creq->op_tmpl);
169 memcpy_toio(engine->sram, &creq->op_tmpl, sizeof(creq->op_tmpl));
172 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
173 for (i = 0; i < digsize / 4; i++)
174 writel_relaxed(creq->state[i], engine->regs + CESA_IVDIG(i));
178 memcpy_toio(engine->sram + CESA_SA_DATA_SRAM_OFFSET,
179 creq->cache, creq->cache_ptr);
181 len = min_t(size_t, req->nbytes + creq->cache_ptr - sreq->offset,
182 CESA_SA_SRAM_PAYLOAD_SIZE);
184 if (!creq->last_req) {
185 new_cache_ptr = len & CESA_HASH_BLOCK_SIZE_MSK;
186 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
189 if (len - creq->cache_ptr)
190 sreq->offset += sg_pcopy_to_buffer(req->src, creq->src_nents,
192 CESA_SA_DATA_SRAM_OFFSET +
194 len - creq->cache_ptr,
199 frag_mode = mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK;
201 if (creq->last_req && sreq->offset == req->nbytes &&
202 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
203 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
204 frag_mode = CESA_SA_DESC_CFG_NOT_FRAG;
205 else if (frag_mode == CESA_SA_DESC_CFG_MID_FRAG)
206 frag_mode = CESA_SA_DESC_CFG_LAST_FRAG;
209 if (frag_mode == CESA_SA_DESC_CFG_NOT_FRAG ||
210 frag_mode == CESA_SA_DESC_CFG_LAST_FRAG) {
212 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
213 mv_cesa_set_mac_op_total_len(op, creq->len);
215 int trailerlen = mv_cesa_ahash_pad_len(creq) + 8;
217 if (len + trailerlen > CESA_SA_SRAM_PAYLOAD_SIZE) {
218 len &= CESA_HASH_BLOCK_SIZE_MSK;
219 new_cache_ptr = 64 - trailerlen;
220 memcpy_fromio(creq->cache,
222 CESA_SA_DATA_SRAM_OFFSET + len,
225 len += mv_cesa_ahash_pad_req(creq,
227 CESA_SA_DATA_SRAM_OFFSET);
230 if (frag_mode == CESA_SA_DESC_CFG_LAST_FRAG)
231 frag_mode = CESA_SA_DESC_CFG_MID_FRAG;
233 frag_mode = CESA_SA_DESC_CFG_FIRST_FRAG;
237 mv_cesa_set_mac_op_frag_len(op, len);
238 mv_cesa_update_op_cfg(op, frag_mode, CESA_SA_DESC_CFG_FRAG_MSK);
240 /* FIXME: only update enc_len field */
241 memcpy_toio(engine->sram, op, sizeof(*op));
243 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
244 mv_cesa_update_op_cfg(op, CESA_SA_DESC_CFG_MID_FRAG,
245 CESA_SA_DESC_CFG_FRAG_MSK);
247 creq->cache_ptr = new_cache_ptr;
249 mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE);
250 writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
251 BUG_ON(readl(engine->regs + CESA_SA_CMD) &
252 CESA_SA_CMD_EN_CESA_SA_ACCL0);
253 writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
256 static int mv_cesa_ahash_std_process(struct ahash_request *req, u32 status)
258 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
259 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
261 if (sreq->offset < (req->nbytes - creq->cache_ptr))
267 static inline void mv_cesa_ahash_dma_prepare(struct ahash_request *req)
269 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
270 struct mv_cesa_req *basereq = &creq->base;
272 mv_cesa_dma_prepare(basereq, basereq->engine);
275 static void mv_cesa_ahash_std_prepare(struct ahash_request *req)
277 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
278 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
283 static void mv_cesa_ahash_dma_step(struct ahash_request *req)
285 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
286 struct mv_cesa_req *base = &creq->base;
288 /* We must explicitly set the digest state. */
289 if (base->chain.first->flags & CESA_TDMA_SET_STATE) {
290 struct mv_cesa_engine *engine = base->engine;
293 /* Set the hash state in the IVDIG regs. */
294 for (i = 0; i < ARRAY_SIZE(creq->state); i++)
295 writel_relaxed(creq->state[i], engine->regs +
299 mv_cesa_dma_step(base);
302 static void mv_cesa_ahash_step(struct crypto_async_request *req)
304 struct ahash_request *ahashreq = ahash_request_cast(req);
305 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
307 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
308 mv_cesa_ahash_dma_step(ahashreq);
310 mv_cesa_ahash_std_step(ahashreq);
313 static int mv_cesa_ahash_process(struct crypto_async_request *req, u32 status)
315 struct ahash_request *ahashreq = ahash_request_cast(req);
316 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
318 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
319 return mv_cesa_dma_process(&creq->base, status);
321 return mv_cesa_ahash_std_process(ahashreq, status);
324 static void mv_cesa_ahash_complete(struct crypto_async_request *req)
326 struct ahash_request *ahashreq = ahash_request_cast(req);
327 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
328 struct mv_cesa_engine *engine = creq->base.engine;
329 unsigned int digsize;
332 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
334 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ &&
335 (creq->base.chain.last->flags & CESA_TDMA_TYPE_MSK) == CESA_TDMA_RESULT) {
339 * Result is already in the correct endianess when the SA is
342 data = creq->base.chain.last->op->ctx.hash.hash;
343 for (i = 0; i < digsize / 4; i++)
344 creq->state[i] = cpu_to_le32(data[i]);
346 memcpy(ahashreq->result, data, digsize);
348 for (i = 0; i < digsize / 4; i++)
349 creq->state[i] = readl_relaxed(engine->regs +
351 if (creq->last_req) {
353 * Hardware's MD5 digest is in little endian format, but
354 * SHA in big endian format
357 __le32 *result = (void *)ahashreq->result;
359 for (i = 0; i < digsize / 4; i++)
360 result[i] = cpu_to_le32(creq->state[i]);
362 __be32 *result = (void *)ahashreq->result;
364 for (i = 0; i < digsize / 4; i++)
365 result[i] = cpu_to_be32(creq->state[i]);
370 atomic_sub(ahashreq->nbytes, &engine->load);
373 static void mv_cesa_ahash_prepare(struct crypto_async_request *req,
374 struct mv_cesa_engine *engine)
376 struct ahash_request *ahashreq = ahash_request_cast(req);
377 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
379 creq->base.engine = engine;
381 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
382 mv_cesa_ahash_dma_prepare(ahashreq);
384 mv_cesa_ahash_std_prepare(ahashreq);
387 static void mv_cesa_ahash_req_cleanup(struct crypto_async_request *req)
389 struct ahash_request *ahashreq = ahash_request_cast(req);
390 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
393 mv_cesa_ahash_last_cleanup(ahashreq);
395 mv_cesa_ahash_cleanup(ahashreq);
398 sg_pcopy_to_buffer(ahashreq->src, creq->src_nents,
401 ahashreq->nbytes - creq->cache_ptr);
404 static const struct mv_cesa_req_ops mv_cesa_ahash_req_ops = {
405 .step = mv_cesa_ahash_step,
406 .process = mv_cesa_ahash_process,
407 .cleanup = mv_cesa_ahash_req_cleanup,
408 .complete = mv_cesa_ahash_complete,
411 static void mv_cesa_ahash_init(struct ahash_request *req,
412 struct mv_cesa_op_ctx *tmpl, bool algo_le)
414 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
416 memset(creq, 0, sizeof(*creq));
417 mv_cesa_update_op_cfg(tmpl,
418 CESA_SA_DESC_CFG_OP_MAC_ONLY |
419 CESA_SA_DESC_CFG_FIRST_FRAG,
420 CESA_SA_DESC_CFG_OP_MSK |
421 CESA_SA_DESC_CFG_FRAG_MSK);
422 mv_cesa_set_mac_op_total_len(tmpl, 0);
423 mv_cesa_set_mac_op_frag_len(tmpl, 0);
424 creq->op_tmpl = *tmpl;
426 creq->algo_le = algo_le;
429 static inline int mv_cesa_ahash_cra_init(struct crypto_tfm *tfm)
431 struct mv_cesa_hash_ctx *ctx = crypto_tfm_ctx(tfm);
433 ctx->base.ops = &mv_cesa_ahash_req_ops;
435 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
436 sizeof(struct mv_cesa_ahash_req));
440 static bool mv_cesa_ahash_cache_req(struct ahash_request *req)
442 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
445 if (creq->cache_ptr + req->nbytes < CESA_MAX_HASH_BLOCK_SIZE && !creq->last_req) {
451 sg_pcopy_to_buffer(req->src, creq->src_nents,
452 creq->cache + creq->cache_ptr,
455 creq->cache_ptr += req->nbytes;
461 static struct mv_cesa_op_ctx *
462 mv_cesa_dma_add_frag(struct mv_cesa_tdma_chain *chain,
463 struct mv_cesa_op_ctx *tmpl, unsigned int frag_len,
466 struct mv_cesa_op_ctx *op;
469 op = mv_cesa_dma_add_op(chain, tmpl, false, flags);
473 /* Set the operation block fragment length. */
474 mv_cesa_set_mac_op_frag_len(op, frag_len);
476 /* Append dummy desc to launch operation */
477 ret = mv_cesa_dma_add_dummy_launch(chain, flags);
481 if (mv_cesa_mac_op_is_first_frag(tmpl))
482 mv_cesa_update_op_cfg(tmpl,
483 CESA_SA_DESC_CFG_MID_FRAG,
484 CESA_SA_DESC_CFG_FRAG_MSK);
490 mv_cesa_ahash_dma_add_cache(struct mv_cesa_tdma_chain *chain,
491 struct mv_cesa_ahash_req *creq,
494 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
497 if (!creq->cache_ptr)
500 ret = mv_cesa_ahash_dma_alloc_cache(ahashdreq, flags);
504 memcpy(ahashdreq->cache, creq->cache, creq->cache_ptr);
506 return mv_cesa_dma_add_data_transfer(chain,
507 CESA_SA_DATA_SRAM_OFFSET,
508 ahashdreq->cache_dma,
510 CESA_TDMA_DST_IN_SRAM,
514 static struct mv_cesa_op_ctx *
515 mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain *chain,
516 struct mv_cesa_ahash_dma_iter *dma_iter,
517 struct mv_cesa_ahash_req *creq,
518 unsigned int frag_len, gfp_t flags)
520 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
521 unsigned int len, trailerlen, padoff = 0;
522 struct mv_cesa_op_ctx *op;
526 * If the transfer is smaller than our maximum length, and we have
527 * some data outstanding, we can ask the engine to finish the hash.
529 if (creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX && frag_len) {
530 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len,
535 mv_cesa_set_mac_op_total_len(op, creq->len);
536 mv_cesa_update_op_cfg(op, mv_cesa_mac_op_is_first_frag(op) ?
537 CESA_SA_DESC_CFG_NOT_FRAG :
538 CESA_SA_DESC_CFG_LAST_FRAG,
539 CESA_SA_DESC_CFG_FRAG_MSK);
541 ret = mv_cesa_dma_add_result_op(chain,
542 CESA_SA_CFG_SRAM_OFFSET,
543 CESA_SA_DATA_SRAM_OFFSET,
544 CESA_TDMA_SRC_IN_SRAM, flags);
546 return ERR_PTR(-ENOMEM);
551 * The request is longer than the engine can handle, or we have
552 * no data outstanding. Manually generate the padding, adding it
553 * as a "mid" fragment.
555 ret = mv_cesa_ahash_dma_alloc_padding(ahashdreq, flags);
559 trailerlen = mv_cesa_ahash_pad_req(creq, ahashdreq->padding);
561 len = min(CESA_SA_SRAM_PAYLOAD_SIZE - frag_len, trailerlen);
563 ret = mv_cesa_dma_add_data_transfer(chain,
564 CESA_SA_DATA_SRAM_OFFSET +
566 ahashdreq->padding_dma,
567 len, CESA_TDMA_DST_IN_SRAM,
572 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len + len,
577 if (len == trailerlen)
583 ret = mv_cesa_dma_add_data_transfer(chain,
584 CESA_SA_DATA_SRAM_OFFSET,
585 ahashdreq->padding_dma +
588 CESA_TDMA_DST_IN_SRAM,
593 return mv_cesa_dma_add_frag(chain, &creq->op_tmpl, trailerlen - padoff,
597 static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
599 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
600 gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
601 GFP_KERNEL : GFP_ATOMIC;
602 struct mv_cesa_req *basereq = &creq->base;
603 struct mv_cesa_ahash_dma_iter iter;
604 struct mv_cesa_op_ctx *op = NULL;
605 unsigned int frag_len;
606 bool set_state = false;
610 basereq->chain.first = NULL;
611 basereq->chain.last = NULL;
613 if (!mv_cesa_mac_op_is_first_frag(&creq->op_tmpl))
616 if (creq->src_nents) {
617 ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
625 mv_cesa_tdma_desc_iter_init(&basereq->chain);
626 mv_cesa_ahash_req_iter_init(&iter, req);
629 * Add the cache (left-over data from a previous block) first.
630 * This will never overflow the SRAM size.
632 ret = mv_cesa_ahash_dma_add_cache(&basereq->chain, creq, flags);
638 * Add all the new data, inserting an operation block and
639 * launch command between each full SRAM block-worth of
640 * data. We intentionally do not add the final op block.
643 ret = mv_cesa_dma_add_op_transfers(&basereq->chain,
649 frag_len = iter.base.op_len;
651 if (!mv_cesa_ahash_req_iter_next_op(&iter))
654 op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl,
662 /* Account for the data that was in the cache. */
663 frag_len = iter.base.op_len;
667 * At this point, frag_len indicates whether we have any data
668 * outstanding which needs an operation. Queue up the final
669 * operation, which depends whether this is the final request.
672 op = mv_cesa_ahash_dma_last_req(&basereq->chain, &iter, creq,
675 op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl,
684 * If results are copied via DMA, this means that this
685 * request can be directly processed by the engine,
686 * without partial updates. So we can chain it at the
687 * DMA level with other requests.
689 type = basereq->chain.last->flags & CESA_TDMA_TYPE_MSK;
691 if (op && type != CESA_TDMA_RESULT) {
692 /* Add dummy desc to wait for crypto operation end */
693 ret = mv_cesa_dma_add_dummy_end(&basereq->chain, flags);
699 creq->cache_ptr = req->nbytes + creq->cache_ptr -
704 basereq->chain.last->flags |= CESA_TDMA_END_OF_REQ;
706 if (type != CESA_TDMA_RESULT)
707 basereq->chain.last->flags |= CESA_TDMA_BREAK_CHAIN;
711 * Put the CESA_TDMA_SET_STATE flag on the first tdma desc to
712 * let the step logic know that the IVDIG registers should be
713 * explicitly set before launching a TDMA chain.
715 basereq->chain.first->flags |= CESA_TDMA_SET_STATE;
721 mv_cesa_dma_cleanup(basereq);
722 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
725 mv_cesa_ahash_last_cleanup(req);
730 static int mv_cesa_ahash_req_init(struct ahash_request *req, bool *cached)
732 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
734 creq->src_nents = sg_nents_for_len(req->src, req->nbytes);
735 if (creq->src_nents < 0) {
736 dev_err(cesa_dev->dev, "Invalid number of src SG");
737 return creq->src_nents;
740 *cached = mv_cesa_ahash_cache_req(req);
745 if (cesa_dev->caps->has_tdma)
746 return mv_cesa_ahash_dma_req_init(req);
751 static int mv_cesa_ahash_queue_req(struct ahash_request *req)
753 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
754 struct mv_cesa_engine *engine;
758 ret = mv_cesa_ahash_req_init(req, &cached);
765 engine = mv_cesa_select_engine(req->nbytes);
766 mv_cesa_ahash_prepare(&req->base, engine);
768 ret = mv_cesa_queue_req(&req->base, &creq->base);
770 if (mv_cesa_req_needs_cleanup(&req->base, ret))
771 mv_cesa_ahash_cleanup(req);
776 static int mv_cesa_ahash_update(struct ahash_request *req)
778 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
780 creq->len += req->nbytes;
782 return mv_cesa_ahash_queue_req(req);
785 static int mv_cesa_ahash_final(struct ahash_request *req)
787 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
788 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
790 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
791 creq->last_req = true;
794 return mv_cesa_ahash_queue_req(req);
797 static int mv_cesa_ahash_finup(struct ahash_request *req)
799 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
800 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
802 creq->len += req->nbytes;
803 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
804 creq->last_req = true;
806 return mv_cesa_ahash_queue_req(req);
809 static int mv_cesa_ahash_export(struct ahash_request *req, void *hash,
810 u64 *len, void *cache)
812 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
813 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
814 unsigned int digsize = crypto_ahash_digestsize(ahash);
815 unsigned int blocksize;
817 blocksize = crypto_ahash_blocksize(ahash);
820 memcpy(hash, creq->state, digsize);
821 memset(cache, 0, blocksize);
822 memcpy(cache, creq->cache, creq->cache_ptr);
827 static int mv_cesa_ahash_import(struct ahash_request *req, const void *hash,
828 u64 len, const void *cache)
830 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
831 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
832 unsigned int digsize = crypto_ahash_digestsize(ahash);
833 unsigned int blocksize;
834 unsigned int cache_ptr;
837 ret = crypto_ahash_init(req);
841 blocksize = crypto_ahash_blocksize(ahash);
842 if (len >= blocksize)
843 mv_cesa_update_op_cfg(&creq->op_tmpl,
844 CESA_SA_DESC_CFG_MID_FRAG,
845 CESA_SA_DESC_CFG_FRAG_MSK);
848 memcpy(creq->state, hash, digsize);
851 cache_ptr = do_div(len, blocksize);
855 memcpy(creq->cache, cache, cache_ptr);
856 creq->cache_ptr = cache_ptr;
861 static int mv_cesa_md5_init(struct ahash_request *req)
863 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
864 struct mv_cesa_op_ctx tmpl = { };
866 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_MD5);
868 mv_cesa_ahash_init(req, &tmpl, true);
870 creq->state[0] = MD5_H0;
871 creq->state[1] = MD5_H1;
872 creq->state[2] = MD5_H2;
873 creq->state[3] = MD5_H3;
878 static int mv_cesa_md5_export(struct ahash_request *req, void *out)
880 struct md5_state *out_state = out;
882 return mv_cesa_ahash_export(req, out_state->hash,
883 &out_state->byte_count, out_state->block);
886 static int mv_cesa_md5_import(struct ahash_request *req, const void *in)
888 const struct md5_state *in_state = in;
890 return mv_cesa_ahash_import(req, in_state->hash, in_state->byte_count,
894 static int mv_cesa_md5_digest(struct ahash_request *req)
898 ret = mv_cesa_md5_init(req);
902 return mv_cesa_ahash_finup(req);
905 struct ahash_alg mv_md5_alg = {
906 .init = mv_cesa_md5_init,
907 .update = mv_cesa_ahash_update,
908 .final = mv_cesa_ahash_final,
909 .finup = mv_cesa_ahash_finup,
910 .digest = mv_cesa_md5_digest,
911 .export = mv_cesa_md5_export,
912 .import = mv_cesa_md5_import,
914 .digestsize = MD5_DIGEST_SIZE,
915 .statesize = sizeof(struct md5_state),
918 .cra_driver_name = "mv-md5",
920 .cra_flags = CRYPTO_ALG_ASYNC |
921 CRYPTO_ALG_KERN_DRIVER_ONLY,
922 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
923 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
924 .cra_init = mv_cesa_ahash_cra_init,
925 .cra_module = THIS_MODULE,
930 static int mv_cesa_sha1_init(struct ahash_request *req)
932 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
933 struct mv_cesa_op_ctx tmpl = { };
935 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA1);
937 mv_cesa_ahash_init(req, &tmpl, false);
939 creq->state[0] = SHA1_H0;
940 creq->state[1] = SHA1_H1;
941 creq->state[2] = SHA1_H2;
942 creq->state[3] = SHA1_H3;
943 creq->state[4] = SHA1_H4;
948 static int mv_cesa_sha1_export(struct ahash_request *req, void *out)
950 struct sha1_state *out_state = out;
952 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
956 static int mv_cesa_sha1_import(struct ahash_request *req, const void *in)
958 const struct sha1_state *in_state = in;
960 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
964 static int mv_cesa_sha1_digest(struct ahash_request *req)
968 ret = mv_cesa_sha1_init(req);
972 return mv_cesa_ahash_finup(req);
975 struct ahash_alg mv_sha1_alg = {
976 .init = mv_cesa_sha1_init,
977 .update = mv_cesa_ahash_update,
978 .final = mv_cesa_ahash_final,
979 .finup = mv_cesa_ahash_finup,
980 .digest = mv_cesa_sha1_digest,
981 .export = mv_cesa_sha1_export,
982 .import = mv_cesa_sha1_import,
984 .digestsize = SHA1_DIGEST_SIZE,
985 .statesize = sizeof(struct sha1_state),
988 .cra_driver_name = "mv-sha1",
990 .cra_flags = CRYPTO_ALG_ASYNC |
991 CRYPTO_ALG_KERN_DRIVER_ONLY,
992 .cra_blocksize = SHA1_BLOCK_SIZE,
993 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
994 .cra_init = mv_cesa_ahash_cra_init,
995 .cra_module = THIS_MODULE,
1000 static int mv_cesa_sha256_init(struct ahash_request *req)
1002 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
1003 struct mv_cesa_op_ctx tmpl = { };
1005 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA256);
1007 mv_cesa_ahash_init(req, &tmpl, false);
1009 creq->state[0] = SHA256_H0;
1010 creq->state[1] = SHA256_H1;
1011 creq->state[2] = SHA256_H2;
1012 creq->state[3] = SHA256_H3;
1013 creq->state[4] = SHA256_H4;
1014 creq->state[5] = SHA256_H5;
1015 creq->state[6] = SHA256_H6;
1016 creq->state[7] = SHA256_H7;
1021 static int mv_cesa_sha256_digest(struct ahash_request *req)
1025 ret = mv_cesa_sha256_init(req);
1029 return mv_cesa_ahash_finup(req);
1032 static int mv_cesa_sha256_export(struct ahash_request *req, void *out)
1034 struct sha256_state *out_state = out;
1036 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
1040 static int mv_cesa_sha256_import(struct ahash_request *req, const void *in)
1042 const struct sha256_state *in_state = in;
1044 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
1048 struct ahash_alg mv_sha256_alg = {
1049 .init = mv_cesa_sha256_init,
1050 .update = mv_cesa_ahash_update,
1051 .final = mv_cesa_ahash_final,
1052 .finup = mv_cesa_ahash_finup,
1053 .digest = mv_cesa_sha256_digest,
1054 .export = mv_cesa_sha256_export,
1055 .import = mv_cesa_sha256_import,
1057 .digestsize = SHA256_DIGEST_SIZE,
1058 .statesize = sizeof(struct sha256_state),
1060 .cra_name = "sha256",
1061 .cra_driver_name = "mv-sha256",
1062 .cra_priority = 300,
1063 .cra_flags = CRYPTO_ALG_ASYNC |
1064 CRYPTO_ALG_KERN_DRIVER_ONLY,
1065 .cra_blocksize = SHA256_BLOCK_SIZE,
1066 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
1067 .cra_init = mv_cesa_ahash_cra_init,
1068 .cra_module = THIS_MODULE,
1073 struct mv_cesa_ahash_result {
1074 struct completion completion;
1078 static void mv_cesa_hmac_ahash_complete(struct crypto_async_request *req,
1081 struct mv_cesa_ahash_result *result = req->data;
1083 if (error == -EINPROGRESS)
1086 result->error = error;
1087 complete(&result->completion);
1090 static int mv_cesa_ahmac_iv_state_init(struct ahash_request *req, u8 *pad,
1091 void *state, unsigned int blocksize)
1093 struct mv_cesa_ahash_result result;
1094 struct scatterlist sg;
1097 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1098 mv_cesa_hmac_ahash_complete, &result);
1099 sg_init_one(&sg, pad, blocksize);
1100 ahash_request_set_crypt(req, &sg, pad, blocksize);
1101 init_completion(&result.completion);
1103 ret = crypto_ahash_init(req);
1107 ret = crypto_ahash_update(req);
1108 if (ret && ret != -EINPROGRESS)
1111 wait_for_completion_interruptible(&result.completion);
1113 return result.error;
1115 ret = crypto_ahash_export(req, state);
1122 static int mv_cesa_ahmac_pad_init(struct ahash_request *req,
1123 const u8 *key, unsigned int keylen,
1125 unsigned int blocksize)
1127 struct mv_cesa_ahash_result result;
1128 struct scatterlist sg;
1132 if (keylen <= blocksize) {
1133 memcpy(ipad, key, keylen);
1135 u8 *keydup = kmemdup(key, keylen, GFP_KERNEL);
1140 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1141 mv_cesa_hmac_ahash_complete,
1143 sg_init_one(&sg, keydup, keylen);
1144 ahash_request_set_crypt(req, &sg, ipad, keylen);
1145 init_completion(&result.completion);
1147 ret = crypto_ahash_digest(req);
1148 if (ret == -EINPROGRESS) {
1149 wait_for_completion_interruptible(&result.completion);
1153 /* Set the memory region to 0 to avoid any leak. */
1154 memset(keydup, 0, keylen);
1160 keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
1163 memset(ipad + keylen, 0, blocksize - keylen);
1164 memcpy(opad, ipad, blocksize);
1166 for (i = 0; i < blocksize; i++) {
1174 static int mv_cesa_ahmac_setkey(const char *hash_alg_name,
1175 const u8 *key, unsigned int keylen,
1176 void *istate, void *ostate)
1178 struct ahash_request *req;
1179 struct crypto_ahash *tfm;
1180 unsigned int blocksize;
1185 tfm = crypto_alloc_ahash(hash_alg_name, CRYPTO_ALG_TYPE_AHASH,
1186 CRYPTO_ALG_TYPE_AHASH_MASK);
1188 return PTR_ERR(tfm);
1190 req = ahash_request_alloc(tfm, GFP_KERNEL);
1196 crypto_ahash_clear_flags(tfm, ~0);
1198 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1200 ipad = kzalloc(2 * blocksize, GFP_KERNEL);
1206 opad = ipad + blocksize;
1208 ret = mv_cesa_ahmac_pad_init(req, key, keylen, ipad, opad, blocksize);
1212 ret = mv_cesa_ahmac_iv_state_init(req, ipad, istate, blocksize);
1216 ret = mv_cesa_ahmac_iv_state_init(req, opad, ostate, blocksize);
1221 ahash_request_free(req);
1223 crypto_free_ahash(tfm);
1228 static int mv_cesa_ahmac_cra_init(struct crypto_tfm *tfm)
1230 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(tfm);
1232 ctx->base.ops = &mv_cesa_ahash_req_ops;
1234 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1235 sizeof(struct mv_cesa_ahash_req));
1239 static int mv_cesa_ahmac_md5_init(struct ahash_request *req)
1241 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1242 struct mv_cesa_op_ctx tmpl = { };
1244 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_MD5);
1245 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1247 mv_cesa_ahash_init(req, &tmpl, true);
1252 static int mv_cesa_ahmac_md5_setkey(struct crypto_ahash *tfm, const u8 *key,
1253 unsigned int keylen)
1255 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1256 struct md5_state istate, ostate;
1259 ret = mv_cesa_ahmac_setkey("mv-md5", key, keylen, &istate, &ostate);
1263 for (i = 0; i < ARRAY_SIZE(istate.hash); i++)
1264 ctx->iv[i] = be32_to_cpu(istate.hash[i]);
1266 for (i = 0; i < ARRAY_SIZE(ostate.hash); i++)
1267 ctx->iv[i + 8] = be32_to_cpu(ostate.hash[i]);
1272 static int mv_cesa_ahmac_md5_digest(struct ahash_request *req)
1276 ret = mv_cesa_ahmac_md5_init(req);
1280 return mv_cesa_ahash_finup(req);
1283 struct ahash_alg mv_ahmac_md5_alg = {
1284 .init = mv_cesa_ahmac_md5_init,
1285 .update = mv_cesa_ahash_update,
1286 .final = mv_cesa_ahash_final,
1287 .finup = mv_cesa_ahash_finup,
1288 .digest = mv_cesa_ahmac_md5_digest,
1289 .setkey = mv_cesa_ahmac_md5_setkey,
1290 .export = mv_cesa_md5_export,
1291 .import = mv_cesa_md5_import,
1293 .digestsize = MD5_DIGEST_SIZE,
1294 .statesize = sizeof(struct md5_state),
1296 .cra_name = "hmac(md5)",
1297 .cra_driver_name = "mv-hmac-md5",
1298 .cra_priority = 300,
1299 .cra_flags = CRYPTO_ALG_ASYNC |
1300 CRYPTO_ALG_KERN_DRIVER_ONLY,
1301 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
1302 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1303 .cra_init = mv_cesa_ahmac_cra_init,
1304 .cra_module = THIS_MODULE,
1309 static int mv_cesa_ahmac_sha1_init(struct ahash_request *req)
1311 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1312 struct mv_cesa_op_ctx tmpl = { };
1314 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA1);
1315 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1317 mv_cesa_ahash_init(req, &tmpl, false);
1322 static int mv_cesa_ahmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key,
1323 unsigned int keylen)
1325 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1326 struct sha1_state istate, ostate;
1329 ret = mv_cesa_ahmac_setkey("mv-sha1", key, keylen, &istate, &ostate);
1333 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1334 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1336 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1337 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1342 static int mv_cesa_ahmac_sha1_digest(struct ahash_request *req)
1346 ret = mv_cesa_ahmac_sha1_init(req);
1350 return mv_cesa_ahash_finup(req);
1353 struct ahash_alg mv_ahmac_sha1_alg = {
1354 .init = mv_cesa_ahmac_sha1_init,
1355 .update = mv_cesa_ahash_update,
1356 .final = mv_cesa_ahash_final,
1357 .finup = mv_cesa_ahash_finup,
1358 .digest = mv_cesa_ahmac_sha1_digest,
1359 .setkey = mv_cesa_ahmac_sha1_setkey,
1360 .export = mv_cesa_sha1_export,
1361 .import = mv_cesa_sha1_import,
1363 .digestsize = SHA1_DIGEST_SIZE,
1364 .statesize = sizeof(struct sha1_state),
1366 .cra_name = "hmac(sha1)",
1367 .cra_driver_name = "mv-hmac-sha1",
1368 .cra_priority = 300,
1369 .cra_flags = CRYPTO_ALG_ASYNC |
1370 CRYPTO_ALG_KERN_DRIVER_ONLY,
1371 .cra_blocksize = SHA1_BLOCK_SIZE,
1372 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1373 .cra_init = mv_cesa_ahmac_cra_init,
1374 .cra_module = THIS_MODULE,
1379 static int mv_cesa_ahmac_sha256_setkey(struct crypto_ahash *tfm, const u8 *key,
1380 unsigned int keylen)
1382 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1383 struct sha256_state istate, ostate;
1386 ret = mv_cesa_ahmac_setkey("mv-sha256", key, keylen, &istate, &ostate);
1390 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1391 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1393 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1394 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1399 static int mv_cesa_ahmac_sha256_init(struct ahash_request *req)
1401 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1402 struct mv_cesa_op_ctx tmpl = { };
1404 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA256);
1405 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1407 mv_cesa_ahash_init(req, &tmpl, false);
1412 static int mv_cesa_ahmac_sha256_digest(struct ahash_request *req)
1416 ret = mv_cesa_ahmac_sha256_init(req);
1420 return mv_cesa_ahash_finup(req);
1423 struct ahash_alg mv_ahmac_sha256_alg = {
1424 .init = mv_cesa_ahmac_sha256_init,
1425 .update = mv_cesa_ahash_update,
1426 .final = mv_cesa_ahash_final,
1427 .finup = mv_cesa_ahash_finup,
1428 .digest = mv_cesa_ahmac_sha256_digest,
1429 .setkey = mv_cesa_ahmac_sha256_setkey,
1430 .export = mv_cesa_sha256_export,
1431 .import = mv_cesa_sha256_import,
1433 .digestsize = SHA256_DIGEST_SIZE,
1434 .statesize = sizeof(struct sha256_state),
1436 .cra_name = "hmac(sha256)",
1437 .cra_driver_name = "mv-hmac-sha256",
1438 .cra_priority = 300,
1439 .cra_flags = CRYPTO_ALG_ASYNC |
1440 CRYPTO_ALG_KERN_DRIVER_ONLY,
1441 .cra_blocksize = SHA256_BLOCK_SIZE,
1442 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1443 .cra_init = mv_cesa_ahmac_cra_init,
1444 .cra_module = THIS_MODULE,