2 * Support for Marvell's crypto engine which can be found on some Orion5X
5 * Author: Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
9 #include <crypto/aes.h>
10 #include <crypto/algapi.h>
11 #include <linux/crypto.h>
12 #include <linux/interrupt.h>
14 #include <linux/kthread.h>
15 #include <linux/platform_device.h>
16 #include <linux/scatterlist.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/clk.h>
20 #include <crypto/internal/hash.h>
21 #include <crypto/sha.h>
25 #define MV_CESA "MV-CESA:"
26 #define MAX_HW_HASH_SIZE 0xFFFF
30 * /---------------------------------------\
31 * | | request complete
33 * IDLE -> new request -> BUSY -> done -> DEQUEUE
35 * | | more scatter entries
45 * struct req_progress - used for every crypt request
46 * @src_sg_it: sg iterator for src
47 * @dst_sg_it: sg iterator for dst
48 * @sg_src_left: bytes left in src to process (scatter list)
49 * @src_start: offset to add to src start position (scatter list)
50 * @crypt_len: length of current hw crypt/hash process
51 * @hw_nbytes: total bytes to process in hw for this request
52 * @copy_back: whether to copy data back (crypt) or not (hash)
53 * @sg_dst_left: bytes left dst to process in this scatter list
54 * @dst_start: offset to add to dst start position (scatter list)
55 * @hw_processed_bytes: number of bytes processed by hw (request).
57 * sg helper are used to iterate over the scatterlist. Since the size of the
58 * SRAM may be less than the scatter size, this struct struct is used to keep
59 * track of progress within current scatterlist.
62 struct sg_mapping_iter src_sg_it;
63 struct sg_mapping_iter dst_sg_it;
64 void (*complete) (void);
65 void (*process) (int is_first);
76 int hw_processed_bytes;
84 struct task_struct *queue_th;
86 /* the lock protects queue and eng_st */
88 struct crypto_queue queue;
89 enum engine_status eng_st;
90 struct crypto_async_request *cur_req;
91 struct req_progress p;
98 static struct crypto_priv *cpg;
101 u8 aes_enc_key[AES_KEY_LEN];
104 u32 need_calc_aes_dkey;
122 struct mv_tfm_hash_ctx {
123 struct crypto_shash *fallback;
124 struct crypto_shash *base_hash;
125 u32 ivs[2 * SHA1_DIGEST_SIZE / 4];
130 struct mv_req_hash_ctx {
132 u32 state[SHA1_DIGEST_SIZE / 4];
133 u8 buffer[SHA1_BLOCK_SIZE];
134 int first_hash; /* marks that we don't have previous state */
135 int last_chunk; /* marks that this is the 'final' request */
136 int extra_bytes; /* unprocessed bytes in buffer */
141 static void compute_aes_dec_key(struct mv_ctx *ctx)
143 struct crypto_aes_ctx gen_aes_key;
146 if (!ctx->need_calc_aes_dkey)
149 crypto_aes_expand_key(&gen_aes_key, ctx->aes_enc_key, ctx->key_len);
151 key_pos = ctx->key_len + 24;
152 memcpy(ctx->aes_dec_key, &gen_aes_key.key_enc[key_pos], 4 * 4);
153 switch (ctx->key_len) {
154 case AES_KEYSIZE_256:
157 case AES_KEYSIZE_192:
159 memcpy(&ctx->aes_dec_key[4], &gen_aes_key.key_enc[key_pos],
163 ctx->need_calc_aes_dkey = 0;
166 static int mv_setkey_aes(struct crypto_ablkcipher *cipher, const u8 *key,
169 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
170 struct mv_ctx *ctx = crypto_tfm_ctx(tfm);
173 case AES_KEYSIZE_128:
174 case AES_KEYSIZE_192:
175 case AES_KEYSIZE_256:
178 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
182 ctx->need_calc_aes_dkey = 1;
184 memcpy(ctx->aes_enc_key, key, AES_KEY_LEN);
188 static void copy_src_to_buf(struct req_progress *p, char *dbuf, int len)
195 if (!p->sg_src_left) {
196 ret = sg_miter_next(&p->src_sg_it);
198 p->sg_src_left = p->src_sg_it.length;
202 sbuf = p->src_sg_it.addr + p->src_start;
204 copy_len = min(p->sg_src_left, len);
205 memcpy(dbuf, sbuf, copy_len);
207 p->src_start += copy_len;
208 p->sg_src_left -= copy_len;
215 static void setup_data_in(void)
217 struct req_progress *p = &cpg->p;
219 min(p->hw_nbytes - p->hw_processed_bytes, cpg->max_req_size);
220 copy_src_to_buf(p, cpg->sram + SRAM_DATA_IN_START + p->crypt_len,
221 data_in_sram - p->crypt_len);
222 p->crypt_len = data_in_sram;
225 static void mv_process_current_q(int first_block)
227 struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
228 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
229 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
230 struct sec_accel_config op;
232 switch (req_ctx->op) {
234 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_ECB;
238 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_CBC;
239 op.enc_iv = ENC_IV_POINT(SRAM_DATA_IV) |
240 ENC_IV_BUF_POINT(SRAM_DATA_IV_BUF);
242 memcpy(cpg->sram + SRAM_DATA_IV, req->info, 16);
245 if (req_ctx->decrypt) {
246 op.config |= CFG_DIR_DEC;
247 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_dec_key,
250 op.config |= CFG_DIR_ENC;
251 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_enc_key,
255 switch (ctx->key_len) {
256 case AES_KEYSIZE_128:
257 op.config |= CFG_AES_LEN_128;
259 case AES_KEYSIZE_192:
260 op.config |= CFG_AES_LEN_192;
262 case AES_KEYSIZE_256:
263 op.config |= CFG_AES_LEN_256;
266 op.enc_p = ENC_P_SRC(SRAM_DATA_IN_START) |
267 ENC_P_DST(SRAM_DATA_OUT_START);
268 op.enc_key_p = SRAM_DATA_KEY_P;
271 op.enc_len = cpg->p.crypt_len;
272 memcpy(cpg->sram + SRAM_CONFIG, &op,
273 sizeof(struct sec_accel_config));
276 writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
279 * XXX: add timer if the interrupt does not occur for some mystery
284 static void mv_crypto_algo_completion(void)
286 struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
287 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
289 sg_miter_stop(&cpg->p.src_sg_it);
290 sg_miter_stop(&cpg->p.dst_sg_it);
292 if (req_ctx->op != COP_AES_CBC)
295 memcpy(req->info, cpg->sram + SRAM_DATA_IV_BUF, 16);
298 static void mv_process_hash_current(int first_block)
300 struct ahash_request *req = ahash_request_cast(cpg->cur_req);
301 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
302 struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
303 struct req_progress *p = &cpg->p;
304 struct sec_accel_config op = { 0 };
307 switch (req_ctx->op) {
310 op.config = CFG_OP_MAC_ONLY | CFG_MACM_SHA1;
313 op.config = CFG_OP_MAC_ONLY | CFG_MACM_HMAC_SHA1;
314 memcpy(cpg->sram + SRAM_HMAC_IV_IN,
315 tfm_ctx->ivs, sizeof(tfm_ctx->ivs));
320 MAC_SRC_DATA_P(SRAM_DATA_IN_START) | MAC_SRC_TOTAL_LEN((u32)
327 MAC_DIGEST_P(SRAM_DIGEST_BUF) | MAC_FRAG_LEN(p->crypt_len);
329 MAC_INNER_IV_P(SRAM_HMAC_IV_IN) |
330 MAC_OUTER_IV_P(SRAM_HMAC_IV_OUT);
332 is_last = req_ctx->last_chunk
333 && (p->hw_processed_bytes + p->crypt_len >= p->hw_nbytes)
334 && (req_ctx->count <= MAX_HW_HASH_SIZE);
335 if (req_ctx->first_hash) {
337 op.config |= CFG_NOT_FRAG;
339 op.config |= CFG_FIRST_FRAG;
341 req_ctx->first_hash = 0;
344 op.config |= CFG_LAST_FRAG;
346 op.config |= CFG_MID_FRAG;
349 writel(req_ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A);
350 writel(req_ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B);
351 writel(req_ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C);
352 writel(req_ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D);
353 writel(req_ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E);
357 memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config));
360 writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
363 * XXX: add timer if the interrupt does not occur for some mystery
368 static inline int mv_hash_import_sha1_ctx(const struct mv_req_hash_ctx *ctx,
369 struct shash_desc *desc)
372 struct sha1_state shash_state;
374 shash_state.count = ctx->count + ctx->count_add;
375 for (i = 0; i < 5; i++)
376 shash_state.state[i] = ctx->state[i];
377 memcpy(shash_state.buffer, ctx->buffer, sizeof(shash_state.buffer));
378 return crypto_shash_import(desc, &shash_state);
381 static int mv_hash_final_fallback(struct ahash_request *req)
383 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
384 struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
386 struct shash_desc shash;
387 char ctx[crypto_shash_descsize(tfm_ctx->fallback)];
391 desc.shash.tfm = tfm_ctx->fallback;
392 desc.shash.flags = CRYPTO_TFM_REQ_MAY_SLEEP;
393 if (unlikely(req_ctx->first_hash)) {
394 crypto_shash_init(&desc.shash);
395 crypto_shash_update(&desc.shash, req_ctx->buffer,
396 req_ctx->extra_bytes);
398 /* only SHA1 for now....
400 rc = mv_hash_import_sha1_ctx(req_ctx, &desc.shash);
404 rc = crypto_shash_final(&desc.shash, req->result);
409 static void mv_hash_algo_completion(void)
411 struct ahash_request *req = ahash_request_cast(cpg->cur_req);
412 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
414 if (ctx->extra_bytes)
415 copy_src_to_buf(&cpg->p, ctx->buffer, ctx->extra_bytes);
416 sg_miter_stop(&cpg->p.src_sg_it);
418 if (likely(ctx->last_chunk)) {
419 if (likely(ctx->count <= MAX_HW_HASH_SIZE)) {
420 memcpy(req->result, cpg->sram + SRAM_DIGEST_BUF,
421 crypto_ahash_digestsize(crypto_ahash_reqtfm
424 mv_hash_final_fallback(req);
426 ctx->state[0] = readl(cpg->reg + DIGEST_INITIAL_VAL_A);
427 ctx->state[1] = readl(cpg->reg + DIGEST_INITIAL_VAL_B);
428 ctx->state[2] = readl(cpg->reg + DIGEST_INITIAL_VAL_C);
429 ctx->state[3] = readl(cpg->reg + DIGEST_INITIAL_VAL_D);
430 ctx->state[4] = readl(cpg->reg + DIGEST_INITIAL_VAL_E);
434 static void dequeue_complete_req(void)
436 struct crypto_async_request *req = cpg->cur_req;
439 cpg->p.hw_processed_bytes += cpg->p.crypt_len;
440 if (cpg->p.copy_back) {
441 int need_copy_len = cpg->p.crypt_len;
446 if (!cpg->p.sg_dst_left) {
447 ret = sg_miter_next(&cpg->p.dst_sg_it);
449 cpg->p.sg_dst_left = cpg->p.dst_sg_it.length;
450 cpg->p.dst_start = 0;
453 buf = cpg->p.dst_sg_it.addr;
454 buf += cpg->p.dst_start;
456 dst_copy = min(need_copy_len, cpg->p.sg_dst_left);
459 cpg->sram + SRAM_DATA_OUT_START + sram_offset,
461 sram_offset += dst_copy;
462 cpg->p.sg_dst_left -= dst_copy;
463 need_copy_len -= dst_copy;
464 cpg->p.dst_start += dst_copy;
465 } while (need_copy_len > 0);
468 cpg->p.crypt_len = 0;
470 BUG_ON(cpg->eng_st != ENGINE_W_DEQUEUE);
471 if (cpg->p.hw_processed_bytes < cpg->p.hw_nbytes) {
472 /* process next scatter list entry */
473 cpg->eng_st = ENGINE_BUSY;
477 cpg->eng_st = ENGINE_IDLE;
479 req->complete(req, 0);
484 static int count_sgs(struct scatterlist *sl, unsigned int total_bytes)
490 cur_len = sl[i].length;
492 if (total_bytes > cur_len)
493 total_bytes -= cur_len;
501 static void mv_start_new_crypt_req(struct ablkcipher_request *req)
503 struct req_progress *p = &cpg->p;
506 cpg->cur_req = &req->base;
507 memset(p, 0, sizeof(struct req_progress));
508 p->hw_nbytes = req->nbytes;
509 p->complete = mv_crypto_algo_completion;
510 p->process = mv_process_current_q;
513 num_sgs = count_sgs(req->src, req->nbytes);
514 sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
516 num_sgs = count_sgs(req->dst, req->nbytes);
517 sg_miter_start(&p->dst_sg_it, req->dst, num_sgs, SG_MITER_TO_SG);
519 mv_process_current_q(1);
522 static void mv_start_new_hash_req(struct ahash_request *req)
524 struct req_progress *p = &cpg->p;
525 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
526 int num_sgs, hw_bytes, old_extra_bytes, rc;
527 cpg->cur_req = &req->base;
528 memset(p, 0, sizeof(struct req_progress));
529 hw_bytes = req->nbytes + ctx->extra_bytes;
530 old_extra_bytes = ctx->extra_bytes;
532 ctx->extra_bytes = hw_bytes % SHA1_BLOCK_SIZE;
533 if (ctx->extra_bytes != 0
534 && (!ctx->last_chunk || ctx->count > MAX_HW_HASH_SIZE))
535 hw_bytes -= ctx->extra_bytes;
537 ctx->extra_bytes = 0;
539 num_sgs = count_sgs(req->src, req->nbytes);
540 sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
543 p->hw_nbytes = hw_bytes;
544 p->complete = mv_hash_algo_completion;
545 p->process = mv_process_hash_current;
547 if (unlikely(old_extra_bytes)) {
548 memcpy(cpg->sram + SRAM_DATA_IN_START, ctx->buffer,
550 p->crypt_len = old_extra_bytes;
553 mv_process_hash_current(1);
555 copy_src_to_buf(p, ctx->buffer + old_extra_bytes,
556 ctx->extra_bytes - old_extra_bytes);
557 sg_miter_stop(&p->src_sg_it);
559 rc = mv_hash_final_fallback(req);
562 cpg->eng_st = ENGINE_IDLE;
564 req->base.complete(&req->base, rc);
569 static int queue_manag(void *data)
571 cpg->eng_st = ENGINE_IDLE;
573 struct crypto_async_request *async_req = NULL;
574 struct crypto_async_request *backlog;
576 __set_current_state(TASK_INTERRUPTIBLE);
578 if (cpg->eng_st == ENGINE_W_DEQUEUE)
579 dequeue_complete_req();
581 spin_lock_irq(&cpg->lock);
582 if (cpg->eng_st == ENGINE_IDLE) {
583 backlog = crypto_get_backlog(&cpg->queue);
584 async_req = crypto_dequeue_request(&cpg->queue);
586 BUG_ON(cpg->eng_st != ENGINE_IDLE);
587 cpg->eng_st = ENGINE_BUSY;
590 spin_unlock_irq(&cpg->lock);
593 backlog->complete(backlog, -EINPROGRESS);
598 if (async_req->tfm->__crt_alg->cra_type !=
599 &crypto_ahash_type) {
600 struct ablkcipher_request *req =
601 ablkcipher_request_cast(async_req);
602 mv_start_new_crypt_req(req);
604 struct ahash_request *req =
605 ahash_request_cast(async_req);
606 mv_start_new_hash_req(req);
613 } while (!kthread_should_stop());
617 static int mv_handle_req(struct crypto_async_request *req)
622 spin_lock_irqsave(&cpg->lock, flags);
623 ret = crypto_enqueue_request(&cpg->queue, req);
624 spin_unlock_irqrestore(&cpg->lock, flags);
625 wake_up_process(cpg->queue_th);
629 static int mv_enc_aes_ecb(struct ablkcipher_request *req)
631 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
633 req_ctx->op = COP_AES_ECB;
634 req_ctx->decrypt = 0;
636 return mv_handle_req(&req->base);
639 static int mv_dec_aes_ecb(struct ablkcipher_request *req)
641 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
642 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
644 req_ctx->op = COP_AES_ECB;
645 req_ctx->decrypt = 1;
647 compute_aes_dec_key(ctx);
648 return mv_handle_req(&req->base);
651 static int mv_enc_aes_cbc(struct ablkcipher_request *req)
653 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
655 req_ctx->op = COP_AES_CBC;
656 req_ctx->decrypt = 0;
658 return mv_handle_req(&req->base);
661 static int mv_dec_aes_cbc(struct ablkcipher_request *req)
663 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
664 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
666 req_ctx->op = COP_AES_CBC;
667 req_ctx->decrypt = 1;
669 compute_aes_dec_key(ctx);
670 return mv_handle_req(&req->base);
673 static int mv_cra_init(struct crypto_tfm *tfm)
675 tfm->crt_ablkcipher.reqsize = sizeof(struct mv_req_ctx);
679 static void mv_init_hash_req_ctx(struct mv_req_hash_ctx *ctx, int op,
680 int is_last, unsigned int req_len,
683 memset(ctx, 0, sizeof(*ctx));
685 ctx->count = req_len;
687 ctx->last_chunk = is_last;
688 ctx->count_add = count_add;
691 static void mv_update_hash_req_ctx(struct mv_req_hash_ctx *ctx, int is_last,
694 ctx->last_chunk = is_last;
695 ctx->count += req_len;
698 static int mv_hash_init(struct ahash_request *req)
700 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
701 mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 0, 0,
706 static int mv_hash_update(struct ahash_request *req)
711 mv_update_hash_req_ctx(ahash_request_ctx(req), 0, req->nbytes);
712 return mv_handle_req(&req->base);
715 static int mv_hash_final(struct ahash_request *req)
717 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
719 ahash_request_set_crypt(req, NULL, req->result, 0);
720 mv_update_hash_req_ctx(ctx, 1, 0);
721 return mv_handle_req(&req->base);
724 static int mv_hash_finup(struct ahash_request *req)
726 mv_update_hash_req_ctx(ahash_request_ctx(req), 1, req->nbytes);
727 return mv_handle_req(&req->base);
730 static int mv_hash_digest(struct ahash_request *req)
732 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
733 mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 1,
734 req->nbytes, tfm_ctx->count_add);
735 return mv_handle_req(&req->base);
738 static void mv_hash_init_ivs(struct mv_tfm_hash_ctx *ctx, const void *istate,
741 const struct sha1_state *isha1_state = istate, *osha1_state = ostate;
743 for (i = 0; i < 5; i++) {
744 ctx->ivs[i] = cpu_to_be32(isha1_state->state[i]);
745 ctx->ivs[i + 5] = cpu_to_be32(osha1_state->state[i]);
749 static int mv_hash_setkey(struct crypto_ahash *tfm, const u8 * key,
753 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(&tfm->base);
759 rc = crypto_shash_setkey(ctx->fallback, key, keylen);
763 /* Can't see a way to extract the ipad/opad from the fallback tfm
764 so I'm basically copying code from the hmac module */
765 bs = crypto_shash_blocksize(ctx->base_hash);
766 ds = crypto_shash_digestsize(ctx->base_hash);
767 ss = crypto_shash_statesize(ctx->base_hash);
771 struct shash_desc shash;
772 char ctx[crypto_shash_descsize(ctx->base_hash)];
778 desc.shash.tfm = ctx->base_hash;
779 desc.shash.flags = crypto_shash_get_flags(ctx->base_hash) &
780 CRYPTO_TFM_REQ_MAY_SLEEP;
786 crypto_shash_digest(&desc.shash, key, keylen, ipad);
792 memcpy(ipad, key, keylen);
794 memset(ipad + keylen, 0, bs - keylen);
795 memcpy(opad, ipad, bs);
797 for (i = 0; i < bs; i++) {
802 rc = crypto_shash_init(&desc.shash) ? :
803 crypto_shash_update(&desc.shash, ipad, bs) ? :
804 crypto_shash_export(&desc.shash, ipad) ? :
805 crypto_shash_init(&desc.shash) ? :
806 crypto_shash_update(&desc.shash, opad, bs) ? :
807 crypto_shash_export(&desc.shash, opad);
810 mv_hash_init_ivs(ctx, ipad, opad);
816 static int mv_cra_hash_init(struct crypto_tfm *tfm, const char *base_hash_name,
817 enum hash_op op, int count_add)
819 const char *fallback_driver_name = tfm->__crt_alg->cra_name;
820 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
821 struct crypto_shash *fallback_tfm = NULL;
822 struct crypto_shash *base_hash = NULL;
826 ctx->count_add = count_add;
828 /* Allocate a fallback and abort if it failed. */
829 fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
830 CRYPTO_ALG_NEED_FALLBACK);
831 if (IS_ERR(fallback_tfm)) {
832 printk(KERN_WARNING MV_CESA
833 "Fallback driver '%s' could not be loaded!\n",
834 fallback_driver_name);
835 err = PTR_ERR(fallback_tfm);
838 ctx->fallback = fallback_tfm;
840 if (base_hash_name) {
841 /* Allocate a hash to compute the ipad/opad of hmac. */
842 base_hash = crypto_alloc_shash(base_hash_name, 0,
843 CRYPTO_ALG_NEED_FALLBACK);
844 if (IS_ERR(base_hash)) {
845 printk(KERN_WARNING MV_CESA
846 "Base driver '%s' could not be loaded!\n",
848 err = PTR_ERR(base_hash);
852 ctx->base_hash = base_hash;
854 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
855 sizeof(struct mv_req_hash_ctx) +
856 crypto_shash_descsize(ctx->fallback));
859 crypto_free_shash(fallback_tfm);
864 static void mv_cra_hash_exit(struct crypto_tfm *tfm)
866 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
868 crypto_free_shash(ctx->fallback);
870 crypto_free_shash(ctx->base_hash);
873 static int mv_cra_hash_sha1_init(struct crypto_tfm *tfm)
875 return mv_cra_hash_init(tfm, NULL, COP_SHA1, 0);
878 static int mv_cra_hash_hmac_sha1_init(struct crypto_tfm *tfm)
880 return mv_cra_hash_init(tfm, "sha1", COP_HMAC_SHA1, SHA1_BLOCK_SIZE);
883 irqreturn_t crypto_int(int irq, void *priv)
887 val = readl(cpg->reg + SEC_ACCEL_INT_STATUS);
888 if (!(val & SEC_INT_ACCEL0_DONE))
891 val &= ~SEC_INT_ACCEL0_DONE;
892 writel(val, cpg->reg + FPGA_INT_STATUS);
893 writel(val, cpg->reg + SEC_ACCEL_INT_STATUS);
894 BUG_ON(cpg->eng_st != ENGINE_BUSY);
895 cpg->eng_st = ENGINE_W_DEQUEUE;
896 wake_up_process(cpg->queue_th);
900 struct crypto_alg mv_aes_alg_ecb = {
901 .cra_name = "ecb(aes)",
902 .cra_driver_name = "mv-ecb-aes",
904 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
905 CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC,
907 .cra_ctxsize = sizeof(struct mv_ctx),
909 .cra_type = &crypto_ablkcipher_type,
910 .cra_module = THIS_MODULE,
911 .cra_init = mv_cra_init,
914 .min_keysize = AES_MIN_KEY_SIZE,
915 .max_keysize = AES_MAX_KEY_SIZE,
916 .setkey = mv_setkey_aes,
917 .encrypt = mv_enc_aes_ecb,
918 .decrypt = mv_dec_aes_ecb,
923 struct crypto_alg mv_aes_alg_cbc = {
924 .cra_name = "cbc(aes)",
925 .cra_driver_name = "mv-cbc-aes",
927 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
928 CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC,
929 .cra_blocksize = AES_BLOCK_SIZE,
930 .cra_ctxsize = sizeof(struct mv_ctx),
932 .cra_type = &crypto_ablkcipher_type,
933 .cra_module = THIS_MODULE,
934 .cra_init = mv_cra_init,
937 .ivsize = AES_BLOCK_SIZE,
938 .min_keysize = AES_MIN_KEY_SIZE,
939 .max_keysize = AES_MAX_KEY_SIZE,
940 .setkey = mv_setkey_aes,
941 .encrypt = mv_enc_aes_cbc,
942 .decrypt = mv_dec_aes_cbc,
947 struct ahash_alg mv_sha1_alg = {
948 .init = mv_hash_init,
949 .update = mv_hash_update,
950 .final = mv_hash_final,
951 .finup = mv_hash_finup,
952 .digest = mv_hash_digest,
954 .digestsize = SHA1_DIGEST_SIZE,
957 .cra_driver_name = "mv-sha1",
960 CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
961 CRYPTO_ALG_NEED_FALLBACK,
962 .cra_blocksize = SHA1_BLOCK_SIZE,
963 .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
964 .cra_init = mv_cra_hash_sha1_init,
965 .cra_exit = mv_cra_hash_exit,
966 .cra_module = THIS_MODULE,
971 struct ahash_alg mv_hmac_sha1_alg = {
972 .init = mv_hash_init,
973 .update = mv_hash_update,
974 .final = mv_hash_final,
975 .finup = mv_hash_finup,
976 .digest = mv_hash_digest,
977 .setkey = mv_hash_setkey,
979 .digestsize = SHA1_DIGEST_SIZE,
981 .cra_name = "hmac(sha1)",
982 .cra_driver_name = "mv-hmac-sha1",
985 CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
986 CRYPTO_ALG_NEED_FALLBACK,
987 .cra_blocksize = SHA1_BLOCK_SIZE,
988 .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
989 .cra_init = mv_cra_hash_hmac_sha1_init,
990 .cra_exit = mv_cra_hash_exit,
991 .cra_module = THIS_MODULE,
996 static int mv_probe(struct platform_device *pdev)
998 struct crypto_priv *cp;
999 struct resource *res;
1004 printk(KERN_ERR MV_CESA "Second crypto dev?\n");
1008 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1012 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
1016 spin_lock_init(&cp->lock);
1017 crypto_init_queue(&cp->queue, 50);
1018 cp->reg = ioremap(res->start, resource_size(res));
1024 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
1029 cp->sram_size = resource_size(res);
1030 cp->max_req_size = cp->sram_size - SRAM_CFG_SPACE;
1031 cp->sram = ioremap(res->start, cp->sram_size);
1037 irq = platform_get_irq(pdev, 0);
1038 if (irq < 0 || irq == NO_IRQ) {
1040 goto err_unmap_sram;
1044 platform_set_drvdata(pdev, cp);
1047 cp->queue_th = kthread_run(queue_manag, cp, "mv_crypto");
1048 if (IS_ERR(cp->queue_th)) {
1049 ret = PTR_ERR(cp->queue_th);
1050 goto err_unmap_sram;
1053 ret = request_irq(irq, crypto_int, IRQF_DISABLED, dev_name(&pdev->dev),
1058 /* Not all platforms can gate the clock, so it is not
1059 an error if the clock does not exists. */
1060 cp->clk = clk_get(&pdev->dev, NULL);
1061 if (!IS_ERR(cp->clk))
1062 clk_prepare_enable(cp->clk);
1064 writel(SEC_INT_ACCEL0_DONE, cpg->reg + SEC_ACCEL_INT_MASK);
1065 writel(SEC_CFG_STOP_DIG_ERR, cpg->reg + SEC_ACCEL_CFG);
1066 writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
1068 ret = crypto_register_alg(&mv_aes_alg_ecb);
1070 printk(KERN_WARNING MV_CESA
1071 "Could not register aes-ecb driver\n");
1075 ret = crypto_register_alg(&mv_aes_alg_cbc);
1077 printk(KERN_WARNING MV_CESA
1078 "Could not register aes-cbc driver\n");
1082 ret = crypto_register_ahash(&mv_sha1_alg);
1086 printk(KERN_WARNING MV_CESA "Could not register sha1 driver\n");
1088 ret = crypto_register_ahash(&mv_hmac_sha1_alg);
1090 cpg->has_hmac_sha1 = 1;
1092 printk(KERN_WARNING MV_CESA
1093 "Could not register hmac-sha1 driver\n");
1098 crypto_unregister_alg(&mv_aes_alg_ecb);
1102 kthread_stop(cp->queue_th);
1110 platform_set_drvdata(pdev, NULL);
1114 static int mv_remove(struct platform_device *pdev)
1116 struct crypto_priv *cp = platform_get_drvdata(pdev);
1118 crypto_unregister_alg(&mv_aes_alg_ecb);
1119 crypto_unregister_alg(&mv_aes_alg_cbc);
1121 crypto_unregister_ahash(&mv_sha1_alg);
1122 if (cp->has_hmac_sha1)
1123 crypto_unregister_ahash(&mv_hmac_sha1_alg);
1124 kthread_stop(cp->queue_th);
1125 free_irq(cp->irq, cp);
1126 memset(cp->sram, 0, cp->sram_size);
1130 if (!IS_ERR(cp->clk)) {
1131 clk_disable_unprepare(cp->clk);
1140 static struct platform_driver marvell_crypto = {
1142 .remove = mv_remove,
1144 .owner = THIS_MODULE,
1145 .name = "mv_crypto",
1148 MODULE_ALIAS("platform:mv_crypto");
1150 module_platform_driver(marvell_crypto);
1152 MODULE_AUTHOR("Sebastian Andrzej Siewior <sebastian@breakpoint.cc>");
1153 MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");
1154 MODULE_LICENSE("GPL");