drivers/crypto/omap-aes.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP AES HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  */
  15
  16 #define pr_fmt(fmt) "%20s: " fmt, __func__
  17 #define prn(num) pr_debug(#num "=%d\n", num)
  18 #define prx(num) pr_debug(#num "=%x\n", num)
  19
  20 #include <linux/err.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/kernel.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/scatterlist.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/omap-dma.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/of_address.h>
  34 #include <linux/io.h>
  35 #include <linux/crypto.h>
  36 #include <linux/interrupt.h>
  37 #include <crypto/scatterwalk.h>
  38 #include <crypto/aes.h>
  39
  40 #define DST_MAXBURST                    4
  41 #define DMA_MIN                         (DST_MAXBURST * sizeof(u32))
  42
  43 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
  44
  45 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  46    number. For example 7:0 */
  47 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  48 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  49
  50 #define AES_REG_KEY(dd, x)              ((dd)->pdata->key_ofs - \
  51                                                 ((x ^ 0x01) * 0x04))
  52 #define AES_REG_IV(dd, x)               ((dd)->pdata->iv_ofs + ((x) * 0x04))
  53
  54 #define AES_REG_CTRL(dd)                ((dd)->pdata->ctrl_ofs)
  55 #define AES_REG_CTRL_CTR_WIDTH_MASK     (3 << 7)
  56 #define AES_REG_CTRL_CTR_WIDTH_32               (0 << 7)
  57 #define AES_REG_CTRL_CTR_WIDTH_64               (1 << 7)
  58 #define AES_REG_CTRL_CTR_WIDTH_96               (2 << 7)
  59 #define AES_REG_CTRL_CTR_WIDTH_128              (3 << 7)
  60 #define AES_REG_CTRL_CTR                (1 << 6)
  61 #define AES_REG_CTRL_CBC                (1 << 5)
  62 #define AES_REG_CTRL_KEY_SIZE           (3 << 3)
  63 #define AES_REG_CTRL_DIRECTION          (1 << 2)
  64 #define AES_REG_CTRL_INPUT_READY        (1 << 1)
  65 #define AES_REG_CTRL_OUTPUT_READY       (1 << 0)
  66
  67 #define AES_REG_DATA_N(dd, x)           ((dd)->pdata->data_ofs + ((x) * 0x04))
  68
  69 #define AES_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  70
  71 #define AES_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  72 #define AES_REG_MASK_SIDLE              (1 << 6)
  73 #define AES_REG_MASK_START              (1 << 5)
  74 #define AES_REG_MASK_DMA_OUT_EN         (1 << 3)
  75 #define AES_REG_MASK_DMA_IN_EN          (1 << 2)
  76 #define AES_REG_MASK_SOFTRESET          (1 << 1)
  77 #define AES_REG_AUTOIDLE                (1 << 0)
  78
  79 #define AES_REG_LENGTH_N(x)             (0x54 + ((x) * 0x04))
  80
  81 #define AES_REG_IRQ_STATUS(dd)         ((dd)->pdata->irq_status_ofs)
  82 #define AES_REG_IRQ_ENABLE(dd)         ((dd)->pdata->irq_enable_ofs)
  83 #define AES_REG_IRQ_DATA_IN            BIT(1)
  84 #define AES_REG_IRQ_DATA_OUT           BIT(2)
  85 #define DEFAULT_TIMEOUT         (5*HZ)
  86
  87 #define FLAGS_MODE_MASK         0x000f
  88 #define FLAGS_ENCRYPT           BIT(0)
  89 #define FLAGS_CBC               BIT(1)
  90 #define FLAGS_GIV               BIT(2)
  91 #define FLAGS_CTR               BIT(3)
  92
  93 #define FLAGS_INIT              BIT(4)
  94 #define FLAGS_FAST              BIT(5)
  95 #define FLAGS_BUSY              BIT(6)
  96
  97 #define AES_BLOCK_WORDS         (AES_BLOCK_SIZE >> 2)
  98
  99 struct omap_aes_ctx {
 100         struct omap_aes_dev *dd;
 101
 102         int             keylen;
 103         u32             key[AES_KEYSIZE_256 / sizeof(u32)];
 104         unsigned long   flags;
 105 };
 106
 107 struct omap_aes_reqctx {
 108         unsigned long mode;
 109 };
 110
 111 #define OMAP_AES_QUEUE_LENGTH   1
 112 #define OMAP_AES_CACHE_SIZE     0
 113
 114 struct omap_aes_algs_info {
 115         struct crypto_alg       *algs_list;
 116         unsigned int            size;
 117         unsigned int            registered;
 118 };
 119
 120 struct omap_aes_pdata {
 121         struct omap_aes_algs_info       *algs_info;
 122         unsigned int    algs_info_size;
 123
 124         void            (*trigger)(struct omap_aes_dev *dd, int length);
 125
 126         u32             key_ofs;
 127         u32             iv_ofs;
 128         u32             ctrl_ofs;
 129         u32             data_ofs;
 130         u32             rev_ofs;
 131         u32             mask_ofs;
 132         u32             irq_enable_ofs;
 133         u32             irq_status_ofs;
 134
 135         u32             dma_enable_in;
 136         u32             dma_enable_out;
 137         u32             dma_start;
 138
 139         u32             major_mask;
 140         u32             major_shift;
 141         u32             minor_mask;
 142         u32             minor_shift;
 143 };
 144
 145 struct omap_aes_dev {
 146         struct list_head        list;
 147         unsigned long           phys_base;
 148         void __iomem            *io_base;
 149         struct omap_aes_ctx     *ctx;
 150         struct device           *dev;
 151         unsigned long           flags;
 152         int                     err;
 153
 154         spinlock_t              lock;
 155         struct crypto_queue     queue;
 156
 157         struct tasklet_struct   done_task;
 158         struct tasklet_struct   queue_task;
 159
 160         struct ablkcipher_request       *req;
 161         size_t                          total;
 162         struct scatterlist              *in_sg;
 163         struct scatterlist              *out_sg;
 164         struct scatter_walk             in_walk;
 165         struct scatter_walk             out_walk;
 166         int                     dma_in;
 167         struct dma_chan         *dma_lch_in;
 168         int                     dma_out;
 169         struct dma_chan         *dma_lch_out;
 170         int                     in_sg_len;
 171         int                     out_sg_len;
 172         int                     pio_only;
 173         const struct omap_aes_pdata     *pdata;
 174 };
 175
 176 /* keep registered devices data here */
 177 static LIST_HEAD(dev_list);
 178 static DEFINE_SPINLOCK(list_lock);
 179
 180 #ifdef DEBUG
 181 #define omap_aes_read(dd, offset)                               \
 182 ({                                                              \
 183         int _read_ret;                                          \
 184         _read_ret = __raw_readl(dd->io_base + offset);          \
 185         pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n",       \
 186                  offset, _read_ret);                            \
 187         _read_ret;                                              \
 188 })
 189 #else
 190 static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
 191 {
 192         return __raw_readl(dd->io_base + offset);
 193 }
 194 #endif
 195
 196 #ifdef DEBUG
 197 #define omap_aes_write(dd, offset, value)                               \
 198         do {                                                            \
 199                 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
 200                          offset, value);                                \
 201                 __raw_writel(value, dd->io_base + offset);              \
 202         } while (0)
 203 #else
 204 static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
 205                                   u32 value)
 206 {
 207         __raw_writel(value, dd->io_base + offset);
 208 }
 209 #endif
 210
 211 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
 212                                         u32 value, u32 mask)
 213 {
 214         u32 val;
 215
 216         val = omap_aes_read(dd, offset);
 217         val &= ~mask;
 218         val |= value;
 219         omap_aes_write(dd, offset, val);
 220 }
 221
 222 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
 223                                         u32 *value, int count)
 224 {
 225         for (; count--; value++, offset += 4)
 226                 omap_aes_write(dd, offset, *value);
 227 }
 228
 229 static int omap_aes_hw_init(struct omap_aes_dev *dd)
 230 {
 231         if (!(dd->flags & FLAGS_INIT)) {
 232                 dd->flags |= FLAGS_INIT;
 233                 dd->err = 0;
 234         }
 235
 236         return 0;
 237 }
 238
 239 static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
 240 {
 241         unsigned int key32;
 242         int i, err;
 243         u32 val, mask = 0;
 244
 245         err = omap_aes_hw_init(dd);
 246         if (err)
 247                 return err;
 248
 249         key32 = dd->ctx->keylen / sizeof(u32);
 250
 251         /* it seems a key should always be set even if it has not changed */
 252         for (i = 0; i < key32; i++) {
 253                 omap_aes_write(dd, AES_REG_KEY(dd, i),
 254                         __le32_to_cpu(dd->ctx->key[i]));
 255         }
 256
 257         if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
 258                 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
 259
 260         val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
 261         if (dd->flags & FLAGS_CBC)
 262                 val |= AES_REG_CTRL_CBC;
 263         if (dd->flags & FLAGS_CTR) {
 264                 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_32;
 265                 mask = AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_MASK;
 266         }
 267         if (dd->flags & FLAGS_ENCRYPT)
 268                 val |= AES_REG_CTRL_DIRECTION;
 269
 270         mask |= AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION |
 271                         AES_REG_CTRL_KEY_SIZE;
 272
 273         omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, mask);
 274
 275         return 0;
 276 }
 277
 278 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
 279 {
 280         u32 mask, val;
 281
 282         val = dd->pdata->dma_start;
 283
 284         if (dd->dma_lch_out != NULL)
 285                 val |= dd->pdata->dma_enable_out;
 286         if (dd->dma_lch_in != NULL)
 287                 val |= dd->pdata->dma_enable_in;
 288
 289         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 290                dd->pdata->dma_start;
 291
 292         omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
 293
 294 }
 295
 296 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
 297 {
 298         omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
 299         omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
 300
 301         omap_aes_dma_trigger_omap2(dd, length);
 302 }
 303
 304 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
 305 {
 306         u32 mask;
 307
 308         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 309                dd->pdata->dma_start;
 310
 311         omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
 312 }
 313
 314 static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
 315 {
 316         struct omap_aes_dev *dd = NULL, *tmp;
 317
 318         spin_lock_bh(&list_lock);
 319         if (!ctx->dd) {
 320                 list_for_each_entry(tmp, &dev_list, list) {
 321                         /* FIXME: take fist available aes core */
 322                         dd = tmp;
 323                         break;
 324                 }
 325                 ctx->dd = dd;
 326         } else {
 327                 /* already found before */
 328                 dd = ctx->dd;
 329         }
 330         spin_unlock_bh(&list_lock);
 331
 332         return dd;
 333 }
 334
 335 static void omap_aes_dma_out_callback(void *data)
 336 {
 337         struct omap_aes_dev *dd = data;
 338
 339         /* dma_lch_out - completed */
 340         tasklet_schedule(&dd->done_task);
 341 }
 342
 343 static int omap_aes_dma_init(struct omap_aes_dev *dd)
 344 {
 345         int err = -ENOMEM;
 346         dma_cap_mask_t mask;
 347
 348         dd->dma_lch_out = NULL;
 349         dd->dma_lch_in = NULL;
 350
 351         dma_cap_zero(mask);
 352         dma_cap_set(DMA_SLAVE, mask);
 353
 354         dd->dma_lch_in = dma_request_slave_channel_compat(mask,
 355                                                           omap_dma_filter_fn,
 356                                                           &dd->dma_in,
 357                                                           dd->dev, "rx");
 358         if (!dd->dma_lch_in) {
 359                 dev_err(dd->dev, "Unable to request in DMA channel\n");
 360                 goto err_dma_in;
 361         }
 362
 363         dd->dma_lch_out = dma_request_slave_channel_compat(mask,
 364                                                            omap_dma_filter_fn,
 365                                                            &dd->dma_out,
 366                                                            dd->dev, "tx");
 367         if (!dd->dma_lch_out) {
 368                 dev_err(dd->dev, "Unable to request out DMA channel\n");
 369                 goto err_dma_out;
 370         }
 371
 372         return 0;
 373
 374 err_dma_out:
 375         dma_release_channel(dd->dma_lch_in);
 376 err_dma_in:
 377         if (err)
 378                 pr_err("error: %d\n", err);
 379         return err;
 380 }
 381
 382 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
 383 {
 384         dma_release_channel(dd->dma_lch_out);
 385         dma_release_channel(dd->dma_lch_in);
 386 }
 387
 388 static void sg_copy_buf(void *buf, struct scatterlist *sg,
 389                               unsigned int start, unsigned int nbytes, int out)
 390 {
 391         struct scatter_walk walk;
 392
 393         if (!nbytes)
 394                 return;
 395
 396         scatterwalk_start(&walk, sg);
 397         scatterwalk_advance(&walk, start);
 398         scatterwalk_copychunks(buf, &walk, nbytes, out);
 399         scatterwalk_done(&walk, out, 0);
 400 }
 401
 402 static int omap_aes_crypt_dma(struct crypto_tfm *tfm,
 403                 struct scatterlist *in_sg, struct scatterlist *out_sg,
 404                 int in_sg_len, int out_sg_len)
 405 {
 406         struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
 407         struct omap_aes_dev *dd = ctx->dd;
 408         struct dma_async_tx_descriptor *tx_in, *tx_out;
 409         struct dma_slave_config cfg;
 410         int ret;
 411
 412         if (dd->pio_only) {
 413                 scatterwalk_start(&dd->in_walk, dd->in_sg);
 414                 scatterwalk_start(&dd->out_walk, dd->out_sg);
 415
 416                 /* Enable DATAIN interrupt and let it take
 417                    care of the rest */
 418                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
 419                 return 0;
 420         }
 421
 422         dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
 423
 424         memset(&cfg, 0, sizeof(cfg));
 425
 426         cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 427         cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 428         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 429         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 430         cfg.src_maxburst = DST_MAXBURST;
 431         cfg.dst_maxburst = DST_MAXBURST;
 432
 433         /* IN */
 434         ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
 435         if (ret) {
 436                 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
 437                         ret);
 438                 return ret;
 439         }
 440
 441         tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
 442                                         DMA_MEM_TO_DEV,
 443                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 444         if (!tx_in) {
 445                 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
 446                 return -EINVAL;
 447         }
 448
 449         /* No callback necessary */
 450         tx_in->callback_param = dd;
 451
 452         /* OUT */
 453         ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
 454         if (ret) {
 455                 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
 456                         ret);
 457                 return ret;
 458         }
 459
 460         tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
 461                                         DMA_DEV_TO_MEM,
 462                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 463         if (!tx_out) {
 464                 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
 465                 return -EINVAL;
 466         }
 467
 468         tx_out->callback = omap_aes_dma_out_callback;
 469         tx_out->callback_param = dd;
 470
 471         dmaengine_submit(tx_in);
 472         dmaengine_submit(tx_out);
 473
 474         dma_async_issue_pending(dd->dma_lch_in);
 475         dma_async_issue_pending(dd->dma_lch_out);
 476
 477         /* start DMA */
 478         dd->pdata->trigger(dd, dd->total);
 479
 480         return 0;
 481 }
 482
 483 static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
 484 {
 485         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
 486                                         crypto_ablkcipher_reqtfm(dd->req));
 487         int err;
 488
 489         pr_debug("total: %d\n", dd->total);
 490
 491         if (!dd->pio_only) {
 492                 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
 493                                  DMA_TO_DEVICE);
 494                 if (!err) {
 495                         dev_err(dd->dev, "dma_map_sg() error\n");
 496                         return -EINVAL;
 497                 }
 498
 499                 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 500                                  DMA_FROM_DEVICE);
 501                 if (!err) {
 502                         dev_err(dd->dev, "dma_map_sg() error\n");
 503                         return -EINVAL;
 504                 }
 505         }
 506
 507         err = omap_aes_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
 508                                  dd->out_sg_len);
 509         if (err && !dd->pio_only) {
 510                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 511                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 512                              DMA_FROM_DEVICE);
 513         }
 514
 515         return err;
 516 }
 517
 518 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
 519 {
 520         struct ablkcipher_request *req = dd->req;
 521
 522         pr_debug("err: %d\n", err);
 523
 524         dd->flags &= ~FLAGS_BUSY;
 525
 526         req->base.complete(&req->base, err);
 527 }
 528
 529 static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
 530 {
 531         int err = 0;
 532
 533         pr_debug("total: %d\n", dd->total);
 534
 535         omap_aes_dma_stop(dd);
 536
 537         dmaengine_terminate_all(dd->dma_lch_in);
 538         dmaengine_terminate_all(dd->dma_lch_out);
 539
 540         dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 541         dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, DMA_FROM_DEVICE);
 542
 543         return err;
 544 }
 545
 546 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
 547                                struct ablkcipher_request *req)
 548 {
 549         struct crypto_async_request *async_req, *backlog;
 550         struct omap_aes_ctx *ctx;
 551         struct omap_aes_reqctx *rctx;
 552         unsigned long flags;
 553         int err, ret = 0;
 554
 555         spin_lock_irqsave(&dd->lock, flags);
 556         if (req)
 557                 ret = ablkcipher_enqueue_request(&dd->queue, req);
 558         if (dd->flags & FLAGS_BUSY) {
 559                 spin_unlock_irqrestore(&dd->lock, flags);
 560                 return ret;
 561         }
 562         backlog = crypto_get_backlog(&dd->queue);
 563         async_req = crypto_dequeue_request(&dd->queue);
 564         if (async_req)
 565                 dd->flags |= FLAGS_BUSY;
 566         spin_unlock_irqrestore(&dd->lock, flags);
 567
 568         if (!async_req)
 569                 return ret;
 570
 571         if (backlog)
 572                 backlog->complete(backlog, -EINPROGRESS);
 573
 574         req = ablkcipher_request_cast(async_req);
 575
 576         /* assign new request to device */
 577         dd->req = req;
 578         dd->total = req->nbytes;
 579         dd->in_sg = req->src;
 580         dd->out_sg = req->dst;
 581
 582         dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, dd->total);
 583         dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, dd->total);
 584         BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0);
 585
 586         rctx = ablkcipher_request_ctx(req);
 587         ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
 588         rctx->mode &= FLAGS_MODE_MASK;
 589         dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
 590
 591         dd->ctx = ctx;
 592         ctx->dd = dd;
 593
 594         err = omap_aes_write_ctrl(dd);
 595         if (!err)
 596                 err = omap_aes_crypt_dma_start(dd);
 597         if (err) {
 598                 /* aes_task will not finish it, so do it here */
 599                 omap_aes_finish_req(dd, err);
 600                 tasklet_schedule(&dd->queue_task);
 601         }
 602
 603         return ret; /* return ret, which is enqueue return value */
 604 }
 605
 606 static void omap_aes_done_task(unsigned long data)
 607 {
 608         struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
 609
 610         pr_debug("enter done_task\n");
 611
 612         if (!dd->pio_only) {
 613                 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
 614                                        DMA_FROM_DEVICE);
 615                 omap_aes_crypt_dma_stop(dd);
 616         }
 617         omap_aes_finish_req(dd, 0);
 618         omap_aes_handle_queue(dd, NULL);
 619
 620         pr_debug("exit\n");
 621 }
 622
 623 static void omap_aes_queue_task(unsigned long data)
 624 {
 625         struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
 626
 627         omap_aes_handle_queue(dd, NULL);
 628 }
 629
 630 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
 631 {
 632         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
 633                         crypto_ablkcipher_reqtfm(req));
 634         struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
 635         struct omap_aes_dev *dd;
 636
 637         pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
 638                   !!(mode & FLAGS_ENCRYPT),
 639                   !!(mode & FLAGS_CBC));
 640
 641         if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
 642                 pr_err("request size is not exact amount of AES blocks\n");
 643                 return -EINVAL;
 644         }
 645
 646         dd = omap_aes_find_dev(ctx);
 647         if (!dd)
 648                 return -ENODEV;
 649
 650         rctx->mode = mode;
 651
 652         return omap_aes_handle_queue(dd, req);
 653 }
 654
 655 /* ********************** ALG API ************************************ */
 656
 657 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 658                            unsigned int keylen)
 659 {
 660         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 661
 662         if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
 663                    keylen != AES_KEYSIZE_256)
 664                 return -EINVAL;
 665
 666         pr_debug("enter, keylen: %d\n", keylen);
 667
 668         memcpy(ctx->key, key, keylen);
 669         ctx->keylen = keylen;
 670
 671         return 0;
 672 }
 673
 674 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
 675 {
 676         return omap_aes_crypt(req, FLAGS_ENCRYPT);
 677 }
 678
 679 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
 680 {
 681         return omap_aes_crypt(req, 0);
 682 }
 683
 684 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
 685 {
 686         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
 687 }
 688
 689 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
 690 {
 691         return omap_aes_crypt(req, FLAGS_CBC);
 692 }
 693
 694 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
 695 {
 696         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
 697 }
 698
 699 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
 700 {
 701         return omap_aes_crypt(req, FLAGS_CTR);
 702 }
 703
 704 static int omap_aes_cra_init(struct crypto_tfm *tfm)
 705 {
 706         struct omap_aes_dev *dd = NULL;
 707
 708         /* Find AES device, currently picks the first device */
 709         spin_lock_bh(&list_lock);
 710         list_for_each_entry(dd, &dev_list, list) {
 711                 break;
 712         }
 713         spin_unlock_bh(&list_lock);
 714
 715         pm_runtime_get_sync(dd->dev);
 716         tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
 717
 718         return 0;
 719 }
 720
 721 static void omap_aes_cra_exit(struct crypto_tfm *tfm)
 722 {
 723         struct omap_aes_dev *dd = NULL;
 724
 725         /* Find AES device, currently picks the first device */
 726         spin_lock_bh(&list_lock);
 727         list_for_each_entry(dd, &dev_list, list) {
 728                 break;
 729         }
 730         spin_unlock_bh(&list_lock);
 731
 732         pm_runtime_put_sync(dd->dev);
 733 }
 734
 735 /* ********************** ALGS ************************************ */
 736
 737 static struct crypto_alg algs_ecb_cbc[] = {
 738 {
 739         .cra_name               = "ecb(aes)",
 740         .cra_driver_name        = "ecb-aes-omap",
 741         .cra_priority           = 100,
 742         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 743                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 744                                   CRYPTO_ALG_ASYNC,
 745         .cra_blocksize          = AES_BLOCK_SIZE,
 746         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 747         .cra_alignmask          = 0,
 748         .cra_type               = &crypto_ablkcipher_type,
 749         .cra_module             = THIS_MODULE,
 750         .cra_init               = omap_aes_cra_init,
 751         .cra_exit               = omap_aes_cra_exit,
 752         .cra_u.ablkcipher = {
 753                 .min_keysize    = AES_MIN_KEY_SIZE,
 754                 .max_keysize    = AES_MAX_KEY_SIZE,
 755                 .setkey         = omap_aes_setkey,
 756                 .encrypt        = omap_aes_ecb_encrypt,
 757                 .decrypt        = omap_aes_ecb_decrypt,
 758         }
 759 },
 760 {
 761         .cra_name               = "cbc(aes)",
 762         .cra_driver_name        = "cbc-aes-omap",
 763         .cra_priority           = 100,
 764         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 765                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 766                                   CRYPTO_ALG_ASYNC,
 767         .cra_blocksize          = AES_BLOCK_SIZE,
 768         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 769         .cra_alignmask          = 0,
 770         .cra_type               = &crypto_ablkcipher_type,
 771         .cra_module             = THIS_MODULE,
 772         .cra_init               = omap_aes_cra_init,
 773         .cra_exit               = omap_aes_cra_exit,
 774         .cra_u.ablkcipher = {
 775                 .min_keysize    = AES_MIN_KEY_SIZE,
 776                 .max_keysize    = AES_MAX_KEY_SIZE,
 777                 .ivsize         = AES_BLOCK_SIZE,
 778                 .setkey         = omap_aes_setkey,
 779                 .encrypt        = omap_aes_cbc_encrypt,
 780                 .decrypt        = omap_aes_cbc_decrypt,
 781         }
 782 }
 783 };
 784
 785 static struct crypto_alg algs_ctr[] = {
 786 {
 787         .cra_name               = "ctr(aes)",
 788         .cra_driver_name        = "ctr-aes-omap",
 789         .cra_priority           = 100,
 790         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 791                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 792                                   CRYPTO_ALG_ASYNC,
 793         .cra_blocksize          = AES_BLOCK_SIZE,
 794         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 795         .cra_alignmask          = 0,
 796         .cra_type               = &crypto_ablkcipher_type,
 797         .cra_module             = THIS_MODULE,
 798         .cra_init               = omap_aes_cra_init,
 799         .cra_exit               = omap_aes_cra_exit,
 800         .cra_u.ablkcipher = {
 801                 .min_keysize    = AES_MIN_KEY_SIZE,
 802                 .max_keysize    = AES_MAX_KEY_SIZE,
 803                 .geniv          = "eseqiv",
 804                 .ivsize         = AES_BLOCK_SIZE,
 805                 .setkey         = omap_aes_setkey,
 806                 .encrypt        = omap_aes_ctr_encrypt,
 807                 .decrypt        = omap_aes_ctr_decrypt,
 808         }
 809 } ,
 810 };
 811
 812 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
 813         {
 814                 .algs_list      = algs_ecb_cbc,
 815                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 816         },
 817 };
 818
 819 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
 820         .algs_info      = omap_aes_algs_info_ecb_cbc,
 821         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
 822         .trigger        = omap_aes_dma_trigger_omap2,
 823         .key_ofs        = 0x1c,
 824         .iv_ofs         = 0x20,
 825         .ctrl_ofs       = 0x30,
 826         .data_ofs       = 0x34,
 827         .rev_ofs        = 0x44,
 828         .mask_ofs       = 0x48,
 829         .dma_enable_in  = BIT(2),
 830         .dma_enable_out = BIT(3),
 831         .dma_start      = BIT(5),
 832         .major_mask     = 0xf0,
 833         .major_shift    = 4,
 834         .minor_mask     = 0x0f,
 835         .minor_shift    = 0,
 836 };
 837
 838 #ifdef CONFIG_OF
 839 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
 840         {
 841                 .algs_list      = algs_ecb_cbc,
 842                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 843         },
 844         {
 845                 .algs_list      = algs_ctr,
 846                 .size           = ARRAY_SIZE(algs_ctr),
 847         },
 848 };
 849
 850 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
 851         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 852         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 853         .trigger        = omap_aes_dma_trigger_omap2,
 854         .key_ofs        = 0x1c,
 855         .iv_ofs         = 0x20,
 856         .ctrl_ofs       = 0x30,
 857         .data_ofs       = 0x34,
 858         .rev_ofs        = 0x44,
 859         .mask_ofs       = 0x48,
 860         .dma_enable_in  = BIT(2),
 861         .dma_enable_out = BIT(3),
 862         .dma_start      = BIT(5),
 863         .major_mask     = 0xf0,
 864         .major_shift    = 4,
 865         .minor_mask     = 0x0f,
 866         .minor_shift    = 0,
 867 };
 868
 869 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
 870         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 871         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 872         .trigger        = omap_aes_dma_trigger_omap4,
 873         .key_ofs        = 0x3c,
 874         .iv_ofs         = 0x40,
 875         .ctrl_ofs       = 0x50,
 876         .data_ofs       = 0x60,
 877         .rev_ofs        = 0x80,
 878         .mask_ofs       = 0x84,
 879         .irq_status_ofs = 0x8c,
 880         .irq_enable_ofs = 0x90,
 881         .dma_enable_in  = BIT(5),
 882         .dma_enable_out = BIT(6),
 883         .major_mask     = 0x0700,
 884         .major_shift    = 8,
 885         .minor_mask     = 0x003f,
 886         .minor_shift    = 0,
 887 };
 888
 889 static irqreturn_t omap_aes_irq(int irq, void *dev_id)
 890 {
 891         struct omap_aes_dev *dd = dev_id;
 892         u32 status, i;
 893         u32 *src, *dst;
 894
 895         status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
 896         if (status & AES_REG_IRQ_DATA_IN) {
 897                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
 898
 899                 BUG_ON(!dd->in_sg);
 900
 901                 BUG_ON(_calc_walked(in) > dd->in_sg->length);
 902
 903                 src = sg_virt(dd->in_sg) + _calc_walked(in);
 904
 905                 for (i = 0; i < AES_BLOCK_WORDS; i++) {
 906                         omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
 907
 908                         scatterwalk_advance(&dd->in_walk, 4);
 909                         if (dd->in_sg->length == _calc_walked(in)) {
 910                                 dd->in_sg = scatterwalk_sg_next(dd->in_sg);
 911                                 if (dd->in_sg) {
 912                                         scatterwalk_start(&dd->in_walk,
 913                                                           dd->in_sg);
 914                                         src = sg_virt(dd->in_sg) +
 915                                               _calc_walked(in);
 916                                 }
 917                         } else {
 918                                 src++;
 919                         }
 920                 }
 921
 922                 /* Clear IRQ status */
 923                 status &= ~AES_REG_IRQ_DATA_IN;
 924                 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
 925
 926                 /* Enable DATA_OUT interrupt */
 927                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
 928
 929         } else if (status & AES_REG_IRQ_DATA_OUT) {
 930                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
 931
 932                 BUG_ON(!dd->out_sg);
 933
 934                 BUG_ON(_calc_walked(out) > dd->out_sg->length);
 935
 936                 dst = sg_virt(dd->out_sg) + _calc_walked(out);
 937
 938                 for (i = 0; i < AES_BLOCK_WORDS; i++) {
 939                         *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
 940                         scatterwalk_advance(&dd->out_walk, 4);
 941                         if (dd->out_sg->length == _calc_walked(out)) {
 942                                 dd->out_sg = scatterwalk_sg_next(dd->out_sg);
 943                                 if (dd->out_sg) {
 944                                         scatterwalk_start(&dd->out_walk,
 945                                                           dd->out_sg);
 946                                         dst = sg_virt(dd->out_sg) +
 947                                               _calc_walked(out);
 948                                 }
 949                         } else {
 950                                 dst++;
 951                         }
 952                 }
 953
 954                 dd->total -= AES_BLOCK_SIZE;
 955
 956                 BUG_ON(dd->total < 0);
 957
 958                 /* Clear IRQ status */
 959                 status &= ~AES_REG_IRQ_DATA_OUT;
 960                 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
 961
 962                 if (!dd->total)
 963                         /* All bytes read! */
 964                         tasklet_schedule(&dd->done_task);
 965                 else
 966                         /* Enable DATA_IN interrupt for next block */
 967                         omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
 968         }
 969
 970         return IRQ_HANDLED;
 971 }
 972
 973 static const struct of_device_id omap_aes_of_match[] = {
 974         {
 975                 .compatible     = "ti,omap2-aes",
 976                 .data           = &omap_aes_pdata_omap2,
 977         },
 978         {
 979                 .compatible     = "ti,omap3-aes",
 980                 .data           = &omap_aes_pdata_omap3,
 981         },
 982         {
 983                 .compatible     = "ti,omap4-aes",
 984                 .data           = &omap_aes_pdata_omap4,
 985         },
 986         {},
 987 };
 988 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
 989
 990 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
 991                 struct device *dev, struct resource *res)
 992 {
 993         struct device_node *node = dev->of_node;
 994         const struct of_device_id *match;
 995         int err = 0;
 996
 997         match = of_match_device(of_match_ptr(omap_aes_of_match), dev);
 998         if (!match) {
 999                 dev_err(dev, "no compatible OF match\n");
1000                 err = -EINVAL;
1001                 goto err;
1002         }
1003
1004         err = of_address_to_resource(node, 0, res);
1005         if (err < 0) {
1006                 dev_err(dev, "can't translate OF node address\n");
1007                 err = -EINVAL;
1008                 goto err;
1009         }
1010
1011         dd->dma_out = -1; /* Dummy value that's unused */
1012         dd->dma_in = -1; /* Dummy value that's unused */
1013
1014         dd->pdata = match->data;
1015
1016 err:
1017         return err;
1018 }
1019 #else
1020 static const struct of_device_id omap_aes_of_match[] = {
1021         {},
1022 };
1023
1024 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1025                 struct device *dev, struct resource *res)
1026 {
1027         return -EINVAL;
1028 }
1029 #endif
1030
1031 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
1032                 struct platform_device *pdev, struct resource *res)
1033 {
1034         struct device *dev = &pdev->dev;
1035         struct resource *r;
1036         int err = 0;
1037
1038         /* Get the base address */
1039         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1040         if (!r) {
1041                 dev_err(dev, "no MEM resource info\n");
1042                 err = -ENODEV;
1043                 goto err;
1044         }
1045         memcpy(res, r, sizeof(*res));
1046
1047         /* Get the DMA out channel */
1048         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1049         if (!r) {
1050                 dev_err(dev, "no DMA out resource info\n");
1051                 err = -ENODEV;
1052                 goto err;
1053         }
1054         dd->dma_out = r->start;
1055
1056         /* Get the DMA in channel */
1057         r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1058         if (!r) {
1059                 dev_err(dev, "no DMA in resource info\n");
1060                 err = -ENODEV;
1061                 goto err;
1062         }
1063         dd->dma_in = r->start;
1064
1065         /* Only OMAP2/3 can be non-DT */
1066         dd->pdata = &omap_aes_pdata_omap2;
1067
1068 err:
1069         return err;
1070 }
1071
1072 static int omap_aes_probe(struct platform_device *pdev)
1073 {
1074         struct device *dev = &pdev->dev;
1075         struct omap_aes_dev *dd;
1076         struct crypto_alg *algp;
1077         struct resource res;
1078         int err = -ENOMEM, i, j, irq = -1;
1079         u32 reg;
1080
1081         dd = kzalloc(sizeof(struct omap_aes_dev), GFP_KERNEL);
1082         if (dd == NULL) {
1083                 dev_err(dev, "unable to alloc data struct.\n");
1084                 goto err_data;
1085         }
1086         dd->dev = dev;
1087         platform_set_drvdata(pdev, dd);
1088
1089         spin_lock_init(&dd->lock);
1090         crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH);
1091
1092         err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1093                                omap_aes_get_res_pdev(dd, pdev, &res);
1094         if (err)
1095                 goto err_res;
1096
1097         dd->io_base = devm_ioremap_resource(dev, &res);
1098         if (IS_ERR(dd->io_base)) {
1099                 err = PTR_ERR(dd->io_base);
1100                 goto err_res;
1101         }
1102         dd->phys_base = res.start;
1103
1104         pm_runtime_enable(dev);
1105         pm_runtime_get_sync(dev);
1106
1107         omap_aes_dma_stop(dd);
1108
1109         reg = omap_aes_read(dd, AES_REG_REV(dd));
1110
1111         pm_runtime_put_sync(dev);
1112
1113         dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1114                  (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1115                  (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1116
1117         tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1118         tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd);
1119
1120         err = omap_aes_dma_init(dd);
1121         if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1122                 dd->pio_only = 1;
1123
1124                 irq = platform_get_irq(pdev, 0);
1125                 if (irq < 0) {
1126                         dev_err(dev, "can't get IRQ resource\n");
1127                         goto err_irq;
1128                 }
1129
1130                 err = request_irq(irq, omap_aes_irq, 0,
1131                                 dev_name(dev), dd);
1132                 if (err) {
1133                         dev_err(dev, "Unable to grab omap-aes IRQ\n");
1134                         goto err_irq;
1135                 }
1136         }
1137
1138
1139         INIT_LIST_HEAD(&dd->list);
1140         spin_lock(&list_lock);
1141         list_add_tail(&dd->list, &dev_list);
1142         spin_unlock(&list_lock);
1143
1144         for (i = 0; i < dd->pdata->algs_info_size; i++) {
1145                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1146                         algp = &dd->pdata->algs_info[i].algs_list[j];
1147
1148                         pr_debug("reg alg: %s\n", algp->cra_name);
1149                         INIT_LIST_HEAD(&algp->cra_list);
1150
1151                         err = crypto_register_alg(algp);
1152                         if (err)
1153                                 goto err_algs;
1154
1155                         dd->pdata->algs_info[i].registered++;
1156                 }
1157         }
1158
1159         return 0;
1160 err_algs:
1161         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1162                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1163                         crypto_unregister_alg(
1164                                         &dd->pdata->algs_info[i].algs_list[j]);
1165         if (dd->pio_only)
1166                 free_irq(irq, dd);
1167         else
1168                 omap_aes_dma_cleanup(dd);
1169 err_irq:
1170         tasklet_kill(&dd->done_task);
1171         tasklet_kill(&dd->queue_task);
1172         pm_runtime_disable(dev);
1173 err_res:
1174         kfree(dd);
1175         dd = NULL;
1176 err_data:
1177         dev_err(dev, "initialization failed.\n");
1178         return err;
1179 }
1180
1181 static int omap_aes_remove(struct platform_device *pdev)
1182 {
1183         struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1184         int i, j;
1185
1186         if (!dd)
1187                 return -ENODEV;
1188
1189         spin_lock(&list_lock);
1190         list_del(&dd->list);
1191         spin_unlock(&list_lock);
1192
1193         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1194                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1195                         crypto_unregister_alg(
1196                                         &dd->pdata->algs_info[i].algs_list[j]);
1197
1198         tasklet_kill(&dd->done_task);
1199         tasklet_kill(&dd->queue_task);
1200         omap_aes_dma_cleanup(dd);
1201         pm_runtime_disable(dd->dev);
1202         kfree(dd);
1203         dd = NULL;
1204
1205         return 0;
1206 }
1207
1208 #ifdef CONFIG_PM_SLEEP
1209 static int omap_aes_suspend(struct device *dev)
1210 {
1211         pm_runtime_put_sync(dev);
1212         return 0;
1213 }
1214
1215 static int omap_aes_resume(struct device *dev)
1216 {
1217         pm_runtime_get_sync(dev);
1218         return 0;
1219 }
1220 #endif
1221
1222 static const struct dev_pm_ops omap_aes_pm_ops = {
1223         SET_SYSTEM_SLEEP_PM_OPS(omap_aes_suspend, omap_aes_resume)
1224 };
1225
1226 static struct platform_driver omap_aes_driver = {
1227         .probe  = omap_aes_probe,
1228         .remove = omap_aes_remove,
1229         .driver = {
1230                 .name   = "omap-aes",
1231                 .owner  = THIS_MODULE,
1232                 .pm     = &omap_aes_pm_ops,
1233                 .of_match_table = omap_aes_of_match,
1234         },
1235 };
1236
1237 module_platform_driver(omap_aes_driver);
1238
1239 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1240 MODULE_LICENSE("GPL v2");
1241 MODULE_AUTHOR("Dmitry Kasatkin");
1242