drivers/crypto/omap-aes.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP AES HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  */
  15
  16 #define pr_fmt(fmt) "%20s: " fmt, __func__
  17 #define prn(num) pr_debug(#num "=%d\n", num)
  18 #define prx(num) pr_debug(#num "=%x\n", num)
  19
  20 #include <linux/err.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/kernel.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/scatterlist.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/omap-dma.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/of_address.h>
  34 #include <linux/io.h>
  35 #include <linux/crypto.h>
  36 #include <linux/interrupt.h>
  37 #include <crypto/scatterwalk.h>
  38 #include <crypto/aes.h>
  39
  40 #define DST_MAXBURST                    4
  41 #define DMA_MIN                         (DST_MAXBURST * sizeof(u32))
  42
  43 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  44    number. For example 7:0 */
  45 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  46 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  47
  48 #define AES_REG_KEY(dd, x)              ((dd)->pdata->key_ofs - \
  49                                                 ((x ^ 0x01) * 0x04))
  50 #define AES_REG_IV(dd, x)               ((dd)->pdata->iv_ofs + ((x) * 0x04))
  51
  52 #define AES_REG_CTRL(dd)                ((dd)->pdata->ctrl_ofs)
  53 #define AES_REG_CTRL_CTR_WIDTH_MASK     (3 << 7)
  54 #define AES_REG_CTRL_CTR_WIDTH_32               (0 << 7)
  55 #define AES_REG_CTRL_CTR_WIDTH_64               (1 << 7)
  56 #define AES_REG_CTRL_CTR_WIDTH_96               (2 << 7)
  57 #define AES_REG_CTRL_CTR_WIDTH_128              (3 << 7)
  58 #define AES_REG_CTRL_CTR                (1 << 6)
  59 #define AES_REG_CTRL_CBC                (1 << 5)
  60 #define AES_REG_CTRL_KEY_SIZE           (3 << 3)
  61 #define AES_REG_CTRL_DIRECTION          (1 << 2)
  62 #define AES_REG_CTRL_INPUT_READY        (1 << 1)
  63 #define AES_REG_CTRL_OUTPUT_READY       (1 << 0)
  64
  65 #define AES_REG_DATA_N(dd, x)           ((dd)->pdata->data_ofs + ((x) * 0x04))
  66
  67 #define AES_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  68
  69 #define AES_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  70 #define AES_REG_MASK_SIDLE              (1 << 6)
  71 #define AES_REG_MASK_START              (1 << 5)
  72 #define AES_REG_MASK_DMA_OUT_EN         (1 << 3)
  73 #define AES_REG_MASK_DMA_IN_EN          (1 << 2)
  74 #define AES_REG_MASK_SOFTRESET          (1 << 1)
  75 #define AES_REG_AUTOIDLE                (1 << 0)
  76
  77 #define AES_REG_LENGTH_N(x)             (0x54 + ((x) * 0x04))
  78
  79 #define DEFAULT_TIMEOUT         (5*HZ)
  80
  81 #define FLAGS_MODE_MASK         0x000f
  82 #define FLAGS_ENCRYPT           BIT(0)
  83 #define FLAGS_CBC               BIT(1)
  84 #define FLAGS_GIV               BIT(2)
  85 #define FLAGS_CTR               BIT(3)
  86
  87 #define FLAGS_INIT              BIT(4)
  88 #define FLAGS_FAST              BIT(5)
  89 #define FLAGS_BUSY              BIT(6)
  90
  91 struct omap_aes_ctx {
  92         struct omap_aes_dev *dd;
  93
  94         int             keylen;
  95         u32             key[AES_KEYSIZE_256 / sizeof(u32)];
  96         unsigned long   flags;
  97 };
  98
  99 struct omap_aes_reqctx {
 100         unsigned long mode;
 101 };
 102
 103 #define OMAP_AES_QUEUE_LENGTH   1
 104 #define OMAP_AES_CACHE_SIZE     0
 105
 106 struct omap_aes_algs_info {
 107         struct crypto_alg       *algs_list;
 108         unsigned int            size;
 109         unsigned int            registered;
 110 };
 111
 112 struct omap_aes_pdata {
 113         struct omap_aes_algs_info       *algs_info;
 114         unsigned int    algs_info_size;
 115
 116         void            (*trigger)(struct omap_aes_dev *dd, int length);
 117
 118         u32             key_ofs;
 119         u32             iv_ofs;
 120         u32             ctrl_ofs;
 121         u32             data_ofs;
 122         u32             rev_ofs;
 123         u32             mask_ofs;
 124
 125         u32             dma_enable_in;
 126         u32             dma_enable_out;
 127         u32             dma_start;
 128
 129         u32             major_mask;
 130         u32             major_shift;
 131         u32             minor_mask;
 132         u32             minor_shift;
 133 };
 134
 135 struct omap_aes_dev {
 136         struct list_head        list;
 137         unsigned long           phys_base;
 138         void __iomem            *io_base;
 139         struct omap_aes_ctx     *ctx;
 140         struct device           *dev;
 141         unsigned long           flags;
 142         int                     err;
 143
 144         spinlock_t              lock;
 145         struct crypto_queue     queue;
 146
 147         struct tasklet_struct   done_task;
 148         struct tasklet_struct   queue_task;
 149
 150         struct ablkcipher_request       *req;
 151         size_t                          total;
 152         struct scatterlist              *in_sg;
 153         struct scatterlist              *out_sg;
 154         int                     dma_in;
 155         struct dma_chan         *dma_lch_in;
 156         int                     dma_out;
 157         struct dma_chan         *dma_lch_out;
 158         int                     in_sg_len;
 159         int                     out_sg_len;
 160         const struct omap_aes_pdata     *pdata;
 161 };
 162
 163 /* keep registered devices data here */
 164 static LIST_HEAD(dev_list);
 165 static DEFINE_SPINLOCK(list_lock);
 166
 167 #ifdef DEBUG
 168 #define omap_aes_read(dd, offset)                               \
 169 ({                                                              \
 170         int _read_ret;                                          \
 171         _read_ret = __raw_readl(dd->io_base + offset);          \
 172         pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n",       \
 173                  offset, _read_ret);                            \
 174         _read_ret;                                              \
 175 })
 176 #else
 177 static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
 178 {
 179         return __raw_readl(dd->io_base + offset);
 180 }
 181 #endif
 182
 183 #ifdef DEBUG
 184 #define omap_aes_write(dd, offset, value)                               \
 185         do {                                                            \
 186                 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
 187                          offset, value);                                \
 188                 __raw_writel(value, dd->io_base + offset);              \
 189         } while (0)
 190 #else
 191 static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
 192                                   u32 value)
 193 {
 194         __raw_writel(value, dd->io_base + offset);
 195 }
 196 #endif
 197
 198 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
 199                                         u32 value, u32 mask)
 200 {
 201         u32 val;
 202
 203         val = omap_aes_read(dd, offset);
 204         val &= ~mask;
 205         val |= value;
 206         omap_aes_write(dd, offset, val);
 207 }
 208
 209 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
 210                                         u32 *value, int count)
 211 {
 212         for (; count--; value++, offset += 4)
 213                 omap_aes_write(dd, offset, *value);
 214 }
 215
 216 static int omap_aes_hw_init(struct omap_aes_dev *dd)
 217 {
 218         if (!(dd->flags & FLAGS_INIT)) {
 219                 dd->flags |= FLAGS_INIT;
 220                 dd->err = 0;
 221         }
 222
 223         return 0;
 224 }
 225
 226 static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
 227 {
 228         unsigned int key32;
 229         int i, err;
 230         u32 val, mask = 0;
 231
 232         err = omap_aes_hw_init(dd);
 233         if (err)
 234                 return err;
 235
 236         key32 = dd->ctx->keylen / sizeof(u32);
 237
 238         /* it seems a key should always be set even if it has not changed */
 239         for (i = 0; i < key32; i++) {
 240                 omap_aes_write(dd, AES_REG_KEY(dd, i),
 241                         __le32_to_cpu(dd->ctx->key[i]));
 242         }
 243
 244         if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
 245                 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
 246
 247         val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
 248         if (dd->flags & FLAGS_CBC)
 249                 val |= AES_REG_CTRL_CBC;
 250         if (dd->flags & FLAGS_CTR) {
 251                 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_32;
 252                 mask = AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_MASK;
 253         }
 254         if (dd->flags & FLAGS_ENCRYPT)
 255                 val |= AES_REG_CTRL_DIRECTION;
 256
 257         mask |= AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION |
 258                         AES_REG_CTRL_KEY_SIZE;
 259
 260         omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, mask);
 261
 262         return 0;
 263 }
 264
 265 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
 266 {
 267         u32 mask, val;
 268
 269         val = dd->pdata->dma_start;
 270
 271         if (dd->dma_lch_out != NULL)
 272                 val |= dd->pdata->dma_enable_out;
 273         if (dd->dma_lch_in != NULL)
 274                 val |= dd->pdata->dma_enable_in;
 275
 276         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 277                dd->pdata->dma_start;
 278
 279         omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
 280
 281 }
 282
 283 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
 284 {
 285         omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
 286         omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
 287
 288         omap_aes_dma_trigger_omap2(dd, length);
 289 }
 290
 291 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
 292 {
 293         u32 mask;
 294
 295         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 296                dd->pdata->dma_start;
 297
 298         omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
 299 }
 300
 301 static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
 302 {
 303         struct omap_aes_dev *dd = NULL, *tmp;
 304
 305         spin_lock_bh(&list_lock);
 306         if (!ctx->dd) {
 307                 list_for_each_entry(tmp, &dev_list, list) {
 308                         /* FIXME: take fist available aes core */
 309                         dd = tmp;
 310                         break;
 311                 }
 312                 ctx->dd = dd;
 313         } else {
 314                 /* already found before */
 315                 dd = ctx->dd;
 316         }
 317         spin_unlock_bh(&list_lock);
 318
 319         return dd;
 320 }
 321
 322 static void omap_aes_dma_out_callback(void *data)
 323 {
 324         struct omap_aes_dev *dd = data;
 325
 326         /* dma_lch_out - completed */
 327         tasklet_schedule(&dd->done_task);
 328 }
 329
 330 static int omap_aes_dma_init(struct omap_aes_dev *dd)
 331 {
 332         int err = -ENOMEM;
 333         dma_cap_mask_t mask;
 334
 335         dd->dma_lch_out = NULL;
 336         dd->dma_lch_in = NULL;
 337
 338         dma_cap_zero(mask);
 339         dma_cap_set(DMA_SLAVE, mask);
 340
 341         dd->dma_lch_in = dma_request_slave_channel_compat(mask,
 342                                                           omap_dma_filter_fn,
 343                                                           &dd->dma_in,
 344                                                           dd->dev, "rx");
 345         if (!dd->dma_lch_in) {
 346                 dev_err(dd->dev, "Unable to request in DMA channel\n");
 347                 goto err_dma_in;
 348         }
 349
 350         dd->dma_lch_out = dma_request_slave_channel_compat(mask,
 351                                                            omap_dma_filter_fn,
 352                                                            &dd->dma_out,
 353                                                            dd->dev, "tx");
 354         if (!dd->dma_lch_out) {
 355                 dev_err(dd->dev, "Unable to request out DMA channel\n");
 356                 goto err_dma_out;
 357         }
 358
 359         return 0;
 360
 361 err_dma_out:
 362         dma_release_channel(dd->dma_lch_in);
 363 err_dma_in:
 364         if (err)
 365                 pr_err("error: %d\n", err);
 366         return err;
 367 }
 368
 369 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
 370 {
 371         dma_release_channel(dd->dma_lch_out);
 372         dma_release_channel(dd->dma_lch_in);
 373 }
 374
 375 static void sg_copy_buf(void *buf, struct scatterlist *sg,
 376                               unsigned int start, unsigned int nbytes, int out)
 377 {
 378         struct scatter_walk walk;
 379
 380         if (!nbytes)
 381                 return;
 382
 383         scatterwalk_start(&walk, sg);
 384         scatterwalk_advance(&walk, start);
 385         scatterwalk_copychunks(buf, &walk, nbytes, out);
 386         scatterwalk_done(&walk, out, 0);
 387 }
 388
 389 static int omap_aes_crypt_dma(struct crypto_tfm *tfm,
 390                 struct scatterlist *in_sg, struct scatterlist *out_sg,
 391                 int in_sg_len, int out_sg_len)
 392 {
 393         struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
 394         struct omap_aes_dev *dd = ctx->dd;
 395         struct dma_async_tx_descriptor *tx_in, *tx_out;
 396         struct dma_slave_config cfg;
 397         int ret;
 398
 399         dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
 400
 401         memset(&cfg, 0, sizeof(cfg));
 402
 403         cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 404         cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 405         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 406         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 407         cfg.src_maxburst = DST_MAXBURST;
 408         cfg.dst_maxburst = DST_MAXBURST;
 409
 410         /* IN */
 411         ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
 412         if (ret) {
 413                 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
 414                         ret);
 415                 return ret;
 416         }
 417
 418         tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
 419                                         DMA_MEM_TO_DEV,
 420                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 421         if (!tx_in) {
 422                 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
 423                 return -EINVAL;
 424         }
 425
 426         /* No callback necessary */
 427         tx_in->callback_param = dd;
 428
 429         /* OUT */
 430         ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
 431         if (ret) {
 432                 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
 433                         ret);
 434                 return ret;
 435         }
 436
 437         tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
 438                                         DMA_DEV_TO_MEM,
 439                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 440         if (!tx_out) {
 441                 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
 442                 return -EINVAL;
 443         }
 444
 445         tx_out->callback = omap_aes_dma_out_callback;
 446         tx_out->callback_param = dd;
 447
 448         dmaengine_submit(tx_in);
 449         dmaengine_submit(tx_out);
 450
 451         dma_async_issue_pending(dd->dma_lch_in);
 452         dma_async_issue_pending(dd->dma_lch_out);
 453
 454         /* start DMA */
 455         dd->pdata->trigger(dd, dd->total);
 456
 457         return 0;
 458 }
 459
 460 static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
 461 {
 462         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
 463                                         crypto_ablkcipher_reqtfm(dd->req));
 464         int err;
 465
 466         pr_debug("total: %d\n", dd->total);
 467
 468         err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 469         if (!err) {
 470                 dev_err(dd->dev, "dma_map_sg() error\n");
 471                 return -EINVAL;
 472         }
 473
 474         err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, DMA_FROM_DEVICE);
 475         if (!err) {
 476                 dev_err(dd->dev, "dma_map_sg() error\n");
 477                 return -EINVAL;
 478         }
 479
 480         err = omap_aes_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
 481                                  dd->out_sg_len);
 482         if (err) {
 483                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 484                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 485                              DMA_FROM_DEVICE);
 486         }
 487
 488         return err;
 489 }
 490
 491 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
 492 {
 493         struct ablkcipher_request *req = dd->req;
 494
 495         pr_debug("err: %d\n", err);
 496
 497         dd->flags &= ~FLAGS_BUSY;
 498
 499         req->base.complete(&req->base, err);
 500 }
 501
 502 static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
 503 {
 504         int err = 0;
 505
 506         pr_debug("total: %d\n", dd->total);
 507
 508         omap_aes_dma_stop(dd);
 509
 510         dmaengine_terminate_all(dd->dma_lch_in);
 511         dmaengine_terminate_all(dd->dma_lch_out);
 512
 513         dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 514         dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, DMA_FROM_DEVICE);
 515
 516         return err;
 517 }
 518
 519 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
 520                                struct ablkcipher_request *req)
 521 {
 522         struct crypto_async_request *async_req, *backlog;
 523         struct omap_aes_ctx *ctx;
 524         struct omap_aes_reqctx *rctx;
 525         unsigned long flags;
 526         int err, ret = 0;
 527
 528         spin_lock_irqsave(&dd->lock, flags);
 529         if (req)
 530                 ret = ablkcipher_enqueue_request(&dd->queue, req);
 531         if (dd->flags & FLAGS_BUSY) {
 532                 spin_unlock_irqrestore(&dd->lock, flags);
 533                 return ret;
 534         }
 535         backlog = crypto_get_backlog(&dd->queue);
 536         async_req = crypto_dequeue_request(&dd->queue);
 537         if (async_req)
 538                 dd->flags |= FLAGS_BUSY;
 539         spin_unlock_irqrestore(&dd->lock, flags);
 540
 541         if (!async_req)
 542                 return ret;
 543
 544         if (backlog)
 545                 backlog->complete(backlog, -EINPROGRESS);
 546
 547         req = ablkcipher_request_cast(async_req);
 548
 549         /* assign new request to device */
 550         dd->req = req;
 551         dd->total = req->nbytes;
 552         dd->in_sg = req->src;
 553         dd->out_sg = req->dst;
 554
 555         dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, dd->total);
 556         dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, dd->total);
 557         BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0);
 558
 559         rctx = ablkcipher_request_ctx(req);
 560         ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
 561         rctx->mode &= FLAGS_MODE_MASK;
 562         dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
 563
 564         dd->ctx = ctx;
 565         ctx->dd = dd;
 566
 567         err = omap_aes_write_ctrl(dd);
 568         if (!err)
 569                 err = omap_aes_crypt_dma_start(dd);
 570         if (err) {
 571                 /* aes_task will not finish it, so do it here */
 572                 omap_aes_finish_req(dd, err);
 573                 tasklet_schedule(&dd->queue_task);
 574         }
 575
 576         return ret; /* return ret, which is enqueue return value */
 577 }
 578
 579 static void omap_aes_done_task(unsigned long data)
 580 {
 581         struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
 582
 583         pr_debug("enter done_task\n");
 584
 585         dma_sync_sg_for_cpu(dd->dev, dd->in_sg, dd->in_sg_len, DMA_FROM_DEVICE);
 586
 587         omap_aes_crypt_dma_stop(dd);
 588         omap_aes_finish_req(dd, 0);
 589         omap_aes_handle_queue(dd, NULL);
 590
 591         pr_debug("exit\n");
 592 }
 593
 594 static void omap_aes_queue_task(unsigned long data)
 595 {
 596         struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
 597
 598         omap_aes_handle_queue(dd, NULL);
 599 }
 600
 601 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
 602 {
 603         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
 604                         crypto_ablkcipher_reqtfm(req));
 605         struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
 606         struct omap_aes_dev *dd;
 607
 608         pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
 609                   !!(mode & FLAGS_ENCRYPT),
 610                   !!(mode & FLAGS_CBC));
 611
 612         if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
 613                 pr_err("request size is not exact amount of AES blocks\n");
 614                 return -EINVAL;
 615         }
 616
 617         dd = omap_aes_find_dev(ctx);
 618         if (!dd)
 619                 return -ENODEV;
 620
 621         rctx->mode = mode;
 622
 623         return omap_aes_handle_queue(dd, req);
 624 }
 625
 626 /* ********************** ALG API ************************************ */
 627
 628 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 629                            unsigned int keylen)
 630 {
 631         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 632
 633         if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
 634                    keylen != AES_KEYSIZE_256)
 635                 return -EINVAL;
 636
 637         pr_debug("enter, keylen: %d\n", keylen);
 638
 639         memcpy(ctx->key, key, keylen);
 640         ctx->keylen = keylen;
 641
 642         return 0;
 643 }
 644
 645 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
 646 {
 647         return omap_aes_crypt(req, FLAGS_ENCRYPT);
 648 }
 649
 650 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
 651 {
 652         return omap_aes_crypt(req, 0);
 653 }
 654
 655 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
 656 {
 657         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
 658 }
 659
 660 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
 661 {
 662         return omap_aes_crypt(req, FLAGS_CBC);
 663 }
 664
 665 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
 666 {
 667         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
 668 }
 669
 670 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
 671 {
 672         return omap_aes_crypt(req, FLAGS_CTR);
 673 }
 674
 675 static int omap_aes_cra_init(struct crypto_tfm *tfm)
 676 {
 677         struct omap_aes_dev *dd = NULL;
 678
 679         /* Find AES device, currently picks the first device */
 680         spin_lock_bh(&list_lock);
 681         list_for_each_entry(dd, &dev_list, list) {
 682                 break;
 683         }
 684         spin_unlock_bh(&list_lock);
 685
 686         pm_runtime_get_sync(dd->dev);
 687         tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
 688
 689         return 0;
 690 }
 691
 692 static void omap_aes_cra_exit(struct crypto_tfm *tfm)
 693 {
 694         struct omap_aes_dev *dd = NULL;
 695
 696         /* Find AES device, currently picks the first device */
 697         spin_lock_bh(&list_lock);
 698         list_for_each_entry(dd, &dev_list, list) {
 699                 break;
 700         }
 701         spin_unlock_bh(&list_lock);
 702
 703         pm_runtime_put_sync(dd->dev);
 704 }
 705
 706 /* ********************** ALGS ************************************ */
 707
 708 static struct crypto_alg algs_ecb_cbc[] = {
 709 {
 710         .cra_name               = "ecb(aes)",
 711         .cra_driver_name        = "ecb-aes-omap",
 712         .cra_priority           = 100,
 713         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 714                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 715                                   CRYPTO_ALG_ASYNC,
 716         .cra_blocksize          = AES_BLOCK_SIZE,
 717         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 718         .cra_alignmask          = 0,
 719         .cra_type               = &crypto_ablkcipher_type,
 720         .cra_module             = THIS_MODULE,
 721         .cra_init               = omap_aes_cra_init,
 722         .cra_exit               = omap_aes_cra_exit,
 723         .cra_u.ablkcipher = {
 724                 .min_keysize    = AES_MIN_KEY_SIZE,
 725                 .max_keysize    = AES_MAX_KEY_SIZE,
 726                 .setkey         = omap_aes_setkey,
 727                 .encrypt        = omap_aes_ecb_encrypt,
 728                 .decrypt        = omap_aes_ecb_decrypt,
 729         }
 730 },
 731 {
 732         .cra_name               = "cbc(aes)",
 733         .cra_driver_name        = "cbc-aes-omap",
 734         .cra_priority           = 100,
 735         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 736                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 737                                   CRYPTO_ALG_ASYNC,
 738         .cra_blocksize          = AES_BLOCK_SIZE,
 739         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 740         .cra_alignmask          = 0,
 741         .cra_type               = &crypto_ablkcipher_type,
 742         .cra_module             = THIS_MODULE,
 743         .cra_init               = omap_aes_cra_init,
 744         .cra_exit               = omap_aes_cra_exit,
 745         .cra_u.ablkcipher = {
 746                 .min_keysize    = AES_MIN_KEY_SIZE,
 747                 .max_keysize    = AES_MAX_KEY_SIZE,
 748                 .ivsize         = AES_BLOCK_SIZE,
 749                 .setkey         = omap_aes_setkey,
 750                 .encrypt        = omap_aes_cbc_encrypt,
 751                 .decrypt        = omap_aes_cbc_decrypt,
 752         }
 753 }
 754 };
 755
 756 static struct crypto_alg algs_ctr[] = {
 757 {
 758         .cra_name               = "ctr(aes)",
 759         .cra_driver_name        = "ctr-aes-omap",
 760         .cra_priority           = 100,
 761         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 762                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 763                                   CRYPTO_ALG_ASYNC,
 764         .cra_blocksize          = AES_BLOCK_SIZE,
 765         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 766         .cra_alignmask          = 0,
 767         .cra_type               = &crypto_ablkcipher_type,
 768         .cra_module             = THIS_MODULE,
 769         .cra_init               = omap_aes_cra_init,
 770         .cra_exit               = omap_aes_cra_exit,
 771         .cra_u.ablkcipher = {
 772                 .min_keysize    = AES_MIN_KEY_SIZE,
 773                 .max_keysize    = AES_MAX_KEY_SIZE,
 774                 .geniv          = "eseqiv",
 775                 .ivsize         = AES_BLOCK_SIZE,
 776                 .setkey         = omap_aes_setkey,
 777                 .encrypt        = omap_aes_ctr_encrypt,
 778                 .decrypt        = omap_aes_ctr_decrypt,
 779         }
 780 } ,
 781 };
 782
 783 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
 784         {
 785                 .algs_list      = algs_ecb_cbc,
 786                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 787         },
 788 };
 789
 790 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
 791         .algs_info      = omap_aes_algs_info_ecb_cbc,
 792         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
 793         .trigger        = omap_aes_dma_trigger_omap2,
 794         .key_ofs        = 0x1c,
 795         .iv_ofs         = 0x20,
 796         .ctrl_ofs       = 0x30,
 797         .data_ofs       = 0x34,
 798         .rev_ofs        = 0x44,
 799         .mask_ofs       = 0x48,
 800         .dma_enable_in  = BIT(2),
 801         .dma_enable_out = BIT(3),
 802         .dma_start      = BIT(5),
 803         .major_mask     = 0xf0,
 804         .major_shift    = 4,
 805         .minor_mask     = 0x0f,
 806         .minor_shift    = 0,
 807 };
 808
 809 #ifdef CONFIG_OF
 810 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
 811         {
 812                 .algs_list      = algs_ecb_cbc,
 813                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 814         },
 815         {
 816                 .algs_list      = algs_ctr,
 817                 .size           = ARRAY_SIZE(algs_ctr),
 818         },
 819 };
 820
 821 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
 822         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 823         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 824         .trigger        = omap_aes_dma_trigger_omap2,
 825         .key_ofs        = 0x1c,
 826         .iv_ofs         = 0x20,
 827         .ctrl_ofs       = 0x30,
 828         .data_ofs       = 0x34,
 829         .rev_ofs        = 0x44,
 830         .mask_ofs       = 0x48,
 831         .dma_enable_in  = BIT(2),
 832         .dma_enable_out = BIT(3),
 833         .dma_start      = BIT(5),
 834         .major_mask     = 0xf0,
 835         .major_shift    = 4,
 836         .minor_mask     = 0x0f,
 837         .minor_shift    = 0,
 838 };
 839
 840 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
 841         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 842         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 843         .trigger        = omap_aes_dma_trigger_omap4,
 844         .key_ofs        = 0x3c,
 845         .iv_ofs         = 0x40,
 846         .ctrl_ofs       = 0x50,
 847         .data_ofs       = 0x60,
 848         .rev_ofs        = 0x80,
 849         .mask_ofs       = 0x84,
 850         .dma_enable_in  = BIT(5),
 851         .dma_enable_out = BIT(6),
 852         .major_mask     = 0x0700,
 853         .major_shift    = 8,
 854         .minor_mask     = 0x003f,
 855         .minor_shift    = 0,
 856 };
 857
 858 static const struct of_device_id omap_aes_of_match[] = {
 859         {
 860                 .compatible     = "ti,omap2-aes",
 861                 .data           = &omap_aes_pdata_omap2,
 862         },
 863         {
 864                 .compatible     = "ti,omap3-aes",
 865                 .data           = &omap_aes_pdata_omap3,
 866         },
 867         {
 868                 .compatible     = "ti,omap4-aes",
 869                 .data           = &omap_aes_pdata_omap4,
 870         },
 871         {},
 872 };
 873 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
 874
 875 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
 876                 struct device *dev, struct resource *res)
 877 {
 878         struct device_node *node = dev->of_node;
 879         const struct of_device_id *match;
 880         int err = 0;
 881
 882         match = of_match_device(of_match_ptr(omap_aes_of_match), dev);
 883         if (!match) {
 884                 dev_err(dev, "no compatible OF match\n");
 885                 err = -EINVAL;
 886                 goto err;
 887         }
 888
 889         err = of_address_to_resource(node, 0, res);
 890         if (err < 0) {
 891                 dev_err(dev, "can't translate OF node address\n");
 892                 err = -EINVAL;
 893                 goto err;
 894         }
 895
 896         dd->dma_out = -1; /* Dummy value that's unused */
 897         dd->dma_in = -1; /* Dummy value that's unused */
 898
 899         dd->pdata = match->data;
 900
 901 err:
 902         return err;
 903 }
 904 #else
 905 static const struct of_device_id omap_aes_of_match[] = {
 906         {},
 907 };
 908
 909 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
 910                 struct device *dev, struct resource *res)
 911 {
 912         return -EINVAL;
 913 }
 914 #endif
 915
 916 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
 917                 struct platform_device *pdev, struct resource *res)
 918 {
 919         struct device *dev = &pdev->dev;
 920         struct resource *r;
 921         int err = 0;
 922
 923         /* Get the base address */
 924         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 925         if (!r) {
 926                 dev_err(dev, "no MEM resource info\n");
 927                 err = -ENODEV;
 928                 goto err;
 929         }
 930         memcpy(res, r, sizeof(*res));
 931
 932         /* Get the DMA out channel */
 933         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 934         if (!r) {
 935                 dev_err(dev, "no DMA out resource info\n");
 936                 err = -ENODEV;
 937                 goto err;
 938         }
 939         dd->dma_out = r->start;
 940
 941         /* Get the DMA in channel */
 942         r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 943         if (!r) {
 944                 dev_err(dev, "no DMA in resource info\n");
 945                 err = -ENODEV;
 946                 goto err;
 947         }
 948         dd->dma_in = r->start;
 949
 950         /* Only OMAP2/3 can be non-DT */
 951         dd->pdata = &omap_aes_pdata_omap2;
 952
 953 err:
 954         return err;
 955 }
 956
 957 static int omap_aes_probe(struct platform_device *pdev)
 958 {
 959         struct device *dev = &pdev->dev;
 960         struct omap_aes_dev *dd;
 961         struct crypto_alg *algp;
 962         struct resource res;
 963         int err = -ENOMEM, i, j;
 964         u32 reg;
 965
 966         dd = kzalloc(sizeof(struct omap_aes_dev), GFP_KERNEL);
 967         if (dd == NULL) {
 968                 dev_err(dev, "unable to alloc data struct.\n");
 969                 goto err_data;
 970         }
 971         dd->dev = dev;
 972         platform_set_drvdata(pdev, dd);
 973
 974         spin_lock_init(&dd->lock);
 975         crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH);
 976
 977         err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
 978                                omap_aes_get_res_pdev(dd, pdev, &res);
 979         if (err)
 980                 goto err_res;
 981
 982         dd->io_base = devm_ioremap_resource(dev, &res);
 983         if (IS_ERR(dd->io_base)) {
 984                 err = PTR_ERR(dd->io_base);
 985                 goto err_res;
 986         }
 987         dd->phys_base = res.start;
 988
 989         pm_runtime_enable(dev);
 990         pm_runtime_get_sync(dev);
 991
 992         omap_aes_dma_stop(dd);
 993
 994         reg = omap_aes_read(dd, AES_REG_REV(dd));
 995
 996         pm_runtime_put_sync(dev);
 997
 998         dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
 999                  (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1000                  (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1001
1002         tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1003         tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd);
1004
1005         err = omap_aes_dma_init(dd);
1006         if (err)
1007                 goto err_dma;
1008
1009         INIT_LIST_HEAD(&dd->list);
1010         spin_lock(&list_lock);
1011         list_add_tail(&dd->list, &dev_list);
1012         spin_unlock(&list_lock);
1013
1014         for (i = 0; i < dd->pdata->algs_info_size; i++) {
1015                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1016                         algp = &dd->pdata->algs_info[i].algs_list[j];
1017
1018                         pr_debug("reg alg: %s\n", algp->cra_name);
1019                         INIT_LIST_HEAD(&algp->cra_list);
1020
1021                         err = crypto_register_alg(algp);
1022                         if (err)
1023                                 goto err_algs;
1024
1025                         dd->pdata->algs_info[i].registered++;
1026                 }
1027         }
1028
1029         return 0;
1030 err_algs:
1031         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1032                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1033                         crypto_unregister_alg(
1034                                         &dd->pdata->algs_info[i].algs_list[j]);
1035         omap_aes_dma_cleanup(dd);
1036 err_dma:
1037         tasklet_kill(&dd->done_task);
1038         tasklet_kill(&dd->queue_task);
1039         pm_runtime_disable(dev);
1040 err_res:
1041         kfree(dd);
1042         dd = NULL;
1043 err_data:
1044         dev_err(dev, "initialization failed.\n");
1045         return err;
1046 }
1047
1048 static int omap_aes_remove(struct platform_device *pdev)
1049 {
1050         struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1051         int i, j;
1052
1053         if (!dd)
1054                 return -ENODEV;
1055
1056         spin_lock(&list_lock);
1057         list_del(&dd->list);
1058         spin_unlock(&list_lock);
1059
1060         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1061                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1062                         crypto_unregister_alg(
1063                                         &dd->pdata->algs_info[i].algs_list[j]);
1064
1065         tasklet_kill(&dd->done_task);
1066         tasklet_kill(&dd->queue_task);
1067         omap_aes_dma_cleanup(dd);
1068         pm_runtime_disable(dd->dev);
1069         kfree(dd);
1070         dd = NULL;
1071
1072         return 0;
1073 }
1074
1075 #ifdef CONFIG_PM_SLEEP
1076 static int omap_aes_suspend(struct device *dev)
1077 {
1078         pm_runtime_put_sync(dev);
1079         return 0;
1080 }
1081
1082 static int omap_aes_resume(struct device *dev)
1083 {
1084         pm_runtime_get_sync(dev);
1085         return 0;
1086 }
1087 #endif
1088
1089 static const struct dev_pm_ops omap_aes_pm_ops = {
1090         SET_SYSTEM_SLEEP_PM_OPS(omap_aes_suspend, omap_aes_resume)
1091 };
1092
1093 static struct platform_driver omap_aes_driver = {
1094         .probe  = omap_aes_probe,
1095         .remove = omap_aes_remove,
1096         .driver = {
1097                 .name   = "omap-aes",
1098                 .owner  = THIS_MODULE,
1099                 .pm     = &omap_aes_pm_ops,
1100                 .of_match_table = omap_aes_of_match,
1101         },
1102 };
1103
1104 module_platform_driver(omap_aes_driver);
1105
1106 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1107 MODULE_LICENSE("GPL v2");
1108 MODULE_AUTHOR("Dmitry Kasatkin");
1109