4 * Support for OMAP SHA1/MD5 HW acceleration.
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 * Copyright (c) 2011 Texas Instruments Incorporated
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
14 * Some ideas are from old omap-sha1-md5.c driver.
17 #define pr_fmt(fmt) "%s: " fmt, __func__
19 #include <linux/err.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/irq.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/of_address.h>
36 #include <linux/of_irq.h>
37 #include <linux/delay.h>
38 #include <linux/crypto.h>
39 #include <linux/cryptohash.h>
40 #include <crypto/scatterwalk.h>
41 #include <crypto/algapi.h>
42 #include <crypto/sha.h>
43 #include <crypto/hash.h>
44 #include <crypto/internal/hash.h>
46 #define MD5_DIGEST_SIZE 16
48 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
49 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
50 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
52 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
54 #define SHA_REG_CTRL 0x18
55 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
56 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
57 #define SHA_REG_CTRL_ALGO_CONST (1 << 3)
58 #define SHA_REG_CTRL_ALGO (1 << 2)
59 #define SHA_REG_CTRL_INPUT_READY (1 << 1)
60 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
62 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
64 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
65 #define SHA_REG_MASK_DMA_EN (1 << 3)
66 #define SHA_REG_MASK_IT_EN (1 << 2)
67 #define SHA_REG_MASK_SOFTRESET (1 << 1)
68 #define SHA_REG_AUTOIDLE (1 << 0)
70 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
71 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
73 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
74 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
75 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
76 #define SHA_REG_MODE_CLOSE_HASH (1 << 4)
77 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
79 #define SHA_REG_MODE_ALGO_MASK (7 << 0)
80 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
81 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
82 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
83 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
84 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
85 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
87 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
89 #define SHA_REG_IRQSTATUS 0x118
90 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
91 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
92 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
93 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
95 #define SHA_REG_IRQENA 0x11C
96 #define SHA_REG_IRQENA_CTX_RDY (1 << 3)
97 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
98 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
99 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
101 #define DEFAULT_TIMEOUT_INTERVAL HZ
103 #define DEFAULT_AUTOSUSPEND_DELAY 1000
105 /* mostly device flags */
107 #define FLAGS_FINAL 1
108 #define FLAGS_DMA_ACTIVE 2
109 #define FLAGS_OUTPUT_READY 3
112 #define FLAGS_DMA_READY 6
113 #define FLAGS_AUTO_XOR 7
114 #define FLAGS_BE32_SHA1 8
115 #define FLAGS_SGS_COPIED 9
116 #define FLAGS_SGS_ALLOCED 10
118 #define FLAGS_FINUP 16
121 #define FLAGS_MODE_SHIFT 18
122 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
123 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
124 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
125 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
126 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
127 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
128 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
130 #define FLAGS_HMAC 21
131 #define FLAGS_ERROR 22
136 #define OMAP_ALIGN_MASK (sizeof(u32)-1)
137 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
139 #define BUFLEN PAGE_SIZE
140 #define OMAP_SHA_DMA_THRESHOLD 256
142 struct omap_sham_dev;
144 struct omap_sham_reqctx {
145 struct omap_sham_dev *dd;
149 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
156 struct scatterlist *sg;
157 struct scatterlist sgl[2];
158 struct scatterlist sgl_tmp;
159 unsigned int offset; /* offset in current sg */
161 unsigned int total; /* total request */
163 u8 buffer[0] OMAP_ALIGNED;
166 struct omap_sham_hmac_ctx {
167 struct crypto_shash *shash;
168 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
169 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
172 struct omap_sham_ctx {
173 struct omap_sham_dev *dd;
178 struct crypto_shash *fallback;
180 struct omap_sham_hmac_ctx base[0];
183 #define OMAP_SHAM_QUEUE_LENGTH 10
185 struct omap_sham_algs_info {
186 struct ahash_alg *algs_list;
188 unsigned int registered;
191 struct omap_sham_pdata {
192 struct omap_sham_algs_info *algs_info;
193 unsigned int algs_info_size;
197 void (*copy_hash)(struct ahash_request *req, int out);
198 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
200 void (*trigger)(struct omap_sham_dev *dd, size_t length);
201 int (*poll_irq)(struct omap_sham_dev *dd);
202 irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
220 struct omap_sham_dev {
221 struct list_head list;
222 unsigned long phys_base;
224 void __iomem *io_base;
228 struct dma_chan *dma_lch;
229 struct tasklet_struct done_task;
234 struct crypto_queue queue;
235 struct ahash_request *req;
237 const struct omap_sham_pdata *pdata;
240 struct omap_sham_drv {
241 struct list_head dev_list;
246 static struct omap_sham_drv sham = {
247 .dev_list = LIST_HEAD_INIT(sham.dev_list),
248 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
251 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
253 return __raw_readl(dd->io_base + offset);
256 static inline void omap_sham_write(struct omap_sham_dev *dd,
257 u32 offset, u32 value)
259 __raw_writel(value, dd->io_base + offset);
262 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
267 val = omap_sham_read(dd, address);
270 omap_sham_write(dd, address, val);
273 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
275 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
277 while (!(omap_sham_read(dd, offset) & bit)) {
278 if (time_is_before_jiffies(timeout))
285 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
287 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
288 struct omap_sham_dev *dd = ctx->dd;
289 u32 *hash = (u32 *)ctx->digest;
292 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
294 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
296 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
300 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
302 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
303 struct omap_sham_dev *dd = ctx->dd;
306 if (ctx->flags & BIT(FLAGS_HMAC)) {
307 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
308 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
309 struct omap_sham_hmac_ctx *bctx = tctx->base;
310 u32 *opad = (u32 *)bctx->opad;
312 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
314 opad[i] = omap_sham_read(dd,
315 SHA_REG_ODIGEST(dd, i));
317 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
322 omap_sham_copy_hash_omap2(req, out);
325 static void omap_sham_copy_ready_hash(struct ahash_request *req)
327 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
328 u32 *in = (u32 *)ctx->digest;
329 u32 *hash = (u32 *)req->result;
330 int i, d, big_endian = 0;
335 switch (ctx->flags & FLAGS_MODE_MASK) {
337 d = MD5_DIGEST_SIZE / sizeof(u32);
339 case FLAGS_MODE_SHA1:
340 /* OMAP2 SHA1 is big endian */
341 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
343 d = SHA1_DIGEST_SIZE / sizeof(u32);
345 case FLAGS_MODE_SHA224:
346 d = SHA224_DIGEST_SIZE / sizeof(u32);
348 case FLAGS_MODE_SHA256:
349 d = SHA256_DIGEST_SIZE / sizeof(u32);
351 case FLAGS_MODE_SHA384:
352 d = SHA384_DIGEST_SIZE / sizeof(u32);
354 case FLAGS_MODE_SHA512:
355 d = SHA512_DIGEST_SIZE / sizeof(u32);
362 for (i = 0; i < d; i++)
363 hash[i] = be32_to_cpu(in[i]);
365 for (i = 0; i < d; i++)
366 hash[i] = le32_to_cpu(in[i]);
369 static int omap_sham_hw_init(struct omap_sham_dev *dd)
373 err = pm_runtime_get_sync(dd->dev);
375 dev_err(dd->dev, "failed to get sync: %d\n", err);
379 if (!test_bit(FLAGS_INIT, &dd->flags)) {
380 set_bit(FLAGS_INIT, &dd->flags);
387 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
390 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
391 u32 val = length << 5, mask;
393 if (likely(ctx->digcnt))
394 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
396 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
397 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
398 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
400 * Setting ALGO_CONST only for the first iteration
401 * and CLOSE_HASH only for the last one.
403 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
404 val |= SHA_REG_CTRL_ALGO;
406 val |= SHA_REG_CTRL_ALGO_CONST;
408 val |= SHA_REG_CTRL_CLOSE_HASH;
410 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
411 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
413 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
416 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
420 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
422 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
425 static int get_block_size(struct omap_sham_reqctx *ctx)
429 switch (ctx->flags & FLAGS_MODE_MASK) {
431 case FLAGS_MODE_SHA1:
434 case FLAGS_MODE_SHA224:
435 case FLAGS_MODE_SHA256:
436 d = SHA256_BLOCK_SIZE;
438 case FLAGS_MODE_SHA384:
439 case FLAGS_MODE_SHA512:
440 d = SHA512_BLOCK_SIZE;
449 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
450 u32 *value, int count)
452 for (; count--; value++, offset += 4)
453 omap_sham_write(dd, offset, *value);
456 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
459 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
463 * Setting ALGO_CONST only for the first iteration and
464 * CLOSE_HASH only for the last one. Note that flags mode bits
465 * correspond to algorithm encoding in mode register.
467 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
469 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
470 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
471 struct omap_sham_hmac_ctx *bctx = tctx->base;
474 val |= SHA_REG_MODE_ALGO_CONSTANT;
476 if (ctx->flags & BIT(FLAGS_HMAC)) {
477 bs = get_block_size(ctx);
478 nr_dr = bs / (2 * sizeof(u32));
479 val |= SHA_REG_MODE_HMAC_KEY_PROC;
480 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
481 (u32 *)bctx->ipad, nr_dr);
482 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
483 (u32 *)bctx->ipad + nr_dr, nr_dr);
489 val |= SHA_REG_MODE_CLOSE_HASH;
491 if (ctx->flags & BIT(FLAGS_HMAC))
492 val |= SHA_REG_MODE_HMAC_OUTER_HASH;
495 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
496 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
497 SHA_REG_MODE_HMAC_KEY_PROC;
499 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
500 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
501 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
502 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
504 (dma ? SHA_REG_MASK_DMA_EN : 0),
505 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
508 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
510 omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
513 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
515 return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
516 SHA_REG_IRQSTATUS_INPUT_RDY);
519 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
520 size_t length, int final)
522 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
523 int count, len32, bs32, offset = 0;
524 const u32 *buffer = (const u32 *)buf;
526 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
527 ctx->digcnt, length, final);
529 dd->pdata->write_ctrl(dd, length, final, 0);
530 dd->pdata->trigger(dd, length);
532 /* should be non-zero before next lines to disable clocks later */
533 ctx->digcnt += length;
536 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
538 set_bit(FLAGS_CPU, &dd->flags);
540 len32 = DIV_ROUND_UP(length, sizeof(u32));
541 bs32 = get_block_size(ctx) / sizeof(u32);
544 if (dd->pdata->poll_irq(dd))
547 for (count = 0; count < min(len32, bs32); count++, offset++)
548 omap_sham_write(dd, SHA_REG_DIN(dd, count),
550 len32 -= min(len32, bs32);
556 static void omap_sham_dma_callback(void *param)
558 struct omap_sham_dev *dd = param;
560 set_bit(FLAGS_DMA_READY, &dd->flags);
561 tasklet_schedule(&dd->done_task);
564 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
565 size_t length, int final, int is_sg)
567 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
568 struct dma_async_tx_descriptor *tx;
569 struct dma_slave_config cfg;
570 int len32, ret, dma_min = get_block_size(ctx);
572 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
573 ctx->digcnt, length, final);
575 memset(&cfg, 0, sizeof(cfg));
577 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
578 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
579 cfg.dst_maxburst = dma_min / DMA_SLAVE_BUSWIDTH_4_BYTES;
581 ret = dmaengine_slave_config(dd->dma_lch, &cfg);
583 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
587 len32 = DIV_ROUND_UP(length, dma_min) * dma_min;
591 * The SG entry passed in may not have the 'length' member
592 * set correctly so use a local SG entry (sgl_tmp) with the
593 * proper value for 'length' instead. If this is not done,
594 * the dmaengine may try to DMA the incorrect amount of data.
596 sg_init_table(&ctx->sgl_tmp, 1);
597 sg_assign_page(&ctx->sgl_tmp, sg_page(ctx->sg));
598 ctx->sgl_tmp.offset = ctx->sg->offset;
599 sg_dma_len(&ctx->sgl_tmp) = len32;
600 sg_dma_address(&ctx->sgl_tmp) = sg_dma_address(ctx->sg);
602 tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl_tmp, 1,
604 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
606 tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32,
607 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
611 dev_err(dd->dev, "prep_slave_sg/single() failed\n");
615 tx->callback = omap_sham_dma_callback;
616 tx->callback_param = dd;
618 dd->pdata->write_ctrl(dd, length, final, 1);
620 ctx->digcnt += length;
623 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
625 set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
627 dmaengine_submit(tx);
628 dma_async_issue_pending(dd->dma_lch);
630 dd->pdata->trigger(dd, length);
635 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
636 struct scatterlist *sg, int bs, int new_len)
638 int n = sg_nents(sg);
639 struct scatterlist *tmp;
640 int offset = ctx->offset;
645 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
649 sg_init_table(ctx->sg, n);
656 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
661 while (sg && new_len) {
662 int len = sg->length - offset;
665 offset -= sg->length;
675 sg_set_page(tmp, sg_page(sg), len, sg->offset);
685 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
692 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
693 struct scatterlist *sg, int bs, int new_len)
699 len = new_len + ctx->bufcnt;
701 pages = get_order(ctx->total);
703 buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
705 pr_err("Couldn't allocate pages for unaligned cases.\n");
710 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
712 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
713 ctx->total - ctx->bufcnt, 0);
714 sg_init_table(ctx->sgl, 1);
715 sg_set_buf(ctx->sgl, buf, len);
717 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
725 static int omap_sham_align_sgs(struct scatterlist *sg,
726 int nbytes, int bs, bool final,
727 struct omap_sham_reqctx *rctx)
732 struct scatterlist *sg_tmp = sg;
734 int offset = rctx->offset;
736 if (!sg || !sg->length || !nbytes)
745 new_len = DIV_ROUND_UP(new_len, bs) * bs;
747 new_len = new_len / bs * bs;
749 while (nbytes > 0 && sg_tmp) {
752 if (offset < sg_tmp->length) {
753 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
758 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
765 offset -= sg_tmp->length;
771 nbytes -= sg_tmp->length;
774 sg_tmp = sg_next(sg_tmp);
783 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
785 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
793 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
795 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
799 bool final = rctx->flags & BIT(FLAGS_FINUP);
800 int xmit_len, hash_later;
805 bs = get_block_size(rctx);
808 nbytes = req->nbytes;
812 rctx->total = nbytes + rctx->bufcnt;
817 if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
818 int len = bs - rctx->bufcnt % bs;
822 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
830 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
832 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
836 xmit_len = rctx->total;
838 if (!IS_ALIGNED(xmit_len, bs)) {
840 xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
842 xmit_len = xmit_len / bs * bs;
845 hash_later = rctx->total - xmit_len;
849 if (rctx->bufcnt && nbytes) {
850 /* have data from previous operation and current */
851 sg_init_table(rctx->sgl, 2);
852 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
854 sg_chain(rctx->sgl, 2, req->src);
856 rctx->sg = rctx->sgl;
859 } else if (rctx->bufcnt) {
860 /* have buffered data only */
861 sg_init_table(rctx->sgl, 1);
862 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
864 rctx->sg = rctx->sgl;
871 scatterwalk_map_and_copy(rctx->buffer, req->src,
872 req->nbytes - hash_later,
875 memcpy(rctx->buffer, rctx->buffer + xmit_len,
878 rctx->bufcnt = hash_later;
884 rctx->total = xmit_len;
889 static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
890 const u8 *data, size_t length)
892 size_t count = min(length, ctx->buflen - ctx->bufcnt);
894 count = min(count, ctx->total);
897 memcpy(ctx->buffer + ctx->bufcnt, data, count);
898 ctx->bufcnt += count;
903 static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
909 vaddr = kmap_atomic(sg_page(ctx->sg));
910 vaddr += ctx->sg->offset;
912 count = omap_sham_append_buffer(ctx,
914 ctx->sg->length - ctx->offset);
916 kunmap_atomic((void *)vaddr);
920 ctx->offset += count;
922 if (ctx->offset == ctx->sg->length) {
923 ctx->sg = sg_next(ctx->sg);
934 static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
935 struct omap_sham_reqctx *ctx,
936 size_t length, int final)
940 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
942 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
943 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
947 ctx->flags &= ~BIT(FLAGS_SG);
949 ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0);
950 if (ret != -EINPROGRESS)
951 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
957 static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
959 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
963 omap_sham_append_sg(ctx);
965 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
967 dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
968 ctx->bufcnt, ctx->digcnt, final);
970 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
973 return omap_sham_xmit_dma_map(dd, ctx, count, final);
979 /* Start address alignment */
980 #define SG_AA(sg) (IS_ALIGNED(sg->offset, sizeof(u32)))
981 /* SHA1 block size alignment */
982 #define SG_SA(sg, bs) (IS_ALIGNED(sg->length, bs))
984 static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
986 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
987 unsigned int length, final, tail;
988 struct scatterlist *sg;
994 if (ctx->bufcnt || ctx->offset)
995 return omap_sham_update_dma_slow(dd);
998 * Don't use the sg interface when the transfer size is less
999 * than the number of elements in a DMA frame. Otherwise,
1000 * the dmaengine infrastructure will calculate that it needs
1001 * to transfer 0 frames which ultimately fails.
1003 if (ctx->total < get_block_size(ctx))
1004 return omap_sham_update_dma_slow(dd);
1006 dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
1007 ctx->digcnt, ctx->bufcnt, ctx->total);
1010 bs = get_block_size(ctx);
1013 return omap_sham_update_dma_slow(dd);
1015 if (!sg_is_last(sg) && !SG_SA(sg, bs))
1016 /* size is not BLOCK_SIZE aligned */
1017 return omap_sham_update_dma_slow(dd);
1019 length = min(ctx->total, sg->length);
1021 if (sg_is_last(sg)) {
1022 if (!(ctx->flags & BIT(FLAGS_FINUP))) {
1023 /* not last sg must be BLOCK_SIZE aligned */
1024 tail = length & (bs - 1);
1025 /* without finup() we need one block to close hash */
1032 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
1033 dev_err(dd->dev, "dma_map_sg error\n");
1037 ctx->flags |= BIT(FLAGS_SG);
1039 ctx->total -= length;
1040 ctx->offset = length; /* offset where to start slow */
1042 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
1044 ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1);
1045 if (ret != -EINPROGRESS)
1046 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
1051 static int omap_sham_update_cpu(struct omap_sham_dev *dd)
1053 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
1059 omap_sham_append_sg(ctx);
1061 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
1063 dev_dbg(dd->dev, "cpu: bufcnt: %u, digcnt: %d, final: %d\n",
1064 ctx->bufcnt, ctx->digcnt, final);
1066 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
1067 bufcnt = ctx->bufcnt;
1069 return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, final);
1075 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
1077 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
1080 if (ctx->flags & BIT(FLAGS_SG)) {
1081 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
1082 if (ctx->sg->length == ctx->offset) {
1083 ctx->sg = sg_next(ctx->sg);
1088 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
1095 static int omap_sham_init(struct ahash_request *req)
1097 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1098 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1099 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1100 struct omap_sham_dev *dd = NULL, *tmp;
1103 spin_lock_bh(&sham.lock);
1105 list_for_each_entry(tmp, &sham.dev_list, list) {
1113 spin_unlock_bh(&sham.lock);
1119 dev_dbg(dd->dev, "init: digest size: %d\n",
1120 crypto_ahash_digestsize(tfm));
1122 switch (crypto_ahash_digestsize(tfm)) {
1123 case MD5_DIGEST_SIZE:
1124 ctx->flags |= FLAGS_MODE_MD5;
1125 bs = SHA1_BLOCK_SIZE;
1127 case SHA1_DIGEST_SIZE:
1128 ctx->flags |= FLAGS_MODE_SHA1;
1129 bs = SHA1_BLOCK_SIZE;
1131 case SHA224_DIGEST_SIZE:
1132 ctx->flags |= FLAGS_MODE_SHA224;
1133 bs = SHA224_BLOCK_SIZE;
1135 case SHA256_DIGEST_SIZE:
1136 ctx->flags |= FLAGS_MODE_SHA256;
1137 bs = SHA256_BLOCK_SIZE;
1139 case SHA384_DIGEST_SIZE:
1140 ctx->flags |= FLAGS_MODE_SHA384;
1141 bs = SHA384_BLOCK_SIZE;
1143 case SHA512_DIGEST_SIZE:
1144 ctx->flags |= FLAGS_MODE_SHA512;
1145 bs = SHA512_BLOCK_SIZE;
1151 ctx->buflen = BUFLEN;
1153 if (tctx->flags & BIT(FLAGS_HMAC)) {
1154 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1155 struct omap_sham_hmac_ctx *bctx = tctx->base;
1157 memcpy(ctx->buffer, bctx->ipad, bs);
1161 ctx->flags |= BIT(FLAGS_HMAC);
1168 static int omap_sham_update_req(struct omap_sham_dev *dd)
1170 struct ahash_request *req = dd->req;
1171 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1174 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
1175 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
1177 if (ctx->flags & BIT(FLAGS_CPU))
1178 err = omap_sham_update_cpu(dd);
1180 err = omap_sham_update_dma_start(dd);
1182 /* wait for dma completion before can take more data */
1183 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1188 static int omap_sham_final_req(struct omap_sham_dev *dd)
1190 struct ahash_request *req = dd->req;
1191 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1192 int err = 0, use_dma = 1;
1194 if ((ctx->bufcnt <= get_block_size(ctx)) || dd->polling_mode)
1196 * faster to handle last block with cpu or
1197 * use cpu when dma is not present.
1202 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
1204 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
1208 dev_dbg(dd->dev, "final_req: err: %d\n", err);
1213 static int omap_sham_finish_hmac(struct ahash_request *req)
1215 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1216 struct omap_sham_hmac_ctx *bctx = tctx->base;
1217 int bs = crypto_shash_blocksize(bctx->shash);
1218 int ds = crypto_shash_digestsize(bctx->shash);
1219 SHASH_DESC_ON_STACK(shash, bctx->shash);
1221 shash->tfm = bctx->shash;
1222 shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
1224 return crypto_shash_init(shash) ?:
1225 crypto_shash_update(shash, bctx->opad, bs) ?:
1226 crypto_shash_finup(shash, req->result, ds, req->result);
1229 static int omap_sham_finish(struct ahash_request *req)
1231 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1232 struct omap_sham_dev *dd = ctx->dd;
1236 omap_sham_copy_ready_hash(req);
1237 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1238 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1239 err = omap_sham_finish_hmac(req);
1242 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1247 static void omap_sham_finish_req(struct ahash_request *req, int err)
1249 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1250 struct omap_sham_dev *dd = ctx->dd;
1253 dd->pdata->copy_hash(req, 1);
1254 if (test_bit(FLAGS_FINAL, &dd->flags))
1255 err = omap_sham_finish(req);
1257 ctx->flags |= BIT(FLAGS_ERROR);
1260 /* atomic operation is not needed here */
1261 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1262 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1264 pm_runtime_mark_last_busy(dd->dev);
1265 pm_runtime_put_autosuspend(dd->dev);
1267 if (req->base.complete)
1268 req->base.complete(&req->base, err);
1271 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1272 struct ahash_request *req)
1274 struct crypto_async_request *async_req, *backlog;
1275 struct omap_sham_reqctx *ctx;
1276 unsigned long flags;
1277 int err = 0, ret = 0;
1280 spin_lock_irqsave(&dd->lock, flags);
1282 ret = ahash_enqueue_request(&dd->queue, req);
1283 if (test_bit(FLAGS_BUSY, &dd->flags)) {
1284 spin_unlock_irqrestore(&dd->lock, flags);
1287 backlog = crypto_get_backlog(&dd->queue);
1288 async_req = crypto_dequeue_request(&dd->queue);
1290 set_bit(FLAGS_BUSY, &dd->flags);
1291 spin_unlock_irqrestore(&dd->lock, flags);
1297 backlog->complete(backlog, -EINPROGRESS);
1299 req = ahash_request_cast(async_req);
1301 ctx = ahash_request_ctx(req);
1303 err = omap_sham_prepare_request(NULL, ctx->op == OP_UPDATE);
1307 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1308 ctx->op, req->nbytes);
1310 err = omap_sham_hw_init(dd);
1315 /* request has changed - restore hash */
1316 dd->pdata->copy_hash(req, 0);
1318 if (ctx->op == OP_UPDATE) {
1319 err = omap_sham_update_req(dd);
1320 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1321 /* no final() after finup() */
1322 err = omap_sham_final_req(dd);
1323 } else if (ctx->op == OP_FINAL) {
1324 err = omap_sham_final_req(dd);
1327 dev_dbg(dd->dev, "exit, err: %d\n", err);
1329 if (err != -EINPROGRESS) {
1330 /* done_task will not finish it, so do it here */
1331 omap_sham_finish_req(req, err);
1335 * Execute next request immediately if there is anything
1344 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1346 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1347 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1348 struct omap_sham_dev *dd = tctx->dd;
1352 return omap_sham_handle_queue(dd, req);
1355 static int omap_sham_update(struct ahash_request *req)
1357 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1358 struct omap_sham_dev *dd = ctx->dd;
1359 int bs = get_block_size(ctx);
1364 ctx->total = req->nbytes;
1368 if (ctx->flags & BIT(FLAGS_FINUP)) {
1369 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 240) {
1371 * OMAP HW accel works only with buffers >= 9
1372 * will switch to bypass in final()
1373 * final has the same request and data
1375 omap_sham_append_sg(ctx);
1377 } else if ((ctx->bufcnt + ctx->total <= bs) ||
1380 * faster to use CPU for short transfers or
1381 * use cpu when dma is not present.
1383 ctx->flags |= BIT(FLAGS_CPU);
1385 } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
1386 omap_sham_append_sg(ctx);
1390 if (dd->polling_mode)
1391 ctx->flags |= BIT(FLAGS_CPU);
1393 return omap_sham_enqueue(req, OP_UPDATE);
1396 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1397 const u8 *data, unsigned int len, u8 *out)
1399 SHASH_DESC_ON_STACK(shash, tfm);
1402 shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1404 return crypto_shash_digest(shash, data, len, out);
1407 static int omap_sham_final_shash(struct ahash_request *req)
1409 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1410 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1414 * If we are running HMAC on limited hardware support, skip
1415 * the ipad in the beginning of the buffer if we are going for
1416 * software fallback algorithm.
1418 if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1419 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1420 offset = get_block_size(ctx);
1422 return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1423 ctx->buffer + offset,
1424 ctx->bufcnt - offset, req->result);
1427 static int omap_sham_final(struct ahash_request *req)
1429 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1431 ctx->flags |= BIT(FLAGS_FINUP);
1433 if (ctx->flags & BIT(FLAGS_ERROR))
1434 return 0; /* uncompleted hash is not needed */
1437 * OMAP HW accel works only with buffers >= 9.
1438 * HMAC is always >= 9 because ipad == block size.
1439 * If buffersize is less than DMA_THRESHOLD, we use fallback
1440 * SW encoding, as using DMA + HW in this case doesn't provide
1443 if (!ctx->digcnt && ctx->bufcnt < OMAP_SHA_DMA_THRESHOLD)
1444 return omap_sham_final_shash(req);
1445 else if (ctx->bufcnt)
1446 return omap_sham_enqueue(req, OP_FINAL);
1448 /* copy ready hash (+ finalize hmac) */
1449 return omap_sham_finish(req);
1452 static int omap_sham_finup(struct ahash_request *req)
1454 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1457 ctx->flags |= BIT(FLAGS_FINUP);
1459 err1 = omap_sham_update(req);
1460 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1463 * final() has to be always called to cleanup resources
1464 * even if udpate() failed, except EINPROGRESS
1466 err2 = omap_sham_final(req);
1468 return err1 ?: err2;
1471 static int omap_sham_digest(struct ahash_request *req)
1473 return omap_sham_init(req) ?: omap_sham_finup(req);
1476 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1477 unsigned int keylen)
1479 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1480 struct omap_sham_hmac_ctx *bctx = tctx->base;
1481 int bs = crypto_shash_blocksize(bctx->shash);
1482 int ds = crypto_shash_digestsize(bctx->shash);
1483 struct omap_sham_dev *dd = NULL, *tmp;
1486 spin_lock_bh(&sham.lock);
1488 list_for_each_entry(tmp, &sham.dev_list, list) {
1496 spin_unlock_bh(&sham.lock);
1498 err = crypto_shash_setkey(tctx->fallback, key, keylen);
1503 err = omap_sham_shash_digest(bctx->shash,
1504 crypto_shash_get_flags(bctx->shash),
1505 key, keylen, bctx->ipad);
1510 memcpy(bctx->ipad, key, keylen);
1513 memset(bctx->ipad + keylen, 0, bs - keylen);
1515 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1516 memcpy(bctx->opad, bctx->ipad, bs);
1518 for (i = 0; i < bs; i++) {
1519 bctx->ipad[i] ^= 0x36;
1520 bctx->opad[i] ^= 0x5c;
1527 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1529 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1530 const char *alg_name = crypto_tfm_alg_name(tfm);
1532 /* Allocate a fallback and abort if it failed. */
1533 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1534 CRYPTO_ALG_NEED_FALLBACK);
1535 if (IS_ERR(tctx->fallback)) {
1536 pr_err("omap-sham: fallback driver '%s' "
1537 "could not be loaded.\n", alg_name);
1538 return PTR_ERR(tctx->fallback);
1541 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1542 sizeof(struct omap_sham_reqctx) + BUFLEN);
1545 struct omap_sham_hmac_ctx *bctx = tctx->base;
1546 tctx->flags |= BIT(FLAGS_HMAC);
1547 bctx->shash = crypto_alloc_shash(alg_base, 0,
1548 CRYPTO_ALG_NEED_FALLBACK);
1549 if (IS_ERR(bctx->shash)) {
1550 pr_err("omap-sham: base driver '%s' "
1551 "could not be loaded.\n", alg_base);
1552 crypto_free_shash(tctx->fallback);
1553 return PTR_ERR(bctx->shash);
1561 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1563 return omap_sham_cra_init_alg(tfm, NULL);
1566 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1568 return omap_sham_cra_init_alg(tfm, "sha1");
1571 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1573 return omap_sham_cra_init_alg(tfm, "sha224");
1576 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1578 return omap_sham_cra_init_alg(tfm, "sha256");
1581 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1583 return omap_sham_cra_init_alg(tfm, "md5");
1586 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1588 return omap_sham_cra_init_alg(tfm, "sha384");
1591 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1593 return omap_sham_cra_init_alg(tfm, "sha512");
1596 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1598 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1600 crypto_free_shash(tctx->fallback);
1601 tctx->fallback = NULL;
1603 if (tctx->flags & BIT(FLAGS_HMAC)) {
1604 struct omap_sham_hmac_ctx *bctx = tctx->base;
1605 crypto_free_shash(bctx->shash);
1609 static int omap_sham_export(struct ahash_request *req, void *out)
1614 static int omap_sham_import(struct ahash_request *req, const void *in)
1619 static struct ahash_alg algs_sha1_md5[] = {
1621 .init = omap_sham_init,
1622 .update = omap_sham_update,
1623 .final = omap_sham_final,
1624 .finup = omap_sham_finup,
1625 .digest = omap_sham_digest,
1626 .halg.digestsize = SHA1_DIGEST_SIZE,
1629 .cra_driver_name = "omap-sha1",
1630 .cra_priority = 400,
1631 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1632 CRYPTO_ALG_KERN_DRIVER_ONLY |
1634 CRYPTO_ALG_NEED_FALLBACK,
1635 .cra_blocksize = SHA1_BLOCK_SIZE,
1636 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1637 .cra_alignmask = OMAP_ALIGN_MASK,
1638 .cra_module = THIS_MODULE,
1639 .cra_init = omap_sham_cra_init,
1640 .cra_exit = omap_sham_cra_exit,
1644 .init = omap_sham_init,
1645 .update = omap_sham_update,
1646 .final = omap_sham_final,
1647 .finup = omap_sham_finup,
1648 .digest = omap_sham_digest,
1649 .halg.digestsize = MD5_DIGEST_SIZE,
1652 .cra_driver_name = "omap-md5",
1653 .cra_priority = 400,
1654 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1655 CRYPTO_ALG_KERN_DRIVER_ONLY |
1657 CRYPTO_ALG_NEED_FALLBACK,
1658 .cra_blocksize = SHA1_BLOCK_SIZE,
1659 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1660 .cra_alignmask = OMAP_ALIGN_MASK,
1661 .cra_module = THIS_MODULE,
1662 .cra_init = omap_sham_cra_init,
1663 .cra_exit = omap_sham_cra_exit,
1667 .init = omap_sham_init,
1668 .update = omap_sham_update,
1669 .final = omap_sham_final,
1670 .finup = omap_sham_finup,
1671 .digest = omap_sham_digest,
1672 .setkey = omap_sham_setkey,
1673 .halg.digestsize = SHA1_DIGEST_SIZE,
1675 .cra_name = "hmac(sha1)",
1676 .cra_driver_name = "omap-hmac-sha1",
1677 .cra_priority = 400,
1678 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1679 CRYPTO_ALG_KERN_DRIVER_ONLY |
1681 CRYPTO_ALG_NEED_FALLBACK,
1682 .cra_blocksize = SHA1_BLOCK_SIZE,
1683 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1684 sizeof(struct omap_sham_hmac_ctx),
1685 .cra_alignmask = OMAP_ALIGN_MASK,
1686 .cra_module = THIS_MODULE,
1687 .cra_init = omap_sham_cra_sha1_init,
1688 .cra_exit = omap_sham_cra_exit,
1692 .init = omap_sham_init,
1693 .update = omap_sham_update,
1694 .final = omap_sham_final,
1695 .finup = omap_sham_finup,
1696 .digest = omap_sham_digest,
1697 .setkey = omap_sham_setkey,
1698 .halg.digestsize = MD5_DIGEST_SIZE,
1700 .cra_name = "hmac(md5)",
1701 .cra_driver_name = "omap-hmac-md5",
1702 .cra_priority = 400,
1703 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1704 CRYPTO_ALG_KERN_DRIVER_ONLY |
1706 CRYPTO_ALG_NEED_FALLBACK,
1707 .cra_blocksize = SHA1_BLOCK_SIZE,
1708 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1709 sizeof(struct omap_sham_hmac_ctx),
1710 .cra_alignmask = OMAP_ALIGN_MASK,
1711 .cra_module = THIS_MODULE,
1712 .cra_init = omap_sham_cra_md5_init,
1713 .cra_exit = omap_sham_cra_exit,
1718 /* OMAP4 has some algs in addition to what OMAP2 has */
1719 static struct ahash_alg algs_sha224_sha256[] = {
1721 .init = omap_sham_init,
1722 .update = omap_sham_update,
1723 .final = omap_sham_final,
1724 .finup = omap_sham_finup,
1725 .digest = omap_sham_digest,
1726 .halg.digestsize = SHA224_DIGEST_SIZE,
1728 .cra_name = "sha224",
1729 .cra_driver_name = "omap-sha224",
1730 .cra_priority = 400,
1731 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1733 CRYPTO_ALG_NEED_FALLBACK,
1734 .cra_blocksize = SHA224_BLOCK_SIZE,
1735 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1736 .cra_alignmask = OMAP_ALIGN_MASK,
1737 .cra_module = THIS_MODULE,
1738 .cra_init = omap_sham_cra_init,
1739 .cra_exit = omap_sham_cra_exit,
1743 .init = omap_sham_init,
1744 .update = omap_sham_update,
1745 .final = omap_sham_final,
1746 .finup = omap_sham_finup,
1747 .digest = omap_sham_digest,
1748 .halg.digestsize = SHA256_DIGEST_SIZE,
1750 .cra_name = "sha256",
1751 .cra_driver_name = "omap-sha256",
1752 .cra_priority = 400,
1753 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1755 CRYPTO_ALG_NEED_FALLBACK,
1756 .cra_blocksize = SHA256_BLOCK_SIZE,
1757 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1758 .cra_alignmask = OMAP_ALIGN_MASK,
1759 .cra_module = THIS_MODULE,
1760 .cra_init = omap_sham_cra_init,
1761 .cra_exit = omap_sham_cra_exit,
1765 .init = omap_sham_init,
1766 .update = omap_sham_update,
1767 .final = omap_sham_final,
1768 .finup = omap_sham_finup,
1769 .digest = omap_sham_digest,
1770 .setkey = omap_sham_setkey,
1771 .halg.digestsize = SHA224_DIGEST_SIZE,
1773 .cra_name = "hmac(sha224)",
1774 .cra_driver_name = "omap-hmac-sha224",
1775 .cra_priority = 400,
1776 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1778 CRYPTO_ALG_NEED_FALLBACK,
1779 .cra_blocksize = SHA224_BLOCK_SIZE,
1780 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1781 sizeof(struct omap_sham_hmac_ctx),
1782 .cra_alignmask = OMAP_ALIGN_MASK,
1783 .cra_module = THIS_MODULE,
1784 .cra_init = omap_sham_cra_sha224_init,
1785 .cra_exit = omap_sham_cra_exit,
1789 .init = omap_sham_init,
1790 .update = omap_sham_update,
1791 .final = omap_sham_final,
1792 .finup = omap_sham_finup,
1793 .digest = omap_sham_digest,
1794 .setkey = omap_sham_setkey,
1795 .halg.digestsize = SHA256_DIGEST_SIZE,
1797 .cra_name = "hmac(sha256)",
1798 .cra_driver_name = "omap-hmac-sha256",
1799 .cra_priority = 400,
1800 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1802 CRYPTO_ALG_NEED_FALLBACK,
1803 .cra_blocksize = SHA256_BLOCK_SIZE,
1804 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1805 sizeof(struct omap_sham_hmac_ctx),
1806 .cra_alignmask = OMAP_ALIGN_MASK,
1807 .cra_module = THIS_MODULE,
1808 .cra_init = omap_sham_cra_sha256_init,
1809 .cra_exit = omap_sham_cra_exit,
1814 static struct ahash_alg algs_sha384_sha512[] = {
1816 .init = omap_sham_init,
1817 .update = omap_sham_update,
1818 .final = omap_sham_final,
1819 .finup = omap_sham_finup,
1820 .digest = omap_sham_digest,
1821 .halg.digestsize = SHA384_DIGEST_SIZE,
1823 .cra_name = "sha384",
1824 .cra_driver_name = "omap-sha384",
1825 .cra_priority = 400,
1826 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1828 CRYPTO_ALG_NEED_FALLBACK,
1829 .cra_blocksize = SHA384_BLOCK_SIZE,
1830 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1831 .cra_alignmask = OMAP_ALIGN_MASK,
1832 .cra_module = THIS_MODULE,
1833 .cra_init = omap_sham_cra_init,
1834 .cra_exit = omap_sham_cra_exit,
1838 .init = omap_sham_init,
1839 .update = omap_sham_update,
1840 .final = omap_sham_final,
1841 .finup = omap_sham_finup,
1842 .digest = omap_sham_digest,
1843 .halg.digestsize = SHA512_DIGEST_SIZE,
1845 .cra_name = "sha512",
1846 .cra_driver_name = "omap-sha512",
1847 .cra_priority = 400,
1848 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1850 CRYPTO_ALG_NEED_FALLBACK,
1851 .cra_blocksize = SHA512_BLOCK_SIZE,
1852 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1853 .cra_alignmask = OMAP_ALIGN_MASK,
1854 .cra_module = THIS_MODULE,
1855 .cra_init = omap_sham_cra_init,
1856 .cra_exit = omap_sham_cra_exit,
1860 .init = omap_sham_init,
1861 .update = omap_sham_update,
1862 .final = omap_sham_final,
1863 .finup = omap_sham_finup,
1864 .digest = omap_sham_digest,
1865 .setkey = omap_sham_setkey,
1866 .halg.digestsize = SHA384_DIGEST_SIZE,
1868 .cra_name = "hmac(sha384)",
1869 .cra_driver_name = "omap-hmac-sha384",
1870 .cra_priority = 400,
1871 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1873 CRYPTO_ALG_NEED_FALLBACK,
1874 .cra_blocksize = SHA384_BLOCK_SIZE,
1875 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1876 sizeof(struct omap_sham_hmac_ctx),
1877 .cra_alignmask = OMAP_ALIGN_MASK,
1878 .cra_module = THIS_MODULE,
1879 .cra_init = omap_sham_cra_sha384_init,
1880 .cra_exit = omap_sham_cra_exit,
1884 .init = omap_sham_init,
1885 .update = omap_sham_update,
1886 .final = omap_sham_final,
1887 .finup = omap_sham_finup,
1888 .digest = omap_sham_digest,
1889 .setkey = omap_sham_setkey,
1890 .halg.digestsize = SHA512_DIGEST_SIZE,
1892 .cra_name = "hmac(sha512)",
1893 .cra_driver_name = "omap-hmac-sha512",
1894 .cra_priority = 400,
1895 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1897 CRYPTO_ALG_NEED_FALLBACK,
1898 .cra_blocksize = SHA512_BLOCK_SIZE,
1899 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1900 sizeof(struct omap_sham_hmac_ctx),
1901 .cra_alignmask = OMAP_ALIGN_MASK,
1902 .cra_module = THIS_MODULE,
1903 .cra_init = omap_sham_cra_sha512_init,
1904 .cra_exit = omap_sham_cra_exit,
1909 static void omap_sham_done_task(unsigned long data)
1911 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1914 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1915 omap_sham_handle_queue(dd, NULL);
1919 if (test_bit(FLAGS_CPU, &dd->flags)) {
1920 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1921 /* hash or semi-hash ready */
1922 err = omap_sham_update_cpu(dd);
1923 if (err != -EINPROGRESS)
1926 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1927 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1928 omap_sham_update_dma_stop(dd);
1934 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1935 /* hash or semi-hash ready */
1936 clear_bit(FLAGS_DMA_READY, &dd->flags);
1937 err = omap_sham_update_dma_start(dd);
1938 if (err != -EINPROGRESS)
1946 dev_dbg(dd->dev, "update done: err: %d\n", err);
1947 /* finish curent request */
1948 omap_sham_finish_req(dd->req, err);
1950 /* If we are not busy, process next req */
1951 if (!test_bit(FLAGS_BUSY, &dd->flags))
1952 omap_sham_handle_queue(dd, NULL);
1955 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1957 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1958 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1960 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1961 tasklet_schedule(&dd->done_task);
1967 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1969 struct omap_sham_dev *dd = dev_id;
1971 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1972 /* final -> allow device to go to power-saving mode */
1973 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1975 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1976 SHA_REG_CTRL_OUTPUT_READY);
1977 omap_sham_read(dd, SHA_REG_CTRL);
1979 return omap_sham_irq_common(dd);
1982 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1984 struct omap_sham_dev *dd = dev_id;
1986 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1988 return omap_sham_irq_common(dd);
1991 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1993 .algs_list = algs_sha1_md5,
1994 .size = ARRAY_SIZE(algs_sha1_md5),
1998 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1999 .algs_info = omap_sham_algs_info_omap2,
2000 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
2001 .flags = BIT(FLAGS_BE32_SHA1),
2002 .digest_size = SHA1_DIGEST_SIZE,
2003 .copy_hash = omap_sham_copy_hash_omap2,
2004 .write_ctrl = omap_sham_write_ctrl_omap2,
2005 .trigger = omap_sham_trigger_omap2,
2006 .poll_irq = omap_sham_poll_irq_omap2,
2007 .intr_hdlr = omap_sham_irq_omap2,
2008 .idigest_ofs = 0x00,
2013 .sysstatus_ofs = 0x64,
2021 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
2023 .algs_list = algs_sha1_md5,
2024 .size = ARRAY_SIZE(algs_sha1_md5),
2027 .algs_list = algs_sha224_sha256,
2028 .size = ARRAY_SIZE(algs_sha224_sha256),
2032 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
2033 .algs_info = omap_sham_algs_info_omap4,
2034 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
2035 .flags = BIT(FLAGS_AUTO_XOR),
2036 .digest_size = SHA256_DIGEST_SIZE,
2037 .copy_hash = omap_sham_copy_hash_omap4,
2038 .write_ctrl = omap_sham_write_ctrl_omap4,
2039 .trigger = omap_sham_trigger_omap4,
2040 .poll_irq = omap_sham_poll_irq_omap4,
2041 .intr_hdlr = omap_sham_irq_omap4,
2042 .idigest_ofs = 0x020,
2045 .digcnt_ofs = 0x040,
2048 .sysstatus_ofs = 0x114,
2051 .major_mask = 0x0700,
2053 .minor_mask = 0x003f,
2057 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
2059 .algs_list = algs_sha1_md5,
2060 .size = ARRAY_SIZE(algs_sha1_md5),
2063 .algs_list = algs_sha224_sha256,
2064 .size = ARRAY_SIZE(algs_sha224_sha256),
2067 .algs_list = algs_sha384_sha512,
2068 .size = ARRAY_SIZE(algs_sha384_sha512),
2072 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
2073 .algs_info = omap_sham_algs_info_omap5,
2074 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
2075 .flags = BIT(FLAGS_AUTO_XOR),
2076 .digest_size = SHA512_DIGEST_SIZE,
2077 .copy_hash = omap_sham_copy_hash_omap4,
2078 .write_ctrl = omap_sham_write_ctrl_omap4,
2079 .trigger = omap_sham_trigger_omap4,
2080 .poll_irq = omap_sham_poll_irq_omap4,
2081 .intr_hdlr = omap_sham_irq_omap4,
2082 .idigest_ofs = 0x240,
2083 .odigest_ofs = 0x200,
2085 .digcnt_ofs = 0x280,
2088 .sysstatus_ofs = 0x114,
2090 .length_ofs = 0x288,
2091 .major_mask = 0x0700,
2093 .minor_mask = 0x003f,
2097 static const struct of_device_id omap_sham_of_match[] = {
2099 .compatible = "ti,omap2-sham",
2100 .data = &omap_sham_pdata_omap2,
2103 .compatible = "ti,omap3-sham",
2104 .data = &omap_sham_pdata_omap2,
2107 .compatible = "ti,omap4-sham",
2108 .data = &omap_sham_pdata_omap4,
2111 .compatible = "ti,omap5-sham",
2112 .data = &omap_sham_pdata_omap5,
2116 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
2118 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
2119 struct device *dev, struct resource *res)
2121 struct device_node *node = dev->of_node;
2122 const struct of_device_id *match;
2125 match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
2127 dev_err(dev, "no compatible OF match\n");
2132 err = of_address_to_resource(node, 0, res);
2134 dev_err(dev, "can't translate OF node address\n");
2139 dd->irq = irq_of_parse_and_map(node, 0);
2141 dev_err(dev, "can't translate OF irq value\n");
2146 dd->pdata = match->data;
2152 static const struct of_device_id omap_sham_of_match[] = {
2156 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
2157 struct device *dev, struct resource *res)
2163 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
2164 struct platform_device *pdev, struct resource *res)
2166 struct device *dev = &pdev->dev;
2170 /* Get the base address */
2171 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2173 dev_err(dev, "no MEM resource info\n");
2177 memcpy(res, r, sizeof(*res));
2180 dd->irq = platform_get_irq(pdev, 0);
2182 dev_err(dev, "no IRQ resource info\n");
2187 /* Only OMAP2/3 can be non-DT */
2188 dd->pdata = &omap_sham_pdata_omap2;
2194 static int omap_sham_probe(struct platform_device *pdev)
2196 struct omap_sham_dev *dd;
2197 struct device *dev = &pdev->dev;
2198 struct resource res;
2199 dma_cap_mask_t mask;
2203 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2205 dev_err(dev, "unable to alloc data struct.\n");
2210 platform_set_drvdata(pdev, dd);
2212 INIT_LIST_HEAD(&dd->list);
2213 spin_lock_init(&dd->lock);
2214 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2215 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2217 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2218 omap_sham_get_res_pdev(dd, pdev, &res);
2222 dd->io_base = devm_ioremap_resource(dev, &res);
2223 if (IS_ERR(dd->io_base)) {
2224 err = PTR_ERR(dd->io_base);
2227 dd->phys_base = res.start;
2229 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2230 IRQF_TRIGGER_NONE, dev_name(dev), dd);
2232 dev_err(dev, "unable to request irq %d, err = %d\n",
2238 dma_cap_set(DMA_SLAVE, mask);
2240 dd->dma_lch = dma_request_chan(dev, "rx");
2241 if (IS_ERR(dd->dma_lch)) {
2242 err = PTR_ERR(dd->dma_lch);
2243 if (err == -EPROBE_DEFER)
2246 dd->polling_mode = 1;
2247 dev_dbg(dev, "using polling mode instead of dma\n");
2250 dd->flags |= dd->pdata->flags;
2252 pm_runtime_use_autosuspend(dev);
2253 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2255 pm_runtime_enable(dev);
2256 pm_runtime_irq_safe(dev);
2258 err = pm_runtime_get_sync(dev);
2260 dev_err(dev, "failed to get sync: %d\n", err);
2264 rev = omap_sham_read(dd, SHA_REG_REV(dd));
2265 pm_runtime_put_sync(&pdev->dev);
2267 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2268 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2269 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2271 spin_lock(&sham.lock);
2272 list_add_tail(&dd->list, &sham.dev_list);
2273 spin_unlock(&sham.lock);
2275 for (i = 0; i < dd->pdata->algs_info_size; i++) {
2276 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2277 struct ahash_alg *alg;
2279 alg = &dd->pdata->algs_info[i].algs_list[j];
2280 alg->export = omap_sham_export;
2281 alg->import = omap_sham_import;
2282 alg->halg.statesize = sizeof(struct omap_sham_reqctx);
2283 err = crypto_register_ahash(alg);
2287 dd->pdata->algs_info[i].registered++;
2294 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2295 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2296 crypto_unregister_ahash(
2297 &dd->pdata->algs_info[i].algs_list[j]);
2299 pm_runtime_disable(dev);
2300 if (!dd->polling_mode)
2301 dma_release_channel(dd->dma_lch);
2303 dev_err(dev, "initialization failed.\n");
2308 static int omap_sham_remove(struct platform_device *pdev)
2310 static struct omap_sham_dev *dd;
2313 dd = platform_get_drvdata(pdev);
2316 spin_lock(&sham.lock);
2317 list_del(&dd->list);
2318 spin_unlock(&sham.lock);
2319 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2320 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2321 crypto_unregister_ahash(
2322 &dd->pdata->algs_info[i].algs_list[j]);
2323 tasklet_kill(&dd->done_task);
2324 pm_runtime_disable(&pdev->dev);
2326 if (!dd->polling_mode)
2327 dma_release_channel(dd->dma_lch);
2332 #ifdef CONFIG_PM_SLEEP
2333 static int omap_sham_suspend(struct device *dev)
2335 pm_runtime_put_sync(dev);
2339 static int omap_sham_resume(struct device *dev)
2341 int err = pm_runtime_get_sync(dev);
2343 dev_err(dev, "failed to get sync: %d\n", err);
2350 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2352 static struct platform_driver omap_sham_driver = {
2353 .probe = omap_sham_probe,
2354 .remove = omap_sham_remove,
2356 .name = "omap-sham",
2357 .pm = &omap_sham_pm_ops,
2358 .of_match_table = omap_sham_of_match,
2362 module_platform_driver(omap_sham_driver);
2364 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2365 MODULE_LICENSE("GPL v2");
2366 MODULE_AUTHOR("Dmitry Kasatkin");
2367 MODULE_ALIAS("platform:omap-sham");