drivers/crypto/omap-sham.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP SHA1/MD5 HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  * Some ideas are from old omap-sha1-md5.c driver.
  15  */
  16
  17 #define pr_fmt(fmt) "%s: " fmt, __func__
  18
  19 #include <linux/err.h>
  20 #include <linux/device.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/delay.h>
  38 #include <linux/crypto.h>
  39 #include <linux/cryptohash.h>
  40 #include <crypto/scatterwalk.h>
  41 #include <crypto/algapi.h>
  42 #include <crypto/sha.h>
  43 #include <crypto/hash.h>
  44 #include <crypto/hmac.h>
  45 #include <crypto/internal/hash.h>
  46
  47 #define MD5_DIGEST_SIZE                 16
  48
  49 #define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  50 #define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  51 #define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  52
  53 #define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  54
  55 #define SHA_REG_CTRL                    0x18
  56 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  57 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  58 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  59 #define SHA_REG_CTRL_ALGO               (1 << 2)
  60 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  61 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  62
  63 #define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  64
  65 #define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  66 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  67 #define SHA_REG_MASK_IT_EN              (1 << 2)
  68 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  69 #define SHA_REG_AUTOIDLE                (1 << 0)
  70
  71 #define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  72 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  73
  74 #define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  75 #define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  76 #define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  77 #define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  78 #define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  79
  80 #define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  81 #define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  82 #define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  83 #define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  84 #define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  85 #define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  86 #define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  87
  88 #define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  89
  90 #define SHA_REG_IRQSTATUS               0x118
  91 #define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  93 #define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  95
  96 #define SHA_REG_IRQENA                  0x11C
  97 #define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  98 #define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  99 #define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
 100 #define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
 101
 102 #define DEFAULT_TIMEOUT_INTERVAL        HZ
 103
 104 #define DEFAULT_AUTOSUSPEND_DELAY       1000
 105
 106 /* mostly device flags */
 107 #define FLAGS_BUSY              0
 108 #define FLAGS_FINAL             1
 109 #define FLAGS_DMA_ACTIVE        2
 110 #define FLAGS_OUTPUT_READY      3
 111 #define FLAGS_INIT              4
 112 #define FLAGS_CPU               5
 113 #define FLAGS_DMA_READY         6
 114 #define FLAGS_AUTO_XOR          7
 115 #define FLAGS_BE32_SHA1         8
 116 #define FLAGS_SGS_COPIED        9
 117 #define FLAGS_SGS_ALLOCED       10
 118 /* context flags */
 119 #define FLAGS_FINUP             16
 120
 121 #define FLAGS_MODE_SHIFT        18
 122 #define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 123 #define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 124 #define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 125 #define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 126 #define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 127 #define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 128 #define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 129
 130 #define FLAGS_HMAC              21
 131 #define FLAGS_ERROR             22
 132
 133 #define OP_UPDATE               1
 134 #define OP_FINAL                2
 135
 136 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 137 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 138
 139 #define BUFLEN                  SHA512_BLOCK_SIZE
 140 #define OMAP_SHA_DMA_THRESHOLD  256
 141
 142 struct omap_sham_dev;
 143
 144 struct omap_sham_reqctx {
 145         struct omap_sham_dev    *dd;
 146         unsigned long           flags;
 147         unsigned long           op;
 148
 149         u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 150         size_t                  digcnt;
 151         size_t                  bufcnt;
 152         size_t                  buflen;
 153
 154         /* walk state */
 155         struct scatterlist      *sg;
 156         struct scatterlist      sgl[2];
 157         int                     offset; /* offset in current sg */
 158         int                     sg_len;
 159         unsigned int            total;  /* total request */
 160
 161         u8                      buffer[0] OMAP_ALIGNED;
 162 };
 163
 164 struct omap_sham_hmac_ctx {
 165         struct crypto_shash     *shash;
 166         u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 167         u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 168 };
 169
 170 struct omap_sham_ctx {
 171         struct omap_sham_dev    *dd;
 172
 173         unsigned long           flags;
 174
 175         /* fallback stuff */
 176         struct crypto_shash     *fallback;
 177
 178         struct omap_sham_hmac_ctx base[0];
 179 };
 180
 181 #define OMAP_SHAM_QUEUE_LENGTH  10
 182
 183 struct omap_sham_algs_info {
 184         struct ahash_alg        *algs_list;
 185         unsigned int            size;
 186         unsigned int            registered;
 187 };
 188
 189 struct omap_sham_pdata {
 190         struct omap_sham_algs_info      *algs_info;
 191         unsigned int    algs_info_size;
 192         unsigned long   flags;
 193         int             digest_size;
 194
 195         void            (*copy_hash)(struct ahash_request *req, int out);
 196         void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 197                                       int final, int dma);
 198         void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 199         int             (*poll_irq)(struct omap_sham_dev *dd);
 200         irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 201
 202         u32             odigest_ofs;
 203         u32             idigest_ofs;
 204         u32             din_ofs;
 205         u32             digcnt_ofs;
 206         u32             rev_ofs;
 207         u32             mask_ofs;
 208         u32             sysstatus_ofs;
 209         u32             mode_ofs;
 210         u32             length_ofs;
 211
 212         u32             major_mask;
 213         u32             major_shift;
 214         u32             minor_mask;
 215         u32             minor_shift;
 216 };
 217
 218 struct omap_sham_dev {
 219         struct list_head        list;
 220         unsigned long           phys_base;
 221         struct device           *dev;
 222         void __iomem            *io_base;
 223         int                     irq;
 224         spinlock_t              lock;
 225         int                     err;
 226         struct dma_chan         *dma_lch;
 227         struct tasklet_struct   done_task;
 228         u8                      polling_mode;
 229         u8                      xmit_buf[BUFLEN];
 230
 231         unsigned long           flags;
 232         struct crypto_queue     queue;
 233         struct ahash_request    *req;
 234
 235         const struct omap_sham_pdata    *pdata;
 236 };
 237
 238 struct omap_sham_drv {
 239         struct list_head        dev_list;
 240         spinlock_t              lock;
 241         unsigned long           flags;
 242 };
 243
 244 static struct omap_sham_drv sham = {
 245         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 246         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 247 };
 248
 249 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 250 {
 251         return __raw_readl(dd->io_base + offset);
 252 }
 253
 254 static inline void omap_sham_write(struct omap_sham_dev *dd,
 255                                         u32 offset, u32 value)
 256 {
 257         __raw_writel(value, dd->io_base + offset);
 258 }
 259
 260 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 261                                         u32 value, u32 mask)
 262 {
 263         u32 val;
 264
 265         val = omap_sham_read(dd, address);
 266         val &= ~mask;
 267         val |= value;
 268         omap_sham_write(dd, address, val);
 269 }
 270
 271 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 272 {
 273         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 274
 275         while (!(omap_sham_read(dd, offset) & bit)) {
 276                 if (time_is_before_jiffies(timeout))
 277                         return -ETIMEDOUT;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 284 {
 285         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 286         struct omap_sham_dev *dd = ctx->dd;
 287         u32 *hash = (u32 *)ctx->digest;
 288         int i;
 289
 290         for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 291                 if (out)
 292                         hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 293                 else
 294                         omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 295         }
 296 }
 297
 298 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 299 {
 300         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 301         struct omap_sham_dev *dd = ctx->dd;
 302         int i;
 303
 304         if (ctx->flags & BIT(FLAGS_HMAC)) {
 305                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 306                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 307                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 308                 u32 *opad = (u32 *)bctx->opad;
 309
 310                 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 311                         if (out)
 312                                 opad[i] = omap_sham_read(dd,
 313                                                 SHA_REG_ODIGEST(dd, i));
 314                         else
 315                                 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 316                                                 opad[i]);
 317                 }
 318         }
 319
 320         omap_sham_copy_hash_omap2(req, out);
 321 }
 322
 323 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 324 {
 325         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 326         u32 *in = (u32 *)ctx->digest;
 327         u32 *hash = (u32 *)req->result;
 328         int i, d, big_endian = 0;
 329
 330         if (!hash)
 331                 return;
 332
 333         switch (ctx->flags & FLAGS_MODE_MASK) {
 334         case FLAGS_MODE_MD5:
 335                 d = MD5_DIGEST_SIZE / sizeof(u32);
 336                 break;
 337         case FLAGS_MODE_SHA1:
 338                 /* OMAP2 SHA1 is big endian */
 339                 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 340                         big_endian = 1;
 341                 d = SHA1_DIGEST_SIZE / sizeof(u32);
 342                 break;
 343         case FLAGS_MODE_SHA224:
 344                 d = SHA224_DIGEST_SIZE / sizeof(u32);
 345                 break;
 346         case FLAGS_MODE_SHA256:
 347                 d = SHA256_DIGEST_SIZE / sizeof(u32);
 348                 break;
 349         case FLAGS_MODE_SHA384:
 350                 d = SHA384_DIGEST_SIZE / sizeof(u32);
 351                 break;
 352         case FLAGS_MODE_SHA512:
 353                 d = SHA512_DIGEST_SIZE / sizeof(u32);
 354                 break;
 355         default:
 356                 d = 0;
 357         }
 358
 359         if (big_endian)
 360                 for (i = 0; i < d; i++)
 361                         hash[i] = be32_to_cpu(in[i]);
 362         else
 363                 for (i = 0; i < d; i++)
 364                         hash[i] = le32_to_cpu(in[i]);
 365 }
 366
 367 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 368 {
 369         int err;
 370
 371         err = pm_runtime_get_sync(dd->dev);
 372         if (err < 0) {
 373                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 374                 return err;
 375         }
 376
 377         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 378                 set_bit(FLAGS_INIT, &dd->flags);
 379                 dd->err = 0;
 380         }
 381
 382         return 0;
 383 }
 384
 385 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 386                                  int final, int dma)
 387 {
 388         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 389         u32 val = length << 5, mask;
 390
 391         if (likely(ctx->digcnt))
 392                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 393
 394         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 395                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 396                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 397         /*
 398          * Setting ALGO_CONST only for the first iteration
 399          * and CLOSE_HASH only for the last one.
 400          */
 401         if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 402                 val |= SHA_REG_CTRL_ALGO;
 403         if (!ctx->digcnt)
 404                 val |= SHA_REG_CTRL_ALGO_CONST;
 405         if (final)
 406                 val |= SHA_REG_CTRL_CLOSE_HASH;
 407
 408         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 409                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 410
 411         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 412 }
 413
 414 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 415 {
 416 }
 417
 418 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 419 {
 420         return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 421 }
 422
 423 static int get_block_size(struct omap_sham_reqctx *ctx)
 424 {
 425         int d;
 426
 427         switch (ctx->flags & FLAGS_MODE_MASK) {
 428         case FLAGS_MODE_MD5:
 429         case FLAGS_MODE_SHA1:
 430                 d = SHA1_BLOCK_SIZE;
 431                 break;
 432         case FLAGS_MODE_SHA224:
 433         case FLAGS_MODE_SHA256:
 434                 d = SHA256_BLOCK_SIZE;
 435                 break;
 436         case FLAGS_MODE_SHA384:
 437         case FLAGS_MODE_SHA512:
 438                 d = SHA512_BLOCK_SIZE;
 439                 break;
 440         default:
 441                 d = 0;
 442         }
 443
 444         return d;
 445 }
 446
 447 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 448                                     u32 *value, int count)
 449 {
 450         for (; count--; value++, offset += 4)
 451                 omap_sham_write(dd, offset, *value);
 452 }
 453
 454 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 455                                  int final, int dma)
 456 {
 457         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 458         u32 val, mask;
 459
 460         /*
 461          * Setting ALGO_CONST only for the first iteration and
 462          * CLOSE_HASH only for the last one. Note that flags mode bits
 463          * correspond to algorithm encoding in mode register.
 464          */
 465         val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 466         if (!ctx->digcnt) {
 467                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 468                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 469                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 470                 int bs, nr_dr;
 471
 472                 val |= SHA_REG_MODE_ALGO_CONSTANT;
 473
 474                 if (ctx->flags & BIT(FLAGS_HMAC)) {
 475                         bs = get_block_size(ctx);
 476                         nr_dr = bs / (2 * sizeof(u32));
 477                         val |= SHA_REG_MODE_HMAC_KEY_PROC;
 478                         omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 479                                           (u32 *)bctx->ipad, nr_dr);
 480                         omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 481                                           (u32 *)bctx->ipad + nr_dr, nr_dr);
 482                         ctx->digcnt += bs;
 483                 }
 484         }
 485
 486         if (final) {
 487                 val |= SHA_REG_MODE_CLOSE_HASH;
 488
 489                 if (ctx->flags & BIT(FLAGS_HMAC))
 490                         val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 491         }
 492
 493         mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 494                SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 495                SHA_REG_MODE_HMAC_KEY_PROC;
 496
 497         dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 498         omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 499         omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 500         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 501                              SHA_REG_MASK_IT_EN |
 502                                      (dma ? SHA_REG_MASK_DMA_EN : 0),
 503                              SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 504 }
 505
 506 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 507 {
 508         omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 509 }
 510
 511 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 512 {
 513         return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 514                               SHA_REG_IRQSTATUS_INPUT_RDY);
 515 }
 516
 517 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
 518                               int final)
 519 {
 520         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 521         int count, len32, bs32, offset = 0;
 522         const u32 *buffer;
 523         int mlen;
 524         struct sg_mapping_iter mi;
 525
 526         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 527                                                 ctx->digcnt, length, final);
 528
 529         dd->pdata->write_ctrl(dd, length, final, 0);
 530         dd->pdata->trigger(dd, length);
 531
 532         /* should be non-zero before next lines to disable clocks later */
 533         ctx->digcnt += length;
 534         ctx->total -= length;
 535
 536         if (final)
 537                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 538
 539         set_bit(FLAGS_CPU, &dd->flags);
 540
 541         len32 = DIV_ROUND_UP(length, sizeof(u32));
 542         bs32 = get_block_size(ctx) / sizeof(u32);
 543
 544         sg_miter_start(&mi, ctx->sg, ctx->sg_len,
 545                        SG_MITER_FROM_SG | SG_MITER_ATOMIC);
 546
 547         mlen = 0;
 548
 549         while (len32) {
 550                 if (dd->pdata->poll_irq(dd))
 551                         return -ETIMEDOUT;
 552
 553                 for (count = 0; count < min(len32, bs32); count++, offset++) {
 554                         if (!mlen) {
 555                                 sg_miter_next(&mi);
 556                                 mlen = mi.length;
 557                                 if (!mlen) {
 558                                         pr_err("sg miter failure.\n");
 559                                         return -EINVAL;
 560                                 }
 561                                 offset = 0;
 562                                 buffer = mi.addr;
 563                         }
 564                         omap_sham_write(dd, SHA_REG_DIN(dd, count),
 565                                         buffer[offset]);
 566                         mlen -= 4;
 567                 }
 568                 len32 -= min(len32, bs32);
 569         }
 570
 571         sg_miter_stop(&mi);
 572
 573         return -EINPROGRESS;
 574 }
 575
 576 static void omap_sham_dma_callback(void *param)
 577 {
 578         struct omap_sham_dev *dd = param;
 579
 580         set_bit(FLAGS_DMA_READY, &dd->flags);
 581         tasklet_schedule(&dd->done_task);
 582 }
 583
 584 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
 585                               int final)
 586 {
 587         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 588         struct dma_async_tx_descriptor *tx;
 589         struct dma_slave_config cfg;
 590         int ret;
 591
 592         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 593                                                 ctx->digcnt, length, final);
 594
 595         if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
 596                 dev_err(dd->dev, "dma_map_sg error\n");
 597                 return -EINVAL;
 598         }
 599
 600         memset(&cfg, 0, sizeof(cfg));
 601
 602         cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 603         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 604         cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
 605
 606         ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 607         if (ret) {
 608                 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 609                 return ret;
 610         }
 611
 612         tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
 613                                      DMA_MEM_TO_DEV,
 614                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 615
 616         if (!tx) {
 617                 dev_err(dd->dev, "prep_slave_sg failed\n");
 618                 return -EINVAL;
 619         }
 620
 621         tx->callback = omap_sham_dma_callback;
 622         tx->callback_param = dd;
 623
 624         dd->pdata->write_ctrl(dd, length, final, 1);
 625
 626         ctx->digcnt += length;
 627         ctx->total -= length;
 628
 629         if (final)
 630                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 631
 632         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 633
 634         dmaengine_submit(tx);
 635         dma_async_issue_pending(dd->dma_lch);
 636
 637         dd->pdata->trigger(dd, length);
 638
 639         return -EINPROGRESS;
 640 }
 641
 642 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
 643                                    struct scatterlist *sg, int bs, int new_len)
 644 {
 645         int n = sg_nents(sg);
 646         struct scatterlist *tmp;
 647         int offset = ctx->offset;
 648
 649         if (ctx->bufcnt)
 650                 n++;
 651
 652         ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
 653         if (!ctx->sg)
 654                 return -ENOMEM;
 655
 656         sg_init_table(ctx->sg, n);
 657
 658         tmp = ctx->sg;
 659
 660         ctx->sg_len = 0;
 661
 662         if (ctx->bufcnt) {
 663                 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
 664                 tmp = sg_next(tmp);
 665                 ctx->sg_len++;
 666         }
 667
 668         while (sg && new_len) {
 669                 int len = sg->length - offset;
 670
 671                 if (offset) {
 672                         offset -= sg->length;
 673                         if (offset < 0)
 674                                 offset = 0;
 675                 }
 676
 677                 if (new_len < len)
 678                         len = new_len;
 679
 680                 if (len > 0) {
 681                         new_len -= len;
 682                         sg_set_page(tmp, sg_page(sg), len, sg->offset);
 683                         if (new_len <= 0)
 684                                 sg_mark_end(tmp);
 685                         tmp = sg_next(tmp);
 686                         ctx->sg_len++;
 687                 }
 688
 689                 sg = sg_next(sg);
 690         }
 691
 692         set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
 693
 694         ctx->bufcnt = 0;
 695
 696         return 0;
 697 }
 698
 699 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
 700                               struct scatterlist *sg, int bs, int new_len)
 701 {
 702         int pages;
 703         void *buf;
 704         int len;
 705
 706         len = new_len + ctx->bufcnt;
 707
 708         pages = get_order(ctx->total);
 709
 710         buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
 711         if (!buf) {
 712                 pr_err("Couldn't allocate pages for unaligned cases.\n");
 713                 return -ENOMEM;
 714         }
 715
 716         if (ctx->bufcnt)
 717                 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
 718
 719         scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
 720                                  ctx->total - ctx->bufcnt, 0);
 721         sg_init_table(ctx->sgl, 1);
 722         sg_set_buf(ctx->sgl, buf, len);
 723         ctx->sg = ctx->sgl;
 724         set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
 725         ctx->sg_len = 1;
 726         ctx->bufcnt = 0;
 727         ctx->offset = 0;
 728
 729         return 0;
 730 }
 731
 732 static int omap_sham_align_sgs(struct scatterlist *sg,
 733                                int nbytes, int bs, bool final,
 734                                struct omap_sham_reqctx *rctx)
 735 {
 736         int n = 0;
 737         bool aligned = true;
 738         bool list_ok = true;
 739         struct scatterlist *sg_tmp = sg;
 740         int new_len;
 741         int offset = rctx->offset;
 742
 743         if (!sg || !sg->length || !nbytes)
 744                 return 0;
 745
 746         new_len = nbytes;
 747
 748         if (offset)
 749                 list_ok = false;
 750
 751         if (final)
 752                 new_len = DIV_ROUND_UP(new_len, bs) * bs;
 753         else
 754                 new_len = new_len / bs * bs;
 755
 756         while (nbytes > 0 && sg_tmp) {
 757                 n++;
 758
 759                 if (offset < sg_tmp->length) {
 760                         if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
 761                                 aligned = false;
 762                                 break;
 763                         }
 764
 765                         if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
 766                                 aligned = false;
 767                                 break;
 768                         }
 769                 }
 770
 771                 if (offset) {
 772                         offset -= sg_tmp->length;
 773                         if (offset < 0) {
 774                                 nbytes += offset;
 775                                 offset = 0;
 776                         }
 777                 } else {
 778                         nbytes -= sg_tmp->length;
 779                 }
 780
 781                 sg_tmp = sg_next(sg_tmp);
 782
 783                 if (nbytes < 0) {
 784                         list_ok = false;
 785                         break;
 786                 }
 787         }
 788
 789         if (!aligned)
 790                 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
 791         else if (!list_ok)
 792                 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
 793
 794         rctx->sg_len = n;
 795         rctx->sg = sg;
 796
 797         return 0;
 798 }
 799
 800 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
 801 {
 802         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
 803         int bs;
 804         int ret;
 805         int nbytes;
 806         bool final = rctx->flags & BIT(FLAGS_FINUP);
 807         int xmit_len, hash_later;
 808
 809         if (!req)
 810                 return 0;
 811
 812         bs = get_block_size(rctx);
 813
 814         if (update)
 815                 nbytes = req->nbytes;
 816         else
 817                 nbytes = 0;
 818
 819         rctx->total = nbytes + rctx->bufcnt;
 820
 821         if (!rctx->total)
 822                 return 0;
 823
 824         if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
 825                 int len = bs - rctx->bufcnt % bs;
 826
 827                 if (len > nbytes)
 828                         len = nbytes;
 829                 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
 830                                          0, len, 0);
 831                 rctx->bufcnt += len;
 832                 nbytes -= len;
 833                 rctx->offset = len;
 834         }
 835
 836         if (rctx->bufcnt)
 837                 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
 838
 839         ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
 840         if (ret)
 841                 return ret;
 842
 843         xmit_len = rctx->total;
 844
 845         if (!IS_ALIGNED(xmit_len, bs)) {
 846                 if (final)
 847                         xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
 848                 else
 849                         xmit_len = xmit_len / bs * bs;
 850         }
 851
 852         hash_later = rctx->total - xmit_len;
 853         if (hash_later < 0)
 854                 hash_later = 0;
 855
 856         if (rctx->bufcnt && nbytes) {
 857                 /* have data from previous operation and current */
 858                 sg_init_table(rctx->sgl, 2);
 859                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
 860
 861                 sg_chain(rctx->sgl, 2, req->src);
 862
 863                 rctx->sg = rctx->sgl;
 864
 865                 rctx->sg_len++;
 866         } else if (rctx->bufcnt) {
 867                 /* have buffered data only */
 868                 sg_init_table(rctx->sgl, 1);
 869                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
 870
 871                 rctx->sg = rctx->sgl;
 872
 873                 rctx->sg_len = 1;
 874         }
 875
 876         if (hash_later) {
 877                 int offset = 0;
 878
 879                 if (hash_later > req->nbytes) {
 880                         memcpy(rctx->buffer, rctx->buffer + xmit_len,
 881                                hash_later - req->nbytes);
 882                         offset = hash_later - req->nbytes;
 883                 }
 884
 885                 if (req->nbytes) {
 886                         scatterwalk_map_and_copy(rctx->buffer + offset,
 887                                                  req->src,
 888                                                  offset + req->nbytes -
 889                                                  hash_later, hash_later, 0);
 890                 }
 891
 892                 rctx->bufcnt = hash_later;
 893         } else {
 894                 rctx->bufcnt = 0;
 895         }
 896
 897         if (!final)
 898                 rctx->total = xmit_len;
 899
 900         return 0;
 901 }
 902
 903 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 904 {
 905         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 906
 907         dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
 908
 909         clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 910
 911         return 0;
 912 }
 913
 914 static int omap_sham_init(struct ahash_request *req)
 915 {
 916         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 917         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 918         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 919         struct omap_sham_dev *dd = NULL, *tmp;
 920         int bs = 0;
 921
 922         spin_lock_bh(&sham.lock);
 923         if (!tctx->dd) {
 924                 list_for_each_entry(tmp, &sham.dev_list, list) {
 925                         dd = tmp;
 926                         break;
 927                 }
 928                 tctx->dd = dd;
 929         } else {
 930                 dd = tctx->dd;
 931         }
 932         spin_unlock_bh(&sham.lock);
 933
 934         ctx->dd = dd;
 935
 936         ctx->flags = 0;
 937
 938         dev_dbg(dd->dev, "init: digest size: %d\n",
 939                 crypto_ahash_digestsize(tfm));
 940
 941         switch (crypto_ahash_digestsize(tfm)) {
 942         case MD5_DIGEST_SIZE:
 943                 ctx->flags |= FLAGS_MODE_MD5;
 944                 bs = SHA1_BLOCK_SIZE;
 945                 break;
 946         case SHA1_DIGEST_SIZE:
 947                 ctx->flags |= FLAGS_MODE_SHA1;
 948                 bs = SHA1_BLOCK_SIZE;
 949                 break;
 950         case SHA224_DIGEST_SIZE:
 951                 ctx->flags |= FLAGS_MODE_SHA224;
 952                 bs = SHA224_BLOCK_SIZE;
 953                 break;
 954         case SHA256_DIGEST_SIZE:
 955                 ctx->flags |= FLAGS_MODE_SHA256;
 956                 bs = SHA256_BLOCK_SIZE;
 957                 break;
 958         case SHA384_DIGEST_SIZE:
 959                 ctx->flags |= FLAGS_MODE_SHA384;
 960                 bs = SHA384_BLOCK_SIZE;
 961                 break;
 962         case SHA512_DIGEST_SIZE:
 963                 ctx->flags |= FLAGS_MODE_SHA512;
 964                 bs = SHA512_BLOCK_SIZE;
 965                 break;
 966         }
 967
 968         ctx->bufcnt = 0;
 969         ctx->digcnt = 0;
 970         ctx->total = 0;
 971         ctx->offset = 0;
 972         ctx->buflen = BUFLEN;
 973
 974         if (tctx->flags & BIT(FLAGS_HMAC)) {
 975                 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 976                         struct omap_sham_hmac_ctx *bctx = tctx->base;
 977
 978                         memcpy(ctx->buffer, bctx->ipad, bs);
 979                         ctx->bufcnt = bs;
 980                 }
 981
 982                 ctx->flags |= BIT(FLAGS_HMAC);
 983         }
 984
 985         return 0;
 986
 987 }
 988
 989 static int omap_sham_update_req(struct omap_sham_dev *dd)
 990 {
 991         struct ahash_request *req = dd->req;
 992         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 993         int err;
 994         bool final = ctx->flags & BIT(FLAGS_FINUP);
 995
 996         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
 997                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
 998
 999         if (ctx->total < get_block_size(ctx) ||
1000             ctx->total < OMAP_SHA_DMA_THRESHOLD)
1001                 ctx->flags |= BIT(FLAGS_CPU);
1002
1003         if (ctx->flags & BIT(FLAGS_CPU))
1004                 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1005         else
1006                 err = omap_sham_xmit_dma(dd, ctx->total, final);
1007
1008         /* wait for dma completion before can take more data */
1009         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1010
1011         return err;
1012 }
1013
1014 static int omap_sham_final_req(struct omap_sham_dev *dd)
1015 {
1016         struct ahash_request *req = dd->req;
1017         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1018         int err = 0, use_dma = 1;
1019
1020         if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1021                 /*
1022                  * faster to handle last block with cpu or
1023                  * use cpu when dma is not present.
1024                  */
1025                 use_dma = 0;
1026
1027         if (use_dma)
1028                 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1029         else
1030                 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1031
1032         ctx->bufcnt = 0;
1033
1034         dev_dbg(dd->dev, "final_req: err: %d\n", err);
1035
1036         return err;
1037 }
1038
1039 static int omap_sham_finish_hmac(struct ahash_request *req)
1040 {
1041         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1042         struct omap_sham_hmac_ctx *bctx = tctx->base;
1043         int bs = crypto_shash_blocksize(bctx->shash);
1044         int ds = crypto_shash_digestsize(bctx->shash);
1045         SHASH_DESC_ON_STACK(shash, bctx->shash);
1046
1047         shash->tfm = bctx->shash;
1048         shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
1049
1050         return crypto_shash_init(shash) ?:
1051                crypto_shash_update(shash, bctx->opad, bs) ?:
1052                crypto_shash_finup(shash, req->result, ds, req->result);
1053 }
1054
1055 static int omap_sham_finish(struct ahash_request *req)
1056 {
1057         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1058         struct omap_sham_dev *dd = ctx->dd;
1059         int err = 0;
1060
1061         if (ctx->digcnt) {
1062                 omap_sham_copy_ready_hash(req);
1063                 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1064                                 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1065                         err = omap_sham_finish_hmac(req);
1066         }
1067
1068         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1069
1070         return err;
1071 }
1072
1073 static void omap_sham_finish_req(struct ahash_request *req, int err)
1074 {
1075         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1076         struct omap_sham_dev *dd = ctx->dd;
1077
1078         if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1079                 free_pages((unsigned long)sg_virt(ctx->sg),
1080                            get_order(ctx->sg->length));
1081
1082         if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1083                 kfree(ctx->sg);
1084
1085         ctx->sg = NULL;
1086
1087         dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1088
1089         if (!err) {
1090                 dd->pdata->copy_hash(req, 1);
1091                 if (test_bit(FLAGS_FINAL, &dd->flags))
1092                         err = omap_sham_finish(req);
1093         } else {
1094                 ctx->flags |= BIT(FLAGS_ERROR);
1095         }
1096
1097         /* atomic operation is not needed here */
1098         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1099                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1100
1101         pm_runtime_mark_last_busy(dd->dev);
1102         pm_runtime_put_autosuspend(dd->dev);
1103
1104         if (req->base.complete)
1105                 req->base.complete(&req->base, err);
1106 }
1107
1108 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1109                                   struct ahash_request *req)
1110 {
1111         struct crypto_async_request *async_req, *backlog;
1112         struct omap_sham_reqctx *ctx;
1113         unsigned long flags;
1114         int err = 0, ret = 0;
1115
1116 retry:
1117         spin_lock_irqsave(&dd->lock, flags);
1118         if (req)
1119                 ret = ahash_enqueue_request(&dd->queue, req);
1120         if (test_bit(FLAGS_BUSY, &dd->flags)) {
1121                 spin_unlock_irqrestore(&dd->lock, flags);
1122                 return ret;
1123         }
1124         backlog = crypto_get_backlog(&dd->queue);
1125         async_req = crypto_dequeue_request(&dd->queue);
1126         if (async_req)
1127                 set_bit(FLAGS_BUSY, &dd->flags);
1128         spin_unlock_irqrestore(&dd->lock, flags);
1129
1130         if (!async_req)
1131                 return ret;
1132
1133         if (backlog)
1134                 backlog->complete(backlog, -EINPROGRESS);
1135
1136         req = ahash_request_cast(async_req);
1137         dd->req = req;
1138         ctx = ahash_request_ctx(req);
1139
1140         err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1141         if (err)
1142                 goto err1;
1143
1144         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1145                                                 ctx->op, req->nbytes);
1146
1147         err = omap_sham_hw_init(dd);
1148         if (err)
1149                 goto err1;
1150
1151         if (ctx->digcnt)
1152                 /* request has changed - restore hash */
1153                 dd->pdata->copy_hash(req, 0);
1154
1155         if (ctx->op == OP_UPDATE) {
1156                 err = omap_sham_update_req(dd);
1157                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1158                         /* no final() after finup() */
1159                         err = omap_sham_final_req(dd);
1160         } else if (ctx->op == OP_FINAL) {
1161                 err = omap_sham_final_req(dd);
1162         }
1163 err1:
1164         dev_dbg(dd->dev, "exit, err: %d\n", err);
1165
1166         if (err != -EINPROGRESS) {
1167                 /* done_task will not finish it, so do it here */
1168                 omap_sham_finish_req(req, err);
1169                 req = NULL;
1170
1171                 /*
1172                  * Execute next request immediately if there is anything
1173                  * in queue.
1174                  */
1175                 goto retry;
1176         }
1177
1178         return ret;
1179 }
1180
1181 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1182 {
1183         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1184         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1185         struct omap_sham_dev *dd = tctx->dd;
1186
1187         ctx->op = op;
1188
1189         return omap_sham_handle_queue(dd, req);
1190 }
1191
1192 static int omap_sham_update(struct ahash_request *req)
1193 {
1194         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1195         struct omap_sham_dev *dd = ctx->dd;
1196
1197         if (!req->nbytes)
1198                 return 0;
1199
1200         if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1201                 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1202                                          0, req->nbytes, 0);
1203                 ctx->bufcnt += req->nbytes;
1204                 return 0;
1205         }
1206
1207         if (dd->polling_mode)
1208                 ctx->flags |= BIT(FLAGS_CPU);
1209
1210         return omap_sham_enqueue(req, OP_UPDATE);
1211 }
1212
1213 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1214                                   const u8 *data, unsigned int len, u8 *out)
1215 {
1216         SHASH_DESC_ON_STACK(shash, tfm);
1217
1218         shash->tfm = tfm;
1219         shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1220
1221         return crypto_shash_digest(shash, data, len, out);
1222 }
1223
1224 static int omap_sham_final_shash(struct ahash_request *req)
1225 {
1226         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1227         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1228         int offset = 0;
1229
1230         /*
1231          * If we are running HMAC on limited hardware support, skip
1232          * the ipad in the beginning of the buffer if we are going for
1233          * software fallback algorithm.
1234          */
1235         if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1236             !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1237                 offset = get_block_size(ctx);
1238
1239         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1240                                       ctx->buffer + offset,
1241                                       ctx->bufcnt - offset, req->result);
1242 }
1243
1244 static int omap_sham_final(struct ahash_request *req)
1245 {
1246         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1247
1248         ctx->flags |= BIT(FLAGS_FINUP);
1249
1250         if (ctx->flags & BIT(FLAGS_ERROR))
1251                 return 0; /* uncompleted hash is not needed */
1252
1253         /*
1254          * OMAP HW accel works only with buffers >= 9.
1255          * HMAC is always >= 9 because ipad == block size.
1256          * If buffersize is less than DMA_THRESHOLD, we use fallback
1257          * SW encoding, as using DMA + HW in this case doesn't provide
1258          * any benefit.
1259          */
1260         if (!ctx->digcnt && ctx->bufcnt < OMAP_SHA_DMA_THRESHOLD)
1261                 return omap_sham_final_shash(req);
1262         else if (ctx->bufcnt)
1263                 return omap_sham_enqueue(req, OP_FINAL);
1264
1265         /* copy ready hash (+ finalize hmac) */
1266         return omap_sham_finish(req);
1267 }
1268
1269 static int omap_sham_finup(struct ahash_request *req)
1270 {
1271         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1272         int err1, err2;
1273
1274         ctx->flags |= BIT(FLAGS_FINUP);
1275
1276         err1 = omap_sham_update(req);
1277         if (err1 == -EINPROGRESS || err1 == -EBUSY)
1278                 return err1;
1279         /*
1280          * final() has to be always called to cleanup resources
1281          * even if udpate() failed, except EINPROGRESS
1282          */
1283         err2 = omap_sham_final(req);
1284
1285         return err1 ?: err2;
1286 }
1287
1288 static int omap_sham_digest(struct ahash_request *req)
1289 {
1290         return omap_sham_init(req) ?: omap_sham_finup(req);
1291 }
1292
1293 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1294                       unsigned int keylen)
1295 {
1296         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1297         struct omap_sham_hmac_ctx *bctx = tctx->base;
1298         int bs = crypto_shash_blocksize(bctx->shash);
1299         int ds = crypto_shash_digestsize(bctx->shash);
1300         struct omap_sham_dev *dd = NULL, *tmp;
1301         int err, i;
1302
1303         spin_lock_bh(&sham.lock);
1304         if (!tctx->dd) {
1305                 list_for_each_entry(tmp, &sham.dev_list, list) {
1306                         dd = tmp;
1307                         break;
1308                 }
1309                 tctx->dd = dd;
1310         } else {
1311                 dd = tctx->dd;
1312         }
1313         spin_unlock_bh(&sham.lock);
1314
1315         err = crypto_shash_setkey(tctx->fallback, key, keylen);
1316         if (err)
1317                 return err;
1318
1319         if (keylen > bs) {
1320                 err = omap_sham_shash_digest(bctx->shash,
1321                                 crypto_shash_get_flags(bctx->shash),
1322                                 key, keylen, bctx->ipad);
1323                 if (err)
1324                         return err;
1325                 keylen = ds;
1326         } else {
1327                 memcpy(bctx->ipad, key, keylen);
1328         }
1329
1330         memset(bctx->ipad + keylen, 0, bs - keylen);
1331
1332         if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1333                 memcpy(bctx->opad, bctx->ipad, bs);
1334
1335                 for (i = 0; i < bs; i++) {
1336                         bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1337                         bctx->opad[i] ^= HMAC_OPAD_VALUE;
1338                 }
1339         }
1340
1341         return err;
1342 }
1343
1344 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1345 {
1346         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1347         const char *alg_name = crypto_tfm_alg_name(tfm);
1348
1349         /* Allocate a fallback and abort if it failed. */
1350         tctx->fallback = crypto_alloc_shash(alg_name, 0,
1351                                             CRYPTO_ALG_NEED_FALLBACK);
1352         if (IS_ERR(tctx->fallback)) {
1353                 pr_err("omap-sham: fallback driver '%s' "
1354                                 "could not be loaded.\n", alg_name);
1355                 return PTR_ERR(tctx->fallback);
1356         }
1357
1358         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1359                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
1360
1361         if (alg_base) {
1362                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1363                 tctx->flags |= BIT(FLAGS_HMAC);
1364                 bctx->shash = crypto_alloc_shash(alg_base, 0,
1365                                                 CRYPTO_ALG_NEED_FALLBACK);
1366                 if (IS_ERR(bctx->shash)) {
1367                         pr_err("omap-sham: base driver '%s' "
1368                                         "could not be loaded.\n", alg_base);
1369                         crypto_free_shash(tctx->fallback);
1370                         return PTR_ERR(bctx->shash);
1371                 }
1372
1373         }
1374
1375         return 0;
1376 }
1377
1378 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1379 {
1380         return omap_sham_cra_init_alg(tfm, NULL);
1381 }
1382
1383 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1384 {
1385         return omap_sham_cra_init_alg(tfm, "sha1");
1386 }
1387
1388 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1389 {
1390         return omap_sham_cra_init_alg(tfm, "sha224");
1391 }
1392
1393 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1394 {
1395         return omap_sham_cra_init_alg(tfm, "sha256");
1396 }
1397
1398 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1399 {
1400         return omap_sham_cra_init_alg(tfm, "md5");
1401 }
1402
1403 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1404 {
1405         return omap_sham_cra_init_alg(tfm, "sha384");
1406 }
1407
1408 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1409 {
1410         return omap_sham_cra_init_alg(tfm, "sha512");
1411 }
1412
1413 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1414 {
1415         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1416
1417         crypto_free_shash(tctx->fallback);
1418         tctx->fallback = NULL;
1419
1420         if (tctx->flags & BIT(FLAGS_HMAC)) {
1421                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1422                 crypto_free_shash(bctx->shash);
1423         }
1424 }
1425
1426 static int omap_sham_export(struct ahash_request *req, void *out)
1427 {
1428         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1429
1430         memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1431
1432         return 0;
1433 }
1434
1435 static int omap_sham_import(struct ahash_request *req, const void *in)
1436 {
1437         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1438         const struct omap_sham_reqctx *ctx_in = in;
1439
1440         memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1441
1442         return 0;
1443 }
1444
1445 static struct ahash_alg algs_sha1_md5[] = {
1446 {
1447         .init           = omap_sham_init,
1448         .update         = omap_sham_update,
1449         .final          = omap_sham_final,
1450         .finup          = omap_sham_finup,
1451         .digest         = omap_sham_digest,
1452         .halg.digestsize        = SHA1_DIGEST_SIZE,
1453         .halg.base      = {
1454                 .cra_name               = "sha1",
1455                 .cra_driver_name        = "omap-sha1",
1456                 .cra_priority           = 400,
1457                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1458                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1459                                                 CRYPTO_ALG_ASYNC |
1460                                                 CRYPTO_ALG_NEED_FALLBACK,
1461                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1462                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1463                 .cra_alignmask          = OMAP_ALIGN_MASK,
1464                 .cra_module             = THIS_MODULE,
1465                 .cra_init               = omap_sham_cra_init,
1466                 .cra_exit               = omap_sham_cra_exit,
1467         }
1468 },
1469 {
1470         .init           = omap_sham_init,
1471         .update         = omap_sham_update,
1472         .final          = omap_sham_final,
1473         .finup          = omap_sham_finup,
1474         .digest         = omap_sham_digest,
1475         .halg.digestsize        = MD5_DIGEST_SIZE,
1476         .halg.base      = {
1477                 .cra_name               = "md5",
1478                 .cra_driver_name        = "omap-md5",
1479                 .cra_priority           = 400,
1480                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1481                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1482                                                 CRYPTO_ALG_ASYNC |
1483                                                 CRYPTO_ALG_NEED_FALLBACK,
1484                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1485                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1486                 .cra_alignmask          = OMAP_ALIGN_MASK,
1487                 .cra_module             = THIS_MODULE,
1488                 .cra_init               = omap_sham_cra_init,
1489                 .cra_exit               = omap_sham_cra_exit,
1490         }
1491 },
1492 {
1493         .init           = omap_sham_init,
1494         .update         = omap_sham_update,
1495         .final          = omap_sham_final,
1496         .finup          = omap_sham_finup,
1497         .digest         = omap_sham_digest,
1498         .setkey         = omap_sham_setkey,
1499         .halg.digestsize        = SHA1_DIGEST_SIZE,
1500         .halg.base      = {
1501                 .cra_name               = "hmac(sha1)",
1502                 .cra_driver_name        = "omap-hmac-sha1",
1503                 .cra_priority           = 400,
1504                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1505                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1506                                                 CRYPTO_ALG_ASYNC |
1507                                                 CRYPTO_ALG_NEED_FALLBACK,
1508                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1509                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1510                                         sizeof(struct omap_sham_hmac_ctx),
1511                 .cra_alignmask          = OMAP_ALIGN_MASK,
1512                 .cra_module             = THIS_MODULE,
1513                 .cra_init               = omap_sham_cra_sha1_init,
1514                 .cra_exit               = omap_sham_cra_exit,
1515         }
1516 },
1517 {
1518         .init           = omap_sham_init,
1519         .update         = omap_sham_update,
1520         .final          = omap_sham_final,
1521         .finup          = omap_sham_finup,
1522         .digest         = omap_sham_digest,
1523         .setkey         = omap_sham_setkey,
1524         .halg.digestsize        = MD5_DIGEST_SIZE,
1525         .halg.base      = {
1526                 .cra_name               = "hmac(md5)",
1527                 .cra_driver_name        = "omap-hmac-md5",
1528                 .cra_priority           = 400,
1529                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1530                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1531                                                 CRYPTO_ALG_ASYNC |
1532                                                 CRYPTO_ALG_NEED_FALLBACK,
1533                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1534                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1535                                         sizeof(struct omap_sham_hmac_ctx),
1536                 .cra_alignmask          = OMAP_ALIGN_MASK,
1537                 .cra_module             = THIS_MODULE,
1538                 .cra_init               = omap_sham_cra_md5_init,
1539                 .cra_exit               = omap_sham_cra_exit,
1540         }
1541 }
1542 };
1543
1544 /* OMAP4 has some algs in addition to what OMAP2 has */
1545 static struct ahash_alg algs_sha224_sha256[] = {
1546 {
1547         .init           = omap_sham_init,
1548         .update         = omap_sham_update,
1549         .final          = omap_sham_final,
1550         .finup          = omap_sham_finup,
1551         .digest         = omap_sham_digest,
1552         .halg.digestsize        = SHA224_DIGEST_SIZE,
1553         .halg.base      = {
1554                 .cra_name               = "sha224",
1555                 .cra_driver_name        = "omap-sha224",
1556                 .cra_priority           = 400,
1557                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1558                                                 CRYPTO_ALG_ASYNC |
1559                                                 CRYPTO_ALG_NEED_FALLBACK,
1560                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1561                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1562                 .cra_alignmask          = OMAP_ALIGN_MASK,
1563                 .cra_module             = THIS_MODULE,
1564                 .cra_init               = omap_sham_cra_init,
1565                 .cra_exit               = omap_sham_cra_exit,
1566         }
1567 },
1568 {
1569         .init           = omap_sham_init,
1570         .update         = omap_sham_update,
1571         .final          = omap_sham_final,
1572         .finup          = omap_sham_finup,
1573         .digest         = omap_sham_digest,
1574         .halg.digestsize        = SHA256_DIGEST_SIZE,
1575         .halg.base      = {
1576                 .cra_name               = "sha256",
1577                 .cra_driver_name        = "omap-sha256",
1578                 .cra_priority           = 400,
1579                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1580                                                 CRYPTO_ALG_ASYNC |
1581                                                 CRYPTO_ALG_NEED_FALLBACK,
1582                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1583                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1584                 .cra_alignmask          = OMAP_ALIGN_MASK,
1585                 .cra_module             = THIS_MODULE,
1586                 .cra_init               = omap_sham_cra_init,
1587                 .cra_exit               = omap_sham_cra_exit,
1588         }
1589 },
1590 {
1591         .init           = omap_sham_init,
1592         .update         = omap_sham_update,
1593         .final          = omap_sham_final,
1594         .finup          = omap_sham_finup,
1595         .digest         = omap_sham_digest,
1596         .setkey         = omap_sham_setkey,
1597         .halg.digestsize        = SHA224_DIGEST_SIZE,
1598         .halg.base      = {
1599                 .cra_name               = "hmac(sha224)",
1600                 .cra_driver_name        = "omap-hmac-sha224",
1601                 .cra_priority           = 400,
1602                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1603                                                 CRYPTO_ALG_ASYNC |
1604                                                 CRYPTO_ALG_NEED_FALLBACK,
1605                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1606                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1607                                         sizeof(struct omap_sham_hmac_ctx),
1608                 .cra_alignmask          = OMAP_ALIGN_MASK,
1609                 .cra_module             = THIS_MODULE,
1610                 .cra_init               = omap_sham_cra_sha224_init,
1611                 .cra_exit               = omap_sham_cra_exit,
1612         }
1613 },
1614 {
1615         .init           = omap_sham_init,
1616         .update         = omap_sham_update,
1617         .final          = omap_sham_final,
1618         .finup          = omap_sham_finup,
1619         .digest         = omap_sham_digest,
1620         .setkey         = omap_sham_setkey,
1621         .halg.digestsize        = SHA256_DIGEST_SIZE,
1622         .halg.base      = {
1623                 .cra_name               = "hmac(sha256)",
1624                 .cra_driver_name        = "omap-hmac-sha256",
1625                 .cra_priority           = 400,
1626                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1627                                                 CRYPTO_ALG_ASYNC |
1628                                                 CRYPTO_ALG_NEED_FALLBACK,
1629                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1630                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1631                                         sizeof(struct omap_sham_hmac_ctx),
1632                 .cra_alignmask          = OMAP_ALIGN_MASK,
1633                 .cra_module             = THIS_MODULE,
1634                 .cra_init               = omap_sham_cra_sha256_init,
1635                 .cra_exit               = omap_sham_cra_exit,
1636         }
1637 },
1638 };
1639
1640 static struct ahash_alg algs_sha384_sha512[] = {
1641 {
1642         .init           = omap_sham_init,
1643         .update         = omap_sham_update,
1644         .final          = omap_sham_final,
1645         .finup          = omap_sham_finup,
1646         .digest         = omap_sham_digest,
1647         .halg.digestsize        = SHA384_DIGEST_SIZE,
1648         .halg.base      = {
1649                 .cra_name               = "sha384",
1650                 .cra_driver_name        = "omap-sha384",
1651                 .cra_priority           = 400,
1652                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1653                                                 CRYPTO_ALG_ASYNC |
1654                                                 CRYPTO_ALG_NEED_FALLBACK,
1655                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1656                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1657                 .cra_alignmask          = OMAP_ALIGN_MASK,
1658                 .cra_module             = THIS_MODULE,
1659                 .cra_init               = omap_sham_cra_init,
1660                 .cra_exit               = omap_sham_cra_exit,
1661         }
1662 },
1663 {
1664         .init           = omap_sham_init,
1665         .update         = omap_sham_update,
1666         .final          = omap_sham_final,
1667         .finup          = omap_sham_finup,
1668         .digest         = omap_sham_digest,
1669         .halg.digestsize        = SHA512_DIGEST_SIZE,
1670         .halg.base      = {
1671                 .cra_name               = "sha512",
1672                 .cra_driver_name        = "omap-sha512",
1673                 .cra_priority           = 400,
1674                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1675                                                 CRYPTO_ALG_ASYNC |
1676                                                 CRYPTO_ALG_NEED_FALLBACK,
1677                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1678                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1679                 .cra_alignmask          = OMAP_ALIGN_MASK,
1680                 .cra_module             = THIS_MODULE,
1681                 .cra_init               = omap_sham_cra_init,
1682                 .cra_exit               = omap_sham_cra_exit,
1683         }
1684 },
1685 {
1686         .init           = omap_sham_init,
1687         .update         = omap_sham_update,
1688         .final          = omap_sham_final,
1689         .finup          = omap_sham_finup,
1690         .digest         = omap_sham_digest,
1691         .setkey         = omap_sham_setkey,
1692         .halg.digestsize        = SHA384_DIGEST_SIZE,
1693         .halg.base      = {
1694                 .cra_name               = "hmac(sha384)",
1695                 .cra_driver_name        = "omap-hmac-sha384",
1696                 .cra_priority           = 400,
1697                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1698                                                 CRYPTO_ALG_ASYNC |
1699                                                 CRYPTO_ALG_NEED_FALLBACK,
1700                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1701                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1702                                         sizeof(struct omap_sham_hmac_ctx),
1703                 .cra_alignmask          = OMAP_ALIGN_MASK,
1704                 .cra_module             = THIS_MODULE,
1705                 .cra_init               = omap_sham_cra_sha384_init,
1706                 .cra_exit               = omap_sham_cra_exit,
1707         }
1708 },
1709 {
1710         .init           = omap_sham_init,
1711         .update         = omap_sham_update,
1712         .final          = omap_sham_final,
1713         .finup          = omap_sham_finup,
1714         .digest         = omap_sham_digest,
1715         .setkey         = omap_sham_setkey,
1716         .halg.digestsize        = SHA512_DIGEST_SIZE,
1717         .halg.base      = {
1718                 .cra_name               = "hmac(sha512)",
1719                 .cra_driver_name        = "omap-hmac-sha512",
1720                 .cra_priority           = 400,
1721                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1722                                                 CRYPTO_ALG_ASYNC |
1723                                                 CRYPTO_ALG_NEED_FALLBACK,
1724                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1725                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1726                                         sizeof(struct omap_sham_hmac_ctx),
1727                 .cra_alignmask          = OMAP_ALIGN_MASK,
1728                 .cra_module             = THIS_MODULE,
1729                 .cra_init               = omap_sham_cra_sha512_init,
1730                 .cra_exit               = omap_sham_cra_exit,
1731         }
1732 },
1733 };
1734
1735 static void omap_sham_done_task(unsigned long data)
1736 {
1737         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1738         int err = 0;
1739
1740         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1741                 omap_sham_handle_queue(dd, NULL);
1742                 return;
1743         }
1744
1745         if (test_bit(FLAGS_CPU, &dd->flags)) {
1746                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1747                         goto finish;
1748         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1749                 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1750                         omap_sham_update_dma_stop(dd);
1751                         if (dd->err) {
1752                                 err = dd->err;
1753                                 goto finish;
1754                         }
1755                 }
1756                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1757                         /* hash or semi-hash ready */
1758                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1759                                 goto finish;
1760                 }
1761         }
1762
1763         return;
1764
1765 finish:
1766         dev_dbg(dd->dev, "update done: err: %d\n", err);
1767         /* finish curent request */
1768         omap_sham_finish_req(dd->req, err);
1769
1770         /* If we are not busy, process next req */
1771         if (!test_bit(FLAGS_BUSY, &dd->flags))
1772                 omap_sham_handle_queue(dd, NULL);
1773 }
1774
1775 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1776 {
1777         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1778                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1779         } else {
1780                 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1781                 tasklet_schedule(&dd->done_task);
1782         }
1783
1784         return IRQ_HANDLED;
1785 }
1786
1787 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1788 {
1789         struct omap_sham_dev *dd = dev_id;
1790
1791         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1792                 /* final -> allow device to go to power-saving mode */
1793                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1794
1795         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1796                                  SHA_REG_CTRL_OUTPUT_READY);
1797         omap_sham_read(dd, SHA_REG_CTRL);
1798
1799         return omap_sham_irq_common(dd);
1800 }
1801
1802 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1803 {
1804         struct omap_sham_dev *dd = dev_id;
1805
1806         omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1807
1808         return omap_sham_irq_common(dd);
1809 }
1810
1811 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1812         {
1813                 .algs_list      = algs_sha1_md5,
1814                 .size           = ARRAY_SIZE(algs_sha1_md5),
1815         },
1816 };
1817
1818 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1819         .algs_info      = omap_sham_algs_info_omap2,
1820         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1821         .flags          = BIT(FLAGS_BE32_SHA1),
1822         .digest_size    = SHA1_DIGEST_SIZE,
1823         .copy_hash      = omap_sham_copy_hash_omap2,
1824         .write_ctrl     = omap_sham_write_ctrl_omap2,
1825         .trigger        = omap_sham_trigger_omap2,
1826         .poll_irq       = omap_sham_poll_irq_omap2,
1827         .intr_hdlr      = omap_sham_irq_omap2,
1828         .idigest_ofs    = 0x00,
1829         .din_ofs        = 0x1c,
1830         .digcnt_ofs     = 0x14,
1831         .rev_ofs        = 0x5c,
1832         .mask_ofs       = 0x60,
1833         .sysstatus_ofs  = 0x64,
1834         .major_mask     = 0xf0,
1835         .major_shift    = 4,
1836         .minor_mask     = 0x0f,
1837         .minor_shift    = 0,
1838 };
1839
1840 #ifdef CONFIG_OF
1841 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1842         {
1843                 .algs_list      = algs_sha1_md5,
1844                 .size           = ARRAY_SIZE(algs_sha1_md5),
1845         },
1846         {
1847                 .algs_list      = algs_sha224_sha256,
1848                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1849         },
1850 };
1851
1852 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1853         .algs_info      = omap_sham_algs_info_omap4,
1854         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1855         .flags          = BIT(FLAGS_AUTO_XOR),
1856         .digest_size    = SHA256_DIGEST_SIZE,
1857         .copy_hash      = omap_sham_copy_hash_omap4,
1858         .write_ctrl     = omap_sham_write_ctrl_omap4,
1859         .trigger        = omap_sham_trigger_omap4,
1860         .poll_irq       = omap_sham_poll_irq_omap4,
1861         .intr_hdlr      = omap_sham_irq_omap4,
1862         .idigest_ofs    = 0x020,
1863         .odigest_ofs    = 0x0,
1864         .din_ofs        = 0x080,
1865         .digcnt_ofs     = 0x040,
1866         .rev_ofs        = 0x100,
1867         .mask_ofs       = 0x110,
1868         .sysstatus_ofs  = 0x114,
1869         .mode_ofs       = 0x44,
1870         .length_ofs     = 0x48,
1871         .major_mask     = 0x0700,
1872         .major_shift    = 8,
1873         .minor_mask     = 0x003f,
1874         .minor_shift    = 0,
1875 };
1876
1877 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1878         {
1879                 .algs_list      = algs_sha1_md5,
1880                 .size           = ARRAY_SIZE(algs_sha1_md5),
1881         },
1882         {
1883                 .algs_list      = algs_sha224_sha256,
1884                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1885         },
1886         {
1887                 .algs_list      = algs_sha384_sha512,
1888                 .size           = ARRAY_SIZE(algs_sha384_sha512),
1889         },
1890 };
1891
1892 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1893         .algs_info      = omap_sham_algs_info_omap5,
1894         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1895         .flags          = BIT(FLAGS_AUTO_XOR),
1896         .digest_size    = SHA512_DIGEST_SIZE,
1897         .copy_hash      = omap_sham_copy_hash_omap4,
1898         .write_ctrl     = omap_sham_write_ctrl_omap4,
1899         .trigger        = omap_sham_trigger_omap4,
1900         .poll_irq       = omap_sham_poll_irq_omap4,
1901         .intr_hdlr      = omap_sham_irq_omap4,
1902         .idigest_ofs    = 0x240,
1903         .odigest_ofs    = 0x200,
1904         .din_ofs        = 0x080,
1905         .digcnt_ofs     = 0x280,
1906         .rev_ofs        = 0x100,
1907         .mask_ofs       = 0x110,
1908         .sysstatus_ofs  = 0x114,
1909         .mode_ofs       = 0x284,
1910         .length_ofs     = 0x288,
1911         .major_mask     = 0x0700,
1912         .major_shift    = 8,
1913         .minor_mask     = 0x003f,
1914         .minor_shift    = 0,
1915 };
1916
1917 static const struct of_device_id omap_sham_of_match[] = {
1918         {
1919                 .compatible     = "ti,omap2-sham",
1920                 .data           = &omap_sham_pdata_omap2,
1921         },
1922         {
1923                 .compatible     = "ti,omap3-sham",
1924                 .data           = &omap_sham_pdata_omap2,
1925         },
1926         {
1927                 .compatible     = "ti,omap4-sham",
1928                 .data           = &omap_sham_pdata_omap4,
1929         },
1930         {
1931                 .compatible     = "ti,omap5-sham",
1932                 .data           = &omap_sham_pdata_omap5,
1933         },
1934         {},
1935 };
1936 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1937
1938 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1939                 struct device *dev, struct resource *res)
1940 {
1941         struct device_node *node = dev->of_node;
1942         const struct of_device_id *match;
1943         int err = 0;
1944
1945         match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1946         if (!match) {
1947                 dev_err(dev, "no compatible OF match\n");
1948                 err = -EINVAL;
1949                 goto err;
1950         }
1951
1952         err = of_address_to_resource(node, 0, res);
1953         if (err < 0) {
1954                 dev_err(dev, "can't translate OF node address\n");
1955                 err = -EINVAL;
1956                 goto err;
1957         }
1958
1959         dd->irq = irq_of_parse_and_map(node, 0);
1960         if (!dd->irq) {
1961                 dev_err(dev, "can't translate OF irq value\n");
1962                 err = -EINVAL;
1963                 goto err;
1964         }
1965
1966         dd->pdata = match->data;
1967
1968 err:
1969         return err;
1970 }
1971 #else
1972 static const struct of_device_id omap_sham_of_match[] = {
1973         {},
1974 };
1975
1976 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1977                 struct device *dev, struct resource *res)
1978 {
1979         return -EINVAL;
1980 }
1981 #endif
1982
1983 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1984                 struct platform_device *pdev, struct resource *res)
1985 {
1986         struct device *dev = &pdev->dev;
1987         struct resource *r;
1988         int err = 0;
1989
1990         /* Get the base address */
1991         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1992         if (!r) {
1993                 dev_err(dev, "no MEM resource info\n");
1994                 err = -ENODEV;
1995                 goto err;
1996         }
1997         memcpy(res, r, sizeof(*res));
1998
1999         /* Get the IRQ */
2000         dd->irq = platform_get_irq(pdev, 0);
2001         if (dd->irq < 0) {
2002                 dev_err(dev, "no IRQ resource info\n");
2003                 err = dd->irq;
2004                 goto err;
2005         }
2006
2007         /* Only OMAP2/3 can be non-DT */
2008         dd->pdata = &omap_sham_pdata_omap2;
2009
2010 err:
2011         return err;
2012 }
2013
2014 static int omap_sham_probe(struct platform_device *pdev)
2015 {
2016         struct omap_sham_dev *dd;
2017         struct device *dev = &pdev->dev;
2018         struct resource res;
2019         dma_cap_mask_t mask;
2020         int err, i, j;
2021         u32 rev;
2022
2023         dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2024         if (dd == NULL) {
2025                 dev_err(dev, "unable to alloc data struct.\n");
2026                 err = -ENOMEM;
2027                 goto data_err;
2028         }
2029         dd->dev = dev;
2030         platform_set_drvdata(pdev, dd);
2031
2032         INIT_LIST_HEAD(&dd->list);
2033         spin_lock_init(&dd->lock);
2034         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2035         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2036
2037         err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2038                                omap_sham_get_res_pdev(dd, pdev, &res);
2039         if (err)
2040                 goto data_err;
2041
2042         dd->io_base = devm_ioremap_resource(dev, &res);
2043         if (IS_ERR(dd->io_base)) {
2044                 err = PTR_ERR(dd->io_base);
2045                 goto data_err;
2046         }
2047         dd->phys_base = res.start;
2048
2049         err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2050                                IRQF_TRIGGER_NONE, dev_name(dev), dd);
2051         if (err) {
2052                 dev_err(dev, "unable to request irq %d, err = %d\n",
2053                         dd->irq, err);
2054                 goto data_err;
2055         }
2056
2057         dma_cap_zero(mask);
2058         dma_cap_set(DMA_SLAVE, mask);
2059
2060         dd->dma_lch = dma_request_chan(dev, "rx");
2061         if (IS_ERR(dd->dma_lch)) {
2062                 err = PTR_ERR(dd->dma_lch);
2063                 if (err == -EPROBE_DEFER)
2064                         goto data_err;
2065
2066                 dd->polling_mode = 1;
2067                 dev_dbg(dev, "using polling mode instead of dma\n");
2068         }
2069
2070         dd->flags |= dd->pdata->flags;
2071
2072         pm_runtime_use_autosuspend(dev);
2073         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2074
2075         pm_runtime_enable(dev);
2076         pm_runtime_irq_safe(dev);
2077
2078         err = pm_runtime_get_sync(dev);
2079         if (err < 0) {
2080                 dev_err(dev, "failed to get sync: %d\n", err);
2081                 goto err_pm;
2082         }
2083
2084         rev = omap_sham_read(dd, SHA_REG_REV(dd));
2085         pm_runtime_put_sync(&pdev->dev);
2086
2087         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2088                 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2089                 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2090
2091         spin_lock(&sham.lock);
2092         list_add_tail(&dd->list, &sham.dev_list);
2093         spin_unlock(&sham.lock);
2094
2095         for (i = 0; i < dd->pdata->algs_info_size; i++) {
2096                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2097                         struct ahash_alg *alg;
2098
2099                         alg = &dd->pdata->algs_info[i].algs_list[j];
2100                         alg->export = omap_sham_export;
2101                         alg->import = omap_sham_import;
2102                         alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2103                                               BUFLEN;
2104                         err = crypto_register_ahash(alg);
2105                         if (err)
2106                                 goto err_algs;
2107
2108                         dd->pdata->algs_info[i].registered++;
2109                 }
2110         }
2111
2112         return 0;
2113
2114 err_algs:
2115         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2116                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2117                         crypto_unregister_ahash(
2118                                         &dd->pdata->algs_info[i].algs_list[j]);
2119 err_pm:
2120         pm_runtime_disable(dev);
2121         if (!dd->polling_mode)
2122                 dma_release_channel(dd->dma_lch);
2123 data_err:
2124         dev_err(dev, "initialization failed.\n");
2125
2126         return err;
2127 }
2128
2129 static int omap_sham_remove(struct platform_device *pdev)
2130 {
2131         static struct omap_sham_dev *dd;
2132         int i, j;
2133
2134         dd = platform_get_drvdata(pdev);
2135         if (!dd)
2136                 return -ENODEV;
2137         spin_lock(&sham.lock);
2138         list_del(&dd->list);
2139         spin_unlock(&sham.lock);
2140         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2141                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2142                         crypto_unregister_ahash(
2143                                         &dd->pdata->algs_info[i].algs_list[j]);
2144         tasklet_kill(&dd->done_task);
2145         pm_runtime_disable(&pdev->dev);
2146
2147         if (!dd->polling_mode)
2148                 dma_release_channel(dd->dma_lch);
2149
2150         return 0;
2151 }
2152
2153 #ifdef CONFIG_PM_SLEEP
2154 static int omap_sham_suspend(struct device *dev)
2155 {
2156         pm_runtime_put_sync(dev);
2157         return 0;
2158 }
2159
2160 static int omap_sham_resume(struct device *dev)
2161 {
2162         int err = pm_runtime_get_sync(dev);
2163         if (err < 0) {
2164                 dev_err(dev, "failed to get sync: %d\n", err);
2165                 return err;
2166         }
2167         return 0;
2168 }
2169 #endif
2170
2171 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2172
2173 static struct platform_driver omap_sham_driver = {
2174         .probe  = omap_sham_probe,
2175         .remove = omap_sham_remove,
2176         .driver = {
2177                 .name   = "omap-sham",
2178                 .pm     = &omap_sham_pm_ops,
2179                 .of_match_table = omap_sham_of_match,
2180         },
2181 };
2182
2183 module_platform_driver(omap_sham_driver);
2184
2185 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2186 MODULE_LICENSE("GPL v2");
2187 MODULE_AUTHOR("Dmitry Kasatkin");
2188 MODULE_ALIAS("platform:omap-sham");