2 * talitos - Freescale Integrated Security Engine (SEC) device driver
4 * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
9 * Crypto algorithm registration code copied from hifn driver:
10 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11 * All rights reserved.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
33 #include <linux/crypto.h>
34 #include <linux/hw_random.h>
35 #include <linux/of_platform.h>
36 #include <linux/dma-mapping.h>
38 #include <linux/spinlock.h>
39 #include <linux/rtnetlink.h>
40 #include <linux/slab.h>
42 #include <crypto/algapi.h>
43 #include <crypto/aes.h>
44 #include <crypto/des.h>
45 #include <crypto/sha.h>
46 #include <crypto/md5.h>
47 #include <crypto/aead.h>
48 #include <crypto/authenc.h>
49 #include <crypto/skcipher.h>
50 #include <crypto/hash.h>
51 #include <crypto/internal/hash.h>
52 #include <crypto/scatterwalk.h>
56 static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
58 talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
59 talitos_ptr->eptr = upper_32_bits(dma_addr);
63 * map virtual single (contiguous) pointer to h/w descriptor pointer
65 static void map_single_talitos_ptr(struct device *dev,
66 struct talitos_ptr *talitos_ptr,
67 unsigned short len, void *data,
69 enum dma_data_direction dir)
71 dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
73 talitos_ptr->len = cpu_to_be16(len);
74 to_talitos_ptr(talitos_ptr, dma_addr);
75 talitos_ptr->j_extent = extent;
79 * unmap bus single (contiguous) h/w descriptor pointer
81 static void unmap_single_talitos_ptr(struct device *dev,
82 struct talitos_ptr *talitos_ptr,
83 enum dma_data_direction dir)
85 dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
86 be16_to_cpu(talitos_ptr->len), dir);
89 static int reset_channel(struct device *dev, int ch)
91 struct talitos_private *priv = dev_get_drvdata(dev);
92 unsigned int timeout = TALITOS_TIMEOUT;
94 setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
96 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
101 dev_err(dev, "failed to reset channel %d\n", ch);
105 /* set 36-bit addressing, done writeback enable and done IRQ enable */
106 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
107 TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
109 /* and ICCR writeback, if available */
110 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
111 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
112 TALITOS_CCCR_LO_IWSE);
117 static int reset_device(struct device *dev)
119 struct talitos_private *priv = dev_get_drvdata(dev);
120 unsigned int timeout = TALITOS_TIMEOUT;
121 u32 mcr = TALITOS_MCR_SWR;
123 setbits32(priv->reg + TALITOS_MCR, mcr);
125 while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
130 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
131 setbits32(priv->reg + TALITOS_MCR, mcr);
135 dev_err(dev, "failed to reset device\n");
143 * Reset and initialize the device
145 static int init_device(struct device *dev)
147 struct talitos_private *priv = dev_get_drvdata(dev);
152 * errata documentation: warning: certain SEC interrupts
153 * are not fully cleared by writing the MCR:SWR bit,
154 * set bit twice to completely reset
156 err = reset_device(dev);
160 err = reset_device(dev);
165 for (ch = 0; ch < priv->num_channels; ch++) {
166 err = reset_channel(dev, ch);
171 /* enable channel done and error interrupts */
172 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
173 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
175 /* disable integrity check error interrupts (use writeback instead) */
176 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
177 setbits32(priv->reg + TALITOS_MDEUICR_LO,
178 TALITOS_MDEUICR_LO_ICE);
184 * talitos_submit - submits a descriptor to the device for processing
185 * @dev: the SEC device to be used
186 * @ch: the SEC device channel to be used
187 * @desc: the descriptor to be processed by the device
188 * @callback: whom to call when processing is complete
189 * @context: a handle for use by caller (optional)
191 * desc must contain valid dma-mapped (bus physical) address pointers.
192 * callback must check err and feedback in descriptor header
193 * for device processing status.
195 int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
196 void (*callback)(struct device *dev,
197 struct talitos_desc *desc,
198 void *context, int error),
201 struct talitos_private *priv = dev_get_drvdata(dev);
202 struct talitos_request *request;
206 spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
208 if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
209 /* h/w fifo is full */
210 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
214 head = priv->chan[ch].head;
215 request = &priv->chan[ch].fifo[head];
217 /* map descriptor and save caller data */
218 request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
220 request->callback = callback;
221 request->context = context;
223 /* increment fifo head */
224 priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
227 request->desc = desc;
231 out_be32(priv->chan[ch].reg + TALITOS_FF,
232 upper_32_bits(request->dma_desc));
233 out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
234 lower_32_bits(request->dma_desc));
236 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
240 EXPORT_SYMBOL(talitos_submit);
243 * process what was done, notify callback of error if not
245 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
247 struct talitos_private *priv = dev_get_drvdata(dev);
248 struct talitos_request *request, saved_req;
252 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
254 tail = priv->chan[ch].tail;
255 while (priv->chan[ch].fifo[tail].desc) {
256 request = &priv->chan[ch].fifo[tail];
258 /* descriptors with their done bits set don't get the error */
260 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
268 dma_unmap_single(dev, request->dma_desc,
269 sizeof(struct talitos_desc),
272 /* copy entries so we can call callback outside lock */
273 saved_req.desc = request->desc;
274 saved_req.callback = request->callback;
275 saved_req.context = request->context;
277 /* release request entry in fifo */
279 request->desc = NULL;
281 /* increment fifo tail */
282 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
284 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
286 atomic_dec(&priv->chan[ch].submit_count);
288 saved_req.callback(dev, saved_req.desc, saved_req.context,
290 /* channel may resume processing in single desc error case */
291 if (error && !reset_ch && status == error)
293 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
294 tail = priv->chan[ch].tail;
297 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
301 * process completed requests for channels that have done status
303 #define DEF_TALITOS_DONE(name, ch_done_mask) \
304 static void talitos_done_##name(unsigned long data) \
306 struct device *dev = (struct device *)data; \
307 struct talitos_private *priv = dev_get_drvdata(dev); \
308 unsigned long flags; \
310 if (ch_done_mask & 1) \
311 flush_channel(dev, 0, 0, 0); \
312 if (priv->num_channels == 1) \
314 if (ch_done_mask & (1 << 2)) \
315 flush_channel(dev, 1, 0, 0); \
316 if (ch_done_mask & (1 << 4)) \
317 flush_channel(dev, 2, 0, 0); \
318 if (ch_done_mask & (1 << 6)) \
319 flush_channel(dev, 3, 0, 0); \
322 /* At this point, all completed channels have been processed */ \
323 /* Unmask done interrupts for channels completed later on. */ \
324 spin_lock_irqsave(&priv->reg_lock, flags); \
325 setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
326 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT); \
327 spin_unlock_irqrestore(&priv->reg_lock, flags); \
329 DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
330 DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
331 DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
334 * locate current (offending) descriptor
336 static u32 current_desc_hdr(struct device *dev, int ch)
338 struct talitos_private *priv = dev_get_drvdata(dev);
339 int tail = priv->chan[ch].tail;
342 cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
344 while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
345 tail = (tail + 1) & (priv->fifo_len - 1);
346 if (tail == priv->chan[ch].tail) {
347 dev_err(dev, "couldn't locate current descriptor\n");
352 return priv->chan[ch].fifo[tail].desc->hdr;
356 * user diagnostics; report root cause of error based on execution unit status
358 static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
360 struct talitos_private *priv = dev_get_drvdata(dev);
364 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
366 switch (desc_hdr & DESC_HDR_SEL0_MASK) {
367 case DESC_HDR_SEL0_AFEU:
368 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
369 in_be32(priv->reg + TALITOS_AFEUISR),
370 in_be32(priv->reg + TALITOS_AFEUISR_LO));
372 case DESC_HDR_SEL0_DEU:
373 dev_err(dev, "DEUISR 0x%08x_%08x\n",
374 in_be32(priv->reg + TALITOS_DEUISR),
375 in_be32(priv->reg + TALITOS_DEUISR_LO));
377 case DESC_HDR_SEL0_MDEUA:
378 case DESC_HDR_SEL0_MDEUB:
379 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
380 in_be32(priv->reg + TALITOS_MDEUISR),
381 in_be32(priv->reg + TALITOS_MDEUISR_LO));
383 case DESC_HDR_SEL0_RNG:
384 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
385 in_be32(priv->reg + TALITOS_RNGUISR),
386 in_be32(priv->reg + TALITOS_RNGUISR_LO));
388 case DESC_HDR_SEL0_PKEU:
389 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
390 in_be32(priv->reg + TALITOS_PKEUISR),
391 in_be32(priv->reg + TALITOS_PKEUISR_LO));
393 case DESC_HDR_SEL0_AESU:
394 dev_err(dev, "AESUISR 0x%08x_%08x\n",
395 in_be32(priv->reg + TALITOS_AESUISR),
396 in_be32(priv->reg + TALITOS_AESUISR_LO));
398 case DESC_HDR_SEL0_CRCU:
399 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
400 in_be32(priv->reg + TALITOS_CRCUISR),
401 in_be32(priv->reg + TALITOS_CRCUISR_LO));
403 case DESC_HDR_SEL0_KEU:
404 dev_err(dev, "KEUISR 0x%08x_%08x\n",
405 in_be32(priv->reg + TALITOS_KEUISR),
406 in_be32(priv->reg + TALITOS_KEUISR_LO));
410 switch (desc_hdr & DESC_HDR_SEL1_MASK) {
411 case DESC_HDR_SEL1_MDEUA:
412 case DESC_HDR_SEL1_MDEUB:
413 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
414 in_be32(priv->reg + TALITOS_MDEUISR),
415 in_be32(priv->reg + TALITOS_MDEUISR_LO));
417 case DESC_HDR_SEL1_CRCU:
418 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
419 in_be32(priv->reg + TALITOS_CRCUISR),
420 in_be32(priv->reg + TALITOS_CRCUISR_LO));
424 for (i = 0; i < 8; i++)
425 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
426 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
427 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
431 * recover from error interrupts
433 static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
435 struct talitos_private *priv = dev_get_drvdata(dev);
436 unsigned int timeout = TALITOS_TIMEOUT;
437 int ch, error, reset_dev = 0, reset_ch = 0;
440 for (ch = 0; ch < priv->num_channels; ch++) {
441 /* skip channels without errors */
442 if (!(isr & (1 << (ch * 2 + 1))))
447 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
448 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
450 if (v_lo & TALITOS_CCPSR_LO_DOF) {
451 dev_err(dev, "double fetch fifo overflow error\n");
455 if (v_lo & TALITOS_CCPSR_LO_SOF) {
456 /* h/w dropped descriptor */
457 dev_err(dev, "single fetch fifo overflow error\n");
460 if (v_lo & TALITOS_CCPSR_LO_MDTE)
461 dev_err(dev, "master data transfer error\n");
462 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
463 dev_err(dev, "s/g data length zero error\n");
464 if (v_lo & TALITOS_CCPSR_LO_FPZ)
465 dev_err(dev, "fetch pointer zero error\n");
466 if (v_lo & TALITOS_CCPSR_LO_IDH)
467 dev_err(dev, "illegal descriptor header error\n");
468 if (v_lo & TALITOS_CCPSR_LO_IEU)
469 dev_err(dev, "invalid execution unit error\n");
470 if (v_lo & TALITOS_CCPSR_LO_EU)
471 report_eu_error(dev, ch, current_desc_hdr(dev, ch));
472 if (v_lo & TALITOS_CCPSR_LO_GB)
473 dev_err(dev, "gather boundary error\n");
474 if (v_lo & TALITOS_CCPSR_LO_GRL)
475 dev_err(dev, "gather return/length error\n");
476 if (v_lo & TALITOS_CCPSR_LO_SB)
477 dev_err(dev, "scatter boundary error\n");
478 if (v_lo & TALITOS_CCPSR_LO_SRL)
479 dev_err(dev, "scatter return/length error\n");
481 flush_channel(dev, ch, error, reset_ch);
484 reset_channel(dev, ch);
486 setbits32(priv->chan[ch].reg + TALITOS_CCCR,
488 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
489 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
490 TALITOS_CCCR_CONT) && --timeout)
493 dev_err(dev, "failed to restart channel %d\n",
499 if (reset_dev || isr & ~TALITOS_ISR_4CHERR || isr_lo) {
500 dev_err(dev, "done overflow, internal time out, or rngu error: "
501 "ISR 0x%08x_%08x\n", isr, isr_lo);
503 /* purge request queues */
504 for (ch = 0; ch < priv->num_channels; ch++)
505 flush_channel(dev, ch, -EIO, 1);
507 /* reset and reinitialize the device */
512 #define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
513 static irqreturn_t talitos_interrupt_##name(int irq, void *data) \
515 struct device *dev = data; \
516 struct talitos_private *priv = dev_get_drvdata(dev); \
518 unsigned long flags; \
520 spin_lock_irqsave(&priv->reg_lock, flags); \
521 isr = in_be32(priv->reg + TALITOS_ISR); \
522 isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
523 /* Acknowledge interrupt */ \
524 out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
525 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
527 if (unlikely(isr & ch_err_mask || isr_lo)) { \
528 spin_unlock_irqrestore(&priv->reg_lock, flags); \
529 talitos_error(dev, isr & ch_err_mask, isr_lo); \
532 if (likely(isr & ch_done_mask)) { \
533 /* mask further done interrupts. */ \
534 clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
535 /* done_task will unmask done interrupts at exit */ \
536 tasklet_schedule(&priv->done_task[tlet]); \
538 spin_unlock_irqrestore(&priv->reg_lock, flags); \
541 return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
544 DEF_TALITOS_INTERRUPT(4ch, TALITOS_ISR_4CHDONE, TALITOS_ISR_4CHERR, 0)
545 DEF_TALITOS_INTERRUPT(ch0_2, TALITOS_ISR_CH_0_2_DONE, TALITOS_ISR_CH_0_2_ERR, 0)
546 DEF_TALITOS_INTERRUPT(ch1_3, TALITOS_ISR_CH_1_3_DONE, TALITOS_ISR_CH_1_3_ERR, 1)
551 static int talitos_rng_data_present(struct hwrng *rng, int wait)
553 struct device *dev = (struct device *)rng->priv;
554 struct talitos_private *priv = dev_get_drvdata(dev);
558 for (i = 0; i < 20; i++) {
559 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
560 TALITOS_RNGUSR_LO_OFL;
569 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
571 struct device *dev = (struct device *)rng->priv;
572 struct talitos_private *priv = dev_get_drvdata(dev);
574 /* rng fifo requires 64-bit accesses */
575 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
576 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
581 static int talitos_rng_init(struct hwrng *rng)
583 struct device *dev = (struct device *)rng->priv;
584 struct talitos_private *priv = dev_get_drvdata(dev);
585 unsigned int timeout = TALITOS_TIMEOUT;
587 setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
588 while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
592 dev_err(dev, "failed to reset rng hw\n");
596 /* start generating */
597 setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
602 static int talitos_register_rng(struct device *dev)
604 struct talitos_private *priv = dev_get_drvdata(dev);
606 priv->rng.name = dev_driver_string(dev),
607 priv->rng.init = talitos_rng_init,
608 priv->rng.data_present = talitos_rng_data_present,
609 priv->rng.data_read = talitos_rng_data_read,
610 priv->rng.priv = (unsigned long)dev;
612 return hwrng_register(&priv->rng);
615 static void talitos_unregister_rng(struct device *dev)
617 struct talitos_private *priv = dev_get_drvdata(dev);
619 hwrng_unregister(&priv->rng);
625 #define TALITOS_CRA_PRIORITY 3000
626 #define TALITOS_MAX_KEY_SIZE 96
627 #define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
629 #define MD5_BLOCK_SIZE 64
634 __be32 desc_hdr_template;
635 u8 key[TALITOS_MAX_KEY_SIZE];
636 u8 iv[TALITOS_MAX_IV_LENGTH];
638 unsigned int enckeylen;
639 unsigned int authkeylen;
640 unsigned int authsize;
643 #define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
644 #define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
646 struct talitos_ahash_req_ctx {
647 u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
648 unsigned int hw_context_size;
649 u8 buf[HASH_MAX_BLOCK_SIZE];
650 u8 bufnext[HASH_MAX_BLOCK_SIZE];
654 unsigned int to_hash_later;
656 struct scatterlist bufsl[2];
657 struct scatterlist *psrc;
660 static int aead_setauthsize(struct crypto_aead *authenc,
661 unsigned int authsize)
663 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
665 ctx->authsize = authsize;
670 static int aead_setkey(struct crypto_aead *authenc,
671 const u8 *key, unsigned int keylen)
673 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
674 struct crypto_authenc_keys keys;
676 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
679 if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
682 memcpy(ctx->key, keys.authkey, keys.authkeylen);
683 memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
685 ctx->keylen = keys.authkeylen + keys.enckeylen;
686 ctx->enckeylen = keys.enckeylen;
687 ctx->authkeylen = keys.authkeylen;
692 crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
697 * talitos_edesc - s/w-extended descriptor
698 * @assoc_nents: number of segments in associated data scatterlist
699 * @src_nents: number of segments in input scatterlist
700 * @dst_nents: number of segments in output scatterlist
701 * @assoc_chained: whether assoc is chained or not
702 * @src_chained: whether src is chained or not
703 * @dst_chained: whether dst is chained or not
704 * @iv_dma: dma address of iv for checking continuity and link table
705 * @dma_len: length of dma mapped link_tbl space
706 * @dma_link_tbl: bus physical address of link_tbl
707 * @desc: h/w descriptor
708 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
710 * if decrypting (with authcheck), or either one of src_nents or dst_nents
711 * is greater than 1, an integrity check value is concatenated to the end
714 struct talitos_edesc {
723 dma_addr_t dma_link_tbl;
724 struct talitos_desc desc;
725 struct talitos_ptr link_tbl[0];
728 static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
729 unsigned int nents, enum dma_data_direction dir,
732 if (unlikely(chained))
734 dma_map_sg(dev, sg, 1, dir);
735 sg = scatterwalk_sg_next(sg);
738 dma_map_sg(dev, sg, nents, dir);
742 static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
743 enum dma_data_direction dir)
746 dma_unmap_sg(dev, sg, 1, dir);
747 sg = scatterwalk_sg_next(sg);
751 static void talitos_sg_unmap(struct device *dev,
752 struct talitos_edesc *edesc,
753 struct scatterlist *src,
754 struct scatterlist *dst)
756 unsigned int src_nents = edesc->src_nents ? : 1;
757 unsigned int dst_nents = edesc->dst_nents ? : 1;
760 if (edesc->src_chained)
761 talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
763 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
766 if (edesc->dst_chained)
767 talitos_unmap_sg_chain(dev, dst,
770 dma_unmap_sg(dev, dst, dst_nents,
774 if (edesc->src_chained)
775 talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
777 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
780 static void ipsec_esp_unmap(struct device *dev,
781 struct talitos_edesc *edesc,
782 struct aead_request *areq)
784 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
785 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
786 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
787 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
789 if (edesc->assoc_chained)
790 talitos_unmap_sg_chain(dev, areq->assoc, DMA_TO_DEVICE);
792 /* assoc_nents counts also for IV in non-contiguous cases */
793 dma_unmap_sg(dev, areq->assoc,
794 edesc->assoc_nents ? edesc->assoc_nents - 1 : 1,
797 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
800 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
805 * ipsec_esp descriptor callbacks
807 static void ipsec_esp_encrypt_done(struct device *dev,
808 struct talitos_desc *desc, void *context,
811 struct aead_request *areq = context;
812 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
813 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
814 struct talitos_edesc *edesc;
815 struct scatterlist *sg;
818 edesc = container_of(desc, struct talitos_edesc, desc);
820 ipsec_esp_unmap(dev, edesc, areq);
822 /* copy the generated ICV to dst */
823 if (edesc->dst_nents) {
824 icvdata = &edesc->link_tbl[edesc->src_nents +
825 edesc->dst_nents + 2 +
827 sg = sg_last(areq->dst, edesc->dst_nents);
828 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
829 icvdata, ctx->authsize);
834 aead_request_complete(areq, err);
837 static void ipsec_esp_decrypt_swauth_done(struct device *dev,
838 struct talitos_desc *desc,
839 void *context, int err)
841 struct aead_request *req = context;
842 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
843 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
844 struct talitos_edesc *edesc;
845 struct scatterlist *sg;
848 edesc = container_of(desc, struct talitos_edesc, desc);
850 ipsec_esp_unmap(dev, edesc, req);
855 icvdata = &edesc->link_tbl[edesc->src_nents +
856 edesc->dst_nents + 2 +
859 icvdata = &edesc->link_tbl[0];
861 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
862 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
863 ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
868 aead_request_complete(req, err);
871 static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
872 struct talitos_desc *desc,
873 void *context, int err)
875 struct aead_request *req = context;
876 struct talitos_edesc *edesc;
878 edesc = container_of(desc, struct talitos_edesc, desc);
880 ipsec_esp_unmap(dev, edesc, req);
882 /* check ICV auth status */
883 if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
884 DESC_HDR_LO_ICCR1_PASS))
889 aead_request_complete(req, err);
893 * convert scatterlist to SEC h/w link table format
894 * stop at cryptlen bytes
896 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
897 int cryptlen, struct talitos_ptr *link_tbl_ptr)
902 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
903 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
904 link_tbl_ptr->j_extent = 0;
906 cryptlen -= sg_dma_len(sg);
907 sg = scatterwalk_sg_next(sg);
910 /* adjust (decrease) last one (or two) entry's len to cryptlen */
912 while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
913 /* Empty this entry, and move to previous one */
914 cryptlen += be16_to_cpu(link_tbl_ptr->len);
915 link_tbl_ptr->len = 0;
919 be16_add_cpu(&link_tbl_ptr->len, cryptlen);
921 /* tag end of link table */
922 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
928 * fill in and submit ipsec_esp descriptor
930 static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
931 u64 seq, void (*callback) (struct device *dev,
932 struct talitos_desc *desc,
933 void *context, int error))
935 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
936 struct talitos_ctx *ctx = crypto_aead_ctx(aead);
937 struct device *dev = ctx->dev;
938 struct talitos_desc *desc = &edesc->desc;
939 unsigned int cryptlen = areq->cryptlen;
940 unsigned int authsize = ctx->authsize;
941 unsigned int ivsize = crypto_aead_ivsize(aead);
946 map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
950 desc->ptr[1].len = cpu_to_be16(areq->assoclen + ivsize);
951 if (edesc->assoc_nents) {
952 int tbl_off = edesc->src_nents + edesc->dst_nents + 2;
953 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
955 to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
956 sizeof(struct talitos_ptr));
957 desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
959 /* assoc_nents - 1 entries for assoc, 1 for IV */
960 sg_count = sg_to_link_tbl(areq->assoc, edesc->assoc_nents - 1,
961 areq->assoclen, tbl_ptr);
963 /* add IV to link table */
964 tbl_ptr += sg_count - 1;
965 tbl_ptr->j_extent = 0;
967 to_talitos_ptr(tbl_ptr, edesc->iv_dma);
968 tbl_ptr->len = cpu_to_be16(ivsize);
969 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
971 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
972 edesc->dma_len, DMA_BIDIRECTIONAL);
974 to_talitos_ptr(&desc->ptr[1], sg_dma_address(areq->assoc));
975 desc->ptr[1].j_extent = 0;
979 to_talitos_ptr(&desc->ptr[2], edesc->iv_dma);
980 desc->ptr[2].len = cpu_to_be16(ivsize);
981 desc->ptr[2].j_extent = 0;
982 /* Sync needed for the aead_givencrypt case */
983 dma_sync_single_for_device(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
986 map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
987 (char *)&ctx->key + ctx->authkeylen, 0,
992 * map and adjust cipher len to aead request cryptlen.
993 * extent is bytes of HMAC postpended to ciphertext,
994 * typically 12 for ipsec
996 desc->ptr[4].len = cpu_to_be16(cryptlen);
997 desc->ptr[4].j_extent = authsize;
999 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1000 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1002 edesc->src_chained);
1004 if (sg_count == 1) {
1005 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
1007 sg_link_tbl_len = cryptlen;
1009 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
1010 sg_link_tbl_len = cryptlen + authsize;
1012 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
1013 &edesc->link_tbl[0]);
1015 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1016 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
1017 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1021 /* Only one segment now, so no link tbl needed */
1022 to_talitos_ptr(&desc->ptr[4],
1023 sg_dma_address(areq->src));
1028 desc->ptr[5].len = cpu_to_be16(cryptlen);
1029 desc->ptr[5].j_extent = authsize;
1031 if (areq->src != areq->dst)
1032 sg_count = talitos_map_sg(dev, areq->dst,
1033 edesc->dst_nents ? : 1,
1034 DMA_FROM_DEVICE, edesc->dst_chained);
1036 if (sg_count == 1) {
1037 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
1039 int tbl_off = edesc->src_nents + 1;
1040 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
1042 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1043 tbl_off * sizeof(struct talitos_ptr));
1044 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1047 /* Add an entry to the link table for ICV data */
1048 tbl_ptr += sg_count - 1;
1049 tbl_ptr->j_extent = 0;
1051 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1052 tbl_ptr->len = cpu_to_be16(authsize);
1054 /* icv data follows link tables */
1055 to_talitos_ptr(tbl_ptr, edesc->dma_link_tbl +
1056 (tbl_off + edesc->dst_nents + 1 +
1057 edesc->assoc_nents) *
1058 sizeof(struct talitos_ptr));
1059 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1060 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1061 edesc->dma_len, DMA_BIDIRECTIONAL);
1065 map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1068 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1069 if (ret != -EINPROGRESS) {
1070 ipsec_esp_unmap(dev, edesc, areq);
1077 * derive number of elements in scatterlist
1079 static int sg_count(struct scatterlist *sg_list, int nbytes, bool *chained)
1081 struct scatterlist *sg = sg_list;
1085 while (nbytes > 0) {
1087 nbytes -= sg->length;
1088 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1090 sg = scatterwalk_sg_next(sg);
1097 * allocate and map the extended descriptor
1099 static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1100 struct scatterlist *assoc,
1101 struct scatterlist *src,
1102 struct scatterlist *dst,
1104 unsigned int assoclen,
1105 unsigned int cryptlen,
1106 unsigned int authsize,
1107 unsigned int ivsize,
1111 struct talitos_edesc *edesc;
1112 int assoc_nents = 0, src_nents, dst_nents, alloc_len, dma_len;
1113 bool assoc_chained = false, src_chained = false, dst_chained = false;
1114 dma_addr_t iv_dma = 0;
1115 gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1118 if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1119 dev_err(dev, "length exceeds h/w max limit\n");
1120 return ERR_PTR(-EINVAL);
1124 iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
1128 * Currently it is assumed that iv is provided whenever assoc
1133 assoc_nents = sg_count(assoc, assoclen, &assoc_chained);
1134 talitos_map_sg(dev, assoc, assoc_nents, DMA_TO_DEVICE,
1136 assoc_nents = (assoc_nents == 1) ? 0 : assoc_nents;
1138 if (assoc_nents || sg_dma_address(assoc) + assoclen != iv_dma)
1139 assoc_nents = assoc_nents ? assoc_nents + 1 : 2;
1142 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
1143 src_nents = (src_nents == 1) ? 0 : src_nents;
1149 dst_nents = src_nents;
1151 dst_nents = sg_count(dst, cryptlen + authsize,
1153 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1158 * allocate space for base edesc plus the link tables,
1159 * allowing for two separate entries for ICV and generated ICV (+ 2),
1160 * and the ICV data itself
1162 alloc_len = sizeof(struct talitos_edesc);
1163 if (assoc_nents || src_nents || dst_nents) {
1164 dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
1165 sizeof(struct talitos_ptr) + authsize;
1166 alloc_len += dma_len;
1169 alloc_len += icv_stashing ? authsize : 0;
1172 edesc = kmalloc(alloc_len, GFP_DMA | flags);
1174 talitos_unmap_sg_chain(dev, assoc, DMA_TO_DEVICE);
1176 dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
1177 dev_err(dev, "could not allocate edescriptor\n");
1178 return ERR_PTR(-ENOMEM);
1181 edesc->assoc_nents = assoc_nents;
1182 edesc->src_nents = src_nents;
1183 edesc->dst_nents = dst_nents;
1184 edesc->assoc_chained = assoc_chained;
1185 edesc->src_chained = src_chained;
1186 edesc->dst_chained = dst_chained;
1187 edesc->iv_dma = iv_dma;
1188 edesc->dma_len = dma_len;
1190 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1197 static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
1200 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1201 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1202 unsigned int ivsize = crypto_aead_ivsize(authenc);
1204 return talitos_edesc_alloc(ctx->dev, areq->assoc, areq->src, areq->dst,
1205 iv, areq->assoclen, areq->cryptlen,
1206 ctx->authsize, ivsize, icv_stashing,
1210 static int aead_encrypt(struct aead_request *req)
1212 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1213 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1214 struct talitos_edesc *edesc;
1216 /* allocate extended descriptor */
1217 edesc = aead_edesc_alloc(req, req->iv, 0);
1219 return PTR_ERR(edesc);
1222 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1224 return ipsec_esp(edesc, req, 0, ipsec_esp_encrypt_done);
1227 static int aead_decrypt(struct aead_request *req)
1229 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1230 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1231 unsigned int authsize = ctx->authsize;
1232 struct talitos_private *priv = dev_get_drvdata(ctx->dev);
1233 struct talitos_edesc *edesc;
1234 struct scatterlist *sg;
1237 req->cryptlen -= authsize;
1239 /* allocate extended descriptor */
1240 edesc = aead_edesc_alloc(req, req->iv, 1);
1242 return PTR_ERR(edesc);
1244 if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
1245 ((!edesc->src_nents && !edesc->dst_nents) ||
1246 priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
1248 /* decrypt and check the ICV */
1249 edesc->desc.hdr = ctx->desc_hdr_template |
1250 DESC_HDR_DIR_INBOUND |
1251 DESC_HDR_MODE1_MDEU_CICV;
1253 /* reset integrity check result bits */
1254 edesc->desc.hdr_lo = 0;
1256 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_hwauth_done);
1259 /* Have to check the ICV with software */
1260 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1262 /* stash incoming ICV for later cmp with ICV generated by the h/w */
1264 icvdata = &edesc->link_tbl[edesc->src_nents +
1265 edesc->dst_nents + 2 +
1266 edesc->assoc_nents];
1268 icvdata = &edesc->link_tbl[0];
1270 sg = sg_last(req->src, edesc->src_nents ? : 1);
1272 memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1275 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_swauth_done);
1278 static int aead_givencrypt(struct aead_givcrypt_request *req)
1280 struct aead_request *areq = &req->areq;
1281 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1282 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1283 struct talitos_edesc *edesc;
1285 /* allocate extended descriptor */
1286 edesc = aead_edesc_alloc(areq, req->giv, 0);
1288 return PTR_ERR(edesc);
1291 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1293 memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1294 /* avoid consecutive packets going out with same IV */
1295 *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
1297 return ipsec_esp(edesc, areq, req->seq, ipsec_esp_encrypt_done);
1300 static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1301 const u8 *key, unsigned int keylen)
1303 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1305 memcpy(&ctx->key, key, keylen);
1306 ctx->keylen = keylen;
1311 static void common_nonsnoop_unmap(struct device *dev,
1312 struct talitos_edesc *edesc,
1313 struct ablkcipher_request *areq)
1315 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1316 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1317 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1319 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1322 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1326 static void ablkcipher_done(struct device *dev,
1327 struct talitos_desc *desc, void *context,
1330 struct ablkcipher_request *areq = context;
1331 struct talitos_edesc *edesc;
1333 edesc = container_of(desc, struct talitos_edesc, desc);
1335 common_nonsnoop_unmap(dev, edesc, areq);
1339 areq->base.complete(&areq->base, err);
1342 static int common_nonsnoop(struct talitos_edesc *edesc,
1343 struct ablkcipher_request *areq,
1344 void (*callback) (struct device *dev,
1345 struct talitos_desc *desc,
1346 void *context, int error))
1348 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1349 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1350 struct device *dev = ctx->dev;
1351 struct talitos_desc *desc = &edesc->desc;
1352 unsigned int cryptlen = areq->nbytes;
1353 unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1356 /* first DWORD empty */
1357 desc->ptr[0].len = 0;
1358 to_talitos_ptr(&desc->ptr[0], 0);
1359 desc->ptr[0].j_extent = 0;
1362 to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
1363 desc->ptr[1].len = cpu_to_be16(ivsize);
1364 desc->ptr[1].j_extent = 0;
1367 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1368 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1373 desc->ptr[3].len = cpu_to_be16(cryptlen);
1374 desc->ptr[3].j_extent = 0;
1376 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1377 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1379 edesc->src_chained);
1381 if (sg_count == 1) {
1382 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
1384 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1385 &edesc->link_tbl[0]);
1387 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1388 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1389 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1393 /* Only one segment now, so no link tbl needed */
1394 to_talitos_ptr(&desc->ptr[3],
1395 sg_dma_address(areq->src));
1400 desc->ptr[4].len = cpu_to_be16(cryptlen);
1401 desc->ptr[4].j_extent = 0;
1403 if (areq->src != areq->dst)
1404 sg_count = talitos_map_sg(dev, areq->dst,
1405 edesc->dst_nents ? : 1,
1406 DMA_FROM_DEVICE, edesc->dst_chained);
1408 if (sg_count == 1) {
1409 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
1411 struct talitos_ptr *link_tbl_ptr =
1412 &edesc->link_tbl[edesc->src_nents + 1];
1414 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1415 (edesc->src_nents + 1) *
1416 sizeof(struct talitos_ptr));
1417 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1418 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1420 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1421 edesc->dma_len, DMA_BIDIRECTIONAL);
1425 map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1428 /* last DWORD empty */
1429 desc->ptr[6].len = 0;
1430 to_talitos_ptr(&desc->ptr[6], 0);
1431 desc->ptr[6].j_extent = 0;
1433 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1434 if (ret != -EINPROGRESS) {
1435 common_nonsnoop_unmap(dev, edesc, areq);
1441 static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1444 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1445 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1446 unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1448 return talitos_edesc_alloc(ctx->dev, NULL, areq->src, areq->dst,
1449 areq->info, 0, areq->nbytes, 0, ivsize, 0,
1453 static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1455 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1456 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1457 struct talitos_edesc *edesc;
1459 /* allocate extended descriptor */
1460 edesc = ablkcipher_edesc_alloc(areq);
1462 return PTR_ERR(edesc);
1465 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1467 return common_nonsnoop(edesc, areq, ablkcipher_done);
1470 static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1472 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1473 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1474 struct talitos_edesc *edesc;
1476 /* allocate extended descriptor */
1477 edesc = ablkcipher_edesc_alloc(areq);
1479 return PTR_ERR(edesc);
1481 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1483 return common_nonsnoop(edesc, areq, ablkcipher_done);
1486 static void common_nonsnoop_hash_unmap(struct device *dev,
1487 struct talitos_edesc *edesc,
1488 struct ahash_request *areq)
1490 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1492 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1494 /* When using hashctx-in, must unmap it. */
1495 if (edesc->desc.ptr[1].len)
1496 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1499 if (edesc->desc.ptr[2].len)
1500 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1503 talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1506 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1511 static void ahash_done(struct device *dev,
1512 struct talitos_desc *desc, void *context,
1515 struct ahash_request *areq = context;
1516 struct talitos_edesc *edesc =
1517 container_of(desc, struct talitos_edesc, desc);
1518 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1520 if (!req_ctx->last && req_ctx->to_hash_later) {
1521 /* Position any partial block for next update/final/finup */
1522 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
1523 req_ctx->nbuf = req_ctx->to_hash_later;
1525 common_nonsnoop_hash_unmap(dev, edesc, areq);
1529 areq->base.complete(&areq->base, err);
1532 static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1533 struct ahash_request *areq, unsigned int length,
1534 void (*callback) (struct device *dev,
1535 struct talitos_desc *desc,
1536 void *context, int error))
1538 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1539 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1540 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1541 struct device *dev = ctx->dev;
1542 struct talitos_desc *desc = &edesc->desc;
1545 /* first DWORD empty */
1546 desc->ptr[0] = zero_entry;
1548 /* hash context in */
1549 if (!req_ctx->first || req_ctx->swinit) {
1550 map_single_talitos_ptr(dev, &desc->ptr[1],
1551 req_ctx->hw_context_size,
1552 (char *)req_ctx->hw_context, 0,
1554 req_ctx->swinit = 0;
1556 desc->ptr[1] = zero_entry;
1557 /* Indicate next op is not the first. */
1563 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1564 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1566 desc->ptr[2] = zero_entry;
1571 desc->ptr[3].len = cpu_to_be16(length);
1572 desc->ptr[3].j_extent = 0;
1574 sg_count = talitos_map_sg(dev, req_ctx->psrc,
1575 edesc->src_nents ? : 1,
1576 DMA_TO_DEVICE, edesc->src_chained);
1578 if (sg_count == 1) {
1579 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1581 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1582 &edesc->link_tbl[0]);
1584 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1585 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1586 dma_sync_single_for_device(ctx->dev,
1587 edesc->dma_link_tbl,
1591 /* Only one segment now, so no link tbl needed */
1592 to_talitos_ptr(&desc->ptr[3],
1593 sg_dma_address(req_ctx->psrc));
1597 /* fifth DWORD empty */
1598 desc->ptr[4] = zero_entry;
1600 /* hash/HMAC out -or- hash context out */
1602 map_single_talitos_ptr(dev, &desc->ptr[5],
1603 crypto_ahash_digestsize(tfm),
1604 areq->result, 0, DMA_FROM_DEVICE);
1606 map_single_talitos_ptr(dev, &desc->ptr[5],
1607 req_ctx->hw_context_size,
1608 req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1610 /* last DWORD empty */
1611 desc->ptr[6] = zero_entry;
1613 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1614 if (ret != -EINPROGRESS) {
1615 common_nonsnoop_hash_unmap(dev, edesc, areq);
1621 static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1622 unsigned int nbytes)
1624 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1625 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1626 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1628 return talitos_edesc_alloc(ctx->dev, NULL, req_ctx->psrc, NULL, NULL, 0,
1629 nbytes, 0, 0, 0, areq->base.flags);
1632 static int ahash_init(struct ahash_request *areq)
1634 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1635 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1637 /* Initialize the context */
1639 req_ctx->first = 1; /* first indicates h/w must init its context */
1640 req_ctx->swinit = 0; /* assume h/w init of context */
1641 req_ctx->hw_context_size =
1642 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1643 ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1644 : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1650 * on h/w without explicit sha224 support, we initialize h/w context
1651 * manually with sha224 constants, and tell it to run sha256.
1653 static int ahash_init_sha224_swinit(struct ahash_request *areq)
1655 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1658 req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1660 req_ctx->hw_context[0] = SHA224_H0;
1661 req_ctx->hw_context[1] = SHA224_H1;
1662 req_ctx->hw_context[2] = SHA224_H2;
1663 req_ctx->hw_context[3] = SHA224_H3;
1664 req_ctx->hw_context[4] = SHA224_H4;
1665 req_ctx->hw_context[5] = SHA224_H5;
1666 req_ctx->hw_context[6] = SHA224_H6;
1667 req_ctx->hw_context[7] = SHA224_H7;
1669 /* init 64-bit count */
1670 req_ctx->hw_context[8] = 0;
1671 req_ctx->hw_context[9] = 0;
1676 static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1678 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1679 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1680 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1681 struct talitos_edesc *edesc;
1682 unsigned int blocksize =
1683 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1684 unsigned int nbytes_to_hash;
1685 unsigned int to_hash_later;
1689 if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1690 /* Buffer up to one whole block */
1691 sg_copy_to_buffer(areq->src,
1692 sg_count(areq->src, nbytes, &chained),
1693 req_ctx->buf + req_ctx->nbuf, nbytes);
1694 req_ctx->nbuf += nbytes;
1698 /* At least (blocksize + 1) bytes are available to hash */
1699 nbytes_to_hash = nbytes + req_ctx->nbuf;
1700 to_hash_later = nbytes_to_hash & (blocksize - 1);
1704 else if (to_hash_later)
1705 /* There is a partial block. Hash the full block(s) now */
1706 nbytes_to_hash -= to_hash_later;
1708 /* Keep one block buffered */
1709 nbytes_to_hash -= blocksize;
1710 to_hash_later = blocksize;
1713 /* Chain in any previously buffered data */
1714 if (req_ctx->nbuf) {
1715 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1716 sg_init_table(req_ctx->bufsl, nsg);
1717 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1719 scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
1720 req_ctx->psrc = req_ctx->bufsl;
1722 req_ctx->psrc = areq->src;
1724 if (to_hash_later) {
1725 int nents = sg_count(areq->src, nbytes, &chained);
1726 sg_pcopy_to_buffer(areq->src, nents,
1729 nbytes - to_hash_later);
1731 req_ctx->to_hash_later = to_hash_later;
1733 /* Allocate extended descriptor */
1734 edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1736 return PTR_ERR(edesc);
1738 edesc->desc.hdr = ctx->desc_hdr_template;
1740 /* On last one, request SEC to pad; otherwise continue */
1742 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1744 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1746 /* request SEC to INIT hash. */
1747 if (req_ctx->first && !req_ctx->swinit)
1748 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1750 /* When the tfm context has a keylen, it's an HMAC.
1751 * A first or last (ie. not middle) descriptor must request HMAC.
1753 if (ctx->keylen && (req_ctx->first || req_ctx->last))
1754 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1756 return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1760 static int ahash_update(struct ahash_request *areq)
1762 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1766 return ahash_process_req(areq, areq->nbytes);
1769 static int ahash_final(struct ahash_request *areq)
1771 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1775 return ahash_process_req(areq, 0);
1778 static int ahash_finup(struct ahash_request *areq)
1780 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1784 return ahash_process_req(areq, areq->nbytes);
1787 static int ahash_digest(struct ahash_request *areq)
1789 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1790 struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
1795 return ahash_process_req(areq, areq->nbytes);
1798 struct keyhash_result {
1799 struct completion completion;
1803 static void keyhash_complete(struct crypto_async_request *req, int err)
1805 struct keyhash_result *res = req->data;
1807 if (err == -EINPROGRESS)
1811 complete(&res->completion);
1814 static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
1817 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1819 struct scatterlist sg[1];
1820 struct ahash_request *req;
1821 struct keyhash_result hresult;
1824 init_completion(&hresult.completion);
1826 req = ahash_request_alloc(tfm, GFP_KERNEL);
1830 /* Keep tfm keylen == 0 during hash of the long key */
1832 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1833 keyhash_complete, &hresult);
1835 sg_init_one(&sg[0], key, keylen);
1837 ahash_request_set_crypt(req, sg, hash, keylen);
1838 ret = crypto_ahash_digest(req);
1844 ret = wait_for_completion_interruptible(
1845 &hresult.completion);
1852 ahash_request_free(req);
1857 static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1858 unsigned int keylen)
1860 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1861 unsigned int blocksize =
1862 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1863 unsigned int digestsize = crypto_ahash_digestsize(tfm);
1864 unsigned int keysize = keylen;
1865 u8 hash[SHA512_DIGEST_SIZE];
1868 if (keylen <= blocksize)
1869 memcpy(ctx->key, key, keysize);
1871 /* Must get the hash of the long key */
1872 ret = keyhash(tfm, key, keylen, hash);
1875 crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1879 keysize = digestsize;
1880 memcpy(ctx->key, hash, digestsize);
1883 ctx->keylen = keysize;
1889 struct talitos_alg_template {
1892 struct crypto_alg crypto;
1893 struct ahash_alg hash;
1895 __be32 desc_hdr_template;
1898 static struct talitos_alg_template driver_algs[] = {
1899 /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
1900 { .type = CRYPTO_ALG_TYPE_AEAD,
1902 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1903 .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1904 .cra_blocksize = AES_BLOCK_SIZE,
1905 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1907 .ivsize = AES_BLOCK_SIZE,
1908 .maxauthsize = SHA1_DIGEST_SIZE,
1911 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1912 DESC_HDR_SEL0_AESU |
1913 DESC_HDR_MODE0_AESU_CBC |
1914 DESC_HDR_SEL1_MDEUA |
1915 DESC_HDR_MODE1_MDEU_INIT |
1916 DESC_HDR_MODE1_MDEU_PAD |
1917 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1919 { .type = CRYPTO_ALG_TYPE_AEAD,
1921 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1922 .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1923 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1924 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1926 .ivsize = DES3_EDE_BLOCK_SIZE,
1927 .maxauthsize = SHA1_DIGEST_SIZE,
1930 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1932 DESC_HDR_MODE0_DEU_CBC |
1933 DESC_HDR_MODE0_DEU_3DES |
1934 DESC_HDR_SEL1_MDEUA |
1935 DESC_HDR_MODE1_MDEU_INIT |
1936 DESC_HDR_MODE1_MDEU_PAD |
1937 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1939 { .type = CRYPTO_ALG_TYPE_AEAD,
1941 .cra_name = "authenc(hmac(sha224),cbc(aes))",
1942 .cra_driver_name = "authenc-hmac-sha224-cbc-aes-talitos",
1943 .cra_blocksize = AES_BLOCK_SIZE,
1944 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1946 .ivsize = AES_BLOCK_SIZE,
1947 .maxauthsize = SHA224_DIGEST_SIZE,
1950 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1951 DESC_HDR_SEL0_AESU |
1952 DESC_HDR_MODE0_AESU_CBC |
1953 DESC_HDR_SEL1_MDEUA |
1954 DESC_HDR_MODE1_MDEU_INIT |
1955 DESC_HDR_MODE1_MDEU_PAD |
1956 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1958 { .type = CRYPTO_ALG_TYPE_AEAD,
1960 .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
1961 .cra_driver_name = "authenc-hmac-sha224-cbc-3des-talitos",
1962 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1963 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1965 .ivsize = DES3_EDE_BLOCK_SIZE,
1966 .maxauthsize = SHA224_DIGEST_SIZE,
1969 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1971 DESC_HDR_MODE0_DEU_CBC |
1972 DESC_HDR_MODE0_DEU_3DES |
1973 DESC_HDR_SEL1_MDEUA |
1974 DESC_HDR_MODE1_MDEU_INIT |
1975 DESC_HDR_MODE1_MDEU_PAD |
1976 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1978 { .type = CRYPTO_ALG_TYPE_AEAD,
1980 .cra_name = "authenc(hmac(sha256),cbc(aes))",
1981 .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1982 .cra_blocksize = AES_BLOCK_SIZE,
1983 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1985 .ivsize = AES_BLOCK_SIZE,
1986 .maxauthsize = SHA256_DIGEST_SIZE,
1989 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1990 DESC_HDR_SEL0_AESU |
1991 DESC_HDR_MODE0_AESU_CBC |
1992 DESC_HDR_SEL1_MDEUA |
1993 DESC_HDR_MODE1_MDEU_INIT |
1994 DESC_HDR_MODE1_MDEU_PAD |
1995 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1997 { .type = CRYPTO_ALG_TYPE_AEAD,
1999 .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
2000 .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
2001 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2002 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2004 .ivsize = DES3_EDE_BLOCK_SIZE,
2005 .maxauthsize = SHA256_DIGEST_SIZE,
2008 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2010 DESC_HDR_MODE0_DEU_CBC |
2011 DESC_HDR_MODE0_DEU_3DES |
2012 DESC_HDR_SEL1_MDEUA |
2013 DESC_HDR_MODE1_MDEU_INIT |
2014 DESC_HDR_MODE1_MDEU_PAD |
2015 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2017 { .type = CRYPTO_ALG_TYPE_AEAD,
2019 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2020 .cra_driver_name = "authenc-hmac-sha384-cbc-aes-talitos",
2021 .cra_blocksize = AES_BLOCK_SIZE,
2022 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2024 .ivsize = AES_BLOCK_SIZE,
2025 .maxauthsize = SHA384_DIGEST_SIZE,
2028 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2029 DESC_HDR_SEL0_AESU |
2030 DESC_HDR_MODE0_AESU_CBC |
2031 DESC_HDR_SEL1_MDEUB |
2032 DESC_HDR_MODE1_MDEU_INIT |
2033 DESC_HDR_MODE1_MDEU_PAD |
2034 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2036 { .type = CRYPTO_ALG_TYPE_AEAD,
2038 .cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
2039 .cra_driver_name = "authenc-hmac-sha384-cbc-3des-talitos",
2040 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2041 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2043 .ivsize = DES3_EDE_BLOCK_SIZE,
2044 .maxauthsize = SHA384_DIGEST_SIZE,
2047 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2049 DESC_HDR_MODE0_DEU_CBC |
2050 DESC_HDR_MODE0_DEU_3DES |
2051 DESC_HDR_SEL1_MDEUB |
2052 DESC_HDR_MODE1_MDEU_INIT |
2053 DESC_HDR_MODE1_MDEU_PAD |
2054 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2056 { .type = CRYPTO_ALG_TYPE_AEAD,
2058 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2059 .cra_driver_name = "authenc-hmac-sha512-cbc-aes-talitos",
2060 .cra_blocksize = AES_BLOCK_SIZE,
2061 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2063 .ivsize = AES_BLOCK_SIZE,
2064 .maxauthsize = SHA512_DIGEST_SIZE,
2067 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2068 DESC_HDR_SEL0_AESU |
2069 DESC_HDR_MODE0_AESU_CBC |
2070 DESC_HDR_SEL1_MDEUB |
2071 DESC_HDR_MODE1_MDEU_INIT |
2072 DESC_HDR_MODE1_MDEU_PAD |
2073 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2075 { .type = CRYPTO_ALG_TYPE_AEAD,
2077 .cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
2078 .cra_driver_name = "authenc-hmac-sha512-cbc-3des-talitos",
2079 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2080 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2082 .ivsize = DES3_EDE_BLOCK_SIZE,
2083 .maxauthsize = SHA512_DIGEST_SIZE,
2086 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2088 DESC_HDR_MODE0_DEU_CBC |
2089 DESC_HDR_MODE0_DEU_3DES |
2090 DESC_HDR_SEL1_MDEUB |
2091 DESC_HDR_MODE1_MDEU_INIT |
2092 DESC_HDR_MODE1_MDEU_PAD |
2093 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2095 { .type = CRYPTO_ALG_TYPE_AEAD,
2097 .cra_name = "authenc(hmac(md5),cbc(aes))",
2098 .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2099 .cra_blocksize = AES_BLOCK_SIZE,
2100 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2102 .ivsize = AES_BLOCK_SIZE,
2103 .maxauthsize = MD5_DIGEST_SIZE,
2106 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2107 DESC_HDR_SEL0_AESU |
2108 DESC_HDR_MODE0_AESU_CBC |
2109 DESC_HDR_SEL1_MDEUA |
2110 DESC_HDR_MODE1_MDEU_INIT |
2111 DESC_HDR_MODE1_MDEU_PAD |
2112 DESC_HDR_MODE1_MDEU_MD5_HMAC,
2114 { .type = CRYPTO_ALG_TYPE_AEAD,
2116 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2117 .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2118 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2119 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2121 .ivsize = DES3_EDE_BLOCK_SIZE,
2122 .maxauthsize = MD5_DIGEST_SIZE,
2125 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2127 DESC_HDR_MODE0_DEU_CBC |
2128 DESC_HDR_MODE0_DEU_3DES |
2129 DESC_HDR_SEL1_MDEUA |
2130 DESC_HDR_MODE1_MDEU_INIT |
2131 DESC_HDR_MODE1_MDEU_PAD |
2132 DESC_HDR_MODE1_MDEU_MD5_HMAC,
2134 /* ABLKCIPHER algorithms. */
2135 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2137 .cra_name = "cbc(aes)",
2138 .cra_driver_name = "cbc-aes-talitos",
2139 .cra_blocksize = AES_BLOCK_SIZE,
2140 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2143 .min_keysize = AES_MIN_KEY_SIZE,
2144 .max_keysize = AES_MAX_KEY_SIZE,
2145 .ivsize = AES_BLOCK_SIZE,
2148 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2149 DESC_HDR_SEL0_AESU |
2150 DESC_HDR_MODE0_AESU_CBC,
2152 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2154 .cra_name = "cbc(des3_ede)",
2155 .cra_driver_name = "cbc-3des-talitos",
2156 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2157 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2160 .min_keysize = DES3_EDE_KEY_SIZE,
2161 .max_keysize = DES3_EDE_KEY_SIZE,
2162 .ivsize = DES3_EDE_BLOCK_SIZE,
2165 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2167 DESC_HDR_MODE0_DEU_CBC |
2168 DESC_HDR_MODE0_DEU_3DES,
2170 /* AHASH algorithms. */
2171 { .type = CRYPTO_ALG_TYPE_AHASH,
2173 .halg.digestsize = MD5_DIGEST_SIZE,
2176 .cra_driver_name = "md5-talitos",
2177 .cra_blocksize = MD5_BLOCK_SIZE,
2178 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2182 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2183 DESC_HDR_SEL0_MDEUA |
2184 DESC_HDR_MODE0_MDEU_MD5,
2186 { .type = CRYPTO_ALG_TYPE_AHASH,
2188 .halg.digestsize = SHA1_DIGEST_SIZE,
2191 .cra_driver_name = "sha1-talitos",
2192 .cra_blocksize = SHA1_BLOCK_SIZE,
2193 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2197 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2198 DESC_HDR_SEL0_MDEUA |
2199 DESC_HDR_MODE0_MDEU_SHA1,
2201 { .type = CRYPTO_ALG_TYPE_AHASH,
2203 .halg.digestsize = SHA224_DIGEST_SIZE,
2205 .cra_name = "sha224",
2206 .cra_driver_name = "sha224-talitos",
2207 .cra_blocksize = SHA224_BLOCK_SIZE,
2208 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2212 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2213 DESC_HDR_SEL0_MDEUA |
2214 DESC_HDR_MODE0_MDEU_SHA224,
2216 { .type = CRYPTO_ALG_TYPE_AHASH,
2218 .halg.digestsize = SHA256_DIGEST_SIZE,
2220 .cra_name = "sha256",
2221 .cra_driver_name = "sha256-talitos",
2222 .cra_blocksize = SHA256_BLOCK_SIZE,
2223 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2227 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2228 DESC_HDR_SEL0_MDEUA |
2229 DESC_HDR_MODE0_MDEU_SHA256,
2231 { .type = CRYPTO_ALG_TYPE_AHASH,
2233 .halg.digestsize = SHA384_DIGEST_SIZE,
2235 .cra_name = "sha384",
2236 .cra_driver_name = "sha384-talitos",
2237 .cra_blocksize = SHA384_BLOCK_SIZE,
2238 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2242 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2243 DESC_HDR_SEL0_MDEUB |
2244 DESC_HDR_MODE0_MDEUB_SHA384,
2246 { .type = CRYPTO_ALG_TYPE_AHASH,
2248 .halg.digestsize = SHA512_DIGEST_SIZE,
2250 .cra_name = "sha512",
2251 .cra_driver_name = "sha512-talitos",
2252 .cra_blocksize = SHA512_BLOCK_SIZE,
2253 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2257 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2258 DESC_HDR_SEL0_MDEUB |
2259 DESC_HDR_MODE0_MDEUB_SHA512,
2261 { .type = CRYPTO_ALG_TYPE_AHASH,
2263 .halg.digestsize = MD5_DIGEST_SIZE,
2265 .cra_name = "hmac(md5)",
2266 .cra_driver_name = "hmac-md5-talitos",
2267 .cra_blocksize = MD5_BLOCK_SIZE,
2268 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2272 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2273 DESC_HDR_SEL0_MDEUA |
2274 DESC_HDR_MODE0_MDEU_MD5,
2276 { .type = CRYPTO_ALG_TYPE_AHASH,
2278 .halg.digestsize = SHA1_DIGEST_SIZE,
2280 .cra_name = "hmac(sha1)",
2281 .cra_driver_name = "hmac-sha1-talitos",
2282 .cra_blocksize = SHA1_BLOCK_SIZE,
2283 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2287 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2288 DESC_HDR_SEL0_MDEUA |
2289 DESC_HDR_MODE0_MDEU_SHA1,
2291 { .type = CRYPTO_ALG_TYPE_AHASH,
2293 .halg.digestsize = SHA224_DIGEST_SIZE,
2295 .cra_name = "hmac(sha224)",
2296 .cra_driver_name = "hmac-sha224-talitos",
2297 .cra_blocksize = SHA224_BLOCK_SIZE,
2298 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2302 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2303 DESC_HDR_SEL0_MDEUA |
2304 DESC_HDR_MODE0_MDEU_SHA224,
2306 { .type = CRYPTO_ALG_TYPE_AHASH,
2308 .halg.digestsize = SHA256_DIGEST_SIZE,
2310 .cra_name = "hmac(sha256)",
2311 .cra_driver_name = "hmac-sha256-talitos",
2312 .cra_blocksize = SHA256_BLOCK_SIZE,
2313 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2317 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2318 DESC_HDR_SEL0_MDEUA |
2319 DESC_HDR_MODE0_MDEU_SHA256,
2321 { .type = CRYPTO_ALG_TYPE_AHASH,
2323 .halg.digestsize = SHA384_DIGEST_SIZE,
2325 .cra_name = "hmac(sha384)",
2326 .cra_driver_name = "hmac-sha384-talitos",
2327 .cra_blocksize = SHA384_BLOCK_SIZE,
2328 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2332 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2333 DESC_HDR_SEL0_MDEUB |
2334 DESC_HDR_MODE0_MDEUB_SHA384,
2336 { .type = CRYPTO_ALG_TYPE_AHASH,
2338 .halg.digestsize = SHA512_DIGEST_SIZE,
2340 .cra_name = "hmac(sha512)",
2341 .cra_driver_name = "hmac-sha512-talitos",
2342 .cra_blocksize = SHA512_BLOCK_SIZE,
2343 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2347 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2348 DESC_HDR_SEL0_MDEUB |
2349 DESC_HDR_MODE0_MDEUB_SHA512,
2353 struct talitos_crypto_alg {
2354 struct list_head entry;
2356 struct talitos_alg_template algt;
2359 static int talitos_cra_init(struct crypto_tfm *tfm)
2361 struct crypto_alg *alg = tfm->__crt_alg;
2362 struct talitos_crypto_alg *talitos_alg;
2363 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2364 struct talitos_private *priv;
2366 if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2367 talitos_alg = container_of(__crypto_ahash_alg(alg),
2368 struct talitos_crypto_alg,
2371 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2374 /* update context with ptr to dev */
2375 ctx->dev = talitos_alg->dev;
2377 /* assign SEC channel to tfm in round-robin fashion */
2378 priv = dev_get_drvdata(ctx->dev);
2379 ctx->ch = atomic_inc_return(&priv->last_chan) &
2380 (priv->num_channels - 1);
2382 /* copy descriptor header template value */
2383 ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
2385 /* select done notification */
2386 ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
2391 static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2393 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2395 talitos_cra_init(tfm);
2397 /* random first IV */
2398 get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
2403 static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2405 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2407 talitos_cra_init(tfm);
2410 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2411 sizeof(struct talitos_ahash_req_ctx));
2417 * given the alg's descriptor header template, determine whether descriptor
2418 * type and primary/secondary execution units required match the hw
2419 * capabilities description provided in the device tree node.
2421 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2423 struct talitos_private *priv = dev_get_drvdata(dev);
2426 ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2427 (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2429 if (SECONDARY_EU(desc_hdr_template))
2430 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2431 & priv->exec_units);
2436 static int talitos_remove(struct platform_device *ofdev)
2438 struct device *dev = &ofdev->dev;
2439 struct talitos_private *priv = dev_get_drvdata(dev);
2440 struct talitos_crypto_alg *t_alg, *n;
2443 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
2444 switch (t_alg->algt.type) {
2445 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2446 case CRYPTO_ALG_TYPE_AEAD:
2447 crypto_unregister_alg(&t_alg->algt.alg.crypto);
2449 case CRYPTO_ALG_TYPE_AHASH:
2450 crypto_unregister_ahash(&t_alg->algt.alg.hash);
2453 list_del(&t_alg->entry);
2457 if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2458 talitos_unregister_rng(dev);
2460 for (i = 0; i < priv->num_channels; i++)
2461 kfree(priv->chan[i].fifo);
2465 for (i = 0; i < 2; i++)
2467 free_irq(priv->irq[i], dev);
2468 irq_dispose_mapping(priv->irq[i]);
2471 tasklet_kill(&priv->done_task[0]);
2473 tasklet_kill(&priv->done_task[1]);
2477 dev_set_drvdata(dev, NULL);
2484 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2485 struct talitos_alg_template
2488 struct talitos_private *priv = dev_get_drvdata(dev);
2489 struct talitos_crypto_alg *t_alg;
2490 struct crypto_alg *alg;
2492 t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2494 return ERR_PTR(-ENOMEM);
2496 t_alg->algt = *template;
2498 switch (t_alg->algt.type) {
2499 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2500 alg = &t_alg->algt.alg.crypto;
2501 alg->cra_init = talitos_cra_init;
2502 alg->cra_type = &crypto_ablkcipher_type;
2503 alg->cra_ablkcipher.setkey = ablkcipher_setkey;
2504 alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
2505 alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
2506 alg->cra_ablkcipher.geniv = "eseqiv";
2508 case CRYPTO_ALG_TYPE_AEAD:
2509 alg = &t_alg->algt.alg.crypto;
2510 alg->cra_init = talitos_cra_init_aead;
2511 alg->cra_type = &crypto_aead_type;
2512 alg->cra_aead.setkey = aead_setkey;
2513 alg->cra_aead.setauthsize = aead_setauthsize;
2514 alg->cra_aead.encrypt = aead_encrypt;
2515 alg->cra_aead.decrypt = aead_decrypt;
2516 alg->cra_aead.givencrypt = aead_givencrypt;
2517 alg->cra_aead.geniv = "<built-in>";
2519 case CRYPTO_ALG_TYPE_AHASH:
2520 alg = &t_alg->algt.alg.hash.halg.base;
2521 alg->cra_init = talitos_cra_init_ahash;
2522 alg->cra_type = &crypto_ahash_type;
2523 t_alg->algt.alg.hash.init = ahash_init;
2524 t_alg->algt.alg.hash.update = ahash_update;
2525 t_alg->algt.alg.hash.final = ahash_final;
2526 t_alg->algt.alg.hash.finup = ahash_finup;
2527 t_alg->algt.alg.hash.digest = ahash_digest;
2528 t_alg->algt.alg.hash.setkey = ahash_setkey;
2530 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
2531 !strncmp(alg->cra_name, "hmac", 4)) {
2533 return ERR_PTR(-ENOTSUPP);
2535 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
2536 (!strcmp(alg->cra_name, "sha224") ||
2537 !strcmp(alg->cra_name, "hmac(sha224)"))) {
2538 t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2539 t_alg->algt.desc_hdr_template =
2540 DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2541 DESC_HDR_SEL0_MDEUA |
2542 DESC_HDR_MODE0_MDEU_SHA256;
2546 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2547 return ERR_PTR(-EINVAL);
2550 alg->cra_module = THIS_MODULE;
2551 alg->cra_priority = TALITOS_CRA_PRIORITY;
2552 alg->cra_alignmask = 0;
2553 alg->cra_ctxsize = sizeof(struct talitos_ctx);
2554 alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
2561 static int talitos_probe_irq(struct platform_device *ofdev)
2563 struct device *dev = &ofdev->dev;
2564 struct device_node *np = ofdev->dev.of_node;
2565 struct talitos_private *priv = dev_get_drvdata(dev);
2568 priv->irq[0] = irq_of_parse_and_map(np, 0);
2569 if (!priv->irq[0]) {
2570 dev_err(dev, "failed to map irq\n");
2574 priv->irq[1] = irq_of_parse_and_map(np, 1);
2576 /* get the primary irq line */
2577 if (!priv->irq[1]) {
2578 err = request_irq(priv->irq[0], talitos_interrupt_4ch, 0,
2579 dev_driver_string(dev), dev);
2583 err = request_irq(priv->irq[0], talitos_interrupt_ch0_2, 0,
2584 dev_driver_string(dev), dev);
2588 /* get the secondary irq line */
2589 err = request_irq(priv->irq[1], talitos_interrupt_ch1_3, 0,
2590 dev_driver_string(dev), dev);
2592 dev_err(dev, "failed to request secondary irq\n");
2593 irq_dispose_mapping(priv->irq[1]);
2601 dev_err(dev, "failed to request primary irq\n");
2602 irq_dispose_mapping(priv->irq[0]);
2609 static int talitos_probe(struct platform_device *ofdev)
2611 struct device *dev = &ofdev->dev;
2612 struct device_node *np = ofdev->dev.of_node;
2613 struct talitos_private *priv;
2614 const unsigned int *prop;
2617 priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2621 dev_set_drvdata(dev, priv);
2623 priv->ofdev = ofdev;
2625 spin_lock_init(&priv->reg_lock);
2627 err = talitos_probe_irq(ofdev);
2631 if (!priv->irq[1]) {
2632 tasklet_init(&priv->done_task[0], talitos_done_4ch,
2633 (unsigned long)dev);
2635 tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
2636 (unsigned long)dev);
2637 tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
2638 (unsigned long)dev);
2641 INIT_LIST_HEAD(&priv->alg_list);
2643 priv->reg = of_iomap(np, 0);
2645 dev_err(dev, "failed to of_iomap\n");
2650 /* get SEC version capabilities from device tree */
2651 prop = of_get_property(np, "fsl,num-channels", NULL);
2653 priv->num_channels = *prop;
2655 prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2657 priv->chfifo_len = *prop;
2659 prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2661 priv->exec_units = *prop;
2663 prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2665 priv->desc_types = *prop;
2667 if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2668 !priv->exec_units || !priv->desc_types) {
2669 dev_err(dev, "invalid property data in device tree node\n");
2674 if (of_device_is_compatible(np, "fsl,sec3.0"))
2675 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2677 if (of_device_is_compatible(np, "fsl,sec2.1"))
2678 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
2679 TALITOS_FTR_SHA224_HWINIT |
2680 TALITOS_FTR_HMAC_OK;
2682 priv->chan = kzalloc(sizeof(struct talitos_channel) *
2683 priv->num_channels, GFP_KERNEL);
2685 dev_err(dev, "failed to allocate channel management space\n");
2690 for (i = 0; i < priv->num_channels; i++) {
2691 priv->chan[i].reg = priv->reg + TALITOS_CH_STRIDE * (i + 1);
2692 if (!priv->irq[1] || !(i & 1))
2693 priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
2696 for (i = 0; i < priv->num_channels; i++) {
2697 spin_lock_init(&priv->chan[i].head_lock);
2698 spin_lock_init(&priv->chan[i].tail_lock);
2701 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2703 for (i = 0; i < priv->num_channels; i++) {
2704 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2705 priv->fifo_len, GFP_KERNEL);
2706 if (!priv->chan[i].fifo) {
2707 dev_err(dev, "failed to allocate request fifo %d\n", i);
2713 for (i = 0; i < priv->num_channels; i++)
2714 atomic_set(&priv->chan[i].submit_count,
2715 -(priv->chfifo_len - 1));
2717 dma_set_mask(dev, DMA_BIT_MASK(36));
2719 /* reset and initialize the h/w */
2720 err = init_device(dev);
2722 dev_err(dev, "failed to initialize device\n");
2726 /* register the RNG, if available */
2727 if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2728 err = talitos_register_rng(dev);
2730 dev_err(dev, "failed to register hwrng: %d\n", err);
2733 dev_info(dev, "hwrng\n");
2736 /* register crypto algorithms the device supports */
2737 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2738 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2739 struct talitos_crypto_alg *t_alg;
2742 t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2743 if (IS_ERR(t_alg)) {
2744 err = PTR_ERR(t_alg);
2745 if (err == -ENOTSUPP)
2750 switch (t_alg->algt.type) {
2751 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2752 case CRYPTO_ALG_TYPE_AEAD:
2753 err = crypto_register_alg(
2754 &t_alg->algt.alg.crypto);
2755 name = t_alg->algt.alg.crypto.cra_driver_name;
2757 case CRYPTO_ALG_TYPE_AHASH:
2758 err = crypto_register_ahash(
2759 &t_alg->algt.alg.hash);
2761 t_alg->algt.alg.hash.halg.base.cra_driver_name;
2765 dev_err(dev, "%s alg registration failed\n",
2769 list_add_tail(&t_alg->entry, &priv->alg_list);
2772 if (!list_empty(&priv->alg_list))
2773 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
2774 (char *)of_get_property(np, "compatible", NULL));
2779 talitos_remove(ofdev);
2784 static const struct of_device_id talitos_match[] = {
2786 .compatible = "fsl,sec2.0",
2790 MODULE_DEVICE_TABLE(of, talitos_match);
2792 static struct platform_driver talitos_driver = {
2795 .owner = THIS_MODULE,
2796 .of_match_table = talitos_match,
2798 .probe = talitos_probe,
2799 .remove = talitos_remove,
2802 module_platform_driver(talitos_driver);
2804 MODULE_LICENSE("GPL");
2805 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2806 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");