2 * Freescale SEC (talitos) device register and descriptor header defines
4 * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
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7 * modification, are permitted provided that the following conditions
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31 #define TALITOS_TIMEOUT 100000
32 #define TALITOS_MAX_DATA_LEN 65535
34 #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
35 #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
36 #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
38 /* descriptor pointer entry */
41 struct { /* SEC2 format */
42 __be16 len; /* length */
43 u8 j_extent; /* jump to sg link table and/or extent*/
44 u8 eptr; /* extended address */
46 struct { /* SEC1 format */
48 __be16 len1; /* length */
51 __be32 ptr; /* address */
54 static const struct talitos_ptr zero_entry = {
63 __be32 hdr; /* header high bits */
65 __be32 hdr_lo; /* header low bits */
66 __be32 hdr1; /* header for SEC1 */
68 struct talitos_ptr ptr[7]; /* ptr/len pair array */
69 __be32 next_desc; /* next descriptor (SEC1) */
73 * talitos_request - descriptor submission request
74 * @desc: descriptor pointer (kernel virtual)
75 * @dma_desc: descriptor's physical bus address
76 * @callback: whom to call when descriptor processing is done
77 * @context: caller context (optional)
79 struct talitos_request {
80 struct talitos_desc *desc;
82 void (*callback) (struct device *dev, struct talitos_desc *desc,
83 void *context, int error);
87 /* per-channel fifo management */
88 struct talitos_channel {
92 struct talitos_request *fifo;
94 /* number of requests pending in channel h/w fifo */
95 atomic_t submit_count ____cacheline_aligned;
97 /* request submission (head) lock */
98 spinlock_t head_lock ____cacheline_aligned;
99 /* index to next free descriptor request */
102 /* request release (tail) lock */
103 spinlock_t tail_lock ____cacheline_aligned;
104 /* index to next in-progress/done descriptor request */
108 struct talitos_private {
110 struct platform_device *ofdev;
114 /* SEC global registers lock */
115 spinlock_t reg_lock ____cacheline_aligned;
117 /* SEC version geometry (from device tree node) */
118 unsigned int num_channels;
119 unsigned int chfifo_len;
120 unsigned int exec_units;
121 unsigned int desc_types;
123 /* SEC Compatibility info */
124 unsigned long features;
127 * length of the request fifo
128 * fifo_len is chfifo_len rounded up to next power of 2
129 * so we can use bitwise ops to wrap
131 unsigned int fifo_len;
133 struct talitos_channel *chan;
135 /* next channel to be assigned next incoming descriptor */
136 atomic_t last_chan ____cacheline_aligned;
138 /* request callback tasklet */
139 struct tasklet_struct done_task[2];
141 /* list of registered algorithms */
142 struct list_head alg_list;
148 extern int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
149 void (*callback)(struct device *dev,
150 struct talitos_desc *desc,
151 void *context, int error),
155 #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
156 #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
157 #define TALITOS_FTR_SHA224_HWINIT 0x00000004
158 #define TALITOS_FTR_HMAC_OK 0x00000008
161 * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
164 /* global register offset addresses */
165 #define TALITOS_MCR 0x1030 /* master control register */
166 #define TALITOS_MCR_RCA0 (1 << 15) /* remap channel 0 */
167 #define TALITOS_MCR_RCA1 (1 << 14) /* remap channel 1 */
168 #define TALITOS_MCR_RCA2 (1 << 13) /* remap channel 2 */
169 #define TALITOS_MCR_RCA3 (1 << 12) /* remap channel 3 */
170 #define TALITOS_MCR_SWR 0x1 /* s/w reset */
171 #define TALITOS_MCR_LO 0x1034
172 #define TALITOS_IMR 0x1008 /* interrupt mask register */
173 #define TALITOS_IMR_INIT 0x100ff /* enable channel IRQs */
174 #define TALITOS_IMR_DONE 0x00055 /* done IRQs */
175 #define TALITOS_IMR_LO 0x100C
176 #define TALITOS_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */
177 #define TALITOS_ISR 0x1010 /* interrupt status register */
178 #define TALITOS_ISR_4CHERR 0xaa /* 4 channel errors mask */
179 #define TALITOS_ISR_4CHDONE 0x55 /* 4 channel done mask */
180 #define TALITOS_ISR_CH_0_2_ERR 0x22 /* channels 0, 2 errors mask */
181 #define TALITOS_ISR_CH_0_2_DONE 0x11 /* channels 0, 2 done mask */
182 #define TALITOS_ISR_CH_1_3_ERR 0x88 /* channels 1, 3 errors mask */
183 #define TALITOS_ISR_CH_1_3_DONE 0x44 /* channels 1, 3 done mask */
184 #define TALITOS_ISR_LO 0x1014
185 #define TALITOS_ICR 0x1018 /* interrupt clear register */
186 #define TALITOS_ICR_LO 0x101C
188 /* channel register address stride */
189 #define TALITOS_CH_BASE_OFFSET 0x1000 /* default channel map base */
190 #define TALITOS_CH_STRIDE 0x100
192 /* channel configuration register */
193 #define TALITOS_CCCR 0x8
194 #define TALITOS_CCCR_CONT 0x2 /* channel continue */
195 #define TALITOS_CCCR_RESET 0x1 /* channel reset */
196 #define TALITOS_CCCR_LO 0xc
197 #define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
198 #define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
199 #define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
200 #define TALITOS_CCCR_LO_NT 0x4 /* notification type */
201 #define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
203 /* CCPSR: channel pointer status register */
204 #define TALITOS_CCPSR 0x10
205 #define TALITOS_CCPSR_LO 0x14
206 #define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
207 #define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
208 #define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
209 #define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
210 #define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
211 #define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
212 #define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
213 #define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
214 #define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
215 #define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
216 #define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
217 #define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
219 /* channel fetch fifo register */
220 #define TALITOS_FF 0x48
221 #define TALITOS_FF_LO 0x4c
223 /* current descriptor pointer register */
224 #define TALITOS_CDPR 0x40
225 #define TALITOS_CDPR_LO 0x44
227 /* descriptor buffer register */
228 #define TALITOS_DESCBUF 0x80
229 #define TALITOS_DESCBUF_LO 0x84
231 /* gather link table */
232 #define TALITOS_GATHER 0xc0
233 #define TALITOS_GATHER_LO 0xc4
235 /* scatter link table */
236 #define TALITOS_SCATTER 0xe0
237 #define TALITOS_SCATTER_LO 0xe4
239 /* execution unit interrupt status registers */
240 #define TALITOS_DEUISR 0x2030 /* DES unit */
241 #define TALITOS_DEUISR_LO 0x2034
242 #define TALITOS_AESUISR 0x4030 /* AES unit */
243 #define TALITOS_AESUISR_LO 0x4034
244 #define TALITOS_MDEUISR 0x6030 /* message digest unit */
245 #define TALITOS_MDEUISR_LO 0x6034
246 #define TALITOS_MDEUICR 0x6038 /* interrupt control */
247 #define TALITOS_MDEUICR_LO 0x603c
248 #define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
249 #define TALITOS_AFEUISR 0x8030 /* arc4 unit */
250 #define TALITOS_AFEUISR_LO 0x8034
251 #define TALITOS_RNGUISR 0xa030 /* random number unit */
252 #define TALITOS_RNGUISR_LO 0xa034
253 #define TALITOS_RNGUSR 0xa028 /* rng status */
254 #define TALITOS_RNGUSR_LO 0xa02c
255 #define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */
256 #define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */
257 #define TALITOS_RNGUDSR 0xa010 /* data size */
258 #define TALITOS_RNGUDSR_LO 0xa014
259 #define TALITOS_RNGU_FIFO 0xa800 /* output FIFO */
260 #define TALITOS_RNGU_FIFO_LO 0xa804 /* output FIFO */
261 #define TALITOS_RNGURCR 0xa018 /* reset control */
262 #define TALITOS_RNGURCR_LO 0xa01c
263 #define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */
264 #define TALITOS_PKEUISR 0xc030 /* public key unit */
265 #define TALITOS_PKEUISR_LO 0xc034
266 #define TALITOS_KEUISR 0xe030 /* kasumi unit */
267 #define TALITOS_KEUISR_LO 0xe034
268 #define TALITOS_CRCUISR 0xf030 /* cyclic redundancy check unit*/
269 #define TALITOS_CRCUISR_LO 0xf034
271 #define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28
272 #define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48
275 * talitos descriptor header (hdr) bits
278 /* written back when done */
279 #define DESC_HDR_DONE cpu_to_be32(0xff000000)
280 #define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
281 #define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
282 #define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
284 /* primary execution unit select */
285 #define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
286 #define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
287 #define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
288 #define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
289 #define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
290 #define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
291 #define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
292 #define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
293 #define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
294 #define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
296 /* primary execution unit mode (MODE0) and derivatives */
297 #define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
298 #define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
299 #define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
300 #define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
301 #define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
302 #define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
303 #define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
304 #define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
305 #define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
306 #define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
307 #define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
308 #define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
309 #define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
310 #define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
311 #define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
312 DESC_HDR_MODE0_MDEU_HMAC)
313 #define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
314 DESC_HDR_MODE0_MDEU_HMAC)
315 #define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \
316 DESC_HDR_MODE0_MDEU_HMAC)
318 /* secondary execution unit select (SEL1) */
319 #define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
320 #define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
321 #define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
322 #define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
324 /* secondary execution unit mode (MODE1) and derivatives */
325 #define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
326 #define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
327 #define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
328 #define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
329 #define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
330 #define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
331 #define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
332 #define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
333 #define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
334 #define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
335 #define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
336 DESC_HDR_MODE1_MDEU_HMAC)
337 #define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
338 DESC_HDR_MODE1_MDEU_HMAC)
339 #define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
340 DESC_HDR_MODE1_MDEU_HMAC)
341 #define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \
342 DESC_HDR_MODE1_MDEU_HMAC)
343 #define DESC_HDR_MODE1_MDEUB_SHA384_HMAC (DESC_HDR_MODE1_MDEUB_SHA384 | \
344 DESC_HDR_MODE1_MDEU_HMAC)
345 #define DESC_HDR_MODE1_MDEUB_SHA512_HMAC (DESC_HDR_MODE1_MDEUB_SHA512 | \
346 DESC_HDR_MODE1_MDEU_HMAC)
348 /* direction of overall data flow (DIR) */
349 #define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
351 /* request done notification (DN) */
352 #define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
354 /* descriptor types */
355 #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
356 #define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
357 #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
358 #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
360 /* link table extent field bits */
361 #define DESC_PTR_LNKTBL_JUMP 0x80
362 #define DESC_PTR_LNKTBL_RETURN 0x02
363 #define DESC_PTR_LNKTBL_NEXT 0x01