drivers/ddr/altera/sequencer.c

   1 /*
   2  * Copyright Altera Corporation (C) 2012-2015
   3  *
   4  * SPDX-License-Identifier:    BSD-3-Clause
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/sdram.h>
  10 #include <errno.h>
  11 #include "sequencer.h"
  12 #include "sequencer_auto.h"
  13 #include "sequencer_auto_ac_init.h"
  14 #include "sequencer_auto_inst_init.h"
  15 #include "sequencer_defines.h"
  16
  17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
  18         (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
  19
  20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
  21         (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
  22
  23 static struct socfpga_sdr_reg_file *sdr_reg_file =
  24         (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
  25
  26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
  27         (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
  28
  29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
  30         (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
  31
  32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
  33         (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
  34
  35 static struct socfpga_data_mgr *data_mgr =
  36         (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
  37
  38 static struct socfpga_sdr_ctrl *sdr_ctrl =
  39         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  40
  41 #define DELTA_D         1
  42
  43 /*
  44  * In order to reduce ROM size, most of the selectable calibration steps are
  45  * decided at compile time based on the user's calibration mode selection,
  46  * as captured by the STATIC_CALIB_STEPS selection below.
  47  *
  48  * However, to support simulation-time selection of fast simulation mode, where
  49  * we skip everything except the bare minimum, we need a few of the steps to
  50  * be dynamic.  In those cases, we either use the DYNAMIC_CALIB_STEPS for the
  51  * check, which is based on the rtl-supplied value, or we dynamically compute
  52  * the value to use based on the dynamically-chosen calibration mode
  53  */
  54
  55 #define DLEVEL 0
  56 #define STATIC_IN_RTL_SIM 0
  57 #define STATIC_SKIP_DELAY_LOOPS 0
  58
  59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
  60         STATIC_SKIP_DELAY_LOOPS)
  61
  62 /* calibration steps requested by the rtl */
  63 uint16_t dyn_calib_steps;
  64
  65 /*
  66  * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
  67  * instead of static, we use boolean logic to select between
  68  * non-skip and skip values
  69  *
  70  * The mask is set to include all bits when not-skipping, but is
  71  * zero when skipping
  72  */
  73
  74 uint16_t skip_delay_mask;       /* mask off bits when skipping/not-skipping */
  75
  76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
  77         ((non_skip_value) & skip_delay_mask)
  78
  79 struct gbl_type *gbl;
  80 struct param_type *param;
  81 uint32_t curr_shadow_reg;
  82
  83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
  84         uint32_t write_group, uint32_t use_dm,
  85         uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
  86
  87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
  88         uint32_t substage)
  89 {
  90         /*
  91          * Only set the global stage if there was not been any other
  92          * failing group
  93          */
  94         if (gbl->error_stage == CAL_STAGE_NIL)  {
  95                 gbl->error_substage = substage;
  96                 gbl->error_stage = stage;
  97                 gbl->error_group = group;
  98         }
  99 }
 100
 101 static void reg_file_set_group(u16 set_group)
 102 {
 103         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
 104 }
 105
 106 static void reg_file_set_stage(u8 set_stage)
 107 {
 108         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
 109 }
 110
 111 static void reg_file_set_sub_stage(u8 set_sub_stage)
 112 {
 113         set_sub_stage &= 0xff;
 114         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
 115 }
 116
 117 /**
 118  * phy_mgr_initialize() - Initialize PHY Manager
 119  *
 120  * Initialize PHY Manager.
 121  */
 122 static void phy_mgr_initialize(void)
 123 {
 124         u32 ratio;
 125
 126         debug("%s:%d\n", __func__, __LINE__);
 127         /* Calibration has control over path to memory */
 128         /*
 129          * In Hard PHY this is a 2-bit control:
 130          * 0: AFI Mux Select
 131          * 1: DDIO Mux Select
 132          */
 133         writel(0x3, &phy_mgr_cfg->mux_sel);
 134
 135         /* USER memory clock is not stable we begin initialization  */
 136         writel(0, &phy_mgr_cfg->reset_mem_stbl);
 137
 138         /* USER calibration status all set to zero */
 139         writel(0, &phy_mgr_cfg->cal_status);
 140
 141         writel(0, &phy_mgr_cfg->cal_debug_info);
 142
 143         /* Init params only if we do NOT skip calibration. */
 144         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
 145                 return;
 146
 147         ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
 148                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
 149         param->read_correct_mask_vg = (1 << ratio) - 1;
 150         param->write_correct_mask_vg = (1 << ratio) - 1;
 151         param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
 152         param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
 153         ratio = RW_MGR_MEM_DATA_WIDTH /
 154                 RW_MGR_MEM_DATA_MASK_WIDTH;
 155         param->dm_correct_mask = (1 << ratio) - 1;
 156 }
 157
 158 /**
 159  * set_rank_and_odt_mask() - Set Rank and ODT mask
 160  * @rank:       Rank mask
 161  * @odt_mode:   ODT mode, OFF or READ_WRITE
 162  *
 163  * Set Rank and ODT mask (On-Die Termination).
 164  */
 165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
 166 {
 167         u32 odt_mask_0 = 0;
 168         u32 odt_mask_1 = 0;
 169         u32 cs_and_odt_mask;
 170
 171         if (odt_mode == RW_MGR_ODT_MODE_OFF) {
 172                 odt_mask_0 = 0x0;
 173                 odt_mask_1 = 0x0;
 174         } else {        /* RW_MGR_ODT_MODE_READ_WRITE */
 175                 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
 176                 case 1: /* 1 Rank */
 177                         /* Read: ODT = 0 ; Write: ODT = 1 */
 178                         odt_mask_0 = 0x0;
 179                         odt_mask_1 = 0x1;
 180                         break;
 181                 case 2: /* 2 Ranks */
 182                         if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
 183                                 /*
 184                                  * - Dual-Slot , Single-Rank (1 CS per DIMM)
 185                                  *   OR
 186                                  * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
 187                                  *
 188                                  * Since MEM_NUMBER_OF_RANKS is 2, they
 189                                  * are both single rank with 2 CS each
 190                                  * (special for RDIMM).
 191                                  *
 192                                  * Read: Turn on ODT on the opposite rank
 193                                  * Write: Turn on ODT on all ranks
 194                                  */
 195                                 odt_mask_0 = 0x3 & ~(1 << rank);
 196                                 odt_mask_1 = 0x3;
 197                         } else {
 198                                 /*
 199                                  * - Single-Slot , Dual-Rank (2 CS per DIMM)
 200                                  *
 201                                  * Read: Turn on ODT off on all ranks
 202                                  * Write: Turn on ODT on active rank
 203                                  */
 204                                 odt_mask_0 = 0x0;
 205                                 odt_mask_1 = 0x3 & (1 << rank);
 206                         }
 207                         break;
 208                 case 4: /* 4 Ranks */
 209                         /* Read:
 210                          * ----------+-----------------------+
 211                          *           |         ODT           |
 212                          * Read From +-----------------------+
 213                          *   Rank    |  3  |  2  |  1  |  0  |
 214                          * ----------+-----+-----+-----+-----+
 215                          *     0     |  0  |  1  |  0  |  0  |
 216                          *     1     |  1  |  0  |  0  |  0  |
 217                          *     2     |  0  |  0  |  0  |  1  |
 218                          *     3     |  0  |  0  |  1  |  0  |
 219                          * ----------+-----+-----+-----+-----+
 220                          *
 221                          * Write:
 222                          * ----------+-----------------------+
 223                          *           |         ODT           |
 224                          * Write To  +-----------------------+
 225                          *   Rank    |  3  |  2  |  1  |  0  |
 226                          * ----------+-----+-----+-----+-----+
 227                          *     0     |  0  |  1  |  0  |  1  |
 228                          *     1     |  1  |  0  |  1  |  0  |
 229                          *     2     |  0  |  1  |  0  |  1  |
 230                          *     3     |  1  |  0  |  1  |  0  |
 231                          * ----------+-----+-----+-----+-----+
 232                          */
 233                         switch (rank) {
 234                         case 0:
 235                                 odt_mask_0 = 0x4;
 236                                 odt_mask_1 = 0x5;
 237                                 break;
 238                         case 1:
 239                                 odt_mask_0 = 0x8;
 240                                 odt_mask_1 = 0xA;
 241                                 break;
 242                         case 2:
 243                                 odt_mask_0 = 0x1;
 244                                 odt_mask_1 = 0x5;
 245                                 break;
 246                         case 3:
 247                                 odt_mask_0 = 0x2;
 248                                 odt_mask_1 = 0xA;
 249                                 break;
 250                         }
 251                         break;
 252                 }
 253         }
 254
 255         cs_and_odt_mask = (0xFF & ~(1 << rank)) |
 256                           ((0xFF & odt_mask_0) << 8) |
 257                           ((0xFF & odt_mask_1) << 16);
 258         writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 259                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 260 }
 261
 262 /**
 263  * scc_mgr_set() - Set SCC Manager register
 264  * @off:        Base offset in SCC Manager space
 265  * @grp:        Read/Write group
 266  * @val:        Value to be set
 267  *
 268  * This function sets the SCC Manager (Scan Chain Control Manager) register.
 269  */
 270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
 271 {
 272         writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
 273 }
 274
 275 /**
 276  * scc_mgr_initialize() - Initialize SCC Manager registers
 277  *
 278  * Initialize SCC Manager registers.
 279  */
 280 static void scc_mgr_initialize(void)
 281 {
 282         /*
 283          * Clear register file for HPS. 16 (2^4) is the size of the
 284          * full register file in the scc mgr:
 285          *      RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
 286          *                             MEM_IF_READ_DQS_WIDTH - 1);
 287          */
 288         int i;
 289
 290         for (i = 0; i < 16; i++) {
 291                 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
 292                            __func__, __LINE__, i);
 293                 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
 294         }
 295 }
 296
 297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
 298 {
 299         scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
 300 }
 301
 302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
 303 {
 304         scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
 305 }
 306
 307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
 308 {
 309         scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
 310 }
 311
 312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
 313 {
 314         scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
 315 }
 316
 317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
 318 {
 319         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 320                     delay);
 321 }
 322
 323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
 324 {
 325         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
 326 }
 327
 328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
 329 {
 330         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
 331 }
 332
 333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
 334 {
 335         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 336                     delay);
 337 }
 338
 339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
 340 {
 341         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
 342                     RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
 343                     delay);
 344 }
 345
 346 /* load up dqs config settings */
 347 static void scc_mgr_load_dqs(uint32_t dqs)
 348 {
 349         writel(dqs, &sdr_scc_mgr->dqs_ena);
 350 }
 351
 352 /* load up dqs io config settings */
 353 static void scc_mgr_load_dqs_io(void)
 354 {
 355         writel(0, &sdr_scc_mgr->dqs_io_ena);
 356 }
 357
 358 /* load up dq config settings */
 359 static void scc_mgr_load_dq(uint32_t dq_in_group)
 360 {
 361         writel(dq_in_group, &sdr_scc_mgr->dq_ena);
 362 }
 363
 364 /* load up dm config settings */
 365 static void scc_mgr_load_dm(uint32_t dm)
 366 {
 367         writel(dm, &sdr_scc_mgr->dm_ena);
 368 }
 369
 370 /**
 371  * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
 372  * @off:        Base offset in SCC Manager space
 373  * @grp:        Read/Write group
 374  * @val:        Value to be set
 375  * @update:     If non-zero, trigger SCC Manager update for all ranks
 376  *
 377  * This function sets the SCC Manager (Scan Chain Control Manager) register
 378  * and optionally triggers the SCC update for all ranks.
 379  */
 380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
 381                                   const int update)
 382 {
 383         u32 r;
 384
 385         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 386              r += NUM_RANKS_PER_SHADOW_REG) {
 387                 scc_mgr_set(off, grp, val);
 388
 389                 if (update || (r == 0)) {
 390                         writel(grp, &sdr_scc_mgr->dqs_ena);
 391                         writel(0, &sdr_scc_mgr->update);
 392                 }
 393         }
 394 }
 395
 396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
 397 {
 398         /*
 399          * USER although the h/w doesn't support different phases per
 400          * shadow register, for simplicity our scc manager modeling
 401          * keeps different phase settings per shadow reg, and it's
 402          * important for us to keep them in sync to match h/w.
 403          * for efficiency, the scan chain update should occur only
 404          * once to sr0.
 405          */
 406         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
 407                               read_group, phase, 0);
 408 }
 409
 410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
 411                                                      uint32_t phase)
 412 {
 413         /*
 414          * USER although the h/w doesn't support different phases per
 415          * shadow register, for simplicity our scc manager modeling
 416          * keeps different phase settings per shadow reg, and it's
 417          * important for us to keep them in sync to match h/w.
 418          * for efficiency, the scan chain update should occur only
 419          * once to sr0.
 420          */
 421         scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
 422                               write_group, phase, 0);
 423 }
 424
 425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
 426                                                uint32_t delay)
 427 {
 428         /*
 429          * In shadow register mode, the T11 settings are stored in
 430          * registers in the core, which are updated by the DQS_ENA
 431          * signals. Not issuing the SCC_MGR_UPD command allows us to
 432          * save lots of rank switching overhead, by calling
 433          * select_shadow_regs_for_update with update_scan_chains
 434          * set to 0.
 435          */
 436         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
 437                               read_group, delay, 1);
 438         writel(0, &sdr_scc_mgr->update);
 439 }
 440
 441 /**
 442  * scc_mgr_set_oct_out1_delay() - Set OCT output delay
 443  * @write_group:        Write group
 444  * @delay:              Delay value
 445  *
 446  * This function sets the OCT output delay in SCC manager.
 447  */
 448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
 449 {
 450         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 451                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 452         const int base = write_group * ratio;
 453         int i;
 454         /*
 455          * Load the setting in the SCC manager
 456          * Although OCT affects only write data, the OCT delay is controlled
 457          * by the DQS logic block which is instantiated once per read group.
 458          * For protocols where a write group consists of multiple read groups,
 459          * the setting must be set multiple times.
 460          */
 461         for (i = 0; i < ratio; i++)
 462                 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
 463 }
 464
 465 /**
 466  * scc_mgr_set_hhp_extras() - Set HHP extras.
 467  *
 468  * Load the fixed setting in the SCC manager HHP extras.
 469  */
 470 static void scc_mgr_set_hhp_extras(void)
 471 {
 472         /*
 473          * Load the fixed setting in the SCC manager
 474          * bits: 0:0 = 1'b1     - DQS bypass
 475          * bits: 1:1 = 1'b1     - DQ bypass
 476          * bits: 4:2 = 3'b001   - rfifo_mode
 477          * bits: 6:5 = 2'b01    - rfifo clock_select
 478          * bits: 7:7 = 1'b0     - separate gating from ungating setting
 479          * bits: 8:8 = 1'b0     - separate OE from Output delay setting
 480          */
 481         const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
 482                           (1 << 2) | (1 << 1) | (1 << 0);
 483         const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
 484                          SCC_MGR_HHP_GLOBALS_OFFSET |
 485                          SCC_MGR_HHP_EXTRAS_OFFSET;
 486
 487         debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
 488                    __func__, __LINE__);
 489         writel(value, addr);
 490         debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
 491                    __func__, __LINE__);
 492 }
 493
 494 /**
 495  * scc_mgr_zero_all() - Zero all DQS config
 496  *
 497  * Zero all DQS config.
 498  */
 499 static void scc_mgr_zero_all(void)
 500 {
 501         int i, r;
 502
 503         /*
 504          * USER Zero all DQS config settings, across all groups and all
 505          * shadow registers
 506          */
 507         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 508              r += NUM_RANKS_PER_SHADOW_REG) {
 509                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
 510                         /*
 511                          * The phases actually don't exist on a per-rank basis,
 512                          * but there's no harm updating them several times, so
 513                          * let's keep the code simple.
 514                          */
 515                         scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
 516                         scc_mgr_set_dqs_en_phase(i, 0);
 517                         scc_mgr_set_dqs_en_delay(i, 0);
 518                 }
 519
 520                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
 521                         scc_mgr_set_dqdqs_output_phase(i, 0);
 522                         /* Arria V/Cyclone V don't have out2. */
 523                         scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
 524                 }
 525         }
 526
 527         /* Multicast to all DQS group enables. */
 528         writel(0xff, &sdr_scc_mgr->dqs_ena);
 529         writel(0, &sdr_scc_mgr->update);
 530 }
 531
 532 /**
 533  * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
 534  * @write_group:        Write group
 535  *
 536  * Set bypass mode and trigger SCC update.
 537  */
 538 static void scc_set_bypass_mode(const u32 write_group)
 539 {
 540         /* Multicast to all DQ enables. */
 541         writel(0xff, &sdr_scc_mgr->dq_ena);
 542         writel(0xff, &sdr_scc_mgr->dm_ena);
 543
 544         /* Update current DQS IO enable. */
 545         writel(0, &sdr_scc_mgr->dqs_io_ena);
 546
 547         /* Update the DQS logic. */
 548         writel(write_group, &sdr_scc_mgr->dqs_ena);
 549
 550         /* Hit update. */
 551         writel(0, &sdr_scc_mgr->update);
 552 }
 553
 554 /**
 555  * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
 556  * @write_group:        Write group
 557  *
 558  * Load DQS settings for Write Group, do not trigger SCC update.
 559  */
 560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
 561 {
 562         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 563                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 564         const int base = write_group * ratio;
 565         int i;
 566         /*
 567          * Load the setting in the SCC manager
 568          * Although OCT affects only write data, the OCT delay is controlled
 569          * by the DQS logic block which is instantiated once per read group.
 570          * For protocols where a write group consists of multiple read groups,
 571          * the setting must be set multiple times.
 572          */
 573         for (i = 0; i < ratio; i++)
 574                 writel(base + i, &sdr_scc_mgr->dqs_ena);
 575 }
 576
 577 /**
 578  * scc_mgr_zero_group() - Zero all configs for a group
 579  *
 580  * Zero DQ, DM, DQS and OCT configs for a group.
 581  */
 582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
 583 {
 584         int i, r;
 585
 586         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 587              r += NUM_RANKS_PER_SHADOW_REG) {
 588                 /* Zero all DQ config settings. */
 589                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 590                         scc_mgr_set_dq_out1_delay(i, 0);
 591                         if (!out_only)
 592                                 scc_mgr_set_dq_in_delay(i, 0);
 593                 }
 594
 595                 /* Multicast to all DQ enables. */
 596                 writel(0xff, &sdr_scc_mgr->dq_ena);
 597
 598                 /* Zero all DM config settings. */
 599                 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 600                         scc_mgr_set_dm_out1_delay(i, 0);
 601
 602                 /* Multicast to all DM enables. */
 603                 writel(0xff, &sdr_scc_mgr->dm_ena);
 604
 605                 /* Zero all DQS IO settings. */
 606                 if (!out_only)
 607                         scc_mgr_set_dqs_io_in_delay(0);
 608
 609                 /* Arria V/Cyclone V don't have out2. */
 610                 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
 611                 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
 612                 scc_mgr_load_dqs_for_write_group(write_group);
 613
 614                 /* Multicast to all DQS IO enables (only 1 in total). */
 615                 writel(0, &sdr_scc_mgr->dqs_io_ena);
 616
 617                 /* Hit update to zero everything. */
 618                 writel(0, &sdr_scc_mgr->update);
 619         }
 620 }
 621
 622 /*
 623  * apply and load a particular input delay for the DQ pins in a group
 624  * group_bgn is the index of the first dq pin (in the write group)
 625  */
 626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
 627 {
 628         uint32_t i, p;
 629
 630         for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
 631                 scc_mgr_set_dq_in_delay(p, delay);
 632                 scc_mgr_load_dq(p);
 633         }
 634 }
 635
 636 /**
 637  * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
 638  * @delay:              Delay value
 639  *
 640  * Apply and load a particular output delay for the DQ pins in a group.
 641  */
 642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
 643 {
 644         int i;
 645
 646         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 647                 scc_mgr_set_dq_out1_delay(i, delay);
 648                 scc_mgr_load_dq(i);
 649         }
 650 }
 651
 652 /* apply and load a particular output delay for the DM pins in a group */
 653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
 654 {
 655         uint32_t i;
 656
 657         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
 658                 scc_mgr_set_dm_out1_delay(i, delay1);
 659                 scc_mgr_load_dm(i);
 660         }
 661 }
 662
 663
 664 /* apply and load delay on both DQS and OCT out1 */
 665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
 666                                                     uint32_t delay)
 667 {
 668         scc_mgr_set_dqs_out1_delay(delay);
 669         scc_mgr_load_dqs_io();
 670
 671         scc_mgr_set_oct_out1_delay(write_group, delay);
 672         scc_mgr_load_dqs_for_write_group(write_group);
 673 }
 674
 675 /**
 676  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
 677  * @write_group:        Write group
 678  * @delay:              Delay value
 679  *
 680  * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
 681  */
 682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
 683                                                   const u32 delay)
 684 {
 685         u32 i, new_delay;
 686
 687         /* DQ shift */
 688         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
 689                 scc_mgr_load_dq(i);
 690
 691         /* DM shift */
 692         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 693                 scc_mgr_load_dm(i);
 694
 695         /* DQS shift */
 696         new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
 697         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 698                 debug_cond(DLEVEL == 1,
 699                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 700                            __func__, __LINE__, write_group, delay, new_delay,
 701                            IO_IO_OUT2_DELAY_MAX,
 702                            new_delay - IO_IO_OUT2_DELAY_MAX);
 703                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 704                 scc_mgr_set_dqs_out1_delay(new_delay);
 705         }
 706
 707         scc_mgr_load_dqs_io();
 708
 709         /* OCT shift */
 710         new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
 711         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 712                 debug_cond(DLEVEL == 1,
 713                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 714                            __func__, __LINE__, write_group, delay,
 715                            new_delay, IO_IO_OUT2_DELAY_MAX,
 716                            new_delay - IO_IO_OUT2_DELAY_MAX);
 717                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 718                 scc_mgr_set_oct_out1_delay(write_group, new_delay);
 719         }
 720
 721         scc_mgr_load_dqs_for_write_group(write_group);
 722 }
 723
 724 /**
 725  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
 726  * @write_group:        Write group
 727  * @delay:              Delay value
 728  *
 729  * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
 730  */
 731 static void
 732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
 733                                                 const u32 delay)
 734 {
 735         int r;
 736
 737         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 738              r += NUM_RANKS_PER_SHADOW_REG) {
 739                 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
 740                 writel(0, &sdr_scc_mgr->update);
 741         }
 742 }
 743
 744 /**
 745  * set_jump_as_return() - Return instruction optimization
 746  *
 747  * Optimization used to recover some slots in ddr3 inst_rom could be
 748  * applied to other protocols if we wanted to
 749  */
 750 static void set_jump_as_return(void)
 751 {
 752         /*
 753          * To save space, we replace return with jump to special shared
 754          * RETURN instruction so we set the counter to large value so that
 755          * we always jump.
 756          */
 757         writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
 758         writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 759 }
 760
 761 /*
 762  * should always use constants as argument to ensure all computations are
 763  * performed at compile time
 764  */
 765 static void delay_for_n_mem_clocks(const uint32_t clocks)
 766 {
 767         uint32_t afi_clocks;
 768         uint8_t inner = 0;
 769         uint8_t outer = 0;
 770         uint16_t c_loop = 0;
 771
 772         debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
 773
 774
 775         afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
 776         /* scale (rounding up) to get afi clocks */
 777
 778         /*
 779          * Note, we don't bother accounting for being off a little bit
 780          * because of a few extra instructions in outer loops
 781          * Note, the loops have a test at the end, and do the test before
 782          * the decrement, and so always perform the loop
 783          * 1 time more than the counter value
 784          */
 785         if (afi_clocks == 0) {
 786                 ;
 787         } else if (afi_clocks <= 0x100) {
 788                 inner = afi_clocks-1;
 789                 outer = 0;
 790                 c_loop = 0;
 791         } else if (afi_clocks <= 0x10000) {
 792                 inner = 0xff;
 793                 outer = (afi_clocks-1) >> 8;
 794                 c_loop = 0;
 795         } else {
 796                 inner = 0xff;
 797                 outer = 0xff;
 798                 c_loop = (afi_clocks-1) >> 16;
 799         }
 800
 801         /*
 802          * rom instructions are structured as follows:
 803          *
 804          *    IDLE_LOOP2: jnz cntr0, TARGET_A
 805          *    IDLE_LOOP1: jnz cntr1, TARGET_B
 806          *                return
 807          *
 808          * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
 809          * TARGET_B is set to IDLE_LOOP2 as well
 810          *
 811          * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
 812          * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
 813          *
 814          * a little confusing, but it helps save precious space in the inst_rom
 815          * and sequencer rom and keeps the delays more accurate and reduces
 816          * overhead
 817          */
 818         if (afi_clocks <= 0x100) {
 819                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 820                         &sdr_rw_load_mgr_regs->load_cntr1);
 821
 822                 writel(RW_MGR_IDLE_LOOP1,
 823                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 824
 825                 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 826                                           RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 827         } else {
 828                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 829                         &sdr_rw_load_mgr_regs->load_cntr0);
 830
 831                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
 832                         &sdr_rw_load_mgr_regs->load_cntr1);
 833
 834                 writel(RW_MGR_IDLE_LOOP2,
 835                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 836
 837                 writel(RW_MGR_IDLE_LOOP2,
 838                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 839
 840                 /* hack to get around compiler not being smart enough */
 841                 if (afi_clocks <= 0x10000) {
 842                         /* only need to run once */
 843                         writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 844                                                   RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 845                 } else {
 846                         do {
 847                                 writel(RW_MGR_IDLE_LOOP2,
 848                                         SDR_PHYGRP_RWMGRGRP_ADDRESS |
 849                                         RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 850                         } while (c_loop-- != 0);
 851                 }
 852         }
 853         debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
 854 }
 855
 856 /**
 857  * rw_mgr_mem_init_load_regs() - Load instruction registers
 858  * @cntr0:      Counter 0 value
 859  * @cntr1:      Counter 1 value
 860  * @cntr2:      Counter 2 value
 861  * @jump:       Jump instruction value
 862  *
 863  * Load instruction registers.
 864  */
 865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
 866 {
 867         uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 868                            RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 869
 870         /* Load counters */
 871         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
 872                &sdr_rw_load_mgr_regs->load_cntr0);
 873         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
 874                &sdr_rw_load_mgr_regs->load_cntr1);
 875         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
 876                &sdr_rw_load_mgr_regs->load_cntr2);
 877
 878         /* Load jump address */
 879         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 880         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 881         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
 882
 883         /* Execute count instruction */
 884         writel(jump, grpaddr);
 885 }
 886
 887 /**
 888  * rw_mgr_mem_load_user() - Load user calibration values
 889  * @fin1:       Final instruction 1
 890  * @fin2:       Final instruction 2
 891  * @precharge:  If 1, precharge the banks at the end
 892  *
 893  * Load user calibration values and optionally precharge the banks.
 894  */
 895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
 896                                  const int precharge)
 897 {
 898         u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 899                       RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 900         u32 r;
 901
 902         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
 903                 if (param->skip_ranks[r]) {
 904                         /* request to skip the rank */
 905                         continue;
 906                 }
 907
 908                 /* set rank */
 909                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
 910
 911                 /* precharge all banks ... */
 912                 if (precharge)
 913                         writel(RW_MGR_PRECHARGE_ALL, grpaddr);
 914
 915                 /*
 916                  * USER Use Mirror-ed commands for odd ranks if address
 917                  * mirrorring is on
 918                  */
 919                 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
 920                         set_jump_as_return();
 921                         writel(RW_MGR_MRS2_MIRR, grpaddr);
 922                         delay_for_n_mem_clocks(4);
 923                         set_jump_as_return();
 924                         writel(RW_MGR_MRS3_MIRR, grpaddr);
 925                         delay_for_n_mem_clocks(4);
 926                         set_jump_as_return();
 927                         writel(RW_MGR_MRS1_MIRR, grpaddr);
 928                         delay_for_n_mem_clocks(4);
 929                         set_jump_as_return();
 930                         writel(fin1, grpaddr);
 931                 } else {
 932                         set_jump_as_return();
 933                         writel(RW_MGR_MRS2, grpaddr);
 934                         delay_for_n_mem_clocks(4);
 935                         set_jump_as_return();
 936                         writel(RW_MGR_MRS3, grpaddr);
 937                         delay_for_n_mem_clocks(4);
 938                         set_jump_as_return();
 939                         writel(RW_MGR_MRS1, grpaddr);
 940                         set_jump_as_return();
 941                         writel(fin2, grpaddr);
 942                 }
 943
 944                 if (precharge)
 945                         continue;
 946
 947                 set_jump_as_return();
 948                 writel(RW_MGR_ZQCL, grpaddr);
 949
 950                 /* tZQinit = tDLLK = 512 ck cycles */
 951                 delay_for_n_mem_clocks(512);
 952         }
 953 }
 954
 955 /**
 956  * rw_mgr_mem_initialize() - Initialize RW Manager
 957  *
 958  * Initialize RW Manager.
 959  */
 960 static void rw_mgr_mem_initialize(void)
 961 {
 962         debug("%s:%d\n", __func__, __LINE__);
 963
 964         /* The reset / cke part of initialization is broadcasted to all ranks */
 965         writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 966                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 967
 968         /*
 969          * Here's how you load register for a loop
 970          * Counters are located @ 0x800
 971          * Jump address are located @ 0xC00
 972          * For both, registers 0 to 3 are selected using bits 3 and 2, like
 973          * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
 974          * I know this ain't pretty, but Avalon bus throws away the 2 least
 975          * significant bits
 976          */
 977
 978         /* Start with memory RESET activated */
 979
 980         /* tINIT = 200us */
 981
 982         /*
 983          * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
 984          * If a and b are the number of iteration in 2 nested loops
 985          * it takes the following number of cycles to complete the operation:
 986          * number_of_cycles = ((2 + n) * a + 2) * b
 987          * where n is the number of instruction in the inner loop
 988          * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
 989          * b = 6A
 990          */
 991         rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
 992                                   SEQ_TINIT_CNTR2_VAL,
 993                                   RW_MGR_INIT_RESET_0_CKE_0);
 994
 995         /* Indicate that memory is stable. */
 996         writel(1, &phy_mgr_cfg->reset_mem_stbl);
 997
 998         /*
 999          * transition the RESET to high
1000          * Wait for 500us
1001          */
1002
1003         /*
1004          * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005          * If a and b are the number of iteration in 2 nested loops
1006          * it takes the following number of cycles to complete the operation
1007          * number_of_cycles = ((2 + n) * a + 2) * b
1008          * where n is the number of instruction in the inner loop
1009          * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1010          * b = FF
1011          */
1012         rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013                                   SEQ_TRESET_CNTR2_VAL,
1014                                   RW_MGR_INIT_RESET_1_CKE_0);
1015
1016         /* Bring up clock enable. */
1017
1018         /* tXRP < 250 ck cycles */
1019         delay_for_n_mem_clocks(250);
1020
1021         rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1022                              0);
1023 }
1024
1025 /*
1026  * At the end of calibration we have to program the user settings in, and
1027  * USER  hand off the memory to the user.
1028  */
1029 static void rw_mgr_mem_handoff(void)
1030 {
1031         rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1032         /*
1033          * USER  need to wait tMOD (12CK or 15ns) time before issuing
1034          * other commands, but we will have plenty of NIOS cycles before
1035          * actual handoff so its okay.
1036          */
1037 }
1038
1039 /**
1040  * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041  * @rank_bgn:   Rank number
1042  * @group:      Read/Write Group
1043  * @all_ranks:  Test all ranks
1044  *
1045  * Performs a guaranteed read on the patterns we are going to use during a
1046  * read test to ensure memory works.
1047  */
1048 static int
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050                                         const u32 all_ranks)
1051 {
1052         const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053                          RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054         const u32 addr_offset =
1055                          (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056         const u32 rank_end = all_ranks ?
1057                                 RW_MGR_MEM_NUMBER_OF_RANKS :
1058                                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059         const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061         const u32 correct_mask_vg = param->read_correct_mask_vg;
1062
1063         u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1064         int vg, r;
1065         int ret = 0;
1066
1067         bit_chk = param->read_correct_mask;
1068
1069         for (r = rank_bgn; r < rank_end; r++) {
1070                 /* Request to skip the rank */
1071                 if (param->skip_ranks[r])
1072                         continue;
1073
1074                 /* Set rank */
1075                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1076
1077                 /* Load up a constant bursts of read commands */
1078                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079                 writel(RW_MGR_GUARANTEED_READ,
1080                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1081
1082                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083                 writel(RW_MGR_GUARANTEED_READ_CONT,
1084                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1085
1086                 tmp_bit_chk = 0;
1087                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1088                      vg >= 0; vg--) {
1089                         /* Reset the FIFOs to get pointers to known state. */
1090                         writel(0, &phy_mgr_cmd->fifo_reset);
1091                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1093                         writel(RW_MGR_GUARANTEED_READ,
1094                                addr + addr_offset + (vg << 2));
1095
1096                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1097                         tmp_bit_chk <<= shift_ratio;
1098                         tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1099                 }
1100
1101                 bit_chk &= tmp_bit_chk;
1102         }
1103
1104         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1105
1106         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1107
1108         if (bit_chk != param->read_correct_mask)
1109                 ret = -EIO;
1110
1111         debug_cond(DLEVEL == 1,
1112                    "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113                    __func__, __LINE__, group, bit_chk,
1114                    param->read_correct_mask, ret);
1115
1116         return ret;
1117 }
1118
1119 /**
1120  * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121  * @rank_bgn:   Rank number
1122  * @all_ranks:  Test all ranks
1123  *
1124  * Load up the patterns we are going to use during a read test.
1125  */
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127                                                     const int all_ranks)
1128 {
1129         const u32 rank_end = all_ranks ?
1130                         RW_MGR_MEM_NUMBER_OF_RANKS :
1131                         (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1132         u32 r;
1133
1134         debug("%s:%d\n", __func__, __LINE__);
1135
1136         for (r = rank_bgn; r < rank_end; r++) {
1137                 if (param->skip_ranks[r])
1138                         /* request to skip the rank */
1139                         continue;
1140
1141                 /* set rank */
1142                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1143
1144                 /* Load up a constant bursts */
1145                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1146
1147                 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1149
1150                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1151
1152                 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1154
1155                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1156
1157                 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1159
1160                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1161
1162                 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1164
1165                 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1167         }
1168
1169         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1170 }
1171
1172 /*
1173  * try a read and see if it returns correct data back. has dummy reads
1174  * inserted into the mix used to align dqs enable. has more thorough checks
1175  * than the regular read test.
1176  */
1177 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1178         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1179         uint32_t all_groups, uint32_t all_ranks)
1180 {
1181         uint32_t r, vg;
1182         uint32_t correct_mask_vg;
1183         uint32_t tmp_bit_chk;
1184         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1185                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1186         uint32_t addr;
1187         uint32_t base_rw_mgr;
1188
1189         *bit_chk = param->read_correct_mask;
1190         correct_mask_vg = param->read_correct_mask_vg;
1191
1192         uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1193                 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1194
1195         for (r = rank_bgn; r < rank_end; r++) {
1196                 if (param->skip_ranks[r])
1197                         /* request to skip the rank */
1198                         continue;
1199
1200                 /* set rank */
1201                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1202
1203                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1204
1205                 writel(RW_MGR_READ_B2B_WAIT1,
1206                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1207
1208                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1209                 writel(RW_MGR_READ_B2B_WAIT2,
1210                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1211
1212                 if (quick_read_mode)
1213                         writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1214                         /* need at least two (1+1) reads to capture failures */
1215                 else if (all_groups)
1216                         writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1217                 else
1218                         writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1219
1220                 writel(RW_MGR_READ_B2B,
1221                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1222                 if (all_groups)
1223                         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1224                                RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1225                                &sdr_rw_load_mgr_regs->load_cntr3);
1226                 else
1227                         writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1228
1229                 writel(RW_MGR_READ_B2B,
1230                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1231
1232                 tmp_bit_chk = 0;
1233                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1234                         /* reset the fifos to get pointers to known state */
1235                         writel(0, &phy_mgr_cmd->fifo_reset);
1236                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1237                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1238
1239                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1240                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1241
1242                         if (all_groups)
1243                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1244                         else
1245                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1246
1247                         writel(RW_MGR_READ_B2B, addr +
1248                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1249                                vg) << 2));
1250
1251                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1252                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1253
1254                         if (vg == 0)
1255                                 break;
1256                 }
1257                 *bit_chk &= tmp_bit_chk;
1258         }
1259
1260         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1261         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1262
1263         if (all_correct) {
1264                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1265                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1266                            (%u == %u) => %lu", __func__, __LINE__, group,
1267                            all_groups, *bit_chk, param->read_correct_mask,
1268                            (long unsigned int)(*bit_chk ==
1269                            param->read_correct_mask));
1270                 return *bit_chk == param->read_correct_mask;
1271         } else  {
1272                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1273                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1274                            (%u != %lu) => %lu\n", __func__, __LINE__,
1275                            group, all_groups, *bit_chk, (long unsigned int)0,
1276                            (long unsigned int)(*bit_chk != 0x00));
1277                 return *bit_chk != 0x00;
1278         }
1279 }
1280
1281 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1282         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1283         uint32_t all_groups)
1284 {
1285         return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1286                                               bit_chk, all_groups, 1);
1287 }
1288
1289 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1290 {
1291         writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1292         (*v)++;
1293 }
1294
1295 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1296 {
1297         uint32_t i;
1298
1299         for (i = 0; i < VFIFO_SIZE-1; i++)
1300                 rw_mgr_incr_vfifo(grp, v);
1301 }
1302
1303 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1304 {
1305         uint32_t  v;
1306         uint32_t fail_cnt = 0;
1307         uint32_t test_status;
1308
1309         for (v = 0; v < VFIFO_SIZE; ) {
1310                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1311                            __func__, __LINE__, v);
1312                 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1313                         (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1314                 if (!test_status) {
1315                         fail_cnt++;
1316
1317                         if (fail_cnt == 2)
1318                                 break;
1319                 }
1320
1321                 /* fiddle with FIFO */
1322                 rw_mgr_incr_vfifo(grp, &v);
1323         }
1324
1325         if (v >= VFIFO_SIZE) {
1326                 /* no failing read found!! Something must have gone wrong */
1327                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1328                            __func__, __LINE__);
1329                 return 0;
1330         } else {
1331                 return v;
1332         }
1333 }
1334
1335 /**
1336  * sdr_find_phase() - Find DQS enable phase
1337  * @working:    If 1, look for working phase, if 0, look for non-working phase
1338  * @grp:        Read/Write group
1339  * @v:          VFIFO value
1340  * @work:       Working window position
1341  * @i:          Iterator
1342  * @p:          DQS Phase Iterator
1343  *
1344  * Find working or non-working DQS enable phase setting.
1345  */
1346 static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
1347                           u32 *i, u32 *p)
1348 {
1349         u32 ret, bit_chk;
1350         const u32 end = VFIFO_SIZE + (working ? 0 : 1);
1351
1352         for (; *i < end; (*i)++) {
1353                 if (working)
1354                         *p = 0;
1355
1356                 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++) {
1357                         scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1358
1359                         ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1360                                                 PASS_ONE_BIT, &bit_chk, 0);
1361                         if (!working)
1362                                 ret = !ret;
1363
1364                         if (ret)
1365                                 return 0;
1366
1367                         *work += IO_DELAY_PER_OPA_TAP;
1368                 }
1369
1370                 if (*p > IO_DQS_EN_PHASE_MAX) {
1371                         /* Fiddle with FIFO. */
1372                         rw_mgr_incr_vfifo(grp, v);
1373                         if (!working)
1374                                 *p = 0;
1375                 }
1376         }
1377
1378         return -EINVAL;
1379 }
1380
1381 static int sdr_working_phase(uint32_t grp, uint32_t *work_bgn,
1382                              uint32_t *v, uint32_t *d, uint32_t *p,
1383                              uint32_t *i)
1384 {
1385         const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
1386                                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1387         int ret;
1388
1389         *work_bgn = 0;
1390
1391         for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1392                 *i = 0;
1393                 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1394                 ret = sdr_find_phase(1, grp, v, work_bgn, i, p);
1395                 if (!ret)
1396                         return 0;
1397                 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1398         }
1399
1400         /* Cannot find working solution */
1401         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1402                    __func__, __LINE__);
1403         return -EINVAL;
1404 }
1405
1406 static void sdr_backup_phase(uint32_t grp,
1407                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1408                              uint32_t *p)
1409 {
1410         uint32_t tmp_delay;
1411         u32 bit_chk;
1412
1413         /* Special case code for backing up a phase */
1414         if (*p == 0) {
1415                 *p = IO_DQS_EN_PHASE_MAX;
1416                 rw_mgr_decr_vfifo(grp, v);
1417         } else {
1418                 (*p)--;
1419         }
1420         tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1421         scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1422
1423         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1424                 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1425                 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1426
1427                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1428                                                              PASS_ONE_BIT,
1429                                                              &bit_chk, 0)) {
1430                         *work_bgn = tmp_delay;
1431                         break;
1432                 }
1433         }
1434
1435         /*
1436          * Restore VFIFO to old state before we decremented it
1437          * (if needed).
1438          */
1439         (*p)++;
1440         if (*p > IO_DQS_EN_PHASE_MAX) {
1441                 *p = 0;
1442                 rw_mgr_incr_vfifo(grp, v);
1443         }
1444
1445         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1446 }
1447
1448 static int sdr_nonworking_phase(uint32_t grp,
1449                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1450                              uint32_t *p, uint32_t *i,
1451                              uint32_t *work_end)
1452 {
1453         int ret;
1454
1455         (*p)++;
1456         *work_end += IO_DELAY_PER_OPA_TAP;
1457         if (*p > IO_DQS_EN_PHASE_MAX) {
1458                 /* Fiddle with FIFO. */
1459                 *p = 0;
1460                 rw_mgr_incr_vfifo(grp, v);
1461         }
1462
1463         ret = sdr_find_phase(0, grp, v, work_end, i, p);
1464         if (ret) {
1465                 /* Cannot see edge of failing read. */
1466                 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1467                            __func__, __LINE__);
1468         }
1469
1470         return ret;
1471 }
1472
1473 /**
1474  * sdr_find_window_center() - Find center of the working DQS window.
1475  * @grp:        Read/Write group
1476  * @work_bgn:   First working settings
1477  * @work_end:   Last working settings
1478  * @val:        VFIFO value
1479  *
1480  * Find center of the working DQS enable window.
1481  */
1482 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1483                                   const u32 work_end, const u32 val)
1484 {
1485         u32 bit_chk, work_mid, v = val;
1486         int tmp_delay = 0;
1487         int i, p, d;
1488
1489         work_mid = (work_bgn + work_end) / 2;
1490
1491         debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1492                    work_bgn, work_end, work_mid);
1493         /* Get the middle delay to be less than a VFIFO delay */
1494         tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1495
1496         debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1497         work_mid %= tmp_delay;
1498         debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1499
1500         tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1501         if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1502                 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1503         p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1504
1505         debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1506
1507         d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1508         if (d > IO_DQS_EN_DELAY_MAX)
1509                 d = IO_DQS_EN_DELAY_MAX;
1510         tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1511
1512         debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1513
1514         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1515         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1516
1517         /*
1518          * push vfifo until we can successfully calibrate. We can do this
1519          * because the largest possible margin in 1 VFIFO cycle.
1520          */
1521         for (i = 0; i < VFIFO_SIZE; i++) {
1522                 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1523                            v);
1524                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1525                                                              PASS_ONE_BIT,
1526                                                              &bit_chk, 0)) {
1527                         debug_cond(DLEVEL == 2,
1528                                    "%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n",
1529                                    __func__, __LINE__, v, p, d);
1530                         return 0;
1531                 }
1532
1533                 /* Fiddle with FIFO. */
1534                 rw_mgr_incr_vfifo(grp, &v);
1535         }
1536
1537         debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1538                    __func__, __LINE__);
1539         return -EINVAL;
1540 }
1541
1542 /* find a good dqs enable to use */
1543 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1544 {
1545         uint32_t v, d, p, i;
1546         uint32_t bit_chk;
1547         uint32_t dtaps_per_ptap;
1548         uint32_t work_bgn, work_end;
1549         uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1550
1551         debug("%s:%d %u\n", __func__, __LINE__, grp);
1552
1553         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1554
1555         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1556         scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1557
1558         /* ************************************************************** */
1559         /* * Step 0 : Determine number of delay taps for each phase tap * */
1560         dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1561
1562         /* ********************************************************* */
1563         /* * Step 1 : First push vfifo until we get a failing read * */
1564         v = find_vfifo_read(grp, &bit_chk);
1565
1566         /* ******************************************************** */
1567         /* * step 2: find first working phase, increment in ptaps * */
1568         work_bgn = 0;
1569         if (sdr_working_phase(grp, &work_bgn, &v, &d, &p, &i))
1570                 return 0;
1571
1572         work_end = work_bgn;
1573
1574         /*
1575          * If d is 0 then the working window covers a phase tap and
1576          * we can follow the old procedure otherwise, we've found the beginning,
1577          * and we need to increment the dtaps until we find the end.
1578          */
1579         if (d == 0) {
1580                 /* ********************************************************* */
1581                 /* * step 3a: if we have room, back off by one and
1582                 increment in dtaps * */
1583
1584                 sdr_backup_phase(grp, &work_bgn, &v, &d, &p);
1585
1586                 /* ********************************************************* */
1587                 /* * step 4a: go forward from working phase to non working
1588                 phase, increment in ptaps * */
1589                 if (sdr_nonworking_phase(grp, &work_bgn, &v, &d, &p,
1590                                          &i, &work_end))
1591                         return 0;
1592
1593                 /* ********************************************************* */
1594                 /* * step 5a:  back off one from last, increment in dtaps  * */
1595
1596                 /* Special case code for backing up a phase */
1597                 if (p == 0) {
1598                         p = IO_DQS_EN_PHASE_MAX;
1599                         rw_mgr_decr_vfifo(grp, &v);
1600                 } else {
1601                         p = p - 1;
1602                 }
1603
1604                 work_end -= IO_DELAY_PER_OPA_TAP;
1605                 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1606
1607                 /* * The actual increment of dtaps is done outside of
1608                 the if/else loop to share code */
1609                 d = 0;
1610
1611                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1612                            vfifo=%u ptap=%u\n", __func__, __LINE__,
1613                            v, p);
1614         } else {
1615                 /* ******************************************************* */
1616                 /* * step 3-5b:  Find the right edge of the window using
1617                 delay taps   * */
1618                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1619                            ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1620                            v, p, d, work_bgn);
1621
1622                 work_end = work_bgn;
1623         }
1624
1625         /* The dtap increment to find the failing edge is done here */
1626         for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1627                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1628                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1629                                    end-2: dtap=%u\n", __func__, __LINE__, d);
1630                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1631
1632                         if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1633                                                                       PASS_ONE_BIT,
1634                                                                       &bit_chk, 0)) {
1635                                 break;
1636                         }
1637         }
1638
1639         /* Go back to working dtap */
1640         if (d != 0)
1641                 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1642
1643         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1644                    ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1645                    v, p, d-1, work_end);
1646
1647         if (work_end < work_bgn) {
1648                 /* nil range */
1649                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1650                            failed\n", __func__, __LINE__);
1651                 return 0;
1652         }
1653
1654         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1655                    __func__, __LINE__, work_bgn, work_end);
1656
1657         /* *************************************************************** */
1658         /*
1659          * * We need to calculate the number of dtaps that equal a ptap
1660          * * To do that we'll back up a ptap and re-find the edge of the
1661          * * window using dtaps
1662          */
1663
1664         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1665                    for tracking\n", __func__, __LINE__);
1666
1667         /* Special case code for backing up a phase */
1668         if (p == 0) {
1669                 p = IO_DQS_EN_PHASE_MAX;
1670                 rw_mgr_decr_vfifo(grp, &v);
1671                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1672                            cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1673                            v, p);
1674         } else {
1675                 p = p - 1;
1676                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1677                            phase only: v=%u p=%u", __func__, __LINE__,
1678                            v, p);
1679         }
1680
1681         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1682
1683         /*
1684          * Increase dtap until we first see a passing read (in case the
1685          * window is smaller than a ptap),
1686          * and then a failing read to mark the edge of the window again
1687          */
1688
1689         /* Find a passing read */
1690         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1691                    __func__, __LINE__);
1692         found_passing_read = 0;
1693         found_failing_read = 0;
1694         initial_failing_dtap = d;
1695         for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1696                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1697                            read d=%u\n", __func__, __LINE__, d);
1698                 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1699
1700                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1701                                                              PASS_ONE_BIT,
1702                                                              &bit_chk, 0)) {
1703                         found_passing_read = 1;
1704                         break;
1705                 }
1706         }
1707
1708         if (found_passing_read) {
1709                 /* Find a failing read */
1710                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1711                            read\n", __func__, __LINE__);
1712                 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1713                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1714                                    testing read d=%u\n", __func__, __LINE__, d);
1715                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1716
1717                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1718                                 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1719                                 found_failing_read = 1;
1720                                 break;
1721                         }
1722                 }
1723         } else {
1724                 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1725                            calculate dtaps", __func__, __LINE__);
1726                 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1727         }
1728
1729         /*
1730          * The dynamically calculated dtaps_per_ptap is only valid if we
1731          * found a passing/failing read. If we didn't, it means d hit the max
1732          * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1733          * statically calculated value.
1734          */
1735         if (found_passing_read && found_failing_read)
1736                 dtaps_per_ptap = d - initial_failing_dtap;
1737
1738         writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1739         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1740                    - %u = %u",  __func__, __LINE__, d,
1741                    initial_failing_dtap, dtaps_per_ptap);
1742
1743         /* ******************************************** */
1744         /* * step 6:  Find the centre of the window   * */
1745         if (sdr_find_window_centre(grp, work_bgn, work_end, v))
1746                 return 0; /* FIXME: Old code, return 0 means failure :-( */
1747
1748         return 1;
1749 }
1750
1751 /* per-bit deskew DQ and center */
1752 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1753         uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1754         uint32_t use_read_test, uint32_t update_fom)
1755 {
1756         uint32_t i, p, d, min_index;
1757         /*
1758          * Store these as signed since there are comparisons with
1759          * signed numbers.
1760          */
1761         uint32_t bit_chk;
1762         uint32_t sticky_bit_chk;
1763         int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1764         int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1765         int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1766         int32_t mid;
1767         int32_t orig_mid_min, mid_min;
1768         int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1769                 final_dqs_en;
1770         int32_t dq_margin, dqs_margin;
1771         uint32_t stop;
1772         uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1773         uint32_t addr;
1774
1775         debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1776
1777         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1778         start_dqs = readl(addr + (read_group << 2));
1779         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1780                 start_dqs_en = readl(addr + ((read_group << 2)
1781                                      - IO_DQS_EN_DELAY_OFFSET));
1782
1783         /* set the left and right edge of each bit to an illegal value */
1784         /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1785         sticky_bit_chk = 0;
1786         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1787                 left_edge[i]  = IO_IO_IN_DELAY_MAX + 1;
1788                 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1789         }
1790
1791         /* Search for the left edge of the window for each bit */
1792         for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1793                 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1794
1795                 writel(0, &sdr_scc_mgr->update);
1796
1797                 /*
1798                  * Stop searching when the read test doesn't pass AND when
1799                  * we've seen a passing read on every bit.
1800                  */
1801                 if (use_read_test) {
1802                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1803                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1804                                 &bit_chk, 0, 0);
1805                 } else {
1806                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1807                                                         0, PASS_ONE_BIT,
1808                                                         &bit_chk, 0);
1809                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1810                                 (read_group - (write_group *
1811                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1812                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1813                         stop = (bit_chk == 0);
1814                 }
1815                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1816                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1817                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1818                            && %u", __func__, __LINE__, d,
1819                            sticky_bit_chk,
1820                         param->read_correct_mask, stop);
1821
1822                 if (stop == 1) {
1823                         break;
1824                 } else {
1825                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1826                                 if (bit_chk & 1) {
1827                                         /* Remember a passing test as the
1828                                         left_edge */
1829                                         left_edge[i] = d;
1830                                 } else {
1831                                         /* If a left edge has not been seen yet,
1832                                         then a future passing test will mark
1833                                         this edge as the right edge */
1834                                         if (left_edge[i] ==
1835                                                 IO_IO_IN_DELAY_MAX + 1) {
1836                                                 right_edge[i] = -(d + 1);
1837                                         }
1838                                 }
1839                                 bit_chk = bit_chk >> 1;
1840                         }
1841                 }
1842         }
1843
1844         /* Reset DQ delay chains to 0 */
1845         scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1846         sticky_bit_chk = 0;
1847         for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1848                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1849                            %d right_edge[%u]: %d\n", __func__, __LINE__,
1850                            i, left_edge[i], i, right_edge[i]);
1851
1852                 /*
1853                  * Check for cases where we haven't found the left edge,
1854                  * which makes our assignment of the the right edge invalid.
1855                  * Reset it to the illegal value.
1856                  */
1857                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1858                         right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1859                         right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1860                         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1861                                    right_edge[%u]: %d\n", __func__, __LINE__,
1862                                    i, right_edge[i]);
1863                 }
1864
1865                 /*
1866                  * Reset sticky bit (except for bits where we have seen
1867                  * both the left and right edge).
1868                  */
1869                 sticky_bit_chk = sticky_bit_chk << 1;
1870                 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1871                     (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1872                         sticky_bit_chk = sticky_bit_chk | 1;
1873                 }
1874
1875                 if (i == 0)
1876                         break;
1877         }
1878
1879         /* Search for the right edge of the window for each bit */
1880         for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1881                 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1882                 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1883                         uint32_t delay = d + start_dqs_en;
1884                         if (delay > IO_DQS_EN_DELAY_MAX)
1885                                 delay = IO_DQS_EN_DELAY_MAX;
1886                         scc_mgr_set_dqs_en_delay(read_group, delay);
1887                 }
1888                 scc_mgr_load_dqs(read_group);
1889
1890                 writel(0, &sdr_scc_mgr->update);
1891
1892                 /*
1893                  * Stop searching when the read test doesn't pass AND when
1894                  * we've seen a passing read on every bit.
1895                  */
1896                 if (use_read_test) {
1897                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1898                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1899                                 &bit_chk, 0, 0);
1900                 } else {
1901                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1902                                                         0, PASS_ONE_BIT,
1903                                                         &bit_chk, 0);
1904                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1905                                 (read_group - (write_group *
1906                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1907                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1908                         stop = (bit_chk == 0);
1909                 }
1910                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1911                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1912
1913                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1914                            %u && %u", __func__, __LINE__, d,
1915                            sticky_bit_chk, param->read_correct_mask, stop);
1916
1917                 if (stop == 1) {
1918                         break;
1919                 } else {
1920                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1921                                 if (bit_chk & 1) {
1922                                         /* Remember a passing test as
1923                                         the right_edge */
1924                                         right_edge[i] = d;
1925                                 } else {
1926                                         if (d != 0) {
1927                                                 /* If a right edge has not been
1928                                                 seen yet, then a future passing
1929                                                 test will mark this edge as the
1930                                                 left edge */
1931                                                 if (right_edge[i] ==
1932                                                 IO_IO_IN_DELAY_MAX + 1) {
1933                                                         left_edge[i] = -(d + 1);
1934                                                 }
1935                                         } else {
1936                                                 /* d = 0 failed, but it passed
1937                                                 when testing the left edge,
1938                                                 so it must be marginal,
1939                                                 set it to -1 */
1940                                                 if (right_edge[i] ==
1941                                                         IO_IO_IN_DELAY_MAX + 1 &&
1942                                                         left_edge[i] !=
1943                                                         IO_IO_IN_DELAY_MAX
1944                                                         + 1) {
1945                                                         right_edge[i] = -1;
1946                                                 }
1947                                                 /* If a right edge has not been
1948                                                 seen yet, then a future passing
1949                                                 test will mark this edge as the
1950                                                 left edge */
1951                                                 else if (right_edge[i] ==
1952                                                         IO_IO_IN_DELAY_MAX +
1953                                                         1) {
1954                                                         left_edge[i] = -(d + 1);
1955                                                 }
1956                                         }
1957                                 }
1958
1959                                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
1960                                            d=%u]: ", __func__, __LINE__, d);
1961                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
1962                                            (int)(bit_chk & 1), i, left_edge[i]);
1963                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
1964                                            right_edge[i]);
1965                                 bit_chk = bit_chk >> 1;
1966                         }
1967                 }
1968         }
1969
1970         /* Check that all bits have a window */
1971         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1972                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1973                            %d right_edge[%u]: %d", __func__, __LINE__,
1974                            i, left_edge[i], i, right_edge[i]);
1975                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
1976                         == IO_IO_IN_DELAY_MAX + 1)) {
1977                         /*
1978                          * Restore delay chain settings before letting the loop
1979                          * in rw_mgr_mem_calibrate_vfifo to retry different
1980                          * dqs/ck relationships.
1981                          */
1982                         scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
1983                         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1984                                 scc_mgr_set_dqs_en_delay(read_group,
1985                                                          start_dqs_en);
1986                         }
1987                         scc_mgr_load_dqs(read_group);
1988                         writel(0, &sdr_scc_mgr->update);
1989
1990                         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
1991                                    find edge [%u]: %d %d", __func__, __LINE__,
1992                                    i, left_edge[i], right_edge[i]);
1993                         if (use_read_test) {
1994                                 set_failing_group_stage(read_group *
1995                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
1996                                         CAL_STAGE_VFIFO,
1997                                         CAL_SUBSTAGE_VFIFO_CENTER);
1998                         } else {
1999                                 set_failing_group_stage(read_group *
2000                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2001                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2002                                         CAL_SUBSTAGE_VFIFO_CENTER);
2003                         }
2004                         return 0;
2005                 }
2006         }
2007
2008         /* Find middle of window for each DQ bit */
2009         mid_min = left_edge[0] - right_edge[0];
2010         min_index = 0;
2011         for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2012                 mid = left_edge[i] - right_edge[i];
2013                 if (mid < mid_min) {
2014                         mid_min = mid;
2015                         min_index = i;
2016                 }
2017         }
2018
2019         /*
2020          * -mid_min/2 represents the amount that we need to move DQS.
2021          * If mid_min is odd and positive we'll need to add one to
2022          * make sure the rounding in further calculations is correct
2023          * (always bias to the right), so just add 1 for all positive values.
2024          */
2025         if (mid_min > 0)
2026                 mid_min++;
2027
2028         mid_min = mid_min / 2;
2029
2030         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2031                    __func__, __LINE__, mid_min, min_index);
2032
2033         /* Determine the amount we can change DQS (which is -mid_min) */
2034         orig_mid_min = mid_min;
2035         new_dqs = start_dqs - mid_min;
2036         if (new_dqs > IO_DQS_IN_DELAY_MAX)
2037                 new_dqs = IO_DQS_IN_DELAY_MAX;
2038         else if (new_dqs < 0)
2039                 new_dqs = 0;
2040
2041         mid_min = start_dqs - new_dqs;
2042         debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2043                    mid_min, new_dqs);
2044
2045         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2046                 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2047                         mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2048                 else if (start_dqs_en - mid_min < 0)
2049                         mid_min += start_dqs_en - mid_min;
2050         }
2051         new_dqs = start_dqs - mid_min;
2052
2053         debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2054                    new_dqs=%d mid_min=%d\n", start_dqs,
2055                    IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2056                    new_dqs, mid_min);
2057
2058         /* Initialize data for export structures */
2059         dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2060         dq_margin  = IO_IO_IN_DELAY_MAX + 1;
2061
2062         /* add delay to bring centre of all DQ windows to the same "level" */
2063         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2064                 /* Use values before divide by 2 to reduce round off error */
2065                 shift_dq = (left_edge[i] - right_edge[i] -
2066                         (left_edge[min_index] - right_edge[min_index]))/2  +
2067                         (orig_mid_min - mid_min);
2068
2069                 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2070                            shift_dq[%u]=%d\n", i, shift_dq);
2071
2072                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2073                 temp_dq_in_delay1 = readl(addr + (p << 2));
2074                 temp_dq_in_delay2 = readl(addr + (i << 2));
2075
2076                 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2077                         (int32_t)IO_IO_IN_DELAY_MAX) {
2078                         shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2079                 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2080                         shift_dq = -(int32_t)temp_dq_in_delay1;
2081                 }
2082                 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2083                            shift_dq[%u]=%d\n", i, shift_dq);
2084                 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2085                 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2086                 scc_mgr_load_dq(p);
2087
2088                 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2089                            left_edge[i] - shift_dq + (-mid_min),
2090                            right_edge[i] + shift_dq - (-mid_min));
2091                 /* To determine values for export structures */
2092                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2093                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2094
2095                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2096                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2097         }
2098
2099         final_dqs = new_dqs;
2100         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2101                 final_dqs_en = start_dqs_en - mid_min;
2102
2103         /* Move DQS-en */
2104         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2105                 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2106                 scc_mgr_load_dqs(read_group);
2107         }
2108
2109         /* Move DQS */
2110         scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2111         scc_mgr_load_dqs(read_group);
2112         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2113                    dqs_margin=%d", __func__, __LINE__,
2114                    dq_margin, dqs_margin);
2115
2116         /*
2117          * Do not remove this line as it makes sure all of our decisions
2118          * have been applied. Apply the update bit.
2119          */
2120         writel(0, &sdr_scc_mgr->update);
2121
2122         return (dq_margin >= 0) && (dqs_margin >= 0);
2123 }
2124
2125 /**
2126  * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2127  * @rw_group:   Read/Write Group
2128  * @phase:      DQ/DQS phase
2129  *
2130  * Because initially no communication ca be reliably performed with the memory
2131  * device, the sequencer uses a guaranteed write mechanism to write data into
2132  * the memory device.
2133  */
2134 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2135                                                  const u32 phase)
2136 {
2137         int ret;
2138
2139         /* Set a particular DQ/DQS phase. */
2140         scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2141
2142         debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2143                    __func__, __LINE__, rw_group, phase);
2144
2145         /*
2146          * Altera EMI_RM 2015.05.04 :: Figure 1-25
2147          * Load up the patterns used by read calibration using the
2148          * current DQDQS phase.
2149          */
2150         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2151
2152         if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2153                 return 0;
2154
2155         /*
2156          * Altera EMI_RM 2015.05.04 :: Figure 1-26
2157          * Back-to-Back reads of the patterns used for calibration.
2158          */
2159         ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2160         if (ret)
2161                 debug_cond(DLEVEL == 1,
2162                            "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2163                            __func__, __LINE__, rw_group, phase);
2164         return ret;
2165 }
2166
2167 /**
2168  * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2169  * @rw_group:   Read/Write Group
2170  * @test_bgn:   Rank at which the test begins
2171  *
2172  * DQS enable calibration ensures reliable capture of the DQ signal without
2173  * glitches on the DQS line.
2174  */
2175 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2176                                                        const u32 test_bgn)
2177 {
2178         /*
2179          * Altera EMI_RM 2015.05.04 :: Figure 1-27
2180          * DQS and DQS Eanble Signal Relationships.
2181          */
2182
2183         /* We start at zero, so have one less dq to devide among */
2184         const u32 delay_step = IO_IO_IN_DELAY_MAX /
2185                                (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2186         int found;
2187         u32 i, p, d, r;
2188
2189         debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2190
2191         /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2192         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2193              r += NUM_RANKS_PER_SHADOW_REG) {
2194                 for (i = 0, p = test_bgn, d = 0;
2195                      i < RW_MGR_MEM_DQ_PER_READ_DQS;
2196                      i++, p++, d += delay_step) {
2197                         debug_cond(DLEVEL == 1,
2198                                    "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2199                                    __func__, __LINE__, rw_group, r, i, p, d);
2200
2201                         scc_mgr_set_dq_in_delay(p, d);
2202                         scc_mgr_load_dq(p);
2203                 }
2204
2205                 writel(0, &sdr_scc_mgr->update);
2206         }
2207
2208         /*
2209          * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2210          * dq_in_delay values
2211          */
2212         found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2213
2214         debug_cond(DLEVEL == 1,
2215                    "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2216                    __func__, __LINE__, rw_group, found);
2217
2218         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2219              r += NUM_RANKS_PER_SHADOW_REG) {
2220                 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2221                 writel(0, &sdr_scc_mgr->update);
2222         }
2223
2224         if (!found)
2225                 return -EINVAL;
2226
2227         return 0;
2228
2229 }
2230
2231 /**
2232  * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2233  * @rw_group:           Read/Write Group
2234  * @test_bgn:           Rank at which the test begins
2235  * @use_read_test:      Perform a read test
2236  * @update_fom:         Update FOM
2237  *
2238  * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2239  * within a group.
2240  */
2241 static int
2242 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2243                                       const int use_read_test,
2244                                       const int update_fom)
2245
2246 {
2247         int ret, grp_calibrated;
2248         u32 rank_bgn, sr;
2249
2250         /*
2251          * Altera EMI_RM 2015.05.04 :: Figure 1-28
2252          * Read per-bit deskew can be done on a per shadow register basis.
2253          */
2254         grp_calibrated = 1;
2255         for (rank_bgn = 0, sr = 0;
2256              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2257              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2258                 /* Check if this set of ranks should be skipped entirely. */
2259                 if (param->skip_shadow_regs[sr])
2260                         continue;
2261
2262                 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2263                                                         rw_group, test_bgn,
2264                                                         use_read_test,
2265                                                         update_fom);
2266                 if (ret)
2267                         continue;
2268
2269                 grp_calibrated = 0;
2270         }
2271
2272         if (!grp_calibrated)
2273                 return -EIO;
2274
2275         return 0;
2276 }
2277
2278 /**
2279  * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2280  * @rw_group:           Read/Write Group
2281  * @test_bgn:           Rank at which the test begins
2282  *
2283  * Stage 1: Calibrate the read valid prediction FIFO.
2284  *
2285  * This function implements UniPHY calibration Stage 1, as explained in
2286  * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2287  *
2288  * - read valid prediction will consist of finding:
2289  *   - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2290  *   - DQS input phase  and DQS input delay (DQ/DQS Centering)
2291  *  - we also do a per-bit deskew on the DQ lines.
2292  */
2293 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2294 {
2295         uint32_t p, d;
2296         uint32_t dtaps_per_ptap;
2297         uint32_t failed_substage;
2298
2299         int ret;
2300
2301         debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2302
2303         /* Update info for sims */
2304         reg_file_set_group(rw_group);
2305         reg_file_set_stage(CAL_STAGE_VFIFO);
2306         reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2307
2308         failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2309
2310         /* USER Determine number of delay taps for each phase tap. */
2311         dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2312                                       IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2313
2314         for (d = 0; d <= dtaps_per_ptap; d += 2) {
2315                 /*
2316                  * In RLDRAMX we may be messing the delay of pins in
2317                  * the same write rw_group but outside of the current read
2318                  * the rw_group, but that's ok because we haven't calibrated
2319                  * output side yet.
2320                  */
2321                 if (d > 0) {
2322                         scc_mgr_apply_group_all_out_delay_add_all_ranks(
2323                                                                 rw_group, d);
2324                 }
2325
2326                 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2327                         /* 1) Guaranteed Write */
2328                         ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2329                         if (ret)
2330                                 break;
2331
2332                         /* 2) DQS Enable Calibration */
2333                         ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2334                                                                           test_bgn);
2335                         if (ret) {
2336                                 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2337                                 continue;
2338                         }
2339
2340                         /* 3) Centering DQ/DQS */
2341                         /*
2342                          * If doing read after write calibration, do not update
2343                          * FOM now. Do it then.
2344                          */
2345                         ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2346                                                                 test_bgn, 1, 0);
2347                         if (ret) {
2348                                 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2349                                 continue;
2350                         }
2351
2352                         /* All done. */
2353                         goto cal_done_ok;
2354                 }
2355         }
2356
2357         /* Calibration Stage 1 failed. */
2358         set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2359         return 0;
2360
2361         /* Calibration Stage 1 completed OK. */
2362 cal_done_ok:
2363         /*
2364          * Reset the delay chains back to zero if they have moved > 1
2365          * (check for > 1 because loop will increase d even when pass in
2366          * first case).
2367          */
2368         if (d > 2)
2369                 scc_mgr_zero_group(rw_group, 1);
2370
2371         return 1;
2372 }
2373
2374 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2375 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2376                                                uint32_t test_bgn)
2377 {
2378         uint32_t rank_bgn, sr;
2379         uint32_t grp_calibrated;
2380         uint32_t write_group;
2381
2382         debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2383
2384         /* update info for sims */
2385
2386         reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2387         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2388
2389         write_group = read_group;
2390
2391         /* update info for sims */
2392         reg_file_set_group(read_group);
2393
2394         grp_calibrated = 1;
2395         /* Read per-bit deskew can be done on a per shadow register basis */
2396         for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2397                 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2398                 /* Determine if this set of ranks should be skipped entirely */
2399                 if (!param->skip_shadow_regs[sr]) {
2400                 /* This is the last calibration round, update FOM here */
2401                         if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2402                                                                 write_group,
2403                                                                 read_group,
2404                                                                 test_bgn, 0,
2405                                                                 1)) {
2406                                 grp_calibrated = 0;
2407                         }
2408                 }
2409         }
2410
2411
2412         if (grp_calibrated == 0) {
2413                 set_failing_group_stage(write_group,
2414                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2415                                         CAL_SUBSTAGE_VFIFO_CENTER);
2416                 return 0;
2417         }
2418
2419         return 1;
2420 }
2421
2422 /* Calibrate LFIFO to find smallest read latency */
2423 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2424 {
2425         uint32_t found_one;
2426         uint32_t bit_chk;
2427
2428         debug("%s:%d\n", __func__, __LINE__);
2429
2430         /* update info for sims */
2431         reg_file_set_stage(CAL_STAGE_LFIFO);
2432         reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2433
2434         /* Load up the patterns used by read calibration for all ranks */
2435         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2436         found_one = 0;
2437
2438         do {
2439                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2440                 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2441                            __func__, __LINE__, gbl->curr_read_lat);
2442
2443                 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2444                                                               NUM_READ_TESTS,
2445                                                               PASS_ALL_BITS,
2446                                                               &bit_chk, 1)) {
2447                         break;
2448                 }
2449
2450                 found_one = 1;
2451                 /* reduce read latency and see if things are working */
2452                 /* correctly */
2453                 gbl->curr_read_lat--;
2454         } while (gbl->curr_read_lat > 0);
2455
2456         /* reset the fifos to get pointers to known state */
2457
2458         writel(0, &phy_mgr_cmd->fifo_reset);
2459
2460         if (found_one) {
2461                 /* add a fudge factor to the read latency that was determined */
2462                 gbl->curr_read_lat += 2;
2463                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2464                 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2465                            read_lat=%u\n", __func__, __LINE__,
2466                            gbl->curr_read_lat);
2467                 return 1;
2468         } else {
2469                 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2470                                         CAL_SUBSTAGE_READ_LATENCY);
2471
2472                 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2473                            read_lat=%u\n", __func__, __LINE__,
2474                            gbl->curr_read_lat);
2475                 return 0;
2476         }
2477 }
2478
2479 /*
2480  * issue write test command.
2481  * two variants are provided. one that just tests a write pattern and
2482  * another that tests datamask functionality.
2483  */
2484 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2485                                                   uint32_t test_dm)
2486 {
2487         uint32_t mcc_instruction;
2488         uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2489                 ENABLE_SUPER_QUICK_CALIBRATION);
2490         uint32_t rw_wl_nop_cycles;
2491         uint32_t addr;
2492
2493         /*
2494          * Set counter and jump addresses for the right
2495          * number of NOP cycles.
2496          * The number of supported NOP cycles can range from -1 to infinity
2497          * Three different cases are handled:
2498          *
2499          * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2500          *    mechanism will be used to insert the right number of NOPs
2501          *
2502          * 2. For a number of NOP cycles equals to 0, the micro-instruction
2503          *    issuing the write command will jump straight to the
2504          *    micro-instruction that turns on DQS (for DDRx), or outputs write
2505          *    data (for RLD), skipping
2506          *    the NOP micro-instruction all together
2507          *
2508          * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2509          *    turned on in the same micro-instruction that issues the write
2510          *    command. Then we need
2511          *    to directly jump to the micro-instruction that sends out the data
2512          *
2513          * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2514          *       (2 and 3). One jump-counter (0) is used to perform multiple
2515          *       write-read operations.
2516          *       one counter left to issue this command in "multiple-group" mode
2517          */
2518
2519         rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2520
2521         if (rw_wl_nop_cycles == -1) {
2522                 /*
2523                  * CNTR 2 - We want to execute the special write operation that
2524                  * turns on DQS right away and then skip directly to the
2525                  * instruction that sends out the data. We set the counter to a
2526                  * large number so that the jump is always taken.
2527                  */
2528                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2529
2530                 /* CNTR 3 - Not used */
2531                 if (test_dm) {
2532                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2533                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2534                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2535                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2536                                &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2537                 } else {
2538                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2539                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2540                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2541                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2542                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2543                 }
2544         } else if (rw_wl_nop_cycles == 0) {
2545                 /*
2546                  * CNTR 2 - We want to skip the NOP operation and go straight
2547                  * to the DQS enable instruction. We set the counter to a large
2548                  * number so that the jump is always taken.
2549                  */
2550                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2551
2552                 /* CNTR 3 - Not used */
2553                 if (test_dm) {
2554                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2555                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2556                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2557                 } else {
2558                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2559                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2560                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2561                 }
2562         } else {
2563                 /*
2564                  * CNTR 2 - In this case we want to execute the next instruction
2565                  * and NOT take the jump. So we set the counter to 0. The jump
2566                  * address doesn't count.
2567                  */
2568                 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2569                 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2570
2571                 /*
2572                  * CNTR 3 - Set the nop counter to the number of cycles we
2573                  * need to loop for, minus 1.
2574                  */
2575                 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2576                 if (test_dm) {
2577                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2578                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2579                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2580                 } else {
2581                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2582                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2583                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2584                 }
2585         }
2586
2587         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2588                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
2589
2590         if (quick_write_mode)
2591                 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2592         else
2593                 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2594
2595         writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2596
2597         /*
2598          * CNTR 1 - This is used to ensure enough time elapses
2599          * for read data to come back.
2600          */
2601         writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2602
2603         if (test_dm) {
2604                 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2605                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2606         } else {
2607                 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2608                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2609         }
2610
2611         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2612         writel(mcc_instruction, addr + (group << 2));
2613 }
2614
2615 /* Test writes, can check for a single bit pass or multiple bit pass */
2616 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2617         uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2618         uint32_t *bit_chk, uint32_t all_ranks)
2619 {
2620         uint32_t r;
2621         uint32_t correct_mask_vg;
2622         uint32_t tmp_bit_chk;
2623         uint32_t vg;
2624         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2625                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2626         uint32_t addr_rw_mgr;
2627         uint32_t base_rw_mgr;
2628
2629         *bit_chk = param->write_correct_mask;
2630         correct_mask_vg = param->write_correct_mask_vg;
2631
2632         for (r = rank_bgn; r < rank_end; r++) {
2633                 if (param->skip_ranks[r]) {
2634                         /* request to skip the rank */
2635                         continue;
2636                 }
2637
2638                 /* set rank */
2639                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2640
2641                 tmp_bit_chk = 0;
2642                 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2643                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2644                         /* reset the fifos to get pointers to known state */
2645                         writel(0, &phy_mgr_cmd->fifo_reset);
2646
2647                         tmp_bit_chk = tmp_bit_chk <<
2648                                 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2649                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2650                         rw_mgr_mem_calibrate_write_test_issue(write_group *
2651                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2652                                 use_dm);
2653
2654                         base_rw_mgr = readl(addr_rw_mgr);
2655                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2656                         if (vg == 0)
2657                                 break;
2658                 }
2659                 *bit_chk &= tmp_bit_chk;
2660         }
2661
2662         if (all_correct) {
2663                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2664                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2665                            %u => %lu", write_group, use_dm,
2666                            *bit_chk, param->write_correct_mask,
2667                            (long unsigned int)(*bit_chk ==
2668                            param->write_correct_mask));
2669                 return *bit_chk == param->write_correct_mask;
2670         } else {
2671                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2672                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2673                        write_group, use_dm, *bit_chk);
2674                 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2675                         (long unsigned int)(*bit_chk != 0));
2676                 return *bit_chk != 0x00;
2677         }
2678 }
2679
2680 /*
2681  * center all windows. do per-bit-deskew to possibly increase size of
2682  * certain windows.
2683  */
2684 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2685         uint32_t write_group, uint32_t test_bgn)
2686 {
2687         uint32_t i, p, min_index;
2688         int32_t d;
2689         /*
2690          * Store these as signed since there are comparisons with
2691          * signed numbers.
2692          */
2693         uint32_t bit_chk;
2694         uint32_t sticky_bit_chk;
2695         int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2696         int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2697         int32_t mid;
2698         int32_t mid_min, orig_mid_min;
2699         int32_t new_dqs, start_dqs, shift_dq;
2700         int32_t dq_margin, dqs_margin, dm_margin;
2701         uint32_t stop;
2702         uint32_t temp_dq_out1_delay;
2703         uint32_t addr;
2704
2705         debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2706
2707         dm_margin = 0;
2708
2709         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2710         start_dqs = readl(addr +
2711                           (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2712
2713         /* per-bit deskew */
2714
2715         /*
2716          * set the left and right edge of each bit to an illegal value
2717          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2718          */
2719         sticky_bit_chk = 0;
2720         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2721                 left_edge[i]  = IO_IO_OUT1_DELAY_MAX + 1;
2722                 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2723         }
2724
2725         /* Search for the left edge of the window for each bit */
2726         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2727                 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2728
2729                 writel(0, &sdr_scc_mgr->update);
2730
2731                 /*
2732                  * Stop searching when the read test doesn't pass AND when
2733                  * we've seen a passing read on every bit.
2734                  */
2735                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2736                         0, PASS_ONE_BIT, &bit_chk, 0);
2737                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2738                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2739                 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2740                            == %u && %u [bit_chk= %u ]\n",
2741                         d, sticky_bit_chk, param->write_correct_mask,
2742                         stop, bit_chk);
2743
2744                 if (stop == 1) {
2745                         break;
2746                 } else {
2747                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2748                                 if (bit_chk & 1) {
2749                                         /*
2750                                          * Remember a passing test as the
2751                                          * left_edge.
2752                                          */
2753                                         left_edge[i] = d;
2754                                 } else {
2755                                         /*
2756                                          * If a left edge has not been seen
2757                                          * yet, then a future passing test will
2758                                          * mark this edge as the right edge.
2759                                          */
2760                                         if (left_edge[i] ==
2761                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2762                                                 right_edge[i] = -(d + 1);
2763                                         }
2764                                 }
2765                                 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2766                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2767                                            (int)(bit_chk & 1), i, left_edge[i]);
2768                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2769                                        right_edge[i]);
2770                                 bit_chk = bit_chk >> 1;
2771                         }
2772                 }
2773         }
2774
2775         /* Reset DQ delay chains to 0 */
2776         scc_mgr_apply_group_dq_out1_delay(0);
2777         sticky_bit_chk = 0;
2778         for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2779                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2780                            %d right_edge[%u]: %d\n", __func__, __LINE__,
2781                            i, left_edge[i], i, right_edge[i]);
2782
2783                 /*
2784                  * Check for cases where we haven't found the left edge,
2785                  * which makes our assignment of the the right edge invalid.
2786                  * Reset it to the illegal value.
2787                  */
2788                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2789                     (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2790                         right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2791                         debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2792                                    right_edge[%u]: %d\n", __func__, __LINE__,
2793                                    i, right_edge[i]);
2794                 }
2795
2796                 /*
2797                  * Reset sticky bit (except for bits where we have
2798                  * seen the left edge).
2799                  */
2800                 sticky_bit_chk = sticky_bit_chk << 1;
2801                 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2802                         sticky_bit_chk = sticky_bit_chk | 1;
2803
2804                 if (i == 0)
2805                         break;
2806         }
2807
2808         /* Search for the right edge of the window for each bit */
2809         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2810                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2811                                                         d + start_dqs);
2812
2813                 writel(0, &sdr_scc_mgr->update);
2814
2815                 /*
2816                  * Stop searching when the read test doesn't pass AND when
2817                  * we've seen a passing read on every bit.
2818                  */
2819                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2820                         0, PASS_ONE_BIT, &bit_chk, 0);
2821
2822                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2823                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2824
2825                 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2826                            %u && %u\n", d, sticky_bit_chk,
2827                            param->write_correct_mask, stop);
2828
2829                 if (stop == 1) {
2830                         if (d == 0) {
2831                                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2832                                         i++) {
2833                                         /* d = 0 failed, but it passed when
2834                                         testing the left edge, so it must be
2835                                         marginal, set it to -1 */
2836                                         if (right_edge[i] ==
2837                                                 IO_IO_OUT1_DELAY_MAX + 1 &&
2838                                                 left_edge[i] !=
2839                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2840                                                 right_edge[i] = -1;
2841                                         }
2842                                 }
2843                         }
2844                         break;
2845                 } else {
2846                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2847                                 if (bit_chk & 1) {
2848                                         /*
2849                                          * Remember a passing test as
2850                                          * the right_edge.
2851                                          */
2852                                         right_edge[i] = d;
2853                                 } else {
2854                                         if (d != 0) {
2855                                                 /*
2856                                                  * If a right edge has not
2857                                                  * been seen yet, then a future
2858                                                  * passing test will mark this
2859                                                  * edge as the left edge.
2860                                                  */
2861                                                 if (right_edge[i] ==
2862                                                     IO_IO_OUT1_DELAY_MAX + 1)
2863                                                         left_edge[i] = -(d + 1);
2864                                         } else {
2865                                                 /*
2866                                                  * d = 0 failed, but it passed
2867                                                  * when testing the left edge,
2868                                                  * so it must be marginal, set
2869                                                  * it to -1.
2870                                                  */
2871                                                 if (right_edge[i] ==
2872                                                     IO_IO_OUT1_DELAY_MAX + 1 &&
2873                                                     left_edge[i] !=
2874                                                     IO_IO_OUT1_DELAY_MAX + 1)
2875                                                         right_edge[i] = -1;
2876                                                 /*
2877                                                  * If a right edge has not been
2878                                                  * seen yet, then a future
2879                                                  * passing test will mark this
2880                                                  * edge as the left edge.
2881                                                  */
2882                                                 else if (right_edge[i] ==
2883                                                         IO_IO_OUT1_DELAY_MAX +
2884                                                         1)
2885                                                         left_edge[i] = -(d + 1);
2886                                         }
2887                                 }
2888                                 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2889                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2890                                            (int)(bit_chk & 1), i, left_edge[i]);
2891                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2892                                            right_edge[i]);
2893                                 bit_chk = bit_chk >> 1;
2894                         }
2895                 }
2896         }
2897
2898         /* Check that all bits have a window */
2899         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2900                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2901                            %d right_edge[%u]: %d", __func__, __LINE__,
2902                            i, left_edge[i], i, right_edge[i]);
2903                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2904                     (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2905                         set_failing_group_stage(test_bgn + i,
2906                                                 CAL_STAGE_WRITES,
2907                                                 CAL_SUBSTAGE_WRITES_CENTER);
2908                         return 0;
2909                 }
2910         }
2911
2912         /* Find middle of window for each DQ bit */
2913         mid_min = left_edge[0] - right_edge[0];
2914         min_index = 0;
2915         for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2916                 mid = left_edge[i] - right_edge[i];
2917                 if (mid < mid_min) {
2918                         mid_min = mid;
2919                         min_index = i;
2920                 }
2921         }
2922
2923         /*
2924          * -mid_min/2 represents the amount that we need to move DQS.
2925          * If mid_min is odd and positive we'll need to add one to
2926          * make sure the rounding in further calculations is correct
2927          * (always bias to the right), so just add 1 for all positive values.
2928          */
2929         if (mid_min > 0)
2930                 mid_min++;
2931         mid_min = mid_min / 2;
2932         debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2933                    __LINE__, mid_min);
2934
2935         /* Determine the amount we can change DQS (which is -mid_min) */
2936         orig_mid_min = mid_min;
2937         new_dqs = start_dqs;
2938         mid_min = 0;
2939         debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2940                    mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2941         /* Initialize data for export structures */
2942         dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2943         dq_margin  = IO_IO_OUT1_DELAY_MAX + 1;
2944
2945         /* add delay to bring centre of all DQ windows to the same "level" */
2946         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2947                 /* Use values before divide by 2 to reduce round off error */
2948                 shift_dq = (left_edge[i] - right_edge[i] -
2949                         (left_edge[min_index] - right_edge[min_index]))/2  +
2950                 (orig_mid_min - mid_min);
2951
2952                 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2953                            [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2954
2955                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2956                 temp_dq_out1_delay = readl(addr + (i << 2));
2957                 if (shift_dq + (int32_t)temp_dq_out1_delay >
2958                         (int32_t)IO_IO_OUT1_DELAY_MAX) {
2959                         shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2960                 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2961                         shift_dq = -(int32_t)temp_dq_out1_delay;
2962                 }
2963                 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2964                            i, shift_dq);
2965                 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2966                 scc_mgr_load_dq(i);
2967
2968                 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2969                            left_edge[i] - shift_dq + (-mid_min),
2970                            right_edge[i] + shift_dq - (-mid_min));
2971                 /* To determine values for export structures */
2972                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2973                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2974
2975                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2976                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2977         }
2978
2979         /* Move DQS */
2980         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2981         writel(0, &sdr_scc_mgr->update);
2982
2983         /* Centre DM */
2984         debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2985
2986         /*
2987          * set the left and right edge of each bit to an illegal value,
2988          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2989          */
2990         left_edge[0]  = IO_IO_OUT1_DELAY_MAX + 1;
2991         right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2992         int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2993         int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2994         int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2995         int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2996         int32_t win_best = 0;
2997
2998         /* Search for the/part of the window with DM shift */
2999         for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
3000                 scc_mgr_apply_group_dm_out1_delay(d);
3001                 writel(0, &sdr_scc_mgr->update);
3002
3003                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3004                                                     PASS_ALL_BITS, &bit_chk,
3005                                                     0)) {
3006                         /* USE Set current end of the window */
3007                         end_curr = -d;
3008                         /*
3009                          * If a starting edge of our window has not been seen
3010                          * this is our current start of the DM window.
3011                          */
3012                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3013                                 bgn_curr = -d;
3014
3015                         /*
3016                          * If current window is bigger than best seen.
3017                          * Set best seen to be current window.
3018                          */
3019                         if ((end_curr-bgn_curr+1) > win_best) {
3020                                 win_best = end_curr-bgn_curr+1;
3021                                 bgn_best = bgn_curr;
3022                                 end_best = end_curr;
3023                         }
3024                 } else {
3025                         /* We just saw a failing test. Reset temp edge */
3026                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3027                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3028                         }
3029                 }
3030
3031
3032         /* Reset DM delay chains to 0 */
3033         scc_mgr_apply_group_dm_out1_delay(0);
3034
3035         /*
3036          * Check to see if the current window nudges up aganist 0 delay.
3037          * If so we need to continue the search by shifting DQS otherwise DQS
3038          * search begins as a new search. */
3039         if (end_curr != 0) {
3040                 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3041                 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3042         }
3043
3044         /* Search for the/part of the window with DQS shifts */
3045         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3046                 /*
3047                  * Note: This only shifts DQS, so are we limiting ourselve to
3048                  * width of DQ unnecessarily.
3049                  */
3050                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3051                                                         d + new_dqs);
3052
3053                 writel(0, &sdr_scc_mgr->update);
3054                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3055                                                     PASS_ALL_BITS, &bit_chk,
3056                                                     0)) {
3057                         /* USE Set current end of the window */
3058                         end_curr = d;
3059                         /*
3060                          * If a beginning edge of our window has not been seen
3061                          * this is our current begin of the DM window.
3062                          */
3063                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3064                                 bgn_curr = d;
3065
3066                         /*
3067                          * If current window is bigger than best seen. Set best
3068                          * seen to be current window.
3069                          */
3070                         if ((end_curr-bgn_curr+1) > win_best) {
3071                                 win_best = end_curr-bgn_curr+1;
3072                                 bgn_best = bgn_curr;
3073                                 end_best = end_curr;
3074                         }
3075                 } else {
3076                         /* We just saw a failing test. Reset temp edge */
3077                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3078                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3079
3080                         /* Early exit optimization: if ther remaining delay
3081                         chain space is less than already seen largest window
3082                         we can exit */
3083                         if ((win_best-1) >
3084                                 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3085                                         break;
3086                                 }
3087                         }
3088                 }
3089
3090         /* assign left and right edge for cal and reporting; */
3091         left_edge[0] = -1*bgn_best;
3092         right_edge[0] = end_best;
3093
3094         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3095                    __LINE__, left_edge[0], right_edge[0]);
3096
3097         /* Move DQS (back to orig) */
3098         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3099
3100         /* Move DM */
3101
3102         /* Find middle of window for the DM bit */
3103         mid = (left_edge[0] - right_edge[0]) / 2;
3104
3105         /* only move right, since we are not moving DQS/DQ */
3106         if (mid < 0)
3107                 mid = 0;
3108
3109         /* dm_marign should fail if we never find a window */
3110         if (win_best == 0)
3111                 dm_margin = -1;
3112         else
3113                 dm_margin = left_edge[0] - mid;
3114
3115         scc_mgr_apply_group_dm_out1_delay(mid);
3116         writel(0, &sdr_scc_mgr->update);
3117
3118         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3119                    dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3120                    right_edge[0], mid, dm_margin);
3121         /* Export values */
3122         gbl->fom_out += dq_margin + dqs_margin;
3123
3124         debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3125                    dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3126                    dq_margin, dqs_margin, dm_margin);
3127
3128         /*
3129          * Do not remove this line as it makes sure all of our
3130          * decisions have been applied.
3131          */
3132         writel(0, &sdr_scc_mgr->update);
3133         return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3134 }
3135
3136 /* calibrate the write operations */
3137 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3138         uint32_t test_bgn)
3139 {
3140         /* update info for sims */
3141         debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3142
3143         reg_file_set_stage(CAL_STAGE_WRITES);
3144         reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3145
3146         reg_file_set_group(g);
3147
3148         if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3149                 set_failing_group_stage(g, CAL_STAGE_WRITES,
3150                                         CAL_SUBSTAGE_WRITES_CENTER);
3151                 return 0;
3152         }
3153
3154         return 1;
3155 }
3156
3157 /**
3158  * mem_precharge_and_activate() - Precharge all banks and activate
3159  *
3160  * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3161  */
3162 static void mem_precharge_and_activate(void)
3163 {
3164         int r;
3165
3166         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3167                 /* Test if the rank should be skipped. */
3168                 if (param->skip_ranks[r])
3169                         continue;
3170
3171                 /* Set rank. */
3172                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3173
3174                 /* Precharge all banks. */
3175                 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3176                                              RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3177
3178                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3179                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3180                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3181
3182                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3183                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3184                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3185
3186                 /* Activate rows. */
3187                 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3188                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3189         }
3190 }
3191
3192 /**
3193  * mem_init_latency() - Configure memory RLAT and WLAT settings
3194  *
3195  * Configure memory RLAT and WLAT parameters.
3196  */
3197 static void mem_init_latency(void)
3198 {
3199         /*
3200          * For AV/CV, LFIFO is hardened and always runs at full rate
3201          * so max latency in AFI clocks, used here, is correspondingly
3202          * smaller.
3203          */
3204         const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3205         u32 rlat, wlat;
3206
3207         debug("%s:%d\n", __func__, __LINE__);
3208
3209         /*
3210          * Read in write latency.
3211          * WL for Hard PHY does not include additive latency.
3212          */
3213         wlat = readl(&data_mgr->t_wl_add);
3214         wlat += readl(&data_mgr->mem_t_add);
3215
3216         gbl->rw_wl_nop_cycles = wlat - 1;
3217
3218         /* Read in readl latency. */
3219         rlat = readl(&data_mgr->t_rl_add);
3220
3221         /* Set a pretty high read latency initially. */
3222         gbl->curr_read_lat = rlat + 16;
3223         if (gbl->curr_read_lat > max_latency)
3224                 gbl->curr_read_lat = max_latency;
3225
3226         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3227
3228         /* Advertise write latency. */
3229         writel(wlat, &phy_mgr_cfg->afi_wlat);
3230 }
3231
3232 /**
3233  * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3234  *
3235  * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3236  */
3237 static void mem_skip_calibrate(void)
3238 {
3239         uint32_t vfifo_offset;
3240         uint32_t i, j, r;
3241
3242         debug("%s:%d\n", __func__, __LINE__);
3243         /* Need to update every shadow register set used by the interface */
3244         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3245              r += NUM_RANKS_PER_SHADOW_REG) {
3246                 /*
3247                  * Set output phase alignment settings appropriate for
3248                  * skip calibration.
3249                  */
3250                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3251                         scc_mgr_set_dqs_en_phase(i, 0);
3252 #if IO_DLL_CHAIN_LENGTH == 6
3253                         scc_mgr_set_dqdqs_output_phase(i, 6);
3254 #else
3255                         scc_mgr_set_dqdqs_output_phase(i, 7);
3256 #endif
3257                         /*
3258                          * Case:33398
3259                          *
3260                          * Write data arrives to the I/O two cycles before write
3261                          * latency is reached (720 deg).
3262                          *   -> due to bit-slip in a/c bus
3263                          *   -> to allow board skew where dqs is longer than ck
3264                          *      -> how often can this happen!?
3265                          *      -> can claim back some ptaps for high freq
3266                          *       support if we can relax this, but i digress...
3267                          *
3268                          * The write_clk leads mem_ck by 90 deg
3269                          * The minimum ptap of the OPA is 180 deg
3270                          * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3271                          * The write_clk is always delayed by 2 ptaps
3272                          *
3273                          * Hence, to make DQS aligned to CK, we need to delay
3274                          * DQS by:
3275                          *    (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3276                          *
3277                          * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3278                          * gives us the number of ptaps, which simplies to:
3279                          *
3280                          *    (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3281                          */
3282                         scc_mgr_set_dqdqs_output_phase(i,
3283                                         1.25 * IO_DLL_CHAIN_LENGTH - 2);
3284                 }
3285                 writel(0xff, &sdr_scc_mgr->dqs_ena);
3286                 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3287
3288                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3289                         writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3290                                   SCC_MGR_GROUP_COUNTER_OFFSET);
3291                 }
3292                 writel(0xff, &sdr_scc_mgr->dq_ena);
3293                 writel(0xff, &sdr_scc_mgr->dm_ena);
3294                 writel(0, &sdr_scc_mgr->update);
3295         }
3296
3297         /* Compensate for simulation model behaviour */
3298         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3299                 scc_mgr_set_dqs_bus_in_delay(i, 10);
3300                 scc_mgr_load_dqs(i);
3301         }
3302         writel(0, &sdr_scc_mgr->update);
3303
3304         /*
3305          * ArriaV has hard FIFOs that can only be initialized by incrementing
3306          * in sequencer.
3307          */
3308         vfifo_offset = CALIB_VFIFO_OFFSET;
3309         for (j = 0; j < vfifo_offset; j++)
3310                 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3311         writel(0, &phy_mgr_cmd->fifo_reset);
3312
3313         /*
3314          * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3315          * setting from generation-time constant.
3316          */
3317         gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3318         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3319 }
3320
3321 /**
3322  * mem_calibrate() - Memory calibration entry point.
3323  *
3324  * Perform memory calibration.
3325  */
3326 static uint32_t mem_calibrate(void)
3327 {
3328         uint32_t i;
3329         uint32_t rank_bgn, sr;
3330         uint32_t write_group, write_test_bgn;
3331         uint32_t read_group, read_test_bgn;
3332         uint32_t run_groups, current_run;
3333         uint32_t failing_groups = 0;
3334         uint32_t group_failed = 0;
3335
3336         const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3337                                 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3338
3339         debug("%s:%d\n", __func__, __LINE__);
3340
3341         /* Initialize the data settings */
3342         gbl->error_substage = CAL_SUBSTAGE_NIL;
3343         gbl->error_stage = CAL_STAGE_NIL;
3344         gbl->error_group = 0xff;
3345         gbl->fom_in = 0;
3346         gbl->fom_out = 0;
3347
3348         /* Initialize WLAT and RLAT. */
3349         mem_init_latency();
3350
3351         /* Initialize bit slips. */
3352         mem_precharge_and_activate();
3353
3354         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3355                 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3356                           SCC_MGR_GROUP_COUNTER_OFFSET);
3357                 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3358                 if (i == 0)
3359                         scc_mgr_set_hhp_extras();
3360
3361                 scc_set_bypass_mode(i);
3362         }
3363
3364         /* Calibration is skipped. */
3365         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3366                 /*
3367                  * Set VFIFO and LFIFO to instant-on settings in skip
3368                  * calibration mode.
3369                  */
3370                 mem_skip_calibrate();
3371
3372                 /*
3373                  * Do not remove this line as it makes sure all of our
3374                  * decisions have been applied.
3375                  */
3376                 writel(0, &sdr_scc_mgr->update);
3377                 return 1;
3378         }
3379
3380         /* Calibration is not skipped. */
3381         for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3382                 /*
3383                  * Zero all delay chain/phase settings for all
3384                  * groups and all shadow register sets.
3385                  */
3386                 scc_mgr_zero_all();
3387
3388                 run_groups = ~param->skip_groups;
3389
3390                 for (write_group = 0, write_test_bgn = 0; write_group
3391                         < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3392                         write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3393
3394                         /* Initialize the group failure */
3395                         group_failed = 0;
3396
3397                         current_run = run_groups & ((1 <<
3398                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3399                         run_groups = run_groups >>
3400                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3401
3402                         if (current_run == 0)
3403                                 continue;
3404
3405                         writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3406                                             SCC_MGR_GROUP_COUNTER_OFFSET);
3407                         scc_mgr_zero_group(write_group, 0);
3408
3409                         for (read_group = write_group * rwdqs_ratio,
3410                              read_test_bgn = 0;
3411                              read_group < (write_group + 1) * rwdqs_ratio;
3412                              read_group++,
3413                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3414                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3415                                         continue;
3416
3417                                 /* Calibrate the VFIFO */
3418                                 if (rw_mgr_mem_calibrate_vfifo(read_group,
3419                                                                read_test_bgn))
3420                                         continue;
3421
3422                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3423                                         return 0;
3424
3425                                 /* The group failed, we're done. */
3426                                 goto grp_failed;
3427                         }
3428
3429                         /* Calibrate the output side */
3430                         for (rank_bgn = 0, sr = 0;
3431                              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3432                              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3433                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3434                                         continue;
3435
3436                                 /* Not needed in quick mode! */
3437                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3438                                         continue;
3439
3440                                 /*
3441                                  * Determine if this set of ranks
3442                                  * should be skipped entirely.
3443                                  */
3444                                 if (param->skip_shadow_regs[sr])
3445                                         continue;
3446
3447                                 /* Calibrate WRITEs */
3448                                 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3449                                                 write_group, write_test_bgn))
3450                                         continue;
3451
3452                                 group_failed = 1;
3453                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3454                                         return 0;
3455                         }
3456
3457                         /* Some group failed, we're done. */
3458                         if (group_failed)
3459                                 goto grp_failed;
3460
3461                         for (read_group = write_group * rwdqs_ratio,
3462                              read_test_bgn = 0;
3463                              read_group < (write_group + 1) * rwdqs_ratio;
3464                              read_group++,
3465                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3466                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3467                                         continue;
3468
3469                                 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3470                                                                 read_test_bgn))
3471                                         continue;
3472
3473                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3474                                         return 0;
3475
3476                                 /* The group failed, we're done. */
3477                                 goto grp_failed;
3478                         }
3479
3480                         /* No group failed, continue as usual. */
3481                         continue;
3482
3483 grp_failed:             /* A group failed, increment the counter. */
3484                         failing_groups++;
3485                 }
3486
3487                 /*
3488                  * USER If there are any failing groups then report
3489                  * the failure.
3490                  */
3491                 if (failing_groups != 0)
3492                         return 0;
3493
3494                 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3495                         continue;
3496
3497                 /*
3498                  * If we're skipping groups as part of debug,
3499                  * don't calibrate LFIFO.
3500                  */
3501                 if (param->skip_groups != 0)
3502                         continue;
3503
3504                 /* Calibrate the LFIFO */
3505                 if (!rw_mgr_mem_calibrate_lfifo())
3506                         return 0;
3507         }
3508
3509         /*
3510          * Do not remove this line as it makes sure all of our decisions
3511          * have been applied.
3512          */
3513         writel(0, &sdr_scc_mgr->update);
3514         return 1;
3515 }
3516
3517 /**
3518  * run_mem_calibrate() - Perform memory calibration
3519  *
3520  * This function triggers the entire memory calibration procedure.
3521  */
3522 static int run_mem_calibrate(void)
3523 {
3524         int pass;
3525
3526         debug("%s:%d\n", __func__, __LINE__);
3527
3528         /* Reset pass/fail status shown on afi_cal_success/fail */
3529         writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3530
3531         /* Stop tracking manager. */
3532         clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3533
3534         phy_mgr_initialize();
3535         rw_mgr_mem_initialize();
3536
3537         /* Perform the actual memory calibration. */
3538         pass = mem_calibrate();
3539
3540         mem_precharge_and_activate();
3541         writel(0, &phy_mgr_cmd->fifo_reset);
3542
3543         /* Handoff. */
3544         rw_mgr_mem_handoff();
3545         /*
3546          * In Hard PHY this is a 2-bit control:
3547          * 0: AFI Mux Select
3548          * 1: DDIO Mux Select
3549          */
3550         writel(0x2, &phy_mgr_cfg->mux_sel);
3551
3552         /* Start tracking manager. */
3553         setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3554
3555         return pass;
3556 }
3557
3558 /**
3559  * debug_mem_calibrate() - Report result of memory calibration
3560  * @pass:       Value indicating whether calibration passed or failed
3561  *
3562  * This function reports the results of the memory calibration
3563  * and writes debug information into the register file.
3564  */
3565 static void debug_mem_calibrate(int pass)
3566 {
3567         uint32_t debug_info;
3568
3569         if (pass) {
3570                 printf("%s: CALIBRATION PASSED\n", __FILE__);
3571
3572                 gbl->fom_in /= 2;
3573                 gbl->fom_out /= 2;
3574
3575                 if (gbl->fom_in > 0xff)
3576                         gbl->fom_in = 0xff;
3577
3578                 if (gbl->fom_out > 0xff)
3579                         gbl->fom_out = 0xff;
3580
3581                 /* Update the FOM in the register file */
3582                 debug_info = gbl->fom_in;
3583                 debug_info |= gbl->fom_out << 8;
3584                 writel(debug_info, &sdr_reg_file->fom);
3585
3586                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3587                 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3588         } else {
3589                 printf("%s: CALIBRATION FAILED\n", __FILE__);
3590
3591                 debug_info = gbl->error_stage;
3592                 debug_info |= gbl->error_substage << 8;
3593                 debug_info |= gbl->error_group << 16;
3594
3595                 writel(debug_info, &sdr_reg_file->failing_stage);
3596                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3597                 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3598
3599                 /* Update the failing group/stage in the register file */
3600                 debug_info = gbl->error_stage;
3601                 debug_info |= gbl->error_substage << 8;
3602                 debug_info |= gbl->error_group << 16;
3603                 writel(debug_info, &sdr_reg_file->failing_stage);
3604         }
3605
3606         printf("%s: Calibration complete\n", __FILE__);
3607 }
3608
3609 /**
3610  * hc_initialize_rom_data() - Initialize ROM data
3611  *
3612  * Initialize ROM data.
3613  */
3614 static void hc_initialize_rom_data(void)
3615 {
3616         u32 i, addr;
3617
3618         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3619         for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3620                 writel(inst_rom_init[i], addr + (i << 2));
3621
3622         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3623         for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3624                 writel(ac_rom_init[i], addr + (i << 2));
3625 }
3626
3627 /**
3628  * initialize_reg_file() - Initialize SDR register file
3629  *
3630  * Initialize SDR register file.
3631  */
3632 static void initialize_reg_file(void)
3633 {
3634         /* Initialize the register file with the correct data */
3635         writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3636         writel(0, &sdr_reg_file->debug_data_addr);
3637         writel(0, &sdr_reg_file->cur_stage);
3638         writel(0, &sdr_reg_file->fom);
3639         writel(0, &sdr_reg_file->failing_stage);
3640         writel(0, &sdr_reg_file->debug1);
3641         writel(0, &sdr_reg_file->debug2);
3642 }
3643
3644 /**
3645  * initialize_hps_phy() - Initialize HPS PHY
3646  *
3647  * Initialize HPS PHY.
3648  */
3649 static void initialize_hps_phy(void)
3650 {
3651         uint32_t reg;
3652         /*
3653          * Tracking also gets configured here because it's in the
3654          * same register.
3655          */
3656         uint32_t trk_sample_count = 7500;
3657         uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3658         /*
3659          * Format is number of outer loops in the 16 MSB, sample
3660          * count in 16 LSB.
3661          */
3662
3663         reg = 0;
3664         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3665         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3666         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3667         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3668         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3669         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3670         /*
3671          * This field selects the intrinsic latency to RDATA_EN/FULL path.
3672          * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3673          */
3674         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3675         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3676                 trk_sample_count);
3677         writel(reg, &sdr_ctrl->phy_ctrl0);
3678
3679         reg = 0;
3680         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3681                 trk_sample_count >>
3682                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3683         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3684                 trk_long_idle_sample_count);
3685         writel(reg, &sdr_ctrl->phy_ctrl1);
3686
3687         reg = 0;
3688         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3689                 trk_long_idle_sample_count >>
3690                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3691         writel(reg, &sdr_ctrl->phy_ctrl2);
3692 }
3693
3694 /**
3695  * initialize_tracking() - Initialize tracking
3696  *
3697  * Initialize the register file with usable initial data.
3698  */
3699 static void initialize_tracking(void)
3700 {
3701         /*
3702          * Initialize the register file with the correct data.
3703          * Compute usable version of value in case we skip full
3704          * computation later.
3705          */
3706         writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3707                &sdr_reg_file->dtaps_per_ptap);
3708
3709         /* trk_sample_count */
3710         writel(7500, &sdr_reg_file->trk_sample_count);
3711
3712         /* longidle outer loop [15:0] */
3713         writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3714
3715         /*
3716          * longidle sample count [31:24]
3717          * trfc, worst case of 933Mhz 4Gb [23:16]
3718          * trcd, worst case [15:8]
3719          * vfifo wait [7:0]
3720          */
3721         writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3722                &sdr_reg_file->delays);
3723
3724         /* mux delay */
3725         writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3726                (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3727                &sdr_reg_file->trk_rw_mgr_addr);
3728
3729         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3730                &sdr_reg_file->trk_read_dqs_width);
3731
3732         /* trefi [7:0] */
3733         writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3734                &sdr_reg_file->trk_rfsh);
3735 }
3736
3737 int sdram_calibration_full(void)
3738 {
3739         struct param_type my_param;
3740         struct gbl_type my_gbl;
3741         uint32_t pass;
3742
3743         memset(&my_param, 0, sizeof(my_param));
3744         memset(&my_gbl, 0, sizeof(my_gbl));
3745
3746         param = &my_param;
3747         gbl = &my_gbl;
3748
3749         /* Set the calibration enabled by default */
3750         gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3751         /*
3752          * Only sweep all groups (regardless of fail state) by default
3753          * Set enabled read test by default.
3754          */
3755 #if DISABLE_GUARANTEED_READ
3756         gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3757 #endif
3758         /* Initialize the register file */
3759         initialize_reg_file();
3760
3761         /* Initialize any PHY CSR */
3762         initialize_hps_phy();
3763
3764         scc_mgr_initialize();
3765
3766         initialize_tracking();
3767
3768         printf("%s: Preparing to start memory calibration\n", __FILE__);
3769
3770         debug("%s:%d\n", __func__, __LINE__);
3771         debug_cond(DLEVEL == 1,
3772                    "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3773                    RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3774                    RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3775                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3776                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3777         debug_cond(DLEVEL == 1,
3778                    "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3779                    RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3780                    RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3781                    IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3782         debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3783                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3784         debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3785                    IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3786                    IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3787         debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3788                    IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3789                    IO_IO_OUT2_DELAY_MAX);
3790         debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3791                    IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3792
3793         hc_initialize_rom_data();
3794
3795         /* update info for sims */
3796         reg_file_set_stage(CAL_STAGE_NIL);
3797         reg_file_set_group(0);
3798
3799         /*
3800          * Load global needed for those actions that require
3801          * some dynamic calibration support.
3802          */
3803         dyn_calib_steps = STATIC_CALIB_STEPS;
3804         /*
3805          * Load global to allow dynamic selection of delay loop settings
3806          * based on calibration mode.
3807          */
3808         if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3809                 skip_delay_mask = 0xff;
3810         else
3811                 skip_delay_mask = 0x0;
3812
3813         pass = run_mem_calibrate();
3814         debug_mem_calibrate(pass);
3815         return pass;
3816 }