drivers/ddr/fsl/interactive.c

   1 /*
   2  * Copyright 2010-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  *         York Sun [at freescale.com]
  12  */
  13
  14 #include <common.h>
  15 #include <cli.h>
  16 #include <linux/ctype.h>
  17 #include <asm/types.h>
  18 #include <asm/io.h>
  19
  20 #include <fsl_ddr_sdram.h>
  21 #include <fsl_ddr.h>
  22
  23 /* Option parameter Structures */
  24 struct options_string {
  25         const char *option_name;
  26         size_t offset;
  27         unsigned int size;
  28         const char printhex;
  29 };
  30
  31 static unsigned int picos_to_mhz(unsigned int picos)
  32 {
  33         return 1000000 / picos;
  34 }
  35
  36 static void print_option_table(const struct options_string *table,
  37                          int table_size,
  38                          const void *base)
  39 {
  40         unsigned int i;
  41         unsigned int *ptr;
  42         unsigned long long *ptr_l;
  43
  44         for (i = 0; i < table_size; i++) {
  45                 switch (table[i].size) {
  46                 case 4:
  47                         ptr = (unsigned int *) (base + table[i].offset);
  48                         if (table[i].printhex) {
  49                                 printf("%s = 0x%08X\n",
  50                                         table[i].option_name, *ptr);
  51                         } else {
  52                                 printf("%s = %u\n",
  53                                         table[i].option_name, *ptr);
  54                         }
  55                         break;
  56                 case 8:
  57                         ptr_l = (unsigned long long *) (base + table[i].offset);
  58                         printf("%s = %llu\n",
  59                                 table[i].option_name, *ptr_l);
  60                         break;
  61                 default:
  62                         printf("Unrecognized size!\n");
  63                         break;
  64                 }
  65         }
  66 }
  67
  68 static int handle_option_table(const struct options_string *table,
  69                          int table_size,
  70                          void *base,
  71                          const char *opt,
  72                          const char *val)
  73 {
  74         unsigned int i;
  75         unsigned int value, *ptr;
  76         unsigned long long value_l, *ptr_l;
  77
  78         for (i = 0; i < table_size; i++) {
  79                 if (strcmp(table[i].option_name, opt) != 0)
  80                         continue;
  81                 switch (table[i].size) {
  82                 case 4:
  83                         value = simple_strtoul(val, NULL, 0);
  84                         ptr = base + table[i].offset;
  85                         *ptr = value;
  86                         break;
  87                 case 8:
  88                         value_l = simple_strtoull(val, NULL, 0);
  89                         ptr_l = base + table[i].offset;
  90                         *ptr_l = value_l;
  91                         break;
  92                 default:
  93                         printf("Unrecognized size!\n");
  94                         break;
  95                 }
  96                 return 1;
  97         }
  98
  99         return 0;
 100 }
 101
 102 static void fsl_ddr_generic_edit(void *pdata,
 103                            void *pend,
 104                            unsigned int element_size,
 105                            unsigned int element_num,
 106                            unsigned int value)
 107 {
 108         char *pcdata = (char *)pdata;           /* BIG ENDIAN ONLY */
 109
 110         pcdata += element_num * element_size;
 111         if ((pcdata + element_size) > (char *) pend) {
 112                 printf("trying to write past end of data\n");
 113                 return;
 114         }
 115
 116         switch (element_size) {
 117         case 1:
 118                 __raw_writeb(value, pcdata);
 119                 break;
 120         case 2:
 121                 __raw_writew(value, pcdata);
 122                 break;
 123         case 4:
 124                 __raw_writel(value, pcdata);
 125                 break;
 126         default:
 127                 printf("unexpected element size %u\n", element_size);
 128                 break;
 129         }
 130 }
 131
 132 static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
 133                        unsigned int ctrl_num,
 134                        unsigned int dimm_num,
 135                        unsigned int element_num,
 136                        unsigned int value)
 137 {
 138         generic_spd_eeprom_t *pspd;
 139
 140         pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
 141         fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
 142 }
 143
 144 #define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
 145         sizeof((common_timing_params_t *)0)->x, 0}
 146
 147 static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 148                                         unsigned int ctrl_num,
 149                                         const char *optname_str,
 150                                         const char *value_str)
 151 {
 152         common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
 153
 154         static const struct options_string options[] = {
 155                 COMMON_TIMING(tckmin_x_ps),
 156                 COMMON_TIMING(tckmax_ps),
 157                 COMMON_TIMING(taamin_ps),
 158                 COMMON_TIMING(trcd_ps),
 159                 COMMON_TIMING(trp_ps),
 160                 COMMON_TIMING(tras_ps),
 161
 162 #ifdef CONFIG_SYS_FSL_DDR4
 163                 COMMON_TIMING(trfc1_ps),
 164                 COMMON_TIMING(trfc2_ps),
 165                 COMMON_TIMING(trfc4_ps),
 166                 COMMON_TIMING(trrds_ps),
 167                 COMMON_TIMING(trrdl_ps),
 168                 COMMON_TIMING(tccdl_ps),
 169 #else
 170                 COMMON_TIMING(twtr_ps),
 171                 COMMON_TIMING(trfc_ps),
 172                 COMMON_TIMING(trrd_ps),
 173                 COMMON_TIMING(trtp_ps),
 174 #endif
 175                 COMMON_TIMING(twr_ps),
 176                 COMMON_TIMING(trc_ps),
 177                 COMMON_TIMING(refresh_rate_ps),
 178                 COMMON_TIMING(extended_op_srt),
 179 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 180                 COMMON_TIMING(tis_ps),
 181                 COMMON_TIMING(tih_ps),
 182                 COMMON_TIMING(tds_ps),
 183                 COMMON_TIMING(tdh_ps),
 184                 COMMON_TIMING(tdqsq_max_ps),
 185                 COMMON_TIMING(tqhs_ps),
 186 #endif
 187                 COMMON_TIMING(ndimms_present),
 188                 COMMON_TIMING(lowest_common_spd_caslat),
 189                 COMMON_TIMING(highest_common_derated_caslat),
 190                 COMMON_TIMING(additive_latency),
 191                 COMMON_TIMING(all_dimms_burst_lengths_bitmask),
 192                 COMMON_TIMING(all_dimms_registered),
 193                 COMMON_TIMING(all_dimms_unbuffered),
 194                 COMMON_TIMING(all_dimms_ecc_capable),
 195                 COMMON_TIMING(total_mem),
 196                 COMMON_TIMING(base_address),
 197         };
 198         static const unsigned int n_opts = ARRAY_SIZE(options);
 199
 200         if (handle_option_table(options, n_opts, p, optname_str, value_str))
 201                 return;
 202
 203         printf("Error: couldn't find option string %s\n", optname_str);
 204 }
 205
 206 #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
 207         sizeof((dimm_params_t *)0)->x, 0}
 208 #define DIMM_PARM_HEX(x) {#x, offsetof(dimm_params_t, x), \
 209         sizeof((dimm_params_t *)0)->x, 1}
 210
 211 static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 212                                    unsigned int ctrl_num,
 213                                    unsigned int dimm_num,
 214                                    const char *optname_str,
 215                                    const char *value_str)
 216 {
 217         dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
 218
 219         static const struct options_string options[] = {
 220                 DIMM_PARM(n_ranks),
 221                 DIMM_PARM(data_width),
 222                 DIMM_PARM(primary_sdram_width),
 223                 DIMM_PARM(ec_sdram_width),
 224                 DIMM_PARM(registered_dimm),
 225                 DIMM_PARM(mirrored_dimm),
 226                 DIMM_PARM(device_width),
 227
 228                 DIMM_PARM(n_row_addr),
 229                 DIMM_PARM(n_col_addr),
 230                 DIMM_PARM(edc_config),
 231 #ifdef CONFIG_SYS_FSL_DDR4
 232                 DIMM_PARM(bank_addr_bits),
 233                 DIMM_PARM(bank_group_bits),
 234 #else
 235                 DIMM_PARM(n_banks_per_sdram_device),
 236 #endif
 237                 DIMM_PARM(burst_lengths_bitmask),
 238                 DIMM_PARM(row_density),
 239
 240                 DIMM_PARM(tckmin_x_ps),
 241                 DIMM_PARM(tckmin_x_minus_1_ps),
 242                 DIMM_PARM(tckmin_x_minus_2_ps),
 243                 DIMM_PARM(tckmax_ps),
 244
 245                 DIMM_PARM(caslat_x),
 246                 DIMM_PARM(caslat_x_minus_1),
 247                 DIMM_PARM(caslat_x_minus_2),
 248
 249                 DIMM_PARM(caslat_lowest_derated),
 250
 251                 DIMM_PARM(trcd_ps),
 252                 DIMM_PARM(trp_ps),
 253                 DIMM_PARM(tras_ps),
 254 #ifdef CONFIG_SYS_FSL_DDR4
 255                 DIMM_PARM(trfc1_ps),
 256                 DIMM_PARM(trfc2_ps),
 257                 DIMM_PARM(trfc4_ps),
 258                 DIMM_PARM(trrds_ps),
 259                 DIMM_PARM(trrdl_ps),
 260                 DIMM_PARM(tccdl_ps),
 261 #else
 262                 DIMM_PARM(twr_ps),
 263                 DIMM_PARM(twtr_ps),
 264                 DIMM_PARM(trfc_ps),
 265                 DIMM_PARM(trrd_ps),
 266                 DIMM_PARM(trtp_ps),
 267 #endif
 268                 DIMM_PARM(trc_ps),
 269                 DIMM_PARM(refresh_rate_ps),
 270                 DIMM_PARM(extended_op_srt),
 271
 272 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 273                 DIMM_PARM(tis_ps),
 274                 DIMM_PARM(tih_ps),
 275                 DIMM_PARM(tds_ps),
 276                 DIMM_PARM(tdh_ps),
 277                 DIMM_PARM(tdqsq_max_ps),
 278                 DIMM_PARM(tqhs_ps),
 279 #endif
 280 #ifdef CONFIG_SYS_FSL_DDR4
 281                 DIMM_PARM_HEX(dq_mapping[0]),
 282                 DIMM_PARM_HEX(dq_mapping[1]),
 283                 DIMM_PARM_HEX(dq_mapping[2]),
 284                 DIMM_PARM_HEX(dq_mapping[3]),
 285                 DIMM_PARM_HEX(dq_mapping[4]),
 286                 DIMM_PARM_HEX(dq_mapping[5]),
 287                 DIMM_PARM_HEX(dq_mapping[6]),
 288                 DIMM_PARM_HEX(dq_mapping[7]),
 289                 DIMM_PARM_HEX(dq_mapping[8]),
 290                 DIMM_PARM_HEX(dq_mapping[9]),
 291                 DIMM_PARM_HEX(dq_mapping[10]),
 292                 DIMM_PARM_HEX(dq_mapping[11]),
 293                 DIMM_PARM_HEX(dq_mapping[12]),
 294                 DIMM_PARM_HEX(dq_mapping[13]),
 295                 DIMM_PARM_HEX(dq_mapping[14]),
 296                 DIMM_PARM_HEX(dq_mapping[15]),
 297                 DIMM_PARM_HEX(dq_mapping[16]),
 298                 DIMM_PARM_HEX(dq_mapping[17]),
 299                 DIMM_PARM(dq_mapping_ors),
 300 #endif
 301                 DIMM_PARM(rank_density),
 302                 DIMM_PARM(capacity),
 303                 DIMM_PARM(base_address),
 304         };
 305
 306         static const unsigned int n_opts = ARRAY_SIZE(options);
 307
 308         if (handle_option_table(options, n_opts, p, optname_str, value_str))
 309                 return;
 310
 311         printf("couldn't find option string %s\n", optname_str);
 312 }
 313
 314 static void print_dimm_parameters(const dimm_params_t *pdimm)
 315 {
 316         static const struct options_string options[] = {
 317                 DIMM_PARM(n_ranks),
 318                 DIMM_PARM(data_width),
 319                 DIMM_PARM(primary_sdram_width),
 320                 DIMM_PARM(ec_sdram_width),
 321                 DIMM_PARM(registered_dimm),
 322                 DIMM_PARM(mirrored_dimm),
 323                 DIMM_PARM(device_width),
 324
 325                 DIMM_PARM(n_row_addr),
 326                 DIMM_PARM(n_col_addr),
 327                 DIMM_PARM(edc_config),
 328 #ifdef CONFIG_SYS_FSL_DDR4
 329                 DIMM_PARM(bank_addr_bits),
 330                 DIMM_PARM(bank_group_bits),
 331 #else
 332                 DIMM_PARM(n_banks_per_sdram_device),
 333 #endif
 334
 335                 DIMM_PARM(tckmin_x_ps),
 336                 DIMM_PARM(tckmin_x_minus_1_ps),
 337                 DIMM_PARM(tckmin_x_minus_2_ps),
 338                 DIMM_PARM(tckmax_ps),
 339
 340                 DIMM_PARM(caslat_x),
 341                 DIMM_PARM_HEX(caslat_x),
 342                 DIMM_PARM(taa_ps),
 343                 DIMM_PARM(caslat_x_minus_1),
 344                 DIMM_PARM(caslat_x_minus_2),
 345                 DIMM_PARM(caslat_lowest_derated),
 346
 347                 DIMM_PARM(trcd_ps),
 348                 DIMM_PARM(trp_ps),
 349                 DIMM_PARM(tras_ps),
 350 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
 351                 DIMM_PARM(tfaw_ps),
 352 #endif
 353 #ifdef CONFIG_SYS_FSL_DDR4
 354                 DIMM_PARM(trfc1_ps),
 355                 DIMM_PARM(trfc2_ps),
 356                 DIMM_PARM(trfc4_ps),
 357                 DIMM_PARM(trrds_ps),
 358                 DIMM_PARM(trrdl_ps),
 359                 DIMM_PARM(tccdl_ps),
 360 #else
 361                 DIMM_PARM(twr_ps),
 362                 DIMM_PARM(twtr_ps),
 363                 DIMM_PARM(trfc_ps),
 364                 DIMM_PARM(trrd_ps),
 365                 DIMM_PARM(trtp_ps),
 366 #endif
 367                 DIMM_PARM(trc_ps),
 368                 DIMM_PARM(refresh_rate_ps),
 369
 370 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 371                 DIMM_PARM(tis_ps),
 372                 DIMM_PARM(tih_ps),
 373                 DIMM_PARM(tds_ps),
 374                 DIMM_PARM(tdh_ps),
 375                 DIMM_PARM(tdqsq_max_ps),
 376                 DIMM_PARM(tqhs_ps),
 377 #endif
 378 #ifdef CONFIG_SYS_FSL_DDR4
 379                 DIMM_PARM_HEX(dq_mapping[0]),
 380                 DIMM_PARM_HEX(dq_mapping[1]),
 381                 DIMM_PARM_HEX(dq_mapping[2]),
 382                 DIMM_PARM_HEX(dq_mapping[3]),
 383                 DIMM_PARM_HEX(dq_mapping[4]),
 384                 DIMM_PARM_HEX(dq_mapping[5]),
 385                 DIMM_PARM_HEX(dq_mapping[6]),
 386                 DIMM_PARM_HEX(dq_mapping[7]),
 387                 DIMM_PARM_HEX(dq_mapping[8]),
 388                 DIMM_PARM_HEX(dq_mapping[9]),
 389                 DIMM_PARM_HEX(dq_mapping[10]),
 390                 DIMM_PARM_HEX(dq_mapping[11]),
 391                 DIMM_PARM_HEX(dq_mapping[12]),
 392                 DIMM_PARM_HEX(dq_mapping[13]),
 393                 DIMM_PARM_HEX(dq_mapping[14]),
 394                 DIMM_PARM_HEX(dq_mapping[15]),
 395                 DIMM_PARM_HEX(dq_mapping[16]),
 396                 DIMM_PARM_HEX(dq_mapping[17]),
 397                 DIMM_PARM(dq_mapping_ors),
 398 #endif
 399         };
 400         static const unsigned int n_opts = ARRAY_SIZE(options);
 401
 402         if (pdimm->n_ranks == 0) {
 403                 printf("DIMM not present\n");
 404                 return;
 405         }
 406         printf("DIMM organization parameters:\n");
 407         printf("module part name = %s\n", pdimm->mpart);
 408         printf("rank_density = %llu bytes (%llu megabytes)\n",
 409                pdimm->rank_density, pdimm->rank_density / 0x100000);
 410         printf("capacity = %llu bytes (%llu megabytes)\n",
 411                pdimm->capacity, pdimm->capacity / 0x100000);
 412         printf("burst_lengths_bitmask = %02X\n",
 413                pdimm->burst_lengths_bitmask);
 414         printf("base_addresss = %llu (%08llX %08llX)\n",
 415                pdimm->base_address,
 416                (pdimm->base_address >> 32),
 417                pdimm->base_address & 0xFFFFFFFF);
 418         print_option_table(options, n_opts, pdimm);
 419 }
 420
 421 static void print_lowest_common_dimm_parameters(
 422                 const common_timing_params_t *plcd_dimm_params)
 423 {
 424         static const struct options_string options[] = {
 425                 COMMON_TIMING(taamin_ps),
 426                 COMMON_TIMING(trcd_ps),
 427                 COMMON_TIMING(trp_ps),
 428                 COMMON_TIMING(tras_ps),
 429 #ifdef CONFIG_SYS_FSL_DDR4
 430                 COMMON_TIMING(trfc1_ps),
 431                 COMMON_TIMING(trfc2_ps),
 432                 COMMON_TIMING(trfc4_ps),
 433                 COMMON_TIMING(trrds_ps),
 434                 COMMON_TIMING(trrdl_ps),
 435                 COMMON_TIMING(tccdl_ps),
 436 #else
 437                 COMMON_TIMING(twtr_ps),
 438                 COMMON_TIMING(trfc_ps),
 439                 COMMON_TIMING(trrd_ps),
 440                 COMMON_TIMING(trtp_ps),
 441 #endif
 442                 COMMON_TIMING(twr_ps),
 443                 COMMON_TIMING(trc_ps),
 444                 COMMON_TIMING(refresh_rate_ps),
 445                 COMMON_TIMING(extended_op_srt),
 446 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 447                 COMMON_TIMING(tis_ps),
 448                 COMMON_TIMING(tih_ps),
 449                 COMMON_TIMING(tds_ps),
 450                 COMMON_TIMING(tdh_ps),
 451                 COMMON_TIMING(tdqsq_max_ps),
 452                 COMMON_TIMING(tqhs_ps),
 453 #endif
 454                 COMMON_TIMING(lowest_common_spd_caslat),
 455                 COMMON_TIMING(highest_common_derated_caslat),
 456                 COMMON_TIMING(additive_latency),
 457                 COMMON_TIMING(ndimms_present),
 458                 COMMON_TIMING(all_dimms_registered),
 459                 COMMON_TIMING(all_dimms_unbuffered),
 460                 COMMON_TIMING(all_dimms_ecc_capable),
 461         };
 462         static const unsigned int n_opts = ARRAY_SIZE(options);
 463
 464         /* Clock frequencies */
 465         printf("tckmin_x_ps = %u (%u MHz)\n",
 466                plcd_dimm_params->tckmin_x_ps,
 467                picos_to_mhz(plcd_dimm_params->tckmin_x_ps));
 468         printf("tckmax_ps = %u (%u MHz)\n",
 469                plcd_dimm_params->tckmax_ps,
 470                picos_to_mhz(plcd_dimm_params->tckmax_ps));
 471         printf("all_dimms_burst_lengths_bitmask = %02X\n",
 472                plcd_dimm_params->all_dimms_burst_lengths_bitmask);
 473
 474         print_option_table(options, n_opts, plcd_dimm_params);
 475
 476         printf("total_mem = %llu (%llu megabytes)\n",
 477                plcd_dimm_params->total_mem,
 478                plcd_dimm_params->total_mem / 0x100000);
 479         printf("base_address = %llu (%llu megabytes)\n",
 480                plcd_dimm_params->base_address,
 481                plcd_dimm_params->base_address / 0x100000);
 482 }
 483
 484 #define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
 485         sizeof((memctl_options_t *)0)->x, 0}
 486 #define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
 487         offsetof(memctl_options_t, cs_local_opts[x].y), \
 488         sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
 489
 490 static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 491                            unsigned int ctl_num,
 492                            const char *optname_str,
 493                            const char *value_str)
 494 {
 495         memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
 496         /*
 497          * This array all on the stack and *computed* each time this
 498          * function is rung.
 499          */
 500         static const struct options_string options[] = {
 501                 CTRL_OPTIONS_CS(0, odt_rd_cfg),
 502                 CTRL_OPTIONS_CS(0, odt_wr_cfg),
 503 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 504                 CTRL_OPTIONS_CS(1, odt_rd_cfg),
 505                 CTRL_OPTIONS_CS(1, odt_wr_cfg),
 506 #endif
 507 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 508                 CTRL_OPTIONS_CS(2, odt_rd_cfg),
 509                 CTRL_OPTIONS_CS(2, odt_wr_cfg),
 510 #endif
 511 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 512                 CTRL_OPTIONS_CS(3, odt_rd_cfg),
 513                 CTRL_OPTIONS_CS(3, odt_wr_cfg),
 514 #endif
 515 #if defined(CONFIG_SYS_FSL_DDR3)
 516                 CTRL_OPTIONS_CS(0, odt_rtt_norm),
 517                 CTRL_OPTIONS_CS(0, odt_rtt_wr),
 518 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 519                 CTRL_OPTIONS_CS(1, odt_rtt_norm),
 520                 CTRL_OPTIONS_CS(1, odt_rtt_wr),
 521 #endif
 522 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 523                 CTRL_OPTIONS_CS(2, odt_rtt_norm),
 524                 CTRL_OPTIONS_CS(2, odt_rtt_wr),
 525 #endif
 526 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 527                 CTRL_OPTIONS_CS(3, odt_rtt_norm),
 528                 CTRL_OPTIONS_CS(3, odt_rtt_wr),
 529 #endif
 530 #endif
 531                 CTRL_OPTIONS(memctl_interleaving),
 532                 CTRL_OPTIONS(memctl_interleaving_mode),
 533                 CTRL_OPTIONS(ba_intlv_ctl),
 534                 CTRL_OPTIONS(ecc_mode),
 535                 CTRL_OPTIONS(ecc_init_using_memctl),
 536                 CTRL_OPTIONS(dqs_config),
 537                 CTRL_OPTIONS(self_refresh_in_sleep),
 538                 CTRL_OPTIONS(dynamic_power),
 539                 CTRL_OPTIONS(data_bus_width),
 540                 CTRL_OPTIONS(burst_length),
 541                 CTRL_OPTIONS(cas_latency_override),
 542                 CTRL_OPTIONS(cas_latency_override_value),
 543                 CTRL_OPTIONS(use_derated_caslat),
 544                 CTRL_OPTIONS(additive_latency_override),
 545                 CTRL_OPTIONS(additive_latency_override_value),
 546                 CTRL_OPTIONS(clk_adjust),
 547                 CTRL_OPTIONS(cpo_override),
 548                 CTRL_OPTIONS(write_data_delay),
 549                 CTRL_OPTIONS(half_strength_driver_enable),
 550
 551                 /*
 552                  * These can probably be changed to 2T_EN and 3T_EN
 553                  * (using a leading numerical character) without problem
 554                  */
 555                 CTRL_OPTIONS(twot_en),
 556                 CTRL_OPTIONS(threet_en),
 557                 CTRL_OPTIONS(ap_en),
 558                 CTRL_OPTIONS(x4_en),
 559                 CTRL_OPTIONS(bstopre),
 560                 CTRL_OPTIONS(wrlvl_override),
 561                 CTRL_OPTIONS(wrlvl_sample),
 562                 CTRL_OPTIONS(wrlvl_start),
 563                 CTRL_OPTIONS(cswl_override),
 564                 CTRL_OPTIONS(rcw_override),
 565                 CTRL_OPTIONS(rcw_1),
 566                 CTRL_OPTIONS(rcw_2),
 567                 CTRL_OPTIONS(ddr_cdr1),
 568                 CTRL_OPTIONS(ddr_cdr2),
 569                 CTRL_OPTIONS(tfaw_window_four_activates_ps),
 570                 CTRL_OPTIONS(trwt_override),
 571                 CTRL_OPTIONS(trwt),
 572                 CTRL_OPTIONS(rtt_override),
 573                 CTRL_OPTIONS(rtt_override_value),
 574                 CTRL_OPTIONS(rtt_wr_override_value),
 575         };
 576
 577         static const unsigned int n_opts = ARRAY_SIZE(options);
 578
 579         if (handle_option_table(options, n_opts, p,
 580                                         optname_str, value_str))
 581                 return;
 582
 583         printf("couldn't find option string %s\n", optname_str);
 584 }
 585
 586 #define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
 587         sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
 588 #define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
 589         offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
 590         sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
 591
 592 static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 593 {
 594         unsigned int i;
 595         static const struct options_string options[] = {
 596                 CFG_REGS_CS(0, bnds),
 597                 CFG_REGS_CS(0, config),
 598                 CFG_REGS_CS(0, config_2),
 599 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 600                 CFG_REGS_CS(1, bnds),
 601                 CFG_REGS_CS(1, config),
 602                 CFG_REGS_CS(1, config_2),
 603 #endif
 604 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 605                 CFG_REGS_CS(2, bnds),
 606                 CFG_REGS_CS(2, config),
 607                 CFG_REGS_CS(2, config_2),
 608 #endif
 609 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 610                 CFG_REGS_CS(3, bnds),
 611                 CFG_REGS_CS(3, config),
 612                 CFG_REGS_CS(3, config_2),
 613 #endif
 614                 CFG_REGS(timing_cfg_3),
 615                 CFG_REGS(timing_cfg_0),
 616                 CFG_REGS(timing_cfg_1),
 617                 CFG_REGS(timing_cfg_2),
 618                 CFG_REGS(ddr_sdram_cfg),
 619                 CFG_REGS(ddr_sdram_cfg_2),
 620                 CFG_REGS(ddr_sdram_cfg_3),
 621                 CFG_REGS(ddr_sdram_mode),
 622                 CFG_REGS(ddr_sdram_mode_2),
 623                 CFG_REGS(ddr_sdram_mode_3),
 624                 CFG_REGS(ddr_sdram_mode_4),
 625                 CFG_REGS(ddr_sdram_mode_5),
 626                 CFG_REGS(ddr_sdram_mode_6),
 627                 CFG_REGS(ddr_sdram_mode_7),
 628                 CFG_REGS(ddr_sdram_mode_8),
 629 #ifdef CONFIG_SYS_FSL_DDR4
 630                 CFG_REGS(ddr_sdram_mode_9),
 631                 CFG_REGS(ddr_sdram_mode_10),
 632                 CFG_REGS(ddr_sdram_mode_11),
 633                 CFG_REGS(ddr_sdram_mode_12),
 634                 CFG_REGS(ddr_sdram_mode_13),
 635                 CFG_REGS(ddr_sdram_mode_14),
 636                 CFG_REGS(ddr_sdram_mode_15),
 637                 CFG_REGS(ddr_sdram_mode_16),
 638 #endif
 639                 CFG_REGS(ddr_sdram_interval),
 640                 CFG_REGS(ddr_data_init),
 641                 CFG_REGS(ddr_sdram_clk_cntl),
 642                 CFG_REGS(ddr_init_addr),
 643                 CFG_REGS(ddr_init_ext_addr),
 644                 CFG_REGS(timing_cfg_4),
 645                 CFG_REGS(timing_cfg_5),
 646 #ifdef CONFIG_SYS_FSL_DDR4
 647                 CFG_REGS(timing_cfg_6),
 648                 CFG_REGS(timing_cfg_7),
 649                 CFG_REGS(timing_cfg_8),
 650                 CFG_REGS(timing_cfg_9),
 651 #endif
 652                 CFG_REGS(ddr_zq_cntl),
 653                 CFG_REGS(ddr_wrlvl_cntl),
 654                 CFG_REGS(ddr_wrlvl_cntl_2),
 655                 CFG_REGS(ddr_wrlvl_cntl_3),
 656                 CFG_REGS(ddr_sr_cntr),
 657                 CFG_REGS(ddr_sdram_rcw_1),
 658                 CFG_REGS(ddr_sdram_rcw_2),
 659                 CFG_REGS(ddr_cdr1),
 660                 CFG_REGS(ddr_cdr2),
 661                 CFG_REGS(dq_map_0),
 662                 CFG_REGS(dq_map_1),
 663                 CFG_REGS(dq_map_2),
 664                 CFG_REGS(dq_map_3),
 665                 CFG_REGS(err_disable),
 666                 CFG_REGS(err_int_en),
 667                 CFG_REGS(ddr_eor),
 668         };
 669         static const unsigned int n_opts = ARRAY_SIZE(options);
 670
 671         print_option_table(options, n_opts, ddr);
 672
 673         for (i = 0; i < 32; i++)
 674                 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
 675 }
 676
 677 static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 678                         unsigned int ctrl_num,
 679                         const char *regname,
 680                         const char *value_str)
 681 {
 682         unsigned int i;
 683         fsl_ddr_cfg_regs_t *ddr;
 684         char buf[20];
 685         static const struct options_string options[] = {
 686                 CFG_REGS_CS(0, bnds),
 687                 CFG_REGS_CS(0, config),
 688                 CFG_REGS_CS(0, config_2),
 689 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 690                 CFG_REGS_CS(1, bnds),
 691                 CFG_REGS_CS(1, config),
 692                 CFG_REGS_CS(1, config_2),
 693 #endif
 694 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 695                 CFG_REGS_CS(2, bnds),
 696                 CFG_REGS_CS(2, config),
 697                 CFG_REGS_CS(2, config_2),
 698 #endif
 699 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 700                 CFG_REGS_CS(3, bnds),
 701                 CFG_REGS_CS(3, config),
 702                 CFG_REGS_CS(3, config_2),
 703 #endif
 704                 CFG_REGS(timing_cfg_3),
 705                 CFG_REGS(timing_cfg_0),
 706                 CFG_REGS(timing_cfg_1),
 707                 CFG_REGS(timing_cfg_2),
 708                 CFG_REGS(ddr_sdram_cfg),
 709                 CFG_REGS(ddr_sdram_cfg_2),
 710                 CFG_REGS(ddr_sdram_cfg_3),
 711                 CFG_REGS(ddr_sdram_mode),
 712                 CFG_REGS(ddr_sdram_mode_2),
 713                 CFG_REGS(ddr_sdram_mode_3),
 714                 CFG_REGS(ddr_sdram_mode_4),
 715                 CFG_REGS(ddr_sdram_mode_5),
 716                 CFG_REGS(ddr_sdram_mode_6),
 717                 CFG_REGS(ddr_sdram_mode_7),
 718                 CFG_REGS(ddr_sdram_mode_8),
 719 #ifdef CONFIG_SYS_FSL_DDR4
 720                 CFG_REGS(ddr_sdram_mode_9),
 721                 CFG_REGS(ddr_sdram_mode_10),
 722                 CFG_REGS(ddr_sdram_mode_11),
 723                 CFG_REGS(ddr_sdram_mode_12),
 724                 CFG_REGS(ddr_sdram_mode_13),
 725                 CFG_REGS(ddr_sdram_mode_14),
 726                 CFG_REGS(ddr_sdram_mode_15),
 727                 CFG_REGS(ddr_sdram_mode_16),
 728 #endif
 729                 CFG_REGS(ddr_sdram_interval),
 730                 CFG_REGS(ddr_data_init),
 731                 CFG_REGS(ddr_sdram_clk_cntl),
 732                 CFG_REGS(ddr_init_addr),
 733                 CFG_REGS(ddr_init_ext_addr),
 734                 CFG_REGS(timing_cfg_4),
 735                 CFG_REGS(timing_cfg_5),
 736 #ifdef CONFIG_SYS_FSL_DDR4
 737                 CFG_REGS(timing_cfg_6),
 738                 CFG_REGS(timing_cfg_7),
 739                 CFG_REGS(timing_cfg_8),
 740                 CFG_REGS(timing_cfg_9),
 741 #endif
 742                 CFG_REGS(ddr_zq_cntl),
 743                 CFG_REGS(ddr_wrlvl_cntl),
 744                 CFG_REGS(ddr_wrlvl_cntl_2),
 745                 CFG_REGS(ddr_wrlvl_cntl_3),
 746                 CFG_REGS(ddr_sr_cntr),
 747                 CFG_REGS(ddr_sdram_rcw_1),
 748                 CFG_REGS(ddr_sdram_rcw_2),
 749                 CFG_REGS(ddr_cdr1),
 750                 CFG_REGS(ddr_cdr2),
 751                 CFG_REGS(dq_map_0),
 752                 CFG_REGS(dq_map_1),
 753                 CFG_REGS(dq_map_2),
 754                 CFG_REGS(dq_map_3),
 755                 CFG_REGS(err_disable),
 756                 CFG_REGS(err_int_en),
 757                 CFG_REGS(ddr_sdram_rcw_2),
 758                 CFG_REGS(ddr_sdram_rcw_2),
 759                 CFG_REGS(ddr_eor),
 760         };
 761         static const unsigned int n_opts = ARRAY_SIZE(options);
 762
 763         debug("fsl_ddr_regs_edit: ctrl_num = %u, "
 764                 "regname = %s, value = %s\n",
 765                 ctrl_num, regname, value_str);
 766         if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
 767                 return;
 768
 769         ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
 770
 771         if (handle_option_table(options, n_opts, ddr, regname, value_str))
 772                 return;
 773
 774         for (i = 0; i < 32; i++) {
 775                 unsigned int value = simple_strtoul(value_str, NULL, 0);
 776                 sprintf(buf, "debug_%u", i + 1);
 777                 if (strcmp(buf, regname) == 0) {
 778                         ddr->debug[i] = value;
 779                         return;
 780                 }
 781         }
 782         printf("Error: couldn't find register string %s\n", regname);
 783 }
 784
 785 #define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
 786         sizeof((memctl_options_t *)0)->x, 1}
 787
 788 static void print_memctl_options(const memctl_options_t *popts)
 789 {
 790         static const struct options_string options[] = {
 791                 CTRL_OPTIONS_CS(0, odt_rd_cfg),
 792                 CTRL_OPTIONS_CS(0, odt_wr_cfg),
 793 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 794                 CTRL_OPTIONS_CS(1, odt_rd_cfg),
 795                 CTRL_OPTIONS_CS(1, odt_wr_cfg),
 796 #endif
 797 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 798                 CTRL_OPTIONS_CS(2, odt_rd_cfg),
 799                 CTRL_OPTIONS_CS(2, odt_wr_cfg),
 800 #endif
 801 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 802                 CTRL_OPTIONS_CS(3, odt_rd_cfg),
 803                 CTRL_OPTIONS_CS(3, odt_wr_cfg),
 804 #endif
 805 #if defined(CONFIG_SYS_FSL_DDR3)
 806                 CTRL_OPTIONS_CS(0, odt_rtt_norm),
 807                 CTRL_OPTIONS_CS(0, odt_rtt_wr),
 808 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 809                 CTRL_OPTIONS_CS(1, odt_rtt_norm),
 810                 CTRL_OPTIONS_CS(1, odt_rtt_wr),
 811 #endif
 812 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 813                 CTRL_OPTIONS_CS(2, odt_rtt_norm),
 814                 CTRL_OPTIONS_CS(2, odt_rtt_wr),
 815 #endif
 816 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 817                 CTRL_OPTIONS_CS(3, odt_rtt_norm),
 818                 CTRL_OPTIONS_CS(3, odt_rtt_wr),
 819 #endif
 820 #endif
 821                 CTRL_OPTIONS(memctl_interleaving),
 822                 CTRL_OPTIONS(memctl_interleaving_mode),
 823                 CTRL_OPTIONS_HEX(ba_intlv_ctl),
 824                 CTRL_OPTIONS(ecc_mode),
 825                 CTRL_OPTIONS(ecc_init_using_memctl),
 826                 CTRL_OPTIONS(dqs_config),
 827                 CTRL_OPTIONS(self_refresh_in_sleep),
 828                 CTRL_OPTIONS(dynamic_power),
 829                 CTRL_OPTIONS(data_bus_width),
 830                 CTRL_OPTIONS(burst_length),
 831                 CTRL_OPTIONS(cas_latency_override),
 832                 CTRL_OPTIONS(cas_latency_override_value),
 833                 CTRL_OPTIONS(use_derated_caslat),
 834                 CTRL_OPTIONS(additive_latency_override),
 835                 CTRL_OPTIONS(additive_latency_override_value),
 836                 CTRL_OPTIONS(clk_adjust),
 837                 CTRL_OPTIONS(cpo_override),
 838                 CTRL_OPTIONS(write_data_delay),
 839                 CTRL_OPTIONS(half_strength_driver_enable),
 840                 /*
 841                  * These can probably be changed to 2T_EN and 3T_EN
 842                  * (using a leading numerical character) without problem
 843                  */
 844                 CTRL_OPTIONS(twot_en),
 845                 CTRL_OPTIONS(threet_en),
 846                 CTRL_OPTIONS(registered_dimm_en),
 847                 CTRL_OPTIONS(ap_en),
 848                 CTRL_OPTIONS(x4_en),
 849                 CTRL_OPTIONS(bstopre),
 850                 CTRL_OPTIONS(wrlvl_override),
 851                 CTRL_OPTIONS(wrlvl_sample),
 852                 CTRL_OPTIONS(wrlvl_start),
 853                 CTRL_OPTIONS_HEX(cswl_override),
 854                 CTRL_OPTIONS(rcw_override),
 855                 CTRL_OPTIONS(rcw_1),
 856                 CTRL_OPTIONS(rcw_2),
 857                 CTRL_OPTIONS_HEX(ddr_cdr1),
 858                 CTRL_OPTIONS_HEX(ddr_cdr2),
 859                 CTRL_OPTIONS(tfaw_window_four_activates_ps),
 860                 CTRL_OPTIONS(trwt_override),
 861                 CTRL_OPTIONS(trwt),
 862                 CTRL_OPTIONS(rtt_override),
 863                 CTRL_OPTIONS(rtt_override_value),
 864                 CTRL_OPTIONS(rtt_wr_override_value),
 865         };
 866         static const unsigned int n_opts = ARRAY_SIZE(options);
 867
 868         print_option_table(options, n_opts, popts);
 869 }
 870
 871 #ifdef CONFIG_SYS_FSL_DDR1
 872 void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
 873 {
 874         unsigned int i;
 875
 876         printf("%-3d    : %02x %s\n", 0, spd->info_size,
 877                " spd->info_size,   *  0 # bytes written into serial memory *");
 878         printf("%-3d    : %02x %s\n", 1, spd->chip_size,
 879                " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
 880         printf("%-3d    : %02x %s\n", 2, spd->mem_type,
 881                " spd->mem_type,    *  2 Fundamental memory type *");
 882         printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
 883                " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
 884         printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
 885                " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
 886         printf("%-3d    : %02x %s\n", 5, spd->nrows,
 887                " spd->nrows        *  5 # of DIMM Banks *");
 888         printf("%-3d    : %02x %s\n", 6, spd->dataw_lsb,
 889                " spd->dataw_lsb,   *  6 Data Width lsb of this assembly *");
 890         printf("%-3d    : %02x %s\n", 7, spd->dataw_msb,
 891                " spd->dataw_msb,   *  7 Data Width msb of this assembly *");
 892         printf("%-3d    : %02x %s\n", 8, spd->voltage,
 893                " spd->voltage,     *  8 Voltage intf std of this assembly *");
 894         printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
 895                " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
 896         printf("%-3d    : %02x %s\n", 10, spd->clk_access,
 897                " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
 898         printf("%-3d    : %02x %s\n", 11, spd->config,
 899                " spd->config,      * 11 DIMM Configuration type *");
 900         printf("%-3d    : %02x %s\n", 12, spd->refresh,
 901                " spd->refresh,     * 12 Refresh Rate/Type *");
 902         printf("%-3d    : %02x %s\n", 13, spd->primw,
 903                " spd->primw,       * 13 Primary SDRAM Width *");
 904         printf("%-3d    : %02x %s\n", 14, spd->ecw,
 905                " spd->ecw,         * 14 Error Checking SDRAM width *");
 906         printf("%-3d    : %02x %s\n", 15, spd->min_delay,
 907                " spd->min_delay,   * 15 Back to Back Random Access *");
 908         printf("%-3d    : %02x %s\n", 16, spd->burstl,
 909                " spd->burstl,      * 16 Burst Lengths Supported *");
 910         printf("%-3d    : %02x %s\n", 17, spd->nbanks,
 911                " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
 912         printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
 913                " spd->cas_lat,     * 18 CAS# Latencies Supported *");
 914         printf("%-3d    : %02x %s\n", 19, spd->cs_lat,
 915                " spd->cs_lat,      * 19 Chip Select Latency *");
 916         printf("%-3d    : %02x %s\n", 20, spd->write_lat,
 917                " spd->write_lat,   * 20 Write Latency/Recovery *");
 918         printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
 919                " spd->mod_attr,    * 21 SDRAM Module Attributes *");
 920         printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
 921                " spd->dev_attr,    * 22 SDRAM Device Attributes *");
 922         printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
 923                " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
 924         printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
 925                " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
 926         printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
 927                " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
 928         printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
 929                " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
 930         printf("%-3d    : %02x %s\n", 27, spd->trp,
 931                " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
 932         printf("%-3d    : %02x %s\n", 28, spd->trrd,
 933                " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
 934         printf("%-3d    : %02x %s\n", 29, spd->trcd,
 935                " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
 936         printf("%-3d    : %02x %s\n", 30, spd->tras,
 937                " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
 938         printf("%-3d    : %02x %s\n", 31, spd->bank_dens,
 939                " spd->bank_dens,   * 31 Density of each bank on module *");
 940         printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
 941                " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
 942         printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
 943                " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
 944         printf("%-3d    : %02x %s\n", 34, spd->data_setup,
 945                " spd->data_setup,  * 34 Data signal input setup time *");
 946         printf("%-3d    : %02x %s\n", 35, spd->data_hold,
 947                " spd->data_hold,   * 35 Data signal input hold time *");
 948         printf("%-3d    : %02x %s\n", 36, spd->res_36_40[0],
 949                " spd->res_36_40[0], * 36 Reserved / tWR *");
 950         printf("%-3d    : %02x %s\n", 37, spd->res_36_40[1],
 951                " spd->res_36_40[1], * 37 Reserved / tWTR *");
 952         printf("%-3d    : %02x %s\n", 38, spd->res_36_40[2],
 953                " spd->res_36_40[2], * 38 Reserved / tRTP *");
 954         printf("%-3d    : %02x %s\n", 39, spd->res_36_40[3],
 955                " spd->res_36_40[3], * 39 Reserved / mem_probe *");
 956         printf("%-3d    : %02x %s\n", 40, spd->res_36_40[4],
 957                " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
 958         printf("%-3d    : %02x %s\n", 41, spd->trc,
 959                " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
 960         printf("%-3d    : %02x %s\n", 42, spd->trfc,
 961                " spd->trfc,        * 42 Min Auto to Active period tRFC *");
 962         printf("%-3d    : %02x %s\n", 43, spd->tckmax,
 963                " spd->tckmax,      * 43 Max device cycle time tCKmax *");
 964         printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
 965                " spd->tdqsq,       * 44 Max DQS to DQ skew *");
 966         printf("%-3d    : %02x %s\n", 45, spd->tqhs,
 967                " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
 968         printf("%-3d    : %02x %s\n", 46, spd->res_46,
 969                " spd->res_46,  * 46 Reserved/ PLL Relock time *");
 970         printf("%-3d    : %02x %s\n", 47, spd->dimm_height,
 971                " spd->dimm_height  * 47 SDRAM DIMM Height *");
 972
 973         printf("%-3d-%3d: ",  48, 61);
 974
 975         for (i = 0; i < 14; i++)
 976                 printf("%02x", spd->res_48_61[i]);
 977
 978         printf(" * 48-61 IDD in SPD and Reserved space *\n");
 979
 980         printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
 981                " spd->spd_rev,     * 62 SPD Data Revision Code *");
 982         printf("%-3d    : %02x %s\n", 63, spd->cksum,
 983                " spd->cksum,       * 63 Checksum for bytes 0-62 *");
 984         printf("%-3d-%3d: ",  64, 71);
 985
 986         for (i = 0; i < 8; i++)
 987                 printf("%02x", spd->mid[i]);
 988
 989         printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
 990         printf("%-3d    : %02x %s\n", 72, spd->mloc,
 991                " spd->mloc,        * 72 Manufacturing Location *");
 992
 993         printf("%-3d-%3d: >>",  73, 90);
 994
 995         for (i = 0; i < 18; i++)
 996                 printf("%c", spd->mpart[i]);
 997
 998         printf("<<* 73 Manufacturer's Part Number *\n");
 999
1000         printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1001                "* 91 Revision Code *");
1002         printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1003                "* 93 Manufacturing Date *");
1004         printf("%-3d-%3d: ", 95, 98);
1005
1006         for (i = 0; i < 4; i++)
1007                 printf("%02x", spd->sernum[i]);
1008
1009         printf("* 95 Assembly Serial Number *\n");
1010
1011         printf("%-3d-%3d: ", 99, 127);
1012
1013         for (i = 0; i < 27; i++)
1014                 printf("%02x", spd->mspec[i]);
1015
1016         printf("* 99 Manufacturer Specific Data *\n");
1017 }
1018 #endif
1019
1020 #ifdef CONFIG_SYS_FSL_DDR2
1021 void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
1022 {
1023         unsigned int i;
1024
1025         printf("%-3d    : %02x %s\n", 0, spd->info_size,
1026                " spd->info_size,   *  0 # bytes written into serial memory *");
1027         printf("%-3d    : %02x %s\n", 1, spd->chip_size,
1028                " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
1029         printf("%-3d    : %02x %s\n", 2, spd->mem_type,
1030                " spd->mem_type,    *  2 Fundamental memory type *");
1031         printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
1032                " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
1033         printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
1034                " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
1035         printf("%-3d    : %02x %s\n", 5, spd->mod_ranks,
1036                " spd->mod_ranks    *  5 # of Module Rows on this assembly *");
1037         printf("%-3d    : %02x %s\n", 6, spd->dataw,
1038                " spd->dataw,       *  6 Data Width of this assembly *");
1039         printf("%-3d    : %02x %s\n", 7, spd->res_7,
1040                " spd->res_7,       *  7 Reserved *");
1041         printf("%-3d    : %02x %s\n", 8, spd->voltage,
1042                " spd->voltage,     *  8 Voltage intf std of this assembly *");
1043         printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
1044                " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
1045         printf("%-3d    : %02x %s\n", 10, spd->clk_access,
1046                " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
1047         printf("%-3d    : %02x %s\n", 11, spd->config,
1048                " spd->config,      * 11 DIMM Configuration type *");
1049         printf("%-3d    : %02x %s\n", 12, spd->refresh,
1050                " spd->refresh,     * 12 Refresh Rate/Type *");
1051         printf("%-3d    : %02x %s\n", 13, spd->primw,
1052                " spd->primw,       * 13 Primary SDRAM Width *");
1053         printf("%-3d    : %02x %s\n", 14, spd->ecw,
1054                " spd->ecw,         * 14 Error Checking SDRAM width *");
1055         printf("%-3d    : %02x %s\n", 15, spd->res_15,
1056                " spd->res_15,      * 15 Reserved *");
1057         printf("%-3d    : %02x %s\n", 16, spd->burstl,
1058                " spd->burstl,      * 16 Burst Lengths Supported *");
1059         printf("%-3d    : %02x %s\n", 17, spd->nbanks,
1060                " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
1061         printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
1062                " spd->cas_lat,     * 18 CAS# Latencies Supported *");
1063         printf("%-3d    : %02x %s\n", 19, spd->mech_char,
1064                " spd->mech_char,   * 19 Mechanical Characteristics *");
1065         printf("%-3d    : %02x %s\n", 20, spd->dimm_type,
1066                " spd->dimm_type,   * 20 DIMM type *");
1067         printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
1068                " spd->mod_attr,    * 21 SDRAM Module Attributes *");
1069         printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
1070                " spd->dev_attr,    * 22 SDRAM Device Attributes *");
1071         printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
1072                " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
1073         printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
1074                " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
1075         printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
1076                " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
1077         printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
1078                " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
1079         printf("%-3d    : %02x %s\n", 27, spd->trp,
1080                " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
1081         printf("%-3d    : %02x %s\n", 28, spd->trrd,
1082                " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
1083         printf("%-3d    : %02x %s\n", 29, spd->trcd,
1084                " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
1085         printf("%-3d    : %02x %s\n", 30, spd->tras,
1086                " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
1087         printf("%-3d    : %02x %s\n", 31, spd->rank_dens,
1088                " spd->rank_dens,   * 31 Density of each rank on module *");
1089         printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
1090                " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
1091         printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
1092                " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
1093         printf("%-3d    : %02x %s\n", 34, spd->data_setup,
1094                " spd->data_setup,  * 34 Data signal input setup time *");
1095         printf("%-3d    : %02x %s\n", 35, spd->data_hold,
1096                " spd->data_hold,   * 35 Data signal input hold time *");
1097         printf("%-3d    : %02x %s\n", 36, spd->twr,
1098                " spd->twr,         * 36 Write Recovery time tWR *");
1099         printf("%-3d    : %02x %s\n", 37, spd->twtr,
1100                " spd->twtr,        * 37 Int write to read delay tWTR *");
1101         printf("%-3d    : %02x %s\n", 38, spd->trtp,
1102                " spd->trtp,        * 38 Int read to precharge delay tRTP *");
1103         printf("%-3d    : %02x %s\n", 39, spd->mem_probe,
1104                " spd->mem_probe,   * 39 Mem analysis probe characteristics *");
1105         printf("%-3d    : %02x %s\n", 40, spd->trctrfc_ext,
1106                " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
1107         printf("%-3d    : %02x %s\n", 41, spd->trc,
1108                " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
1109         printf("%-3d    : %02x %s\n", 42, spd->trfc,
1110                " spd->trfc,        * 42 Min Auto to Active period tRFC *");
1111         printf("%-3d    : %02x %s\n", 43, spd->tckmax,
1112                " spd->tckmax,      * 43 Max device cycle time tCKmax *");
1113         printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
1114                " spd->tdqsq,       * 44 Max DQS to DQ skew *");
1115         printf("%-3d    : %02x %s\n", 45, spd->tqhs,
1116                " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
1117         printf("%-3d    : %02x %s\n", 46, spd->pll_relock,
1118                " spd->pll_relock,  * 46 PLL Relock time *");
1119         printf("%-3d    : %02x %s\n", 47, spd->t_casemax,
1120                " spd->t_casemax,    * 47 t_casemax *");
1121         printf("%-3d    : %02x %s\n", 48, spd->psi_ta_dram,
1122                " spd->psi_ta_dram,   * 48 Thermal Resistance of DRAM Package "
1123                "from Top (Case) to Ambient (Psi T-A DRAM) *");
1124         printf("%-3d    : %02x %s\n", 49, spd->dt0_mode,
1125                " spd->dt0_mode,    * 49 DRAM Case Temperature Rise from "
1126                "Ambient due to Activate-Precharge/Mode Bits "
1127                "(DT0/Mode Bits) *)");
1128         printf("%-3d    : %02x %s\n", 50, spd->dt2n_dt2q,
1129                " spd->dt2n_dt2q,   * 50 DRAM Case Temperature Rise from "
1130                "Ambient due to Precharge/Quiet Standby "
1131                "(DT2N/DT2Q) *");
1132         printf("%-3d    : %02x %s\n", 51, spd->dt2p,
1133                " spd->dt2p,        * 51 DRAM Case Temperature Rise from "
1134                "Ambient due to Precharge Power-Down (DT2P) *");
1135         printf("%-3d    : %02x %s\n", 52, spd->dt3n,
1136                " spd->dt3n,        * 52 DRAM Case Temperature Rise from "
1137                "Ambient due to Active Standby (DT3N) *");
1138         printf("%-3d    : %02x %s\n", 53, spd->dt3pfast,
1139                " spd->dt3pfast,    * 53 DRAM Case Temperature Rise from "
1140                "Ambient due to Active Power-Down with Fast PDN Exit "
1141                "(DT3Pfast) *");
1142         printf("%-3d    : %02x %s\n", 54, spd->dt3pslow,
1143                " spd->dt3pslow,    * 54 DRAM Case Temperature Rise from "
1144                "Ambient due to Active Power-Down with Slow PDN Exit "
1145                "(DT3Pslow) *");
1146         printf("%-3d    : %02x %s\n", 55, spd->dt4r_dt4r4w,
1147                " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
1148                "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
1149                "(DT4R/DT4R4W Mode Bit) *");
1150         printf("%-3d    : %02x %s\n", 56, spd->dt5b,
1151                " spd->dt5b,        * 56 DRAM Case Temperature Rise from "
1152                "Ambient due to Burst Refresh (DT5B) *");
1153         printf("%-3d    : %02x %s\n", 57, spd->dt7,
1154                " spd->dt7,         * 57 DRAM Case Temperature Rise from "
1155                "Ambient due to Bank Interleave Reads with "
1156                "Auto-Precharge (DT7) *");
1157         printf("%-3d    : %02x %s\n", 58, spd->psi_ta_pll,
1158                " spd->psi_ta_pll,    * 58 Thermal Resistance of PLL Package form"
1159                " Top (Case) to Ambient (Psi T-A PLL) *");
1160         printf("%-3d    : %02x %s\n", 59, spd->psi_ta_reg,
1161                " spd->psi_ta_reg,    * 59 Thermal Reisitance of Register Package"
1162                " from Top (Case) to Ambient (Psi T-A Register) *");
1163         printf("%-3d    : %02x %s\n", 60, spd->dtpllactive,
1164                " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
1165                "Ambient due to PLL Active (DT PLL Active) *");
1166         printf("%-3d    : %02x %s\n", 61, spd->dtregact,
1167                " spd->dtregact,    "
1168                "* 61 Register Case Temperature Rise from Ambient due to "
1169                "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
1170         printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
1171                " spd->spd_rev,     * 62 SPD Data Revision Code *");
1172         printf("%-3d    : %02x %s\n", 63, spd->cksum,
1173                " spd->cksum,       * 63 Checksum for bytes 0-62 *");
1174
1175         printf("%-3d-%3d: ",  64, 71);
1176
1177         for (i = 0; i < 8; i++)
1178                 printf("%02x", spd->mid[i]);
1179
1180         printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1181
1182         printf("%-3d    : %02x %s\n", 72, spd->mloc,
1183                " spd->mloc,        * 72 Manufacturing Location *");
1184
1185         printf("%-3d-%3d: >>",  73, 90);
1186         for (i = 0; i < 18; i++)
1187                 printf("%c", spd->mpart[i]);
1188
1189
1190         printf("<<* 73 Manufacturer's Part Number *\n");
1191
1192         printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1193                "* 91 Revision Code *");
1194         printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1195                "* 93 Manufacturing Date *");
1196         printf("%-3d-%3d: ", 95, 98);
1197
1198         for (i = 0; i < 4; i++)
1199                 printf("%02x", spd->sernum[i]);
1200
1201         printf("* 95 Assembly Serial Number *\n");
1202
1203         printf("%-3d-%3d: ", 99, 127);
1204         for (i = 0; i < 27; i++)
1205                 printf("%02x", spd->mspec[i]);
1206
1207
1208         printf("* 99 Manufacturer Specific Data *\n");
1209 }
1210 #endif
1211
1212 #ifdef CONFIG_SYS_FSL_DDR3
1213 void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
1214 {
1215         unsigned int i;
1216
1217         /* General Section: Bytes 0-59 */
1218
1219 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1220 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1221         printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1222
1223         PRINT_NXS(0, spd->info_size_crc,
1224                 "info_size_crc  bytes written into serial memory, "
1225                 "CRC coverage");
1226         PRINT_NXS(1, spd->spd_rev,
1227                 "spd_rev        SPD Revision");
1228         PRINT_NXS(2, spd->mem_type,
1229                 "mem_type       Key Byte / DRAM Device Type");
1230         PRINT_NXS(3, spd->module_type,
1231                 "module_type    Key Byte / Module Type");
1232         PRINT_NXS(4, spd->density_banks,
1233                 "density_banks  SDRAM Density and Banks");
1234         PRINT_NXS(5, spd->addressing,
1235                 "addressing     SDRAM Addressing");
1236         PRINT_NXS(6, spd->module_vdd,
1237                 "module_vdd     Module Nominal Voltage, VDD");
1238         PRINT_NXS(7, spd->organization,
1239                 "organization   Module Organization");
1240         PRINT_NXS(8, spd->bus_width,
1241                 "bus_width      Module Memory Bus Width");
1242         PRINT_NXS(9, spd->ftb_div,
1243                 "ftb_div        Fine Timebase (FTB) Dividend / Divisor");
1244         PRINT_NXS(10, spd->mtb_dividend,
1245                 "mtb_dividend   Medium Timebase (MTB) Dividend");
1246         PRINT_NXS(11, spd->mtb_divisor,
1247                 "mtb_divisor    Medium Timebase (MTB) Divisor");
1248         PRINT_NXS(12, spd->tck_min,
1249                   "tck_min        SDRAM Minimum Cycle Time");
1250         PRINT_NXS(13, spd->res_13,
1251                 "res_13         Reserved");
1252         PRINT_NXS(14, spd->caslat_lsb,
1253                 "caslat_lsb     CAS Latencies Supported, LSB");
1254         PRINT_NXS(15, spd->caslat_msb,
1255                 "caslat_msb     CAS Latencies Supported, MSB");
1256         PRINT_NXS(16, spd->taa_min,
1257                   "taa_min        Min CAS Latency Time");
1258         PRINT_NXS(17, spd->twr_min,
1259                   "twr_min        Min Write REcovery Time");
1260         PRINT_NXS(18, spd->trcd_min,
1261                   "trcd_min       Min RAS# to CAS# Delay Time");
1262         PRINT_NXS(19, spd->trrd_min,
1263                   "trrd_min       Min Row Active to Row Active Delay Time");
1264         PRINT_NXS(20, spd->trp_min,
1265                   "trp_min        Min Row Precharge Delay Time");
1266         PRINT_NXS(21, spd->tras_trc_ext,
1267                   "tras_trc_ext   Upper Nibbles for tRAS and tRC");
1268         PRINT_NXS(22, spd->tras_min_lsb,
1269                   "tras_min_lsb   Min Active to Precharge Delay Time, LSB");
1270         PRINT_NXS(23, spd->trc_min_lsb,
1271                   "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB");
1272         PRINT_NXS(24, spd->trfc_min_lsb,
1273                   "trfc_min_lsb   Min Refresh Recovery Delay Time LSB");
1274         PRINT_NXS(25, spd->trfc_min_msb,
1275                   "trfc_min_msb   Min Refresh Recovery Delay Time MSB");
1276         PRINT_NXS(26, spd->twtr_min,
1277                   "twtr_min Min Internal Write to Read Command Delay Time");
1278         PRINT_NXS(27, spd->trtp_min,
1279                   "trtp_min "
1280                   "Min Internal Read to Precharge Command Delay Time");
1281         PRINT_NXS(28, spd->tfaw_msb,
1282                   "tfaw_msb       Upper Nibble for tFAW");
1283         PRINT_NXS(29, spd->tfaw_min,
1284                   "tfaw_min       Min Four Activate Window Delay Time");
1285         PRINT_NXS(30, spd->opt_features,
1286                 "opt_features   SDRAM Optional Features");
1287         PRINT_NXS(31, spd->therm_ref_opt,
1288                 "therm_ref_opt  SDRAM Thermal and Refresh Opts");
1289         PRINT_NXS(32, spd->therm_sensor,
1290                 "therm_sensor  SDRAM Thermal Sensor");
1291         PRINT_NXS(33, spd->device_type,
1292                 "device_type  SDRAM Device Type");
1293         PRINT_NXS(34, spd->fine_tck_min,
1294                   "fine_tck_min  Fine offset for tCKmin");
1295         PRINT_NXS(35, spd->fine_taa_min,
1296                   "fine_taa_min  Fine offset for tAAmin");
1297         PRINT_NXS(36, spd->fine_trcd_min,
1298                   "fine_trcd_min Fine offset for tRCDmin");
1299         PRINT_NXS(37, spd->fine_trp_min,
1300                   "fine_trp_min  Fine offset for tRPmin");
1301         PRINT_NXS(38, spd->fine_trc_min,
1302                   "fine_trc_min  Fine offset for tRCmin");
1303
1304         printf("%-3d-%3d: ",  39, 59);  /* Reserved, General Section */
1305
1306         for (i = 39; i <= 59; i++)
1307                 printf("%02x ", spd->res_39_59[i - 39]);
1308
1309         puts("\n");
1310
1311         switch (spd->module_type) {
1312         case 0x02:  /* UDIMM */
1313         case 0x03:  /* SO-DIMM */
1314         case 0x04:  /* Micro-DIMM */
1315         case 0x06:  /* Mini-UDIMM */
1316                 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
1317                         "mod_height    (Unbuffered) Module Nominal Height");
1318                 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
1319                         "mod_thickness (Unbuffered) Module Maximum Thickness");
1320                 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
1321                         "ref_raw_card  (Unbuffered) Reference Raw Card Used");
1322                 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
1323                         "addr_mapping  (Unbuffered) Address mapping from "
1324                         "Edge Connector to DRAM");
1325                 break;
1326         case 0x01:  /* RDIMM */
1327         case 0x05:  /* Mini-RDIMM */
1328                 PRINT_NXS(60, spd->mod_section.registered.mod_height,
1329                         "mod_height    (Registered) Module Nominal Height");
1330                 PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
1331                         "mod_thickness (Registered) Module Maximum Thickness");
1332                 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
1333                         "ref_raw_card  (Registered) Reference Raw Card Used");
1334                 PRINT_NXS(63, spd->mod_section.registered.modu_attr,
1335                         "modu_attr     (Registered) DIMM Module Attributes");
1336                 PRINT_NXS(64, spd->mod_section.registered.thermal,
1337                         "thermal       (Registered) Thermal Heat "
1338                         "Spreader Solution");
1339                 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
1340                         "reg_id_lo     (Registered) Register Manufacturer ID "
1341                         "Code, LSB");
1342                 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
1343                         "reg_id_hi     (Registered) Register Manufacturer ID "
1344                         "Code, MSB");
1345                 PRINT_NXS(67, spd->mod_section.registered.reg_rev,
1346                         "reg_rev       (Registered) Register "
1347                         "Revision Number");
1348                 PRINT_NXS(68, spd->mod_section.registered.reg_type,
1349                         "reg_type      (Registered) Register Type");
1350                 for (i = 69; i <= 76; i++) {
1351                         printf("%-3d    : %02x rcw[%d]\n", i,
1352                                 spd->mod_section.registered.rcw[i-69], i-69);
1353                 }
1354                 break;
1355         default:
1356                 /* Module-specific Section, Unsupported Module Type */
1357                 printf("%-3d-%3d: ", 60, 116);
1358
1359                 for (i = 60; i <= 116; i++)
1360                         printf("%02x", spd->mod_section.uc[i - 60]);
1361
1362                 break;
1363         }
1364
1365         /* Unique Module ID: Bytes 117-125 */
1366         PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1367         PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1368         PRINT_NXS(119, spd->mloc,     "Mfg Location");
1369         PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
1370
1371         printf("%-3d-%3d: ", 122, 125);
1372
1373         for (i = 122; i <= 125; i++)
1374                 printf("%02x ", spd->sernum[i - 122]);
1375         printf("   Module Serial Number\n");
1376
1377         /* CRC: Bytes 126-127 */
1378         PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1379
1380         /* Other Manufacturer Fields and User Space: Bytes 128-255 */
1381         printf("%-3d-%3d: ", 128, 145);
1382         for (i = 128; i <= 145; i++)
1383                 printf("%02x ", spd->mpart[i - 128]);
1384         printf("   Mfg's Module Part Number\n");
1385
1386         PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
1387                 "Module Revision code");
1388
1389         PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1390         PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1391
1392         printf("%-3d-%3d: ", 150, 175);
1393         for (i = 150; i <= 175; i++)
1394                 printf("%02x ", spd->msd[i - 150]);
1395         printf("   Mfg's Specific Data\n");
1396
1397         printf("%-3d-%3d: ", 176, 255);
1398         for (i = 176; i <= 255; i++)
1399                 printf("%02x", spd->cust[i - 176]);
1400         printf("   Mfg's Specific Data\n");
1401
1402 }
1403 #endif
1404
1405 #ifdef CONFIG_SYS_FSL_DDR4
1406 void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd)
1407 {
1408         unsigned int i;
1409
1410         /* General Section: Bytes 0-127 */
1411
1412 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1413 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1414         printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1415
1416         PRINT_NXS(0, spd->info_size_crc,
1417                   "info_size_crc  bytes written into serial memory, CRC coverage");
1418         PRINT_NXS(1, spd->spd_rev,
1419                   "spd_rev        SPD Revision");
1420         PRINT_NXS(2, spd->mem_type,
1421                   "mem_type       Key Byte / DRAM Device Type");
1422         PRINT_NXS(3, spd->module_type,
1423                   "module_type    Key Byte / Module Type");
1424         PRINT_NXS(4, spd->density_banks,
1425                   "density_banks  SDRAM Density and Banks");
1426         PRINT_NXS(5, spd->addressing,
1427                   "addressing     SDRAM Addressing");
1428         PRINT_NXS(6, spd->package_type,
1429                   "package_type   Package type");
1430         PRINT_NXS(7, spd->opt_feature,
1431                   "opt_feature    Optional features");
1432         PRINT_NXS(8, spd->thermal_ref,
1433                   "thermal_ref    Thermal and Refresh options");
1434         PRINT_NXS(9, spd->oth_opt_features,
1435                   "oth_opt_features Other SDRAM optional features");
1436         PRINT_NXS(10, spd->res_10,
1437                   "res_10         Reserved");
1438         PRINT_NXS(11, spd->module_vdd,
1439                   "module_vdd     Module Nominal Voltage, VDD");
1440         PRINT_NXS(12, spd->organization,
1441                   "organization Module Organization");
1442         PRINT_NXS(13, spd->bus_width,
1443                   "bus_width      Module Memory Bus Width");
1444         PRINT_NXS(14, spd->therm_sensor,
1445                   "therm_sensor   Module Thermal Sensor");
1446         PRINT_NXS(15, spd->ext_type,
1447                   "ext_type       Extended module type");
1448         PRINT_NXS(16, spd->res_16,
1449                   "res_16       Reserved");
1450         PRINT_NXS(17, spd->timebases,
1451                   "timebases    MTb and FTB");
1452         PRINT_NXS(18, spd->tck_min,
1453                   "tck_min      tCKAVGmin");
1454         PRINT_NXS(19, spd->tck_max,
1455                   "tck_max      TCKAVGmax");
1456         PRINT_NXS(20, spd->caslat_b1,
1457                   "caslat_b1    CAS latencies, 1st byte");
1458         PRINT_NXS(21, spd->caslat_b2,
1459                   "caslat_b2    CAS latencies, 2nd byte");
1460         PRINT_NXS(22, spd->caslat_b3,
1461                   "caslat_b3    CAS latencies, 3rd byte ");
1462         PRINT_NXS(23, spd->caslat_b4,
1463                   "caslat_b4    CAS latencies, 4th byte");
1464         PRINT_NXS(24, spd->taa_min,
1465                   "taa_min      Min CAS Latency Time");
1466         PRINT_NXS(25, spd->trcd_min,
1467                   "trcd_min     Min RAS# to CAS# Delay Time");
1468         PRINT_NXS(26, spd->trp_min,
1469                   "trp_min      Min Row Precharge Delay Time");
1470         PRINT_NXS(27, spd->tras_trc_ext,
1471                   "tras_trc_ext Upper Nibbles for tRAS and tRC");
1472         PRINT_NXS(28, spd->tras_min_lsb,
1473                   "tras_min_lsb tRASmin, lsb");
1474         PRINT_NXS(29, spd->trc_min_lsb,
1475                   "trc_min_lsb  tRCmin, lsb");
1476         PRINT_NXS(30, spd->trfc1_min_lsb,
1477                   "trfc1_min_lsb  Min Refresh Recovery Delay Time, LSB");
1478         PRINT_NXS(31, spd->trfc1_min_msb,
1479                   "trfc1_min_msb  Min Refresh Recovery Delay Time, MSB ");
1480         PRINT_NXS(32, spd->trfc2_min_lsb,
1481                   "trfc2_min_lsb  Min Refresh Recovery Delay Time, LSB");
1482         PRINT_NXS(33, spd->trfc2_min_msb,
1483                   "trfc2_min_msb  Min Refresh Recovery Delay Time, MSB");
1484         PRINT_NXS(34, spd->trfc4_min_lsb,
1485                   "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB");
1486         PRINT_NXS(35, spd->trfc4_min_msb,
1487                   "trfc4_min_msb Min Refresh Recovery Delay Time, MSB");
1488         PRINT_NXS(36, spd->tfaw_msb,
1489                   "tfaw_msb      Upper Nibble for tFAW");
1490         PRINT_NXS(37, spd->tfaw_min,
1491                   "tfaw_min      tFAW, lsb");
1492         PRINT_NXS(38, spd->trrds_min,
1493                   "trrds_min     tRRD_Smin, MTB");
1494         PRINT_NXS(39, spd->trrdl_min,
1495                   "trrdl_min     tRRD_Lmin, MTB");
1496         PRINT_NXS(40, spd->tccdl_min,
1497                   "tccdl_min     tCCS_Lmin, MTB");
1498
1499         printf("%-3d-%3d: ", 41, 59);  /* Reserved, General Section */
1500         for (i = 41; i <= 59; i++)
1501                 printf("%02x ", spd->res_41[i - 41]);
1502
1503         puts("\n");
1504         printf("%-3d-%3d: ", 60, 77);
1505         for (i = 60; i <= 77; i++)
1506                 printf("%02x ", spd->mapping[i - 60]);
1507         puts("   mapping[] Connector to SDRAM bit map\n");
1508
1509         PRINT_NXS(117, spd->fine_tccdl_min,
1510                   "fine_tccdl_min Fine offset for tCCD_Lmin");
1511         PRINT_NXS(118, spd->fine_trrdl_min,
1512                   "fine_trrdl_min Fine offset for tRRD_Lmin");
1513         PRINT_NXS(119, spd->fine_trrds_min,
1514                   "fine_trrds_min Fine offset for tRRD_Smin");
1515         PRINT_NXS(120, spd->fine_trc_min,
1516                   "fine_trc_min   Fine offset for tRCmin");
1517         PRINT_NXS(121, spd->fine_trp_min,
1518                   "fine_trp_min   Fine offset for tRPmin");
1519         PRINT_NXS(122, spd->fine_trcd_min,
1520                   "fine_trcd_min  Fine offset for tRCDmin");
1521         PRINT_NXS(123, spd->fine_taa_min,
1522                   "fine_taa_min   Fine offset for tAAmin");
1523         PRINT_NXS(124, spd->fine_tck_max,
1524                   "fine_tck_max   Fine offset for tCKAVGmax");
1525         PRINT_NXS(125, spd->fine_tck_min,
1526                   "fine_tck_min   Fine offset for tCKAVGmin");
1527
1528         /* CRC: Bytes 126-127 */
1529         PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1530
1531         switch (spd->module_type) {
1532         case 0x02:  /* UDIMM */
1533         case 0x03:  /* SO-DIMM */
1534                 PRINT_NXS(128, spd->mod_section.unbuffered.mod_height,
1535                           "mod_height    (Unbuffered) Module Nominal Height");
1536                 PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness,
1537                           "mod_thickness (Unbuffered) Module Maximum Thickness");
1538                 PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card,
1539                           "ref_raw_card  (Unbuffered) Reference Raw Card Used");
1540                 PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping,
1541                           "addr_mapping  (Unbuffered) Address mapping from Edge Connector to DRAM");
1542                 PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0],
1543                             spd->mod_section.unbuffered.crc[1], "  Module CRC");
1544                 break;
1545         case 0x01:  /* RDIMM */
1546                 PRINT_NXS(128, spd->mod_section.registered.mod_height,
1547                           "mod_height    (Registered) Module Nominal Height");
1548                 PRINT_NXS(129, spd->mod_section.registered.mod_thickness,
1549                           "mod_thickness (Registered) Module Maximum Thickness");
1550                 PRINT_NXS(130, spd->mod_section.registered.ref_raw_card,
1551                           "ref_raw_card  (Registered) Reference Raw Card Used");
1552                 PRINT_NXS(131, spd->mod_section.registered.modu_attr,
1553                           "modu_attr     (Registered) DIMM Module Attributes");
1554                 PRINT_NXS(132, spd->mod_section.registered.thermal,
1555                           "thermal       (Registered) Thermal Heat Spreader Solution");
1556                 PRINT_NXS(133, spd->mod_section.registered.reg_id_lo,
1557                           "reg_id_lo     (Registered) Register Manufacturer ID Code, LSB");
1558                 PRINT_NXS(134, spd->mod_section.registered.reg_id_hi,
1559                           "reg_id_hi     (Registered) Register Manufacturer ID Code, MSB");
1560                 PRINT_NXS(135, spd->mod_section.registered.reg_rev,
1561                           "reg_rev       (Registered) Register Revision Number");
1562                 PRINT_NXS(136, spd->mod_section.registered.reg_map,
1563                           "reg_map       (Registered) Address mapping");
1564                 PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0],
1565                             spd->mod_section.registered.crc[1], "  Module CRC");
1566                 break;
1567         case 0x04:  /* LRDIMM */
1568                 PRINT_NXS(128, spd->mod_section.loadreduced.mod_height,
1569                           "mod_height    (Loadreduced) Module Nominal Height");
1570                 PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness,
1571                           "mod_thickness (Loadreduced) Module Maximum Thickness");
1572                 PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card,
1573                           "ref_raw_card  (Loadreduced) Reference Raw Card Used");
1574                 PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr,
1575                           "modu_attr     (Loadreduced) DIMM Module Attributes");
1576                 PRINT_NXS(132, spd->mod_section.loadreduced.thermal,
1577                           "thermal       (Loadreduced) Thermal Heat Spreader Solution");
1578                 PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo,
1579                           "reg_id_lo     (Loadreduced) Register Manufacturer ID Code, LSB");
1580                 PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi,
1581                           "reg_id_hi     (Loadreduced) Register Manufacturer ID Code, MSB");
1582                 PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev,
1583                           "reg_rev       (Loadreduced) Register Revision Number");
1584                 PRINT_NXS(136, spd->mod_section.loadreduced.reg_map,
1585                           "reg_map       (Loadreduced) Address mapping");
1586                 PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv,
1587                           "reg_drv       (Loadreduced) Reg output drive strength");
1588                 PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck,
1589                           "reg_drv_ck    (Loadreduced) Reg output drive strength for CK");
1590                 PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev,
1591                           "data_buf_rev  (Loadreduced) Data Buffer Revision Numbe");
1592                 PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0,
1593                           "vrefqe_r0     (Loadreduced) DRAM VrefDQ for Package Rank 0");
1594                 PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1,
1595                           "vrefqe_r1     (Loadreduced) DRAM VrefDQ for Package Rank 1");
1596                 PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2,
1597                           "vrefqe_r2     (Loadreduced) DRAM VrefDQ for Package Rank 2");
1598                 PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3,
1599                           "vrefqe_r3     (Loadreduced) DRAM VrefDQ for Package Rank 3");
1600                 PRINT_NXS(144, spd->mod_section.loadreduced.data_intf,
1601                           "data_intf     (Loadreduced) Data Buffer VrefDQ for DRAM Interface");
1602                 PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866,
1603                           "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1604                 PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400,
1605                           "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1606                 PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200,
1607                           "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1608                 PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv,
1609                           "dram_drv      (Loadreduced) DRAM Drive Strength");
1610                 PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866,
1611                           "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1612                 PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400,
1613                           "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1614                 PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200,
1615                           "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1616                 PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866,
1617                           "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)");
1618                 PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400,
1619                           "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)");
1620                 PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200,
1621                           "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)");
1622                 PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0],
1623                             spd->mod_section.loadreduced.crc[1],
1624                             "  Module CRC");
1625                 break;
1626         default:
1627                 /* Module-specific Section, Unsupported Module Type */
1628                 printf("%-3d-%3d: ", 128, 255);
1629
1630                 for (i = 128; i <= 255; i++)
1631                         printf("%02x", spd->mod_section.uc[i - 128]);
1632
1633                 break;
1634         }
1635
1636         /* Unique Module ID: Bytes 320-383 */
1637         PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1638         PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1639         PRINT_NXS(322, spd->mloc,     "Mfg Location");
1640         PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date");
1641
1642         printf("%-3d-%3d: ", 325, 328);
1643
1644         for (i = 325; i <= 328; i++)
1645                 printf("%02x ", spd->sernum[i - 325]);
1646         printf("   Module Serial Number\n");
1647
1648         printf("%-3d-%3d: ", 329, 348);
1649         for (i = 329; i <= 348; i++)
1650                 printf("%02x ", spd->mpart[i - 329]);
1651         printf("   Mfg's Module Part Number\n");
1652
1653         PRINT_NXS(349, spd->mrev, "Module Revision code");
1654         PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1655         PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1656         PRINT_NXS(352, spd->stepping, "DRAM stepping");
1657
1658         printf("%-3d-%3d: ", 353, 381);
1659         for (i = 353; i <= 381; i++)
1660                 printf("%02x ", spd->msd[i - 353]);
1661         printf("   Mfg's Specific Data\n");
1662 }
1663 #endif
1664
1665 static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1666 {
1667 #if defined(CONFIG_SYS_FSL_DDR1)
1668         ddr1_spd_dump(spd);
1669 #elif defined(CONFIG_SYS_FSL_DDR2)
1670         ddr2_spd_dump(spd);
1671 #elif defined(CONFIG_SYS_FSL_DDR3)
1672         ddr3_spd_dump(spd);
1673 #elif defined(CONFIG_SYS_FSL_DDR4)
1674         ddr4_spd_dump(spd);
1675 #endif
1676 }
1677
1678 static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1679                         unsigned int ctrl_mask,
1680                         unsigned int dimm_mask,
1681                         unsigned int do_mask)
1682 {
1683         unsigned int i, j, retval;
1684
1685         /* STEP 1:  DIMM SPD data */
1686         if (do_mask & STEP_GET_SPD) {
1687                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1688                         if (!(ctrl_mask & (1 << i)))
1689                                 continue;
1690
1691                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1692                                 if (!(dimm_mask & (1 << j)))
1693                                         continue;
1694
1695                                 printf("SPD info:  Controller=%u "
1696                                                 "DIMM=%u\n", i, j);
1697                                 generic_spd_dump(
1698                                         &(pinfo->spd_installed_dimms[i][j]));
1699                                 printf("\n");
1700                         }
1701                         printf("\n");
1702                 }
1703                 printf("\n");
1704         }
1705
1706         /* STEP 2:  DIMM Parameters */
1707         if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
1708                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1709                         if (!(ctrl_mask & (1 << i)))
1710                                 continue;
1711                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1712                                 if (!(dimm_mask & (1 << j)))
1713                                         continue;
1714                                 printf("DIMM parameters:  Controller=%u "
1715                                                 "DIMM=%u\n", i, j);
1716                                 print_dimm_parameters(
1717                                         &(pinfo->dimm_params[i][j]));
1718                                 printf("\n");
1719                         }
1720                         printf("\n");
1721                 }
1722                 printf("\n");
1723         }
1724
1725         /* STEP 3:  Common Parameters */
1726         if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
1727                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1728                         if (!(ctrl_mask & (1 << i)))
1729                                 continue;
1730                         printf("\"lowest common\" DIMM parameters:  "
1731                                         "Controller=%u\n", i);
1732                         print_lowest_common_dimm_parameters(
1733                                 &pinfo->common_timing_params[i]);
1734                         printf("\n");
1735                 }
1736                 printf("\n");
1737         }
1738
1739         /* STEP 4:  User Configuration Options */
1740         if (do_mask & STEP_GATHER_OPTS) {
1741                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1742                         if (!(ctrl_mask & (1 << i)))
1743                                 continue;
1744                         printf("User Config Options: Controller=%u\n", i);
1745                         print_memctl_options(&pinfo->memctl_opts[i]);
1746                         printf("\n");
1747                 }
1748                 printf("\n");
1749         }
1750
1751         /* STEP 5:  Address assignment */
1752         if (do_mask & STEP_ASSIGN_ADDRESSES) {
1753                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1754                         if (!(ctrl_mask & (1 << i)))
1755                                 continue;
1756                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1757                                 printf("Address Assignment: Controller=%u "
1758                                                 "DIMM=%u\n", i, j);
1759                                 printf("Don't have this functionality yet\n");
1760                         }
1761                         printf("\n");
1762                 }
1763                 printf("\n");
1764         }
1765
1766         /* STEP 6:  computed controller register values */
1767         if (do_mask & STEP_COMPUTE_REGS) {
1768                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1769                         if (!(ctrl_mask & (1 << i)))
1770                                 continue;
1771                         printf("Computed Register Values: Controller=%u\n", i);
1772                         print_fsl_memctl_config_regs(
1773                                 &pinfo->fsl_ddr_config_reg[i]);
1774                         retval = check_fsl_memctl_config_regs(
1775                                 &pinfo->fsl_ddr_config_reg[i]);
1776                         if (retval) {
1777                                 printf("check_fsl_memctl_config_regs "
1778                                         "result = %u\n", retval);
1779                         }
1780                         printf("\n");
1781                 }
1782                 printf("\n");
1783         }
1784 }
1785
1786 struct data_strings {
1787         const char *data_name;
1788         unsigned int step_mask;
1789         unsigned int dimm_number_required;
1790 };
1791
1792 #define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
1793
1794 static unsigned int fsl_ddr_parse_interactive_cmd(
1795         char **argv,
1796         int argc,
1797         unsigned int *pstep_mask,
1798         unsigned int *pctlr_mask,
1799         unsigned int *pdimm_mask,
1800         unsigned int *pdimm_number_required
1801          ) {
1802
1803         static const struct data_strings options[] = {
1804                 DATA_OPTIONS(spd, STEP_GET_SPD, 1),
1805                 DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
1806                 DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
1807                 DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
1808                 DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
1809                 DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
1810         };
1811         static const unsigned int n_opts = ARRAY_SIZE(options);
1812
1813         unsigned int i, j;
1814         unsigned int error = 0;
1815
1816         for (i = 1; i < argc; i++) {
1817                 unsigned int matched = 0;
1818
1819                 for (j = 0; j < n_opts; j++) {
1820                         if (strcmp(options[j].data_name, argv[i]) != 0)
1821                                 continue;
1822                         *pstep_mask |= options[j].step_mask;
1823                         *pdimm_number_required =
1824                                 options[j].dimm_number_required;
1825                         matched = 1;
1826                         break;
1827                 }
1828
1829                 if (matched)
1830                         continue;
1831
1832                 if (argv[i][0] == 'c') {
1833                         char c = argv[i][1];
1834                         if (isdigit(c))
1835                                 *pctlr_mask |= 1 << (c - '0');
1836                         continue;
1837                 }
1838
1839                 if (argv[i][0] == 'd') {
1840                         char c = argv[i][1];
1841                         if (isdigit(c))
1842                                 *pdimm_mask |= 1 << (c - '0');
1843                         continue;
1844                 }
1845
1846                 printf("unknown arg %s\n", argv[i]);
1847                 *pstep_mask = 0;
1848                 error = 1;
1849                 break;
1850         }
1851
1852         return error;
1853 }
1854
1855 int fsl_ddr_interactive_env_var_exists(void)
1856 {
1857         char buffer[CONFIG_SYS_CBSIZE];
1858
1859         if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
1860                 return 1;
1861
1862         return 0;
1863 }
1864
1865 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
1866 {
1867         unsigned long long ddrsize;
1868         const char *prompt = "FSL DDR>";
1869         char buffer[CONFIG_SYS_CBSIZE];
1870         char buffer2[CONFIG_SYS_CBSIZE];
1871         char *p = NULL;
1872         char *argv[CONFIG_SYS_MAXARGS + 1];     /* NULL terminated */
1873         int argc;
1874         unsigned int next_step = STEP_GET_SPD;
1875         const char *usage = {
1876                 "commands:\n"
1877                 "print      print SPD and intermediate computed data\n"
1878                 "reset      reboot machine\n"
1879                 "recompute  reload SPD and options to default and recompute regs\n"
1880                 "edit       modify spd, parameter, or option\n"
1881                 "compute    recompute registers from current next_step to end\n"
1882                 "copy       copy parameters\n"
1883                 "next_step  shows current next_step\n"
1884                 "help       this message\n"
1885                 "go         program the memory controller and continue with u-boot\n"
1886         };
1887
1888         if (var_is_set) {
1889                 if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
1890                         p = buffer2;
1891                 } else {
1892                         var_is_set = 0;
1893                 }
1894         }
1895
1896         /*
1897          * The strategy for next_step is that it points to the next
1898          * step in the computation process that needs to be done.
1899          */
1900         while (1) {
1901                 if (var_is_set) {
1902                         char *pend = strchr(p, ';');
1903                         if (pend) {
1904                                 /* found command separator, copy sub-command */
1905                                 *pend = '\0';
1906                                 strcpy(buffer, p);
1907                                 p = pend + 1;
1908                         } else {
1909                                 /* separator not found, copy whole string */
1910                                 strcpy(buffer, p);
1911                                 p = NULL;
1912                                 var_is_set = 0;
1913                         }
1914                 } else {
1915                         /*
1916                          * No need to worry for buffer overflow here in
1917                          * this function;  cli_readline() maxes out at
1918                          * CFG_CBSIZE
1919                          */
1920                         cli_readline_into_buffer(prompt, buffer, 0);
1921                 }
1922                 argc = cli_simple_parse_line(buffer, argv);
1923                 if (argc == 0)
1924                         continue;
1925
1926
1927                 if (strcmp(argv[0], "help") == 0) {
1928                         puts(usage);
1929                         continue;
1930                 }
1931
1932                 if (strcmp(argv[0], "next_step") == 0) {
1933                         printf("next_step = 0x%02X (%s)\n",
1934                                next_step,
1935                                step_to_string(next_step));
1936                         continue;
1937                 }
1938
1939                 if (strcmp(argv[0], "copy") == 0) {
1940                         unsigned int error = 0;
1941                         unsigned int step_mask = 0;
1942                         unsigned int src_ctlr_mask = 0;
1943                         unsigned int src_dimm_mask = 0;
1944                         unsigned int dimm_number_required = 0;
1945                         unsigned int src_ctlr_num = 0;
1946                         unsigned int src_dimm_num = 0;
1947                         unsigned int dst_ctlr_num = -1;
1948                         unsigned int dst_dimm_num = -1;
1949                         unsigned int i, num_dest_parms;
1950
1951                         if (argc == 1) {
1952                                 printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
1953                                 continue;
1954                         }
1955
1956                         error = fsl_ddr_parse_interactive_cmd(
1957                                 argv, argc,
1958                                 &step_mask,
1959                                 &src_ctlr_mask,
1960                                 &src_dimm_mask,
1961                                 &dimm_number_required
1962                         );
1963
1964                         /* XXX: only dimm_number_required and step_mask will
1965                            be used by this function.  Parse the controller and
1966                            DIMM number separately because it is easier.  */
1967
1968                         if (error)
1969                                 continue;
1970
1971                         /* parse source destination controller / DIMM */
1972
1973                         num_dest_parms = dimm_number_required ? 2 : 1;
1974
1975                         for (i = 0; i < argc; i++) {
1976                                 if (argv[i][0] == 'c') {
1977                                         char c = argv[i][1];
1978                                         if (isdigit(c)) {
1979                                                 src_ctlr_num = (c - '0');
1980                                                 break;
1981                                         }
1982                                 }
1983                         }
1984
1985                         for (i = 0; i < argc; i++) {
1986                                 if (argv[i][0] == 'd') {
1987                                         char c = argv[i][1];
1988                                         if (isdigit(c)) {
1989                                                 src_dimm_num = (c - '0');
1990                                                 break;
1991                                         }
1992                                 }
1993                         }
1994
1995                         /* parse destination controller / DIMM */
1996
1997                         for (i = argc - 1; i >= argc - num_dest_parms; i--) {
1998                                 if (argv[i][0] == 'c') {
1999                                         char c = argv[i][1];
2000                                         if (isdigit(c)) {
2001                                                 dst_ctlr_num = (c - '0');
2002                                                 break;
2003                                         }
2004                                 }
2005                         }
2006
2007                         for (i = argc - 1; i >= argc - num_dest_parms; i--) {
2008                                 if (argv[i][0] == 'd') {
2009                                         char c = argv[i][1];
2010                                         if (isdigit(c)) {
2011                                                 dst_dimm_num = (c - '0');
2012                                                 break;
2013                                         }
2014                                 }
2015                         }
2016
2017                         /* TODO: validate inputs */
2018
2019                         debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
2020                                 src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
2021
2022
2023                         switch (step_mask) {
2024
2025                         case STEP_GET_SPD:
2026                                 memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
2027                                         &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
2028                                         sizeof(pinfo->spd_installed_dimms[0][0]));
2029                                 break;
2030
2031                         case STEP_COMPUTE_DIMM_PARMS:
2032                                 memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
2033                                         &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
2034                                         sizeof(pinfo->dimm_params[0][0]));
2035                                 break;
2036
2037                         case STEP_COMPUTE_COMMON_PARMS:
2038                                 memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
2039                                         &(pinfo->common_timing_params[src_ctlr_num]),
2040                                         sizeof(pinfo->common_timing_params[0]));
2041                                 break;
2042
2043                         case STEP_GATHER_OPTS:
2044                                 memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
2045                                         &(pinfo->memctl_opts[src_ctlr_num]),
2046                                         sizeof(pinfo->memctl_opts[0]));
2047                                 break;
2048
2049                         /* someday be able to have addresses to copy addresses... */
2050
2051                         case STEP_COMPUTE_REGS:
2052                                 memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
2053                                         &(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
2054                                         sizeof(pinfo->memctl_opts[0]));
2055                                 break;
2056
2057                         default:
2058                                 printf("unexpected step_mask value\n");
2059                         }
2060
2061                         continue;
2062
2063                 }
2064
2065                 if (strcmp(argv[0], "edit") == 0) {
2066                         unsigned int error = 0;
2067                         unsigned int step_mask = 0;
2068                         unsigned int ctlr_mask = 0;
2069                         unsigned int dimm_mask = 0;
2070                         char *p_element = NULL;
2071                         char *p_value = NULL;
2072                         unsigned int dimm_number_required = 0;
2073                         unsigned int ctrl_num;
2074                         unsigned int dimm_num;
2075
2076                         if (argc == 1) {
2077                                 /* Only the element and value must be last */
2078                                 printf("edit <c#> <d#> "
2079                                         "<spd|dimmparms|commonparms|opts|"
2080                                         "addresses|regs> <element> <value>\n");
2081                                 printf("for spd, specify byte number for "
2082                                         "element\n");
2083                                 continue;
2084                         }
2085
2086                         error = fsl_ddr_parse_interactive_cmd(
2087                                 argv, argc - 2,
2088                                 &step_mask,
2089                                 &ctlr_mask,
2090                                 &dimm_mask,
2091                                 &dimm_number_required
2092                         );
2093
2094                         if (error)
2095                                 continue;
2096
2097
2098                         /* Check arguments */
2099
2100                         /* ERROR: If no steps were found */
2101                         if (step_mask == 0) {
2102                                 printf("Error: No valid steps were specified "
2103                                                 "in argument.\n");
2104                                 continue;
2105                         }
2106
2107                         /* ERROR: If multiple steps were found */
2108                         if (step_mask & (step_mask - 1)) {
2109                                 printf("Error: Multiple steps specified in "
2110                                                 "argument.\n");
2111                                 continue;
2112                         }
2113
2114                         /* ERROR: Controller not specified */
2115                         if (ctlr_mask == 0) {
2116                                 printf("Error: controller number not "
2117                                         "specified or no element and "
2118                                         "value specified\n");
2119                                 continue;
2120                         }
2121
2122                         if (ctlr_mask & (ctlr_mask - 1)) {
2123                                 printf("Error: multiple controllers "
2124                                                 "specified, %X\n", ctlr_mask);
2125                                 continue;
2126                         }
2127
2128                         /* ERROR: DIMM number not specified */
2129                         if (dimm_number_required && dimm_mask == 0) {
2130                                 printf("Error: DIMM number number not "
2131                                         "specified or no element and "
2132                                         "value specified\n");
2133                                 continue;
2134                         }
2135
2136                         if (dimm_mask & (dimm_mask - 1)) {
2137                                 printf("Error: multipled DIMMs specified\n");
2138                                 continue;
2139                         }
2140
2141                         p_element = argv[argc - 2];
2142                         p_value = argv[argc - 1];
2143
2144                         ctrl_num = __ilog2(ctlr_mask);
2145                         dimm_num = __ilog2(dimm_mask);
2146
2147                         switch (step_mask) {
2148                         case STEP_GET_SPD:
2149                                 {
2150                                         unsigned int element_num;
2151                                         unsigned int value;
2152
2153                                         element_num = simple_strtoul(p_element,
2154                                                                      NULL, 0);
2155                                         value = simple_strtoul(p_value,
2156                                                                NULL, 0);
2157                                         fsl_ddr_spd_edit(pinfo,
2158                                                                ctrl_num,
2159                                                                dimm_num,
2160                                                                element_num,
2161                                                                value);
2162                                         next_step = STEP_COMPUTE_DIMM_PARMS;
2163                                 }
2164                                 break;
2165
2166                         case STEP_COMPUTE_DIMM_PARMS:
2167                                 fsl_ddr_dimm_parameters_edit(
2168                                                  pinfo, ctrl_num, dimm_num,
2169                                                  p_element, p_value);
2170                                 next_step = STEP_COMPUTE_COMMON_PARMS;
2171                                 break;
2172
2173                         case STEP_COMPUTE_COMMON_PARMS:
2174                                 lowest_common_dimm_parameters_edit(pinfo,
2175                                                 ctrl_num, p_element, p_value);
2176                                 next_step = STEP_GATHER_OPTS;
2177                                 break;
2178
2179                         case STEP_GATHER_OPTS:
2180                                 fsl_ddr_options_edit(pinfo, ctrl_num,
2181                                                            p_element, p_value);
2182                                 next_step = STEP_ASSIGN_ADDRESSES;
2183                                 break;
2184
2185                         case STEP_ASSIGN_ADDRESSES:
2186                                 printf("editing of address assignment "
2187                                                 "not yet implemented\n");
2188                                 break;
2189
2190                         case STEP_COMPUTE_REGS:
2191                                 {
2192                                         fsl_ddr_regs_edit(pinfo,
2193                                                                 ctrl_num,
2194                                                                 p_element,
2195                                                                 p_value);
2196                                         next_step = STEP_PROGRAM_REGS;
2197                                 }
2198                                 break;
2199
2200                         default:
2201                                 printf("programming error\n");
2202                                 while (1)
2203                                         ;
2204                                 break;
2205                         }
2206                         continue;
2207                 }
2208
2209                 if (strcmp(argv[0], "reset") == 0) {
2210                         /*
2211                          * Reboot machine.
2212                          * Args don't seem to matter because this
2213                          * doesn't return
2214                          */
2215                         do_reset(NULL, 0, 0, NULL);
2216                         printf("Reset didn't work\n");
2217                 }
2218
2219                 if (strcmp(argv[0], "recompute") == 0) {
2220                         /*
2221                          * Recalculate everything, starting with
2222                          * loading SPD EEPROM from DIMMs
2223                          */
2224                         next_step = STEP_GET_SPD;
2225                         ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2226                         continue;
2227                 }
2228
2229                 if (strcmp(argv[0], "compute") == 0) {
2230                         /*
2231                          * Compute rest of steps starting at
2232                          * the current next_step/
2233                          */
2234                         ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2235                         continue;
2236                 }
2237
2238                 if (strcmp(argv[0], "print") == 0) {
2239                         unsigned int error = 0;
2240                         unsigned int step_mask = 0;
2241                         unsigned int ctlr_mask = 0;
2242                         unsigned int dimm_mask = 0;
2243                         unsigned int dimm_number_required = 0;
2244
2245                         if (argc == 1) {
2246                                 printf("print [c<n>] [d<n>] [spd] [dimmparms] "
2247                                   "[commonparms] [opts] [addresses] [regs]\n");
2248                                 continue;
2249                         }
2250
2251                         error = fsl_ddr_parse_interactive_cmd(
2252                                 argv, argc,
2253                                 &step_mask,
2254                                 &ctlr_mask,
2255                                 &dimm_mask,
2256                                 &dimm_number_required
2257                         );
2258
2259                         if (error)
2260                                 continue;
2261
2262                         /* If no particular controller was found, print all */
2263                         if (ctlr_mask == 0)
2264                                 ctlr_mask = 0xFF;
2265
2266                         /* If no particular dimm was found, print all dimms. */
2267                         if (dimm_mask == 0)
2268                                 dimm_mask = 0xFF;
2269
2270                         /* If no steps were found, print all steps. */
2271                         if (step_mask == 0)
2272                                 step_mask = STEP_ALL;
2273
2274                         fsl_ddr_printinfo(pinfo, ctlr_mask,
2275                                                 dimm_mask, step_mask);
2276                         continue;
2277                 }
2278
2279                 if (strcmp(argv[0], "go") == 0) {
2280                         if (next_step)
2281                                 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2282                         break;
2283                 }
2284
2285                 printf("unknown command %s\n", argv[0]);
2286         }
2287
2288         debug("end of memory = %llu\n", (u64)ddrsize);
2289
2290         return ddrsize;
2291 }