2 * Copyright (C) Marvell International Ltd. and its affiliates
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _DDR_TOPOLOGY_DEF_H
8 #define _DDR_TOPOLOGY_DEF_H
10 #include "ddr3_training_ip_def.h"
11 #include "ddr3_topology_def.h"
13 #if defined(CONFIG_ARMADA_38X)
14 #include "ddr3_a38x.h"
17 /* bus width in bits */
25 enum hws_temperature {
41 /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
45 * mirror enable/disable
46 * (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)
48 int mirror_enable_bitmask;
50 /* DQS Swap (polarity) - true if enable */
53 /* CK swap (polarity) - true if enable */
58 /* bus configuration */
59 struct bus_params as_bus_params[MAX_BUS_NUM];
62 enum hws_speed_bin speed_bin_index;
64 /* bus width of memory */
65 enum hws_bus_width bus_width;
67 /* Bus memory size (MBit) */
68 enum hws_mem_size memory_size;
70 /* The DDR frequency for each interfaces */
71 enum hws_ddr_freq memory_freq;
74 * delay CAS Write Latency
75 * - 0 for using default value (jedec suggested)
81 * - 0 for using default value (jedec suggested)
85 /* operation temperature */
86 enum hws_temperature interface_temp;
89 struct hws_topology_map {
90 /* Number of interfaces (default is 12) */
93 /* Controller configuration per interface */
94 struct if_params interface_params[MAX_INTERFACE_NUM];
96 /* BUS per interface (default is 4) */
97 u8 num_of_bus_per_interface;
99 /* Bit mask for active buses */
103 /* DDR3 training global configuration parameters */
104 struct tune_train_params {
112 #endif /* _DDR_TOPOLOGY_DEF_H */