2 * Copyright (C) Marvell International Ltd. and its affiliates
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef __AXP_TRAINING_STATIC_H
8 #define __AXP_TRAINING_STATIC_H
11 * STATIC_TRAINING - Set only if static parameters for training are set and
15 MV_DRAM_TRAINING_INIT ddr3_db_rev2_667[MV_MAX_DDR3_STATIC_SIZE] = {
17 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
19 {0x000016A0, 0xC002011A},
21 {0x000016A0, 0xC0420100},
23 {0x000016A0, 0xC082020A},
25 {0x000016A0, 0xC0C20017},
27 {0x000016A0, 0xC1020113},
29 {0x000016A0, 0xC1420107},
31 {0x000016A0, 0xC182011F},
33 {0x000016A0, 0xC1C2001C},
35 {0x000016A0, 0xC202010D},
39 {0x000016A0, 0xC0004A06},
41 {0x000016A0, 0xC040690D},
43 {0x000016A0, 0xC0806A0D},
45 {0x000016A0, 0xC0C0A01B},
47 {0x000016A0, 0xC1003A01},
49 {0x000016A0, 0xC1408113},
51 {0x000016A0, 0xC1805609},
53 {0x000016A0, 0xC1C04504},
55 {0x000016A0, 0xC2009518},
57 /*center DQS on read cycle */
58 {0x000016A0, 0xC803000F},
60 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
61 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
64 {0x00001480, 0x00000001},
68 MV_DRAM_TRAINING_INIT ddr3_db_rev2_800[MV_MAX_DDR3_STATIC_SIZE] = {
70 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
72 {0x000016A0, 0xC0020301},
74 {0x000016A0, 0xC0420202},
76 {0x000016A0, 0xC0820314},
78 {0x000016A0, 0xC0C20117},
80 {0x000016A0, 0xC1020219},
82 {0x000016A0, 0xC142020B},
84 {0x000016A0, 0xC182030A},
86 {0x000016A0, 0xC1C2011D},
88 {0x000016A0, 0xC2020212},
92 {0x000016A0, 0xC0007A12},
94 {0x000016A0, 0xC0408D16},
96 {0x000016A0, 0xC0809E1B},
98 {0x000016A0, 0xC0C0AC1F},
100 {0x000016A0, 0xC1005E0A},
102 {0x000016A0, 0xC140A91D},
104 {0x000016A0, 0xC1808E17},
106 {0x000016A0, 0xC1C05509},
108 {0x000016A0, 0xC2003A01},
112 {0x000016A0, 0xC0007A12},
114 {0x000016A0, 0xC0408D16},
116 {0x000016A0, 0xC0809E1B},
118 {0x000016A0, 0xC0C0AC1F},
120 {0x000016A0, 0xC1005E0A},
122 {0x000016A0, 0xC140A91D},
124 {0x000016A0, 0xC1808E17},
126 {0x000016A0, 0xC1C05509},
128 {0x000016A0, 0xC2003A01},
130 /*center DQS on read cycle */
131 {0x000016A0, 0xC803000B},
133 {0x00001538, 0x0000000D}, /*Read Data Sample Delays Register */
134 {0x0000153C, 0x00000011}, /*Read Data Ready Delay Register */
137 {0x00001480, 0x00000001},
141 MV_DRAM_TRAINING_INIT ddr3_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
143 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
145 {0x000016A0, 0xC002010C},
147 {0x000016A0, 0xC042001C},
149 {0x000016A0, 0xC0820115},
151 {0x000016A0, 0xC0C20019},
153 {0x000016A0, 0xC1020108},
155 {0x000016A0, 0xC1420100},
157 {0x000016A0, 0xC1820111},
159 {0x000016A0, 0xC1C2001B},
161 /*{0x000016A0, 0xC2020117}, */
162 {0x000016A0, 0xC202010C},
166 {0x000016A0, 0xC0005508},
168 {0x000016A0, 0xC0409819},
170 {0x000016A0, 0xC080650C},
172 {0x000016A0, 0xC0C0700F},
174 {0x000016A0, 0xC1004103},
176 {0x000016A0, 0xC140A81D},
178 {0x000016A0, 0xC180650C},
180 {0x000016A0, 0xC1C08013},
182 {0x000016A0, 0xC2005508},
184 /*center DQS on read cycle */
185 {0x000016A0, 0xC803000F},
187 {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
188 {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
191 {0x00001480, 0x00000001},
195 MV_DRAM_TRAINING_INIT ddr3_db_533[MV_MAX_DDR3_STATIC_SIZE] = {
197 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
199 {0x000016A0, 0xC002040C},
201 {0x000016A0, 0xC0420117},
203 {0x000016A0, 0xC082041B},
205 {0x000016A0, 0xC0C20117},
207 {0x000016A0, 0xC102040A},
209 {0x000016A0, 0xC1420117},
211 {0x000016A0, 0xC1820419},
213 {0x000016A0, 0xC1C20117},
215 {0x000016A0, 0xC2020117},
219 {0x000016A0, 0xC0008113},
221 {0x000016A0, 0xC0404504},
223 {0x000016A0, 0xC0808514},
225 {0x000016A0, 0xC0C09418},
227 {0x000016A0, 0xC1006D0E},
229 {0x000016A0, 0xC1405508},
231 {0x000016A0, 0xC1807D12},
233 {0x000016A0, 0xC1C0b01F},
235 {0x000016A0, 0xC2005D0A},
237 /*center DQS on read cycle */
238 {0x000016A0, 0xC803000F},
240 {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
241 {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
244 {0x00001480, 0x00000001},
248 MV_DRAM_TRAINING_INIT ddr3_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
250 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
252 {0x000016A0, 0xC0020104},
254 {0x000016A0, 0xC0420010},
256 {0x000016A0, 0xC0820112},
258 {0x000016A0, 0xC0C20009},
260 {0x000016A0, 0xC102001F},
262 {0x000016A0, 0xC1420014},
264 {0x000016A0, 0xC1820109},
266 {0x000016A0, 0xC1C2000C},
268 {0x000016A0, 0xC2020112},
272 {0x000016A0, 0xC0009919},
274 {0x000016A0, 0xC0405508},
276 {0x000016A0, 0xC0809919},
278 {0x000016A0, 0xC0C09C1A},
280 {0x000016A0, 0xC1008113},
282 {0x000016A0, 0xC140650C},
284 {0x000016A0, 0xC1809518},
286 {0x000016A0, 0xC1C04103},
288 {0x000016A0, 0xC2006D0E},
290 /*center DQS on read cycle */
291 {0x000016A0, 0xC803000F},
293 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
294 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
296 {0x00001480, 0x00000001},
300 MV_DRAM_TRAINING_INIT ddr3_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
303 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
305 {0x000016A0, 0xC0020103},
307 {0x000016A0, 0xC0420012},
309 {0x000016A0, 0xC0820113},
311 {0x000016A0, 0xC0C20012},
313 {0x000016A0, 0xC1020100},
315 {0x000016A0, 0xC1420016},
317 {0x000016A0, 0xC1820109},
319 {0x000016A0, 0xC1C20010},
321 {0x000016A0, 0xC2020112},
325 {0x000016A0, 0xC000b11F},
327 {0x000016A0, 0xC040690D},
329 {0x000016A0, 0xC0803600},
331 {0x000016A0, 0xC0C0a81D},
333 {0x000016A0, 0xC1009919},
335 {0x000016A0, 0xC1407911},
337 {0x000016A0, 0xC180ad1e},
339 {0x000016A0, 0xC1C04d06},
341 {0x000016A0, 0xC2008514},
343 /*center DQS on read cycle */
344 {0x000016A0, 0xC803000F},
346 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
347 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
350 {0x00001480, 0x00000001},
354 MV_DRAM_TRAINING_INIT ddr3_db_800[MV_MAX_DDR3_STATIC_SIZE] = {
357 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
359 {0x000016A0, 0xC0020213},
361 {0x000016A0, 0xC0420108},
363 {0x000016A0, 0xC0820210},
365 {0x000016A0, 0xC0C20108},
367 {0x000016A0, 0xC102011A},
369 {0x000016A0, 0xC1420300},
371 {0x000016A0, 0xC1820204},
373 {0x000016A0, 0xC1C20106},
375 {0x000016A0, 0xC2020112},
379 {0x000016A0, 0xC000620B},
381 {0x000016A0, 0xC0408D16},
383 {0x000016A0, 0xC0806A0D},
385 {0x000016A0, 0xC0C03D02},
387 {0x000016A0, 0xC1004a05},
389 {0x000016A0, 0xC140A11B},
391 {0x000016A0, 0xC1805E0A},
393 {0x000016A0, 0xC1C06D0E},
395 {0x000016A0, 0xC200AD1E},
397 /*center DQS on read cycle */
398 {0x000016A0, 0xC803000F},
400 {0x00001538, 0x0000000C}, /*Read Data Sample Delays Register */
401 {0x0000153C, 0x0000000E}, /*Read Data Ready Delay Register */
404 {0x00001480, 0x00000001},
408 MV_DRAM_TRAINING_INIT ddr3_rd_667_0[MV_MAX_DDR3_STATIC_SIZE] = {
410 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
412 {0x000016A0, 0xC002010E},
414 {0x000016A0, 0xC042001E},
416 {0x000016A0, 0xC0820118},
418 {0x000016A0, 0xC0C2001E},
420 {0x000016A0, 0xC102010C},
422 {0x000016A0, 0xC1420102},
424 {0x000016A0, 0xC1820111},
426 {0x000016A0, 0xC1C2001C},
428 {0x000016A0, 0xC2020109},
432 {0x000016A0, 0xC0003600},
434 {0x000016A0, 0xC040690D},
436 {0x000016A0, 0xC0805207},
438 {0x000016A0, 0xC0C0A81D},
440 {0x000016A0, 0xC1009919},
442 {0x000016A0, 0xC1407911},
444 {0x000016A0, 0xC1803E02},
446 {0x000016A0, 0xC1C05107},
448 {0x000016A0, 0xC2008113},
450 /*center DQS on read cycle */
451 {0x000016A0, 0xC803000F},
453 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
454 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
457 {0x00001480, 0x00000001},
461 MV_DRAM_TRAINING_INIT ddr3_rd_667_1[MV_MAX_DDR3_STATIC_SIZE] = {
463 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
465 {0x000016A0, 0xC0020106},
467 {0x000016A0, 0xC0420016},
469 {0x000016A0, 0xC0820117},
471 {0x000016A0, 0xC0C2000F},
473 {0x000016A0, 0xC1020105},
475 {0x000016A0, 0xC142001B},
477 {0x000016A0, 0xC182010C},
479 {0x000016A0, 0xC1C20011},
481 {0x000016A0, 0xC2020101},
485 {0x000016A0, 0xC0003600},
487 {0x000016A0, 0xC0406D0E},
489 {0x000016A0, 0xC0803600},
491 {0x000016A0, 0xC0C04504},
493 {0x000016A0, 0xC1009919},
495 {0x000016A0, 0xC1407911},
497 {0x000016A0, 0xC1803600},
499 {0x000016A0, 0xC1C0610B},
501 {0x000016A0, 0xC2008113},
503 /*center DQS on read cycle */
504 {0x000016A0, 0xC803000F},
506 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
507 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
510 {0x00001480, 0x00000001},
514 MV_DRAM_TRAINING_INIT ddr3_rd_667_2[MV_MAX_DDR3_STATIC_SIZE] = {
516 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
518 {0x000016A0, 0xC002010C},
520 {0x000016A0, 0xC042001B},
522 {0x000016A0, 0xC082011D},
524 {0x000016A0, 0xC0C20015},
526 {0x000016A0, 0xC102010B},
528 {0x000016A0, 0xC1420101},
530 {0x000016A0, 0xC1820113},
532 {0x000016A0, 0xC1C20017},
534 {0x000016A0, 0xC2020107},
538 {0x000016A0, 0xC0003600},
540 {0x000016A0, 0xC0406D0E},
542 {0x000016A0, 0xC0803600},
544 {0x000016A0, 0xC0C04504},
546 {0x000016A0, 0xC1009919},
548 {0x000016A0, 0xC1407911},
550 {0x000016A0, 0xC180B11F},
552 {0x000016A0, 0xC1C0610B},
554 {0x000016A0, 0xC2008113},
556 /*center DQS on read cycle */
557 {0x000016A0, 0xC803000F},
559 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
560 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
563 {0x00001480, 0x00000001},
567 MV_DRAM_TRAINING_INIT ddr3_db_667_M[MV_MAX_DDR3_STATIC_SIZE] = {
569 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
572 {0x000016A0, 0xC0020103},
574 {0x000016A0, 0xC0420012},
576 {0x000016A0, 0xC0820113},
578 {0x000016A0, 0xC0C20012},
580 {0x000016A0, 0xC1020100},
582 {0x000016A0, 0xC1420016},
584 {0x000016A0, 0xC1820109},
586 {0x000016A0, 0xC1C20010},
588 {0x000016A0, 0xC2020112},
592 {0x000016A0, 0xC000b11F},
594 {0x000016A0, 0xC040690D},
596 {0x000016A0, 0xC0803600},
598 {0x000016A0, 0xC0C0a81D},
600 {0x000016A0, 0xC1009919},
602 {0x000016A0, 0xC1407911},
604 {0x000016A0, 0xC180ad1e},
606 {0x000016A0, 0xC1C04d06},
608 {0x000016A0, 0xC2008514},
610 /*center DQS on read cycle */
611 {0x000016A0, 0xC803000F},
615 {0x000016A0, 0xC0060103},
617 {0x000016A0, 0xC0460012},
619 {0x000016A0, 0xC0860113},
621 {0x000016A0, 0xC0C60012},
623 {0x000016A0, 0xC1060100},
625 {0x000016A0, 0xC1460016},
627 {0x000016A0, 0xC1860109},
629 {0x000016A0, 0xC1C60010},
631 {0x000016A0, 0xC2060112},
635 {0x000016A0, 0xC004b11F},
637 {0x000016A0, 0xC044690D},
639 {0x000016A0, 0xC0843600},
641 {0x000016A0, 0xC0C4a81D},
643 {0x000016A0, 0xC1049919},
645 {0x000016A0, 0xC1447911},
647 {0x000016A0, 0xC184ad1e},
649 {0x000016A0, 0xC1C44d06},
651 {0x000016A0, 0xC2048514},
653 /*center DQS on read cycle */
654 {0x000016A0, 0xC807000F},
658 {0x00001538, 0x00000B0B}, /*Read Data Sample Delays Register */
659 {0x0000153C, 0x00000F0F}, /*Read Data Ready Delay Register */
662 {0x00001480, 0x00000001},
666 MV_DRAM_TRAINING_INIT ddr3_rd_667_3[MV_MAX_DDR3_STATIC_SIZE] = {
668 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
670 {0x000016A0, 0xC0020118},
672 {0x000016A0, 0xC0420108},
674 {0x000016A0, 0xC0820202},
676 {0x000016A0, 0xC0C20108},
678 {0x000016A0, 0xC1020117},
680 {0x000016A0, 0xC142010C},
682 {0x000016A0, 0xC182011B},
684 {0x000016A0, 0xC1C20107},
686 {0x000016A0, 0xC2020113},
690 {0x000016A0, 0xC0003600},
692 {0x000016A0, 0xC0406D0E},
694 {0x000016A0, 0xC0805207},
696 {0x000016A0, 0xC0C0A81D},
698 {0x000016A0, 0xC1009919},
700 {0x000016A0, 0xC1407911},
702 {0x000016A0, 0xC1803E02},
704 {0x000016A0, 0xC1C04D06},
706 {0x000016A0, 0xC2008113},
708 /*center DQS on read cycle */
709 {0x000016A0, 0xC803000F},
711 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
712 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
715 {0x00001480, 0x00000001},
719 MV_DRAM_TRAINING_INIT ddr3_pcac_600[MV_MAX_DDR3_STATIC_SIZE] = {
721 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
723 {0x000016A0, 0xC0020404},
725 {0x000016A0, 0xC042031E},
727 {0x000016A0, 0xC0820411},
729 {0x000016A0, 0xC0C20400},
731 {0x000016A0, 0xC1020404},
733 {0x000016A0, 0xC142031D},
735 {0x000016A0, 0xC182040C},
737 {0x000016A0, 0xC1C2031B},
739 {0x000016A0, 0xC2020112},
743 {0x000016A0, 0xC0004905},
745 {0x000016A0, 0xC040A81D},
747 {0x000016A0, 0xC0804504},
749 {0x000016A0, 0xC0C08013},
751 {0x000016A0, 0xC1004504},
753 {0x000016A0, 0xC140A81D},
755 {0x000016A0, 0xC1805909},
757 {0x000016A0, 0xC1C09418},
759 {0x000016A0, 0xC2006D0E},
761 /*center DQS on read cycle */
762 {0x000016A0, 0xC803000F},
763 {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */
764 {0x0000153C, 0x0000000D}, /*Read Data Ready Delay Register */
766 {0x00001480, 0x00000001},
770 #endif /* __AXP_TRAINING_STATIC_H */