2 * Copyright (C) Marvell International Ltd. and its affiliates
4 * SPDX-License-Identifier: GPL-2.0
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
14 #include "ddr3_hw_training.h"
18 static void ddr3_flush_l1_line(u32 line);
20 extern u32 pbs_pattern[2][LEN_16BIT_PBS_PATTERN];
21 extern u32 pbs_pattern_32b[2][LEN_PBS_PATTERN];
22 #if defined(MV88F78X60)
23 extern u32 pbs_pattern_64b[2][LEN_PBS_PATTERN];
25 extern u32 pbs_dq_mapping[PUP_NUM_64BIT][DQ_NUM];
27 #if defined(MV88F78X60) || defined(MV88F672X)
28 /* PBS locked dq (per pup) */
29 u32 pbs_locked_dq[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
30 u32 pbs_locked_dm[MAX_PUP_NUM] = { 0 };
31 u32 pbs_locked_value[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
33 int per_bit_data[MAX_PUP_NUM][DQ_NUM];
36 static u32 sdram_data[LEN_KILLER_PATTERN] __aligned(32) = { 0 };
38 static struct crc_dma_desc dma_desc __aligned(32) = { 0 };
40 #define XOR_TIMEOUT 0x8000000
42 struct xor_channel_t {
43 struct crc_dma_desc *desc;
44 unsigned long desc_phys_addr;
47 #define XOR_CAUSE_DONE_MASK(chan) ((0x1 | 0x2) << (chan * 16))
49 void xor_waiton_eng(int chan)
54 while (!(reg_read(XOR_CAUSE_REG(XOR_UNIT(chan))) &
55 XOR_CAUSE_DONE_MASK(XOR_CHAN(chan)))) {
56 if (timeout > XOR_TIMEOUT)
63 while (mv_xor_state_get(chan) != MV_IDLE) {
64 if (timeout > XOR_TIMEOUT)
71 reg_write(XOR_CAUSE_REG(XOR_UNIT(chan)),
72 ~(XOR_CAUSE_DONE_MASK(XOR_CHAN(chan))));
78 static int special_compare_pattern(u32 uj)
80 if ((uj == 30) || (uj == 31) || (uj == 61) || (uj == 62) ||
81 (uj == 93) || (uj == 94) || (uj == 126) || (uj == 127))
88 * Compare code extracted as its used by multiple functions. This
89 * reduces code-size and makes it easier to maintain it. Additionally
90 * the code is not indented that much and therefore easier to read.
92 static void compare_pattern_v1(u32 uj, u32 *pup, u32 *pattern,
93 u32 pup_groups, int debug_dqs)
99 __maybe_unused u32 dq;
101 if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0xFF)) {
102 for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
103 val = CMP_BYTE_SHIFT * uk;
104 var1 = ((sdram_data[uj] >> val) & CMP_BYTE_MASK);
105 var2 = ((pattern[uj] >> val) & CMP_BYTE_MASK);
108 *pup |= (1 << (uk + (PUP_NUM_32BIT *
109 (uj % pup_groups))));
115 for (dq = 0; dq < DQ_NUM; dq++) {
116 val = uk + (PUP_NUM_32BIT *
118 if (((var1 >> dq) & 0x1) !=
119 ((var2 >> dq) & 0x1))
120 per_bit_data[val][dq] = 1;
122 per_bit_data[val][dq] = 0;
130 static void compare_pattern_v2(u32 uj, u32 *pup, u32 *pattern)
137 if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0x3)) {
139 for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
140 val = CMP_BYTE_SHIFT * uk;
141 var1 = (sdram_data[uj] >> val) & CMP_BYTE_MASK;
142 var2 = (pattern[uj] >> val) & CMP_BYTE_MASK;
144 *pup |= (1 << (uk % PUP_NUM_16BIT));
150 * Name: ddr3_sdram_compare
151 * Desc: Execute compare per PUP
152 * Args: unlock_pup Bit array of the unlock pups
153 * new_locked_pup Output bit array of the pups with failed compare
154 * pattern Pattern to compare
155 * pattern_len Length of pattern (in bytes)
156 * sdram_offset offset address to the SDRAM
157 * write write to the SDRAM before read
158 * mask compare pattern with mask;
159 * mask_pattern Mask to compare pattern
162 * Returns: MV_OK if success, other error code if fail.
164 int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
165 u32 *new_locked_pup, u32 *pattern,
166 u32 pattern_len, u32 sdram_offset, int write,
167 int mask, u32 *mask_pattern,
171 __maybe_unused u32 pup_groups;
172 __maybe_unused u32 dq;
174 #if !defined(MV88F67XX)
175 if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
181 ddr3_reset_phy_read_fifo();
183 /* Check if need to write to sdram before read */
185 ddr3_dram_sram_burst((u32)pattern, sdram_offset, pattern_len);
187 ddr3_dram_sram_burst(sdram_offset, (u32)sdram_data, pattern_len);
189 /* Compare read result to write */
190 for (uj = 0; uj < pattern_len; uj++) {
191 if (special_compare && special_compare_pattern(uj))
194 #if defined(MV88F78X60) || defined(MV88F672X)
195 compare_pattern_v1(uj, new_locked_pup, pattern, pup_groups, 1);
196 #elif defined(MV88F67XX)
197 compare_pattern_v2(uj, new_locked_pup, pattern);
204 #if defined(MV88F78X60) || defined(MV88F672X)
206 * Name: ddr3_sdram_dm_compare
207 * Desc: Execute compare per PUP
208 * Args: unlock_pup Bit array of the unlock pups
209 * new_locked_pup Output bit array of the pups with failed compare
210 * pattern Pattern to compare
211 * pattern_len Length of pattern (in bytes)
212 * sdram_offset offset address to the SDRAM
213 * write write to the SDRAM before read
214 * mask compare pattern with mask;
215 * mask_pattern Mask to compare pattern
218 * Returns: MV_OK if success, other error code if fail.
220 int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
221 u32 *new_locked_pup, u32 *pattern,
224 u32 uj, uk, var1, var2, pup_groups;
228 if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
233 ddr3_dram_sram_burst((u32)pattern, SDRAM_PBS_TX_OFFS,
235 ddr3_dram_sram_burst(SDRAM_PBS_TX_OFFS, (u32)sdram_data,
238 /* Validate the correctness of the results */
239 for (uj = 0; uj < LEN_PBS_PATTERN; uj++)
240 compare_pattern_v1(uj, &pup, pattern, pup_groups, 0);
242 /* Test the DM Signals */
243 *(u32 *)(SDRAM_PBS_TX_OFFS + 0x10) = 0x12345678;
244 *(u32 *)(SDRAM_PBS_TX_OFFS + 0x14) = 0x12345678;
246 sdram_data[0] = *(u32 *)(SDRAM_PBS_TX_OFFS + 0x10);
247 sdram_data[1] = *(u32 *)(SDRAM_PBS_TX_OFFS + 0x14);
249 for (uj = 0; uj < 2; uj++) {
250 if (((sdram_data[uj]) != (pattern[uj])) &&
251 (*new_locked_pup != 0xFF)) {
252 for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
253 val = CMP_BYTE_SHIFT * uk;
254 var1 = ((sdram_data[uj] >> val) & CMP_BYTE_MASK);
255 var2 = ((pattern[uj] >> val) & CMP_BYTE_MASK);
257 *new_locked_pup |= (1 << (uk +
258 (PUP_NUM_32BIT * (uj % pup_groups))));
259 *new_locked_pup |= pup;
269 * Name: ddr3_sdram_pbs_compare
270 * Desc: Execute SRAM compare per PUP and DQ.
271 * Args: pup_locked bit array of locked pups
272 * is_tx Indicate whether Rx or Tx
273 * pbs_pattern_idx Index of PBS pattern
274 * pbs_curr_val The PBS value
275 * pbs_lock_val The value to set to locked PBS
276 * skew_array Global array to update with the compare results
277 * ai_unlock_pup_dq_array bit array of the locked / unlocked pups per dq.
279 * Returns: MV_OK if success, other error code if fail.
281 int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked,
282 int is_tx, u32 pbs_pattern_idx,
283 u32 pbs_curr_val, u32 pbs_lock_val,
284 u32 *skew_array, u8 *unlock_pup_dq_array,
287 /* bit array failed dq per pup for current compare */
288 u32 pbs_write_pup[DQ_NUM] = { 0 };
289 u32 update_pup; /* pup as HW convention */
290 u32 max_pup; /* maximal pup index */
294 u32 sdram_offset, pup_groups, tmp_pup;
299 switch (dram_info->ddr_width) {
300 #if defined(MV88F672X)
302 pattern_ptr = (u32 *)&pbs_pattern[pbs_pattern_idx];
306 pattern_ptr = (u32 *)&pbs_pattern_32b[pbs_pattern_idx];
308 #if defined(MV88F78X60)
310 pattern_ptr = (u32 *)&pbs_pattern_64b[pbs_pattern_idx];
317 max_pup = dram_info->num_of_std_pups;
319 sdram_offset = SDRAM_PBS_I_OFFS + pbs_pattern_idx * SDRAM_PBS_NEXT_OFFS;
321 if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
326 ddr3_reset_phy_read_fifo();
328 /* Check if need to write to sdram before read */
330 ddr3_dram_sram_burst((u32)pattern_ptr, sdram_offset,
334 ddr3_dram_sram_read(sdram_offset, (u32)sdram_data, LEN_PBS_PATTERN);
336 /* Compare read result to write */
337 for (ui = 0; ui < LEN_PBS_PATTERN; ui++) {
338 if ((sdram_data[ui]) != (pattern_ptr[ui])) {
340 /* error in low pup group */
341 for (pup = 0; pup < PUP_NUM_32BIT; pup++) {
342 val = CMP_BYTE_SHIFT * pup;
343 var1 = ((sdram_data[ui] >> val) &
345 var2 = ((pattern_ptr[ui] >> val) &
349 if (dram_info->ddr_width > 16) {
350 tmp_pup = (pup + PUP_NUM_32BIT *
353 tmp_pup = (pup % PUP_NUM_16BIT);
356 update_pup = (1 << tmp_pup);
357 if (ecc && (update_pup != 0x1))
361 * Pup is failed - Go over all DQs and
364 for (dq = 0; dq < DQ_NUM; dq++) {
365 val = tmp_pup * (1 - ecc) +
367 if (((var1 >> dq) & 0x1) !=
368 ((var2 >> dq) & 0x1)) {
369 if (pbs_locked_dq[val][dq] == 1 &&
370 pbs_locked_value[val][dq] != pbs_curr_val)
383 * unlock_pup_dq_array
385 unlock_pup_dq_array[dq] &=
393 skew_array[tmp_pup * DQ_NUM + dq] =
402 pup_addr = (is_tx == 1) ? PUP_PBS_TX : PUP_PBS_RX;
404 /* Set last failed bits PBS to min / max pbs value */
405 for (dq = 0; dq < DQ_NUM; dq++) {
406 for (pup = 0; pup < max_pup; pup++) {
407 if (pbs_write_pup[dq] & (1 << pup)) {
408 val = pup * (1 - ecc) + ecc * ECC_PUP;
409 if (pbs_locked_dq[val][dq] == 1 &&
410 pbs_locked_value[val][dq] != pbs_curr_val)
413 /* Mark the dq as locked */
414 pbs_locked_dq[val][dq] = 1;
415 pbs_locked_value[val][dq] = pbs_curr_val;
416 ddr3_write_pup_reg(pup_addr +
417 pbs_dq_mapping[val][dq],
418 CS0, val, 0, pbs_lock_val);
428 * Name: ddr3_sdram_direct_compare
429 * Desc: Execute compare per PUP without DMA (no burst mode)
430 * Args: unlock_pup Bit array of the unlock pups
431 * new_locked_pup Output bit array of the pups with failed compare
432 * pattern Pattern to compare
433 * pattern_len Length of pattern (in bytes)
434 * sdram_offset offset address to the SDRAM
435 * write write to the SDRAM before read
436 * mask compare pattern with mask;
437 * auiMaskPatter Mask to compare pattern
440 * Returns: MV_OK if success, other error code if fail.
442 int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
443 u32 *new_locked_pup, u32 *pattern,
444 u32 pattern_len, u32 sdram_offset,
445 int write, int mask, u32 *mask_pattern)
447 u32 uj, uk, pup_groups;
448 u32 *sdram_addr; /* used to read from SDRAM */
450 sdram_addr = (u32 *)sdram_offset;
452 if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
457 /* Check if need to write before read */
459 for (uk = 0; uk < pattern_len; uk++) {
460 *sdram_addr = pattern[uk];
465 sdram_addr = (u32 *)sdram_offset;
467 for (uk = 0; uk < pattern_len; uk++) {
468 sdram_data[uk] = *sdram_addr;
472 /* Compare read result to write */
473 for (uj = 0; uj < pattern_len; uj++) {
474 if (dram_info->ddr_width > 16) {
475 compare_pattern_v1(uj, new_locked_pup, pattern,
478 compare_pattern_v2(uj, new_locked_pup, pattern);
486 * Name: ddr3_dram_sram_burst
487 * Desc: Read from the SDRAM in burst of 64 bytes
490 * Notes: Using the XOR mechanism
491 * Returns: MV_OK if success, other error code if fail.
493 int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len)
495 u32 chan, byte_count, cs_num, byte;
496 struct xor_channel_t channel;
499 byte_count = len * 4;
501 /* Wait for previous transfer completion */
502 while (mv_xor_state_get(chan) != MV_IDLE)
505 /* Build the channel descriptor */
506 channel.desc = &dma_desc;
508 /* Enable Address Override and set correct src and dst */
509 if (src < SRAM_BASE) {
510 /* src is DRAM CS, dst is SRAM */
511 cs_num = (src / (1 + SDRAM_CS_SIZE));
512 reg_write(XOR_ADDR_OVRD_REG(0, 0),
513 ((cs_num << 1) | (1 << 0)));
514 channel.desc->src_addr0 = (src % (1 + SDRAM_CS_SIZE));
515 channel.desc->dst_addr = dst;
517 /* src is SRAM, dst is DRAM CS */
518 cs_num = (dst / (1 + SDRAM_CS_SIZE));
519 reg_write(XOR_ADDR_OVRD_REG(0, 0),
520 ((cs_num << 25) | (1 << 24)));
521 channel.desc->src_addr0 = (src);
522 channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
523 channel.desc->src_addr0 = src;
524 channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
527 channel.desc->src_addr1 = 0;
528 channel.desc->byte_cnt = byte_count;
529 channel.desc->next_desc_ptr = 0;
530 channel.desc->status = 1 << 31;
531 channel.desc->desc_cmd = 0x0;
532 channel.desc_phys_addr = (unsigned long)&dma_desc;
534 ddr3_flush_l1_line((u32)&dma_desc);
536 /* Issue the transfer */
537 if (mv_xor_transfer(chan, MV_DMA, channel.desc_phys_addr) != MV_OK)
540 /* Wait for completion */
541 xor_waiton_eng(chan);
543 if (dst > SRAM_BASE) {
544 for (byte = 0; byte < byte_count; byte += 0x20)
545 cache_inv(dst + byte);
552 * Name: ddr3_flush_l1_line
556 * Returns: MV_OK if success, other error code if fail.
558 static void ddr3_flush_l1_line(u32 line)
562 #if defined(MV88F672X)
565 reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR) &
566 (1 << REG_SAMPLE_RESET_CPU_ARCH_OFFS);
568 reg = ~reg & (1 << REG_SAMPLE_RESET_CPU_ARCH_OFFS);
575 flush_l1_v7(line + CACHE_LINE_SIZE);
579 flush_l1_v6(line + CACHE_LINE_SIZE);
583 int ddr3_dram_sram_read(u32 src, u32 dst, u32 len)
586 u32 *dst_ptr, *src_ptr;
588 dst_ptr = (u32 *)dst;
589 src_ptr = (u32 *)src;
591 for (ui = 0; ui < len; ui++) {
600 int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
601 u32 *new_locked_pup, u32 *pattern,
602 u32 pattern_len, u32 sdram_offset, int write,
603 int mask, u32 *mask_pattern,
608 if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
613 ddr3_reset_phy_read_fifo();
615 /* Check if need to write to sdram before read */
617 ddr3_dram_sram_burst((u32)pattern, sdram_offset, pattern_len);
619 ddr3_dram_sram_burst(sdram_offset, (u32)sdram_data, pattern_len);
621 /* Compare read result to write */
622 for (uj = 0; uj < pattern_len; uj++) {
623 if (special_compare && special_compare_pattern(uj))
626 if (dram_info->ddr_width > 16) {
627 compare_pattern_v1(uj, new_locked_pup, pattern,
630 compare_pattern_v2(uj, new_locked_pup, pattern);
637 void ddr3_reset_phy_read_fifo(void)
641 /* reset read FIFO */
642 reg = reg_read(REG_DRAM_TRAINING_ADDR);
643 /* Start Auto Read Leveling procedure */
644 reg |= (1 << REG_DRAM_TRAINING_RL_OFFS);
646 /* 0x15B0 - Training Register */
647 reg_write(REG_DRAM_TRAINING_ADDR, reg);
649 reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
650 reg |= ((1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS) +
651 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS));
653 /* [0] = 1 - Enable SW override, [4] = 1 - FIFO reset */
654 /* 0x15B8 - Training SW 2 Register */
655 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
658 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) &
659 (1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS);
660 } while (reg); /* Wait for '0' */
662 reg = reg_read(REG_DRAM_TRAINING_ADDR);
664 /* Clear Auto Read Leveling procedure */
665 reg &= ~(1 << REG_DRAM_TRAINING_RL_OFFS);
667 /* 0x15B0 - Training Register */
668 reg_write(REG_DRAM_TRAINING_ADDR, reg);