drivers/dma/amba-pl08x.c

   1 /*
   2  * Copyright (c) 2006 ARM Ltd.
   3  * Copyright (c) 2010 ST-Ericsson SA
   4  *
   5  * Author: Peter Pearse <peter.pearse@arm.com>
   6  * Author: Linus Walleij <linus.walleij@stericsson.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the Free
  10  * Software Foundation; either version 2 of the License, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program; if not, write to the Free Software Foundation, Inc., 59
  20  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  21  *
  22  * The full GNU General Public License is in this distribution in the
  23  * file called COPYING.
  24  *
  25  * Documentation: ARM DDI 0196G == PL080
  26  * Documentation: ARM DDI 0218E == PL081
  27  *
  28  * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
  29  * any channel.
  30  *
  31  * The PL080 has 8 channels available for simultaneous use, and the PL081
  32  * has only two channels. So on these DMA controllers the number of channels
  33  * and the number of incoming DMA signals are two totally different things.
  34  * It is usually not possible to theoretically handle all physical signals,
  35  * so a multiplexing scheme with possible denial of use is necessary.
  36  *
  37  * The PL080 has a dual bus master, PL081 has a single master.
  38  *
  39  * Memory to peripheral transfer may be visualized as
  40  *      Get data from memory to DMAC
  41  *      Until no data left
  42  *              On burst request from peripheral
  43  *                      Destination burst from DMAC to peripheral
  44  *                      Clear burst request
  45  *      Raise terminal count interrupt
  46  *
  47  * For peripherals with a FIFO:
  48  * Source      burst size == half the depth of the peripheral FIFO
  49  * Destination burst size == the depth of the peripheral FIFO
  50  *
  51  * (Bursts are irrelevant for mem to mem transfers - there are no burst
  52  * signals, the DMA controller will simply facilitate its AHB master.)
  53  *
  54  * ASSUMES default (little) endianness for DMA transfers
  55  *
  56  * The PL08x has two flow control settings:
  57  *  - DMAC flow control: the transfer size defines the number of transfers
  58  *    which occur for the current LLI entry, and the DMAC raises TC at the
  59  *    end of every LLI entry.  Observed behaviour shows the DMAC listening
  60  *    to both the BREQ and SREQ signals (contrary to documented),
  61  *    transferring data if either is active.  The LBREQ and LSREQ signals
  62  *    are ignored.
  63  *
  64  *  - Peripheral flow control: the transfer size is ignored (and should be
  65  *    zero).  The data is transferred from the current LLI entry, until
  66  *    after the final transfer signalled by LBREQ or LSREQ.  The DMAC
  67  *    will then move to the next LLI entry.
  68  *
  69  * Only the former works sanely with scatter lists, so we only implement
  70  * the DMAC flow control method.  However, peripherals which use the LBREQ
  71  * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
  72  * these hardware restrictions prevents them from using scatter DMA.
  73  *
  74  * Global TODO:
  75  * - Break out common code from arch/arm/mach-s3c64xx and share
  76  */
  77 #include <linux/device.h>
  78 #include <linux/init.h>
  79 #include <linux/module.h>
  80 #include <linux/interrupt.h>
  81 #include <linux/slab.h>
  82 #include <linux/dmapool.h>
  83 #include <linux/dmaengine.h>
  84 #include <linux/amba/bus.h>
  85 #include <linux/amba/pl08x.h>
  86 #include <linux/debugfs.h>
  87 #include <linux/seq_file.h>
  88
  89 #include <asm/hardware/pl080.h>
  90
  91 #define DRIVER_NAME     "pl08xdmac"
  92
  93 /**
  94  * struct vendor_data - vendor-specific config parameters
  95  * for PL08x derivatives
  96  * @channels: the number of channels available in this variant
  97  * @dualmaster: whether this version supports dual AHB masters
  98  * or not.
  99  */
 100 struct vendor_data {
 101         u8 channels;
 102         bool dualmaster;
 103 };
 104
 105 /*
 106  * PL08X private data structures
 107  * An LLI struct - see PL08x TRM.  Note that next uses bit[0] as a bus bit,
 108  * start & end do not - their bus bit info is in cctl.
 109  */
 110 struct pl08x_lli {
 111         dma_addr_t src;
 112         dma_addr_t dst;
 113         dma_addr_t next;
 114         u32 cctl;
 115 };
 116
 117 /**
 118  * struct pl08x_driver_data - the local state holder for the PL08x
 119  * @slave: slave engine for this instance
 120  * @memcpy: memcpy engine for this instance
 121  * @base: virtual memory base (remapped) for the PL08x
 122  * @adev: the corresponding AMBA (PrimeCell) bus entry
 123  * @vd: vendor data for this PL08x variant
 124  * @pd: platform data passed in from the platform/machine
 125  * @phy_chans: array of data for the physical channels
 126  * @pool: a pool for the LLI descriptors
 127  * @pool_ctr: counter of LLIs in the pool
 128  * @lock: a spinlock for this struct
 129  */
 130 struct pl08x_driver_data {
 131         struct dma_device slave;
 132         struct dma_device memcpy;
 133         void __iomem *base;
 134         struct amba_device *adev;
 135         const struct vendor_data *vd;
 136         struct pl08x_platform_data *pd;
 137         struct pl08x_phy_chan *phy_chans;
 138         struct dma_pool *pool;
 139         int pool_ctr;
 140         spinlock_t lock;
 141 };
 142
 143 /*
 144  * PL08X specific defines
 145  */
 146
 147 /*
 148  * Memory boundaries: the manual for PL08x says that the controller
 149  * cannot read past a 1KiB boundary, so these defines are used to
 150  * create transfer LLIs that do not cross such boundaries.
 151  */
 152 #define PL08X_BOUNDARY_SHIFT            (10)    /* 1KB 0x400 */
 153 #define PL08X_BOUNDARY_SIZE             (1 << PL08X_BOUNDARY_SHIFT)
 154
 155 /* Minimum period between work queue runs */
 156 #define PL08X_WQ_PERIODMIN      20
 157
 158 /* Size (bytes) of each LLI buffer allocated for one transfer */
 159 # define PL08X_LLI_TSFR_SIZE    0x2000
 160
 161 /* Maximum times we call dma_pool_alloc on this pool without freeing */
 162 #define PL08X_MAX_ALLOCS        0x40
 163 #define MAX_NUM_TSFR_LLIS       (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
 164 #define PL08X_ALIGN             8
 165
 166 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
 167 {
 168         return container_of(chan, struct pl08x_dma_chan, chan);
 169 }
 170
 171 /*
 172  * Physical channel handling
 173  */
 174
 175 /* Whether a certain channel is busy or not */
 176 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
 177 {
 178         unsigned int val;
 179
 180         val = readl(ch->base + PL080_CH_CONFIG);
 181         return val & PL080_CONFIG_ACTIVE;
 182 }
 183
 184 /*
 185  * Set the initial DMA register values i.e. those for the first LLI
 186  * The next LLI pointer and the configuration interrupt bit have
 187  * been set when the LLIs were constructed
 188  */
 189 static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
 190                             struct pl08x_phy_chan *ch)
 191 {
 192         /* Wait for channel inactive */
 193         while (pl08x_phy_channel_busy(ch))
 194                 cpu_relax();
 195
 196         dev_vdbg(&pl08x->adev->dev,
 197                 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
 198                  "cctl=0x%08x, clli=0x%08x, ccfg=0x%08x\n",
 199                 ch->id,
 200                 ch->csrc,
 201                 ch->cdst,
 202                 ch->cctl,
 203                 ch->clli,
 204                 ch->ccfg);
 205
 206         writel(ch->csrc, ch->base + PL080_CH_SRC_ADDR);
 207         writel(ch->cdst, ch->base + PL080_CH_DST_ADDR);
 208         writel(ch->clli, ch->base + PL080_CH_LLI);
 209         writel(ch->cctl, ch->base + PL080_CH_CONTROL);
 210         writel(ch->ccfg, ch->base + PL080_CH_CONFIG);
 211 }
 212
 213 static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan *plchan)
 214 {
 215         struct pl08x_channel_data *cd = plchan->cd;
 216         struct pl08x_phy_chan *phychan = plchan->phychan;
 217         struct pl08x_txd *txd = plchan->at;
 218
 219         /* Copy the basic control register calculated at transfer config */
 220         phychan->csrc = txd->csrc;
 221         phychan->cdst = txd->cdst;
 222         phychan->clli = txd->clli;
 223         phychan->cctl = txd->cctl;
 224
 225         /* Assign the signal to the proper control registers */
 226         phychan->ccfg = cd->ccfg;
 227         phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
 228         phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
 229         /* If it wasn't set from AMBA, ignore it */
 230         if (txd->direction == DMA_TO_DEVICE)
 231                 /* Select signal as destination */
 232                 phychan->ccfg |=
 233                         (phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
 234         else if (txd->direction == DMA_FROM_DEVICE)
 235                 /* Select signal as source */
 236                 phychan->ccfg |=
 237                         (phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
 238         /* Always enable error interrupts */
 239         phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
 240         /* Always enable terminal interrupts */
 241         phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
 242 }
 243
 244 /*
 245  * Enable the DMA channel
 246  * Assumes all other configuration bits have been set
 247  * as desired before this code is called
 248  */
 249 static void pl08x_enable_phy_chan(struct pl08x_driver_data *pl08x,
 250                                   struct pl08x_phy_chan *ch)
 251 {
 252         u32 val;
 253
 254         /*
 255          * Do not access config register until channel shows as disabled
 256          */
 257         while (readl(pl08x->base + PL080_EN_CHAN) & (1 << ch->id))
 258                 cpu_relax();
 259
 260         /*
 261          * Do not access config register until channel shows as inactive
 262          */
 263         val = readl(ch->base + PL080_CH_CONFIG);
 264         while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
 265                 val = readl(ch->base + PL080_CH_CONFIG);
 266
 267         writel(val | PL080_CONFIG_ENABLE, ch->base + PL080_CH_CONFIG);
 268 }
 269
 270 /*
 271  * Overall DMAC remains enabled always.
 272  *
 273  * Disabling individual channels could lose data.
 274  *
 275  * Disable the peripheral DMA after disabling the DMAC
 276  * in order to allow the DMAC FIFO to drain, and
 277  * hence allow the channel to show inactive
 278  *
 279  */
 280 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
 281 {
 282         u32 val;
 283
 284         /* Set the HALT bit and wait for the FIFO to drain */
 285         val = readl(ch->base + PL080_CH_CONFIG);
 286         val |= PL080_CONFIG_HALT;
 287         writel(val, ch->base + PL080_CH_CONFIG);
 288
 289         /* Wait for channel inactive */
 290         while (pl08x_phy_channel_busy(ch))
 291                 cpu_relax();
 292 }
 293
 294 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
 295 {
 296         u32 val;
 297
 298         /* Clear the HALT bit */
 299         val = readl(ch->base + PL080_CH_CONFIG);
 300         val &= ~PL080_CONFIG_HALT;
 301         writel(val, ch->base + PL080_CH_CONFIG);
 302 }
 303
 304
 305 /* Stops the channel */
 306 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
 307 {
 308         u32 val;
 309
 310         pl08x_pause_phy_chan(ch);
 311
 312         /* Disable channel */
 313         val = readl(ch->base + PL080_CH_CONFIG);
 314         val &= ~PL080_CONFIG_ENABLE;
 315         val &= ~PL080_CONFIG_ERR_IRQ_MASK;
 316         val &= ~PL080_CONFIG_TC_IRQ_MASK;
 317         writel(val, ch->base + PL080_CH_CONFIG);
 318 }
 319
 320 static inline u32 get_bytes_in_cctl(u32 cctl)
 321 {
 322         /* The source width defines the number of bytes */
 323         u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
 324
 325         switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 326         case PL080_WIDTH_8BIT:
 327                 break;
 328         case PL080_WIDTH_16BIT:
 329                 bytes *= 2;
 330                 break;
 331         case PL080_WIDTH_32BIT:
 332                 bytes *= 4;
 333                 break;
 334         }
 335         return bytes;
 336 }
 337
 338 /* The channel should be paused when calling this */
 339 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 340 {
 341         struct pl08x_phy_chan *ch;
 342         struct pl08x_txd *txdi = NULL;
 343         struct pl08x_txd *txd;
 344         unsigned long flags;
 345         u32 bytes = 0;
 346
 347         spin_lock_irqsave(&plchan->lock, flags);
 348
 349         ch = plchan->phychan;
 350         txd = plchan->at;
 351
 352         /*
 353          * Next follow the LLIs to get the number of pending bytes in the
 354          * currently active transaction.
 355          */
 356         if (ch && txd) {
 357                 struct pl08x_lli *llis_va = txd->llis_va;
 358                 struct pl08x_lli *llis_bus = (struct pl08x_lli *) txd->llis_bus;
 359                 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
 360
 361                 /* First get the bytes in the current active LLI */
 362                 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
 363
 364                 if (clli) {
 365                         int i = 0;
 366
 367                         /* Forward to the LLI pointed to by clli */
 368                         while ((clli != (u32) &(llis_bus[i])) &&
 369                                (i < MAX_NUM_TSFR_LLIS))
 370                                 i++;
 371
 372                         while (clli) {
 373                                 bytes += get_bytes_in_cctl(llis_va[i].cctl);
 374                                 /*
 375                                  * A LLI pointer of 0 terminates the LLI list
 376                                  */
 377                                 clli = llis_va[i].next;
 378                                 i++;
 379                         }
 380                 }
 381         }
 382
 383         /* Sum up all queued transactions */
 384         if (!list_empty(&plchan->desc_list)) {
 385                 list_for_each_entry(txdi, &plchan->desc_list, node) {
 386                         bytes += txdi->len;
 387                 }
 388
 389         }
 390
 391         spin_unlock_irqrestore(&plchan->lock, flags);
 392
 393         return bytes;
 394 }
 395
 396 /*
 397  * Allocate a physical channel for a virtual channel
 398  */
 399 static struct pl08x_phy_chan *
 400 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
 401                       struct pl08x_dma_chan *virt_chan)
 402 {
 403         struct pl08x_phy_chan *ch = NULL;
 404         unsigned long flags;
 405         int i;
 406
 407         /*
 408          * Try to locate a physical channel to be used for
 409          * this transfer. If all are taken return NULL and
 410          * the requester will have to cope by using some fallback
 411          * PIO mode or retrying later.
 412          */
 413         for (i = 0; i < pl08x->vd->channels; i++) {
 414                 ch = &pl08x->phy_chans[i];
 415
 416                 spin_lock_irqsave(&ch->lock, flags);
 417
 418                 if (!ch->serving) {
 419                         ch->serving = virt_chan;
 420                         ch->signal = -1;
 421                         spin_unlock_irqrestore(&ch->lock, flags);
 422                         break;
 423                 }
 424
 425                 spin_unlock_irqrestore(&ch->lock, flags);
 426         }
 427
 428         if (i == pl08x->vd->channels) {
 429                 /* No physical channel available, cope with it */
 430                 return NULL;
 431         }
 432
 433         return ch;
 434 }
 435
 436 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
 437                                          struct pl08x_phy_chan *ch)
 438 {
 439         unsigned long flags;
 440
 441         /* Stop the channel and clear its interrupts */
 442         pl08x_stop_phy_chan(ch);
 443         writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
 444         writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
 445
 446         /* Mark it as free */
 447         spin_lock_irqsave(&ch->lock, flags);
 448         ch->serving = NULL;
 449         spin_unlock_irqrestore(&ch->lock, flags);
 450 }
 451
 452 /*
 453  * LLI handling
 454  */
 455
 456 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
 457 {
 458         switch (coded) {
 459         case PL080_WIDTH_8BIT:
 460                 return 1;
 461         case PL080_WIDTH_16BIT:
 462                 return 2;
 463         case PL080_WIDTH_32BIT:
 464                 return 4;
 465         default:
 466                 break;
 467         }
 468         BUG();
 469         return 0;
 470 }
 471
 472 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
 473                                   u32 tsize)
 474 {
 475         u32 retbits = cctl;
 476
 477         /* Remove all src, dst and transfer size bits */
 478         retbits &= ~PL080_CONTROL_DWIDTH_MASK;
 479         retbits &= ~PL080_CONTROL_SWIDTH_MASK;
 480         retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
 481
 482         /* Then set the bits according to the parameters */
 483         switch (srcwidth) {
 484         case 1:
 485                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
 486                 break;
 487         case 2:
 488                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
 489                 break;
 490         case 4:
 491                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
 492                 break;
 493         default:
 494                 BUG();
 495                 break;
 496         }
 497
 498         switch (dstwidth) {
 499         case 1:
 500                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
 501                 break;
 502         case 2:
 503                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
 504                 break;
 505         case 4:
 506                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
 507                 break;
 508         default:
 509                 BUG();
 510                 break;
 511         }
 512
 513         retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
 514         return retbits;
 515 }
 516
 517 /*
 518  * Autoselect a master bus to use for the transfer
 519  * this prefers the destination bus if both available
 520  * if fixed address on one bus the other will be chosen
 521  */
 522 static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
 523         struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
 524         struct pl08x_bus_data **sbus, u32 cctl)
 525 {
 526         if (!(cctl & PL080_CONTROL_DST_INCR)) {
 527                 *mbus = src_bus;
 528                 *sbus = dst_bus;
 529         } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
 530                 *mbus = dst_bus;
 531                 *sbus = src_bus;
 532         } else {
 533                 if (dst_bus->buswidth == 4) {
 534                         *mbus = dst_bus;
 535                         *sbus = src_bus;
 536                 } else if (src_bus->buswidth == 4) {
 537                         *mbus = src_bus;
 538                         *sbus = dst_bus;
 539                 } else if (dst_bus->buswidth == 2) {
 540                         *mbus = dst_bus;
 541                         *sbus = src_bus;
 542                 } else if (src_bus->buswidth == 2) {
 543                         *mbus = src_bus;
 544                         *sbus = dst_bus;
 545                 } else {
 546                         /* src_bus->buswidth == 1 */
 547                         *mbus = dst_bus;
 548                         *sbus = src_bus;
 549                 }
 550         }
 551 }
 552
 553 /*
 554  * Fills in one LLI for a certain transfer descriptor
 555  * and advance the counter
 556  */
 557 static int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
 558                             struct pl08x_txd *txd, int num_llis, int len,
 559                             u32 cctl, u32 *remainder)
 560 {
 561         struct pl08x_lli *llis_va = txd->llis_va;
 562         struct pl08x_lli *llis_bus = (struct pl08x_lli *) txd->llis_bus;
 563
 564         BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
 565
 566         llis_va[num_llis].cctl          = cctl;
 567         llis_va[num_llis].src           = txd->srcbus.addr;
 568         llis_va[num_llis].dst           = txd->dstbus.addr;
 569
 570         /*
 571          * On versions with dual masters, you can optionally AND on
 572          * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
 573          * in new LLIs with that controller, but we always try to
 574          * choose AHB1 to point into memory. The idea is to have AHB2
 575          * fixed on the peripheral and AHB1 messing around in the
 576          * memory. So we don't manipulate this bit currently.
 577          */
 578
 579         llis_va[num_llis].next =
 580                 (dma_addr_t)((u32) &(llis_bus[num_llis + 1]));
 581
 582         if (cctl & PL080_CONTROL_SRC_INCR)
 583                 txd->srcbus.addr += len;
 584         if (cctl & PL080_CONTROL_DST_INCR)
 585                 txd->dstbus.addr += len;
 586
 587         *remainder -= len;
 588
 589         return num_llis + 1;
 590 }
 591
 592 /*
 593  * Return number of bytes to fill to boundary, or len
 594  */
 595 static inline u32 pl08x_pre_boundary(u32 addr, u32 len)
 596 {
 597         u32 boundary;
 598
 599         boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
 600                 << PL08X_BOUNDARY_SHIFT;
 601
 602         if (boundary < addr + len)
 603                 return boundary - addr;
 604         else
 605                 return len;
 606 }
 607
 608 /*
 609  * This fills in the table of LLIs for the transfer descriptor
 610  * Note that we assume we never have to change the burst sizes
 611  * Return 0 for error
 612  */
 613 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 614                               struct pl08x_txd *txd)
 615 {
 616         struct pl08x_channel_data *cd = txd->cd;
 617         struct pl08x_bus_data *mbus, *sbus;
 618         u32 remainder;
 619         int num_llis = 0;
 620         u32 cctl;
 621         int max_bytes_per_lli;
 622         int total_bytes = 0;
 623         struct pl08x_lli *llis_va;
 624         struct pl08x_lli *llis_bus;
 625
 626         txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
 627                                       &txd->llis_bus);
 628         if (!txd->llis_va) {
 629                 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
 630                 return 0;
 631         }
 632
 633         pl08x->pool_ctr++;
 634
 635         /*
 636          * Initialize bus values for this transfer
 637          * from the passed optimal values
 638          */
 639         if (!cd) {
 640                 dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
 641                 return 0;
 642         }
 643
 644         /* Get the default CCTL from the platform data */
 645         cctl = cd->cctl;
 646
 647         /*
 648          * On the PL080 we have two bus masters and we
 649          * should select one for source and one for
 650          * destination. We try to use AHB2 for the
 651          * bus which does not increment (typically the
 652          * peripheral) else we just choose something.
 653          */
 654         cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
 655         if (pl08x->vd->dualmaster) {
 656                 if (cctl & PL080_CONTROL_SRC_INCR)
 657                         /* Source increments, use AHB2 for destination */
 658                         cctl |= PL080_CONTROL_DST_AHB2;
 659                 else if (cctl & PL080_CONTROL_DST_INCR)
 660                         /* Destination increments, use AHB2 for source */
 661                         cctl |= PL080_CONTROL_SRC_AHB2;
 662                 else
 663                         /* Just pick something, source AHB1 dest AHB2 */
 664                         cctl |= PL080_CONTROL_DST_AHB2;
 665         }
 666
 667         /* Find maximum width of the source bus */
 668         txd->srcbus.maxwidth =
 669                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
 670                                        PL080_CONTROL_SWIDTH_SHIFT);
 671
 672         /* Find maximum width of the destination bus */
 673         txd->dstbus.maxwidth =
 674                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
 675                                        PL080_CONTROL_DWIDTH_SHIFT);
 676
 677         /* Set up the bus widths to the maximum */
 678         txd->srcbus.buswidth = txd->srcbus.maxwidth;
 679         txd->dstbus.buswidth = txd->dstbus.maxwidth;
 680         dev_vdbg(&pl08x->adev->dev,
 681                  "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
 682                  __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
 683
 684
 685         /*
 686          * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
 687          */
 688         max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
 689                 PL080_CONTROL_TRANSFER_SIZE_MASK;
 690         dev_vdbg(&pl08x->adev->dev,
 691                  "%s max bytes per lli = %d\n",
 692                  __func__, max_bytes_per_lli);
 693
 694         /* We need to count this down to zero */
 695         remainder = txd->len;
 696         dev_vdbg(&pl08x->adev->dev,
 697                  "%s remainder = %d\n",
 698                  __func__, remainder);
 699
 700         /*
 701          * Choose bus to align to
 702          * - prefers destination bus if both available
 703          * - if fixed address on one bus chooses other
 704          * - modifies cctl to choose an appropriate master
 705          */
 706         pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
 707                                 &mbus, &sbus, cctl);
 708
 709
 710         /*
 711          * The lowest bit of the LLI register
 712          * is also used to indicate which master to
 713          * use for reading the LLIs.
 714          */
 715
 716         if (txd->len < mbus->buswidth) {
 717                 /*
 718                  * Less than a bus width available
 719                  * - send as single bytes
 720                  */
 721                 while (remainder) {
 722                         dev_vdbg(&pl08x->adev->dev,
 723                                  "%s single byte LLIs for a transfer of "
 724                                  "less than a bus width (remain 0x%08x)\n",
 725                                  __func__, remainder);
 726                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 727                         num_llis =
 728                                 pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
 729                                         cctl, &remainder);
 730                         total_bytes++;
 731                 }
 732         } else {
 733                 /*
 734                  *  Make one byte LLIs until master bus is aligned
 735                  *  - slave will then be aligned also
 736                  */
 737                 while ((mbus->addr) % (mbus->buswidth)) {
 738                         dev_vdbg(&pl08x->adev->dev,
 739                                 "%s adjustment lli for less than bus width "
 740                                  "(remain 0x%08x)\n",
 741                                  __func__, remainder);
 742                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 743                         num_llis = pl08x_fill_lli_for_desc
 744                                 (pl08x, txd, num_llis, 1, cctl, &remainder);
 745                         total_bytes++;
 746                 }
 747
 748                 /*
 749                  *  Master now aligned
 750                  * - if slave is not then we must set its width down
 751                  */
 752                 if (sbus->addr % sbus->buswidth) {
 753                         dev_dbg(&pl08x->adev->dev,
 754                                 "%s set down bus width to one byte\n",
 755                                  __func__);
 756
 757                         sbus->buswidth = 1;
 758                 }
 759
 760                 /*
 761                  * Make largest possible LLIs until less than one bus
 762                  * width left
 763                  */
 764                 while (remainder > (mbus->buswidth - 1)) {
 765                         int lli_len, target_len;
 766                         int tsize;
 767                         int odd_bytes;
 768
 769                         /*
 770                          * If enough left try to send max possible,
 771                          * otherwise try to send the remainder
 772                          */
 773                         target_len = remainder;
 774                         if (remainder > max_bytes_per_lli)
 775                                 target_len = max_bytes_per_lli;
 776
 777                         /*
 778                          * Set bus lengths for incrementing buses
 779                          * to number of bytes which fill to next memory
 780                          * boundary
 781                          */
 782                         if (cctl & PL080_CONTROL_SRC_INCR)
 783                                 txd->srcbus.fill_bytes =
 784                                         pl08x_pre_boundary(
 785                                                 txd->srcbus.addr,
 786                                                 remainder);
 787                         else
 788                                 txd->srcbus.fill_bytes =
 789                                         max_bytes_per_lli;
 790
 791                         if (cctl & PL080_CONTROL_DST_INCR)
 792                                 txd->dstbus.fill_bytes =
 793                                         pl08x_pre_boundary(
 794                                                 txd->dstbus.addr,
 795                                                 remainder);
 796                         else
 797                                 txd->dstbus.fill_bytes =
 798                                                 max_bytes_per_lli;
 799
 800                         /*
 801                          *  Find the nearest
 802                          */
 803                         lli_len = min(txd->srcbus.fill_bytes,
 804                                 txd->dstbus.fill_bytes);
 805
 806                         BUG_ON(lli_len > remainder);
 807
 808                         if (lli_len <= 0) {
 809                                 dev_err(&pl08x->adev->dev,
 810                                         "%s lli_len is %d, <= 0\n",
 811                                                 __func__, lli_len);
 812                                 return 0;
 813                         }
 814
 815                         if (lli_len == target_len) {
 816                                 /*
 817                                  * Can send what we wanted
 818                                  */
 819                                 /*
 820                                  *  Maintain alignment
 821                                  */
 822                                 lli_len = (lli_len/mbus->buswidth) *
 823                                                         mbus->buswidth;
 824                                 odd_bytes = 0;
 825                         } else {
 826                                 /*
 827                                  * So now we know how many bytes to transfer
 828                                  * to get to the nearest boundary
 829                                  * The next LLI will past the boundary
 830                                  * - however we may be working to a boundary
 831                                  *   on the slave bus
 832                                  *   We need to ensure the master stays aligned
 833                                  */
 834                                 odd_bytes = lli_len % mbus->buswidth;
 835                                 /*
 836                                  * - and that we are working in multiples
 837                                  *   of the bus widths
 838                                  */
 839                                 lli_len -= odd_bytes;
 840
 841                         }
 842
 843                         if (lli_len) {
 844                                 /*
 845                                  * Check against minimum bus alignment:
 846                                  * Calculate actual transfer size in relation
 847                                  * to bus width an get a maximum remainder of
 848                                  * the smallest bus width - 1
 849                                  */
 850                                 /* FIXME: use round_down()? */
 851                                 tsize = lli_len / min(mbus->buswidth,
 852                                                       sbus->buswidth);
 853                                 lli_len = tsize * min(mbus->buswidth,
 854                                                       sbus->buswidth);
 855
 856                                 if (target_len != lli_len) {
 857                                         dev_vdbg(&pl08x->adev->dev,
 858                                         "%s can't send what we want. Desired 0x%08x, lli of 0x%08x bytes in txd of 0x%08x\n",
 859                                         __func__, target_len, lli_len, txd->len);
 860                                 }
 861
 862                                 cctl = pl08x_cctl_bits(cctl,
 863                                                        txd->srcbus.buswidth,
 864                                                        txd->dstbus.buswidth,
 865                                                        tsize);
 866
 867                                 dev_vdbg(&pl08x->adev->dev,
 868                                         "%s fill lli with single lli chunk of size 0x%08x (remainder 0x%08x)\n",
 869                                         __func__, lli_len, remainder);
 870                                 num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
 871                                                 num_llis, lli_len, cctl,
 872                                                 &remainder);
 873                                 total_bytes += lli_len;
 874                         }
 875
 876
 877                         if (odd_bytes) {
 878                                 /*
 879                                  * Creep past the boundary,
 880                                  * maintaining master alignment
 881                                  */
 882                                 int j;
 883                                 for (j = 0; (j < mbus->buswidth)
 884                                                 && (remainder); j++) {
 885                                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 886                                         dev_vdbg(&pl08x->adev->dev,
 887                                                 "%s align with boundary, single byte (remain 0x%08x)\n",
 888                                                 __func__, remainder);
 889                                         num_llis =
 890                                                 pl08x_fill_lli_for_desc(pl08x,
 891                                                         txd, num_llis, 1,
 892                                                         cctl, &remainder);
 893                                         total_bytes++;
 894                                 }
 895                         }
 896                 }
 897
 898                 /*
 899                  * Send any odd bytes
 900                  */
 901                 if (remainder < 0) {
 902                         dev_err(&pl08x->adev->dev, "%s remainder not fitted 0x%08x bytes\n",
 903                                         __func__, remainder);
 904                         return 0;
 905                 }
 906
 907                 while (remainder) {
 908                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 909                         dev_vdbg(&pl08x->adev->dev,
 910                                 "%s align with boundary, single odd byte (remain %d)\n",
 911                                 __func__, remainder);
 912                         num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
 913                                         1, cctl, &remainder);
 914                         total_bytes++;
 915                 }
 916         }
 917         if (total_bytes != txd->len) {
 918                 dev_err(&pl08x->adev->dev,
 919                         "%s size of encoded lli:s don't match total txd, transferred 0x%08x from size 0x%08x\n",
 920                         __func__, total_bytes, txd->len);
 921                 return 0;
 922         }
 923
 924         if (num_llis >= MAX_NUM_TSFR_LLIS) {
 925                 dev_err(&pl08x->adev->dev,
 926                         "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
 927                         __func__, (u32) MAX_NUM_TSFR_LLIS);
 928                 return 0;
 929         }
 930
 931         llis_va = txd->llis_va;
 932         /*
 933          * The final LLI terminates the LLI.
 934          */
 935         llis_va[num_llis - 1].next = 0;
 936         /*
 937          * The final LLI element shall also fire an interrupt
 938          */
 939         llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
 940
 941         /* Now store the channel register values */
 942         txd->csrc = llis_va[0].src;
 943         txd->cdst = llis_va[0].dst;
 944         txd->clli = llis_va[0].next;
 945         txd->cctl = llis_va[0].cctl;
 946         /* ccfg will be set at physical channel allocation time */
 947
 948 #ifdef VERBOSE_DEBUG
 949         {
 950                 int i;
 951
 952                 for (i = 0; i < num_llis; i++) {
 953                         dev_vdbg(&pl08x->adev->dev,
 954                                  "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
 955                                  i,
 956                                  &llis_va[i],
 957                                  llis_va[i].src,
 958                                  llis_va[i].dst,
 959                                  llis_va[i].cctl,
 960                                  llis_va[i].next
 961                                 );
 962                 }
 963         }
 964 #endif
 965
 966         return num_llis;
 967 }
 968
 969 /* You should call this with the struct pl08x lock held */
 970 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
 971                            struct pl08x_txd *txd)
 972 {
 973         /* Free the LLI */
 974         dma_pool_free(pl08x->pool, txd->llis_va,
 975                       txd->llis_bus);
 976
 977         pl08x->pool_ctr--;
 978
 979         kfree(txd);
 980 }
 981
 982 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
 983                                 struct pl08x_dma_chan *plchan)
 984 {
 985         struct pl08x_txd *txdi = NULL;
 986         struct pl08x_txd *next;
 987
 988         if (!list_empty(&plchan->desc_list)) {
 989                 list_for_each_entry_safe(txdi,
 990                                          next, &plchan->desc_list, node) {
 991                         list_del(&txdi->node);
 992                         pl08x_free_txd(pl08x, txdi);
 993                 }
 994
 995         }
 996 }
 997
 998 /*
 999  * The DMA ENGINE API
1000  */
1001 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
1002 {
1003         return 0;
1004 }
1005
1006 static void pl08x_free_chan_resources(struct dma_chan *chan)
1007 {
1008 }
1009
1010 /*
1011  * This should be called with the channel plchan->lock held
1012  */
1013 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
1014                             struct pl08x_txd *txd)
1015 {
1016         struct pl08x_driver_data *pl08x = plchan->host;
1017         struct pl08x_phy_chan *ch;
1018         int ret;
1019
1020         /* Check if we already have a channel */
1021         if (plchan->phychan)
1022                 return 0;
1023
1024         ch = pl08x_get_phy_channel(pl08x, plchan);
1025         if (!ch) {
1026                 /* No physical channel available, cope with it */
1027                 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
1028                 return -EBUSY;
1029         }
1030
1031         /*
1032          * OK we have a physical channel: for memcpy() this is all we
1033          * need, but for slaves the physical signals may be muxed!
1034          * Can the platform allow us to use this channel?
1035          */
1036         if (plchan->slave &&
1037             ch->signal < 0 &&
1038             pl08x->pd->get_signal) {
1039                 ret = pl08x->pd->get_signal(plchan);
1040                 if (ret < 0) {
1041                         dev_dbg(&pl08x->adev->dev,
1042                                 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1043                                 ch->id, plchan->name);
1044                         /* Release physical channel & return */
1045                         pl08x_put_phy_channel(pl08x, ch);
1046                         return -EBUSY;
1047                 }
1048                 ch->signal = ret;
1049         }
1050
1051         dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
1052                  ch->id,
1053                  ch->signal,
1054                  plchan->name);
1055
1056         plchan->phychan = ch;
1057
1058         return 0;
1059 }
1060
1061 static void release_phy_channel(struct pl08x_dma_chan *plchan)
1062 {
1063         struct pl08x_driver_data *pl08x = plchan->host;
1064
1065         if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
1066                 pl08x->pd->put_signal(plchan);
1067                 plchan->phychan->signal = -1;
1068         }
1069         pl08x_put_phy_channel(pl08x, plchan->phychan);
1070         plchan->phychan = NULL;
1071 }
1072
1073 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
1074 {
1075         struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
1076
1077         plchan->chan.cookie += 1;
1078         if (plchan->chan.cookie < 0)
1079                 plchan->chan.cookie = 1;
1080         tx->cookie = plchan->chan.cookie;
1081         /* This unlock follows the lock in the prep() function */
1082         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1083
1084         return tx->cookie;
1085 }
1086
1087 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1088                 struct dma_chan *chan, unsigned long flags)
1089 {
1090         struct dma_async_tx_descriptor *retval = NULL;
1091
1092         return retval;
1093 }
1094
1095 /*
1096  * Code accessing dma_async_is_complete() in a tight loop
1097  * may give problems - could schedule where indicated.
1098  * If slaves are relying on interrupts to signal completion this
1099  * function must not be called with interrupts disabled
1100  */
1101 static enum dma_status
1102 pl08x_dma_tx_status(struct dma_chan *chan,
1103                     dma_cookie_t cookie,
1104                     struct dma_tx_state *txstate)
1105 {
1106         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1107         dma_cookie_t last_used;
1108         dma_cookie_t last_complete;
1109         enum dma_status ret;
1110         u32 bytesleft = 0;
1111
1112         last_used = plchan->chan.cookie;
1113         last_complete = plchan->lc;
1114
1115         ret = dma_async_is_complete(cookie, last_complete, last_used);
1116         if (ret == DMA_SUCCESS) {
1117                 dma_set_tx_state(txstate, last_complete, last_used, 0);
1118                 return ret;
1119         }
1120
1121         /*
1122          * schedule(); could be inserted here
1123          */
1124
1125         /*
1126          * This cookie not complete yet
1127          */
1128         last_used = plchan->chan.cookie;
1129         last_complete = plchan->lc;
1130
1131         /* Get number of bytes left in the active transactions and queue */
1132         bytesleft = pl08x_getbytes_chan(plchan);
1133
1134         dma_set_tx_state(txstate, last_complete, last_used,
1135                          bytesleft);
1136
1137         if (plchan->state == PL08X_CHAN_PAUSED)
1138                 return DMA_PAUSED;
1139
1140         /* Whether waiting or running, we're in progress */
1141         return DMA_IN_PROGRESS;
1142 }
1143
1144 /* PrimeCell DMA extension */
1145 struct burst_table {
1146         int burstwords;
1147         u32 reg;
1148 };
1149
1150 static const struct burst_table burst_sizes[] = {
1151         {
1152                 .burstwords = 256,
1153                 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1154                         (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1155         },
1156         {
1157                 .burstwords = 128,
1158                 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1159                         (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1160         },
1161         {
1162                 .burstwords = 64,
1163                 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1164                         (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1165         },
1166         {
1167                 .burstwords = 32,
1168                 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1169                         (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1170         },
1171         {
1172                 .burstwords = 16,
1173                 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1174                         (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1175         },
1176         {
1177                 .burstwords = 8,
1178                 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1179                         (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1180         },
1181         {
1182                 .burstwords = 4,
1183                 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1184                         (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1185         },
1186         {
1187                 .burstwords = 1,
1188                 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1189                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1190         },
1191 };
1192
1193 static void dma_set_runtime_config(struct dma_chan *chan,
1194                                struct dma_slave_config *config)
1195 {
1196         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1197         struct pl08x_driver_data *pl08x = plchan->host;
1198         struct pl08x_channel_data *cd = plchan->cd;
1199         enum dma_slave_buswidth addr_width;
1200         u32 maxburst;
1201         u32 cctl = 0;
1202         /* Mask out all except src and dst channel */
1203         u32 ccfg = cd->ccfg & 0x000003DEU;
1204         int i;
1205
1206         /* Transfer direction */
1207         plchan->runtime_direction = config->direction;
1208         if (config->direction == DMA_TO_DEVICE) {
1209                 plchan->runtime_addr = config->dst_addr;
1210                 cctl |= PL080_CONTROL_SRC_INCR;
1211                 ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1212                 addr_width = config->dst_addr_width;
1213                 maxburst = config->dst_maxburst;
1214         } else if (config->direction == DMA_FROM_DEVICE) {
1215                 plchan->runtime_addr = config->src_addr;
1216                 cctl |= PL080_CONTROL_DST_INCR;
1217                 ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1218                 addr_width = config->src_addr_width;
1219                 maxburst = config->src_maxburst;
1220         } else {
1221                 dev_err(&pl08x->adev->dev,
1222                         "bad runtime_config: alien transfer direction\n");
1223                 return;
1224         }
1225
1226         switch (addr_width) {
1227         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1228                 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1229                         (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1230                 break;
1231         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1232                 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1233                         (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1234                 break;
1235         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1236                 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1237                         (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1238                 break;
1239         default:
1240                 dev_err(&pl08x->adev->dev,
1241                         "bad runtime_config: alien address width\n");
1242                 return;
1243         }
1244
1245         /*
1246          * Now decide on a maxburst:
1247          * If this channel will only request single transfers, set this
1248          * down to ONE element.  Also select one element if no maxburst
1249          * is specified.
1250          */
1251         if (plchan->cd->single || maxburst == 0) {
1252                 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1253                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1254         } else {
1255                 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1256                         if (burst_sizes[i].burstwords <= maxburst)
1257                                 break;
1258                 cctl |= burst_sizes[i].reg;
1259         }
1260
1261         /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1262         cctl &= ~PL080_CONTROL_PROT_MASK;
1263         cctl |= PL080_CONTROL_PROT_SYS;
1264
1265         /* Modify the default channel data to fit PrimeCell request */
1266         cd->cctl = cctl;
1267         cd->ccfg = ccfg;
1268
1269         dev_dbg(&pl08x->adev->dev,
1270                 "configured channel %s (%s) for %s, data width %d, "
1271                 "maxburst %d words, LE, CCTL=0x%08x, CCFG=0x%08x\n",
1272                 dma_chan_name(chan), plchan->name,
1273                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1274                 addr_width,
1275                 maxburst,
1276                 cctl, ccfg);
1277 }
1278
1279 /*
1280  * Slave transactions callback to the slave device to allow
1281  * synchronization of slave DMA signals with the DMAC enable
1282  */
1283 static void pl08x_issue_pending(struct dma_chan *chan)
1284 {
1285         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1286         struct pl08x_driver_data *pl08x = plchan->host;
1287         unsigned long flags;
1288
1289         spin_lock_irqsave(&plchan->lock, flags);
1290         /* Something is already active, or we're waiting for a channel... */
1291         if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1292                 spin_unlock_irqrestore(&plchan->lock, flags);
1293                 return;
1294         }
1295
1296         /* Take the first element in the queue and execute it */
1297         if (!list_empty(&plchan->desc_list)) {
1298                 struct pl08x_txd *next;
1299
1300                 next = list_first_entry(&plchan->desc_list,
1301                                         struct pl08x_txd,
1302                                         node);
1303                 list_del(&next->node);
1304                 plchan->at = next;
1305                 plchan->state = PL08X_CHAN_RUNNING;
1306
1307                 /* Configure the physical channel for the active txd */
1308                 pl08x_config_phychan_for_txd(plchan);
1309                 pl08x_set_cregs(pl08x, plchan->phychan);
1310                 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1311         }
1312
1313         spin_unlock_irqrestore(&plchan->lock, flags);
1314 }
1315
1316 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1317                                         struct pl08x_txd *txd)
1318 {
1319         int num_llis;
1320         struct pl08x_driver_data *pl08x = plchan->host;
1321         int ret;
1322
1323         num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1324         if (!num_llis) {
1325                 kfree(txd);
1326                 return -EINVAL;
1327         }
1328
1329         spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1330
1331         list_add_tail(&txd->node, &plchan->desc_list);
1332
1333         /*
1334          * See if we already have a physical channel allocated,
1335          * else this is the time to try to get one.
1336          */
1337         ret = prep_phy_channel(plchan, txd);
1338         if (ret) {
1339                 /*
1340                  * No physical channel available, we will
1341                  * stack up the memcpy channels until there is a channel
1342                  * available to handle it whereas slave transfers may
1343                  * have been denied due to platform channel muxing restrictions
1344                  * and since there is no guarantee that this will ever be
1345                  * resolved, and since the signal must be acquired AFTER
1346                  * acquiring the physical channel, we will let them be NACK:ed
1347                  * with -EBUSY here. The drivers can alway retry the prep()
1348                  * call if they are eager on doing this using DMA.
1349                  */
1350                 if (plchan->slave) {
1351                         pl08x_free_txd_list(pl08x, plchan);
1352                         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1353                         return -EBUSY;
1354                 }
1355                 /* Do this memcpy whenever there is a channel ready */
1356                 plchan->state = PL08X_CHAN_WAITING;
1357                 plchan->waiting = txd;
1358         } else
1359                 /*
1360                  * Else we're all set, paused and ready to roll,
1361                  * status will switch to PL08X_CHAN_RUNNING when
1362                  * we call issue_pending(). If there is something
1363                  * running on the channel already we don't change
1364                  * its state.
1365                  */
1366                 if (plchan->state == PL08X_CHAN_IDLE)
1367                         plchan->state = PL08X_CHAN_PAUSED;
1368
1369         /*
1370          * Notice that we leave plchan->lock locked on purpose:
1371          * it will be unlocked in the subsequent tx_submit()
1372          * call. This is a consequence of the current API.
1373          */
1374
1375         return 0;
1376 }
1377
1378 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1379 {
1380         struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1381
1382         if (txd) {
1383                 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1384                 txd->tx.tx_submit = pl08x_tx_submit;
1385                 INIT_LIST_HEAD(&txd->node);
1386         }
1387         return txd;
1388 }
1389
1390 /*
1391  * Initialize a descriptor to be used by memcpy submit
1392  */
1393 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1394                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1395                 size_t len, unsigned long flags)
1396 {
1397         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1398         struct pl08x_driver_data *pl08x = plchan->host;
1399         struct pl08x_txd *txd;
1400         int ret;
1401
1402         txd = pl08x_get_txd(plchan);
1403         if (!txd) {
1404                 dev_err(&pl08x->adev->dev,
1405                         "%s no memory for descriptor\n", __func__);
1406                 return NULL;
1407         }
1408
1409         txd->direction = DMA_NONE;
1410         txd->srcbus.addr = src;
1411         txd->dstbus.addr = dest;
1412
1413         /* Set platform data for m2m */
1414         txd->cd = &pl08x->pd->memcpy_channel;
1415         /* Both to be incremented or the code will break */
1416         txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1417         txd->len = len;
1418
1419         ret = pl08x_prep_channel_resources(plchan, txd);
1420         if (ret)
1421                 return NULL;
1422         /*
1423          * NB: the channel lock is held at this point so tx_submit()
1424          * must be called in direct succession.
1425          */
1426
1427         return &txd->tx;
1428 }
1429
1430 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1431                 struct dma_chan *chan, struct scatterlist *sgl,
1432                 unsigned int sg_len, enum dma_data_direction direction,
1433                 unsigned long flags)
1434 {
1435         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1436         struct pl08x_driver_data *pl08x = plchan->host;
1437         struct pl08x_txd *txd;
1438         int ret;
1439
1440         /*
1441          * Current implementation ASSUMES only one sg
1442          */
1443         if (sg_len != 1) {
1444                 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1445                         __func__);
1446                 BUG();
1447         }
1448
1449         dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1450                 __func__, sgl->length, plchan->name);
1451
1452         txd = pl08x_get_txd(plchan);
1453         if (!txd) {
1454                 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1455                 return NULL;
1456         }
1457
1458         if (direction != plchan->runtime_direction)
1459                 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1460                         "the direction configured for the PrimeCell\n",
1461                         __func__);
1462
1463         /*
1464          * Set up addresses, the PrimeCell configured address
1465          * will take precedence since this may configure the
1466          * channel target address dynamically at runtime.
1467          */
1468         txd->direction = direction;
1469         if (direction == DMA_TO_DEVICE) {
1470                 txd->srcbus.addr = sgl->dma_address;
1471                 if (plchan->runtime_addr)
1472                         txd->dstbus.addr = plchan->runtime_addr;
1473                 else
1474                         txd->dstbus.addr = plchan->cd->addr;
1475         } else if (direction == DMA_FROM_DEVICE) {
1476                 if (plchan->runtime_addr)
1477                         txd->srcbus.addr = plchan->runtime_addr;
1478                 else
1479                         txd->srcbus.addr = plchan->cd->addr;
1480                 txd->dstbus.addr = sgl->dma_address;
1481         } else {
1482                 dev_err(&pl08x->adev->dev,
1483                         "%s direction unsupported\n", __func__);
1484                 return NULL;
1485         }
1486         txd->cd = plchan->cd;
1487         txd->len = sgl->length;
1488
1489         ret = pl08x_prep_channel_resources(plchan, txd);
1490         if (ret)
1491                 return NULL;
1492         /*
1493          * NB: the channel lock is held at this point so tx_submit()
1494          * must be called in direct succession.
1495          */
1496
1497         return &txd->tx;
1498 }
1499
1500 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1501                          unsigned long arg)
1502 {
1503         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1504         struct pl08x_driver_data *pl08x = plchan->host;
1505         unsigned long flags;
1506         int ret = 0;
1507
1508         /* Controls applicable to inactive channels */
1509         if (cmd == DMA_SLAVE_CONFIG) {
1510                 dma_set_runtime_config(chan,
1511                                        (struct dma_slave_config *)
1512                                        arg);
1513                 return 0;
1514         }
1515
1516         /*
1517          * Anything succeeds on channels with no physical allocation and
1518          * no queued transfers.
1519          */
1520         spin_lock_irqsave(&plchan->lock, flags);
1521         if (!plchan->phychan && !plchan->at) {
1522                 spin_unlock_irqrestore(&plchan->lock, flags);
1523                 return 0;
1524         }
1525
1526         switch (cmd) {
1527         case DMA_TERMINATE_ALL:
1528                 plchan->state = PL08X_CHAN_IDLE;
1529
1530                 if (plchan->phychan) {
1531                         pl08x_stop_phy_chan(plchan->phychan);
1532
1533                         /*
1534                          * Mark physical channel as free and free any slave
1535                          * signal
1536                          */
1537                         release_phy_channel(plchan);
1538                 }
1539                 /* Dequeue jobs and free LLIs */
1540                 if (plchan->at) {
1541                         pl08x_free_txd(pl08x, plchan->at);
1542                         plchan->at = NULL;
1543                 }
1544                 /* Dequeue jobs not yet fired as well */
1545                 pl08x_free_txd_list(pl08x, plchan);
1546                 break;
1547         case DMA_PAUSE:
1548                 pl08x_pause_phy_chan(plchan->phychan);
1549                 plchan->state = PL08X_CHAN_PAUSED;
1550                 break;
1551         case DMA_RESUME:
1552                 pl08x_resume_phy_chan(plchan->phychan);
1553                 plchan->state = PL08X_CHAN_RUNNING;
1554                 break;
1555         default:
1556                 /* Unknown command */
1557                 ret = -ENXIO;
1558                 break;
1559         }
1560
1561         spin_unlock_irqrestore(&plchan->lock, flags);
1562
1563         return ret;
1564 }
1565
1566 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1567 {
1568         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1569         char *name = chan_id;
1570
1571         /* Check that the channel is not taken! */
1572         if (!strcmp(plchan->name, name))
1573                 return true;
1574
1575         return false;
1576 }
1577
1578 /*
1579  * Just check that the device is there and active
1580  * TODO: turn this bit on/off depending on the number of
1581  * physical channels actually used, if it is zero... well
1582  * shut it off. That will save some power. Cut the clock
1583  * at the same time.
1584  */
1585 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1586 {
1587         u32 val;
1588
1589         val = readl(pl08x->base + PL080_CONFIG);
1590         val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1591         /* We implicitly clear bit 1 and that means little-endian mode */
1592         val |= PL080_CONFIG_ENABLE;
1593         writel(val, pl08x->base + PL080_CONFIG);
1594 }
1595
1596 static void pl08x_tasklet(unsigned long data)
1597 {
1598         struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1599         struct pl08x_driver_data *pl08x = plchan->host;
1600         unsigned long flags;
1601
1602         spin_lock_irqsave(&plchan->lock, flags);
1603
1604         if (plchan->at) {
1605                 dma_async_tx_callback callback =
1606                         plchan->at->tx.callback;
1607                 void *callback_param =
1608                         plchan->at->tx.callback_param;
1609
1610                 /*
1611                  * Update last completed
1612                  */
1613                 plchan->lc = plchan->at->tx.cookie;
1614
1615                 /*
1616                  * Callback to signal completion
1617                  */
1618                 if (callback)
1619                         callback(callback_param);
1620
1621                 /*
1622                  * Free the descriptor
1623                  */
1624                 pl08x_free_txd(pl08x, plchan->at);
1625                 plchan->at = NULL;
1626         }
1627         /*
1628          * If a new descriptor is queued, set it up
1629          * plchan->at is NULL here
1630          */
1631         if (!list_empty(&plchan->desc_list)) {
1632                 struct pl08x_txd *next;
1633
1634                 next = list_first_entry(&plchan->desc_list,
1635                                         struct pl08x_txd,
1636                                         node);
1637                 list_del(&next->node);
1638                 plchan->at = next;
1639                 /* Configure the physical channel for the next txd */
1640                 pl08x_config_phychan_for_txd(plchan);
1641                 pl08x_set_cregs(pl08x, plchan->phychan);
1642                 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1643         } else {
1644                 struct pl08x_dma_chan *waiting = NULL;
1645
1646                 /*
1647                  * No more jobs, so free up the physical channel
1648                  * Free any allocated signal on slave transfers too
1649                  */
1650                 release_phy_channel(plchan);
1651                 plchan->state = PL08X_CHAN_IDLE;
1652
1653                 /*
1654                  * And NOW before anyone else can grab that free:d
1655                  * up physical channel, see if there is some memcpy
1656                  * pending that seriously needs to start because of
1657                  * being stacked up while we were choking the
1658                  * physical channels with data.
1659                  */
1660                 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1661                                     chan.device_node) {
1662                   if (waiting->state == PL08X_CHAN_WAITING &&
1663                             waiting->waiting != NULL) {
1664                                 int ret;
1665
1666                                 /* This should REALLY not fail now */
1667                                 ret = prep_phy_channel(waiting,
1668                                                        waiting->waiting);
1669                                 BUG_ON(ret);
1670                                 waiting->state = PL08X_CHAN_RUNNING;
1671                                 waiting->waiting = NULL;
1672                                 pl08x_issue_pending(&waiting->chan);
1673                                 break;
1674                         }
1675                 }
1676         }
1677
1678         spin_unlock_irqrestore(&plchan->lock, flags);
1679 }
1680
1681 static irqreturn_t pl08x_irq(int irq, void *dev)
1682 {
1683         struct pl08x_driver_data *pl08x = dev;
1684         u32 mask = 0;
1685         u32 val;
1686         int i;
1687
1688         val = readl(pl08x->base + PL080_ERR_STATUS);
1689         if (val) {
1690                 /*
1691                  * An error interrupt (on one or more channels)
1692                  */
1693                 dev_err(&pl08x->adev->dev,
1694                         "%s error interrupt, register value 0x%08x\n",
1695                                 __func__, val);
1696                 /*
1697                  * Simply clear ALL PL08X error interrupts,
1698                  * regardless of channel and cause
1699                  * FIXME: should be 0x00000003 on PL081 really.
1700                  */
1701                 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1702         }
1703         val = readl(pl08x->base + PL080_INT_STATUS);
1704         for (i = 0; i < pl08x->vd->channels; i++) {
1705                 if ((1 << i) & val) {
1706                         /* Locate physical channel */
1707                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1708                         struct pl08x_dma_chan *plchan = phychan->serving;
1709
1710                         /* Schedule tasklet on this channel */
1711                         tasklet_schedule(&plchan->tasklet);
1712
1713                         mask |= (1 << i);
1714                 }
1715         }
1716         /*
1717          * Clear only the terminal interrupts on channels we processed
1718          */
1719         writel(mask, pl08x->base + PL080_TC_CLEAR);
1720
1721         return mask ? IRQ_HANDLED : IRQ_NONE;
1722 }
1723
1724 /*
1725  * Initialise the DMAC memcpy/slave channels.
1726  * Make a local wrapper to hold required data
1727  */
1728 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1729                                            struct dma_device *dmadev,
1730                                            unsigned int channels,
1731                                            bool slave)
1732 {
1733         struct pl08x_dma_chan *chan;
1734         int i;
1735
1736         INIT_LIST_HEAD(&dmadev->channels);
1737         /*
1738          * Register as many many memcpy as we have physical channels,
1739          * we won't always be able to use all but the code will have
1740          * to cope with that situation.
1741          */
1742         for (i = 0; i < channels; i++) {
1743                 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1744                 if (!chan) {
1745                         dev_err(&pl08x->adev->dev,
1746                                 "%s no memory for channel\n", __func__);
1747                         return -ENOMEM;
1748                 }
1749
1750                 chan->host = pl08x;
1751                 chan->state = PL08X_CHAN_IDLE;
1752
1753                 if (slave) {
1754                         chan->slave = true;
1755                         chan->name = pl08x->pd->slave_channels[i].bus_id;
1756                         chan->cd = &pl08x->pd->slave_channels[i];
1757                 } else {
1758                         chan->cd = &pl08x->pd->memcpy_channel;
1759                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1760                         if (!chan->name) {
1761                                 kfree(chan);
1762                                 return -ENOMEM;
1763                         }
1764                 }
1765                 if (chan->cd->circular_buffer) {
1766                         dev_err(&pl08x->adev->dev,
1767                                 "channel %s: circular buffers not supported\n",
1768                                 chan->name);
1769                         kfree(chan);
1770                         continue;
1771                 }
1772                 dev_info(&pl08x->adev->dev,
1773                          "initialize virtual channel \"%s\"\n",
1774                          chan->name);
1775
1776                 chan->chan.device = dmadev;
1777                 chan->chan.cookie = 0;
1778                 chan->lc = 0;
1779
1780                 spin_lock_init(&chan->lock);
1781                 INIT_LIST_HEAD(&chan->desc_list);
1782                 tasklet_init(&chan->tasklet, pl08x_tasklet,
1783                              (unsigned long) chan);
1784
1785                 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1786         }
1787         dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1788                  i, slave ? "slave" : "memcpy");
1789         return i;
1790 }
1791
1792 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1793 {
1794         struct pl08x_dma_chan *chan = NULL;
1795         struct pl08x_dma_chan *next;
1796
1797         list_for_each_entry_safe(chan,
1798                                  next, &dmadev->channels, chan.device_node) {
1799                 list_del(&chan->chan.device_node);
1800                 kfree(chan);
1801         }
1802 }
1803
1804 #ifdef CONFIG_DEBUG_FS
1805 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1806 {
1807         switch (state) {
1808         case PL08X_CHAN_IDLE:
1809                 return "idle";
1810         case PL08X_CHAN_RUNNING:
1811                 return "running";
1812         case PL08X_CHAN_PAUSED:
1813                 return "paused";
1814         case PL08X_CHAN_WAITING:
1815                 return "waiting";
1816         default:
1817                 break;
1818         }
1819         return "UNKNOWN STATE";
1820 }
1821
1822 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1823 {
1824         struct pl08x_driver_data *pl08x = s->private;
1825         struct pl08x_dma_chan *chan;
1826         struct pl08x_phy_chan *ch;
1827         unsigned long flags;
1828         int i;
1829
1830         seq_printf(s, "PL08x physical channels:\n");
1831         seq_printf(s, "CHANNEL:\tUSER:\n");
1832         seq_printf(s, "--------\t-----\n");
1833         for (i = 0; i < pl08x->vd->channels; i++) {
1834                 struct pl08x_dma_chan *virt_chan;
1835
1836                 ch = &pl08x->phy_chans[i];
1837
1838                 spin_lock_irqsave(&ch->lock, flags);
1839                 virt_chan = ch->serving;
1840
1841                 seq_printf(s, "%d\t\t%s\n",
1842                            ch->id, virt_chan ? virt_chan->name : "(none)");
1843
1844                 spin_unlock_irqrestore(&ch->lock, flags);
1845         }
1846
1847         seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1848         seq_printf(s, "CHANNEL:\tSTATE:\n");
1849         seq_printf(s, "--------\t------\n");
1850         list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1851                 seq_printf(s, "%s\t\t%s\n", chan->name,
1852                            pl08x_state_str(chan->state));
1853         }
1854
1855         seq_printf(s, "\nPL08x virtual slave channels:\n");
1856         seq_printf(s, "CHANNEL:\tSTATE:\n");
1857         seq_printf(s, "--------\t------\n");
1858         list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1859                 seq_printf(s, "%s\t\t%s\n", chan->name,
1860                            pl08x_state_str(chan->state));
1861         }
1862
1863         return 0;
1864 }
1865
1866 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1867 {
1868         return single_open(file, pl08x_debugfs_show, inode->i_private);
1869 }
1870
1871 static const struct file_operations pl08x_debugfs_operations = {
1872         .open           = pl08x_debugfs_open,
1873         .read           = seq_read,
1874         .llseek         = seq_lseek,
1875         .release        = single_release,
1876 };
1877
1878 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1879 {
1880         /* Expose a simple debugfs interface to view all clocks */
1881         (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1882                                    NULL, pl08x,
1883                                    &pl08x_debugfs_operations);
1884 }
1885
1886 #else
1887 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1888 {
1889 }
1890 #endif
1891
1892 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1893 {
1894         struct pl08x_driver_data *pl08x;
1895         const struct vendor_data *vd = id->data;
1896         int ret = 0;
1897         int i;
1898
1899         ret = amba_request_regions(adev, NULL);
1900         if (ret)
1901                 return ret;
1902
1903         /* Create the driver state holder */
1904         pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1905         if (!pl08x) {
1906                 ret = -ENOMEM;
1907                 goto out_no_pl08x;
1908         }
1909
1910         /* Initialize memcpy engine */
1911         dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1912         pl08x->memcpy.dev = &adev->dev;
1913         pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1914         pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1915         pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1916         pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1917         pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1918         pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1919         pl08x->memcpy.device_control = pl08x_control;
1920
1921         /* Initialize slave engine */
1922         dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1923         pl08x->slave.dev = &adev->dev;
1924         pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1925         pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1926         pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1927         pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1928         pl08x->slave.device_issue_pending = pl08x_issue_pending;
1929         pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1930         pl08x->slave.device_control = pl08x_control;
1931
1932         /* Get the platform data */
1933         pl08x->pd = dev_get_platdata(&adev->dev);
1934         if (!pl08x->pd) {
1935                 dev_err(&adev->dev, "no platform data supplied\n");
1936                 goto out_no_platdata;
1937         }
1938
1939         /* Assign useful pointers to the driver state */
1940         pl08x->adev = adev;
1941         pl08x->vd = vd;
1942
1943         /* A DMA memory pool for LLIs, align on 1-byte boundary */
1944         pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1945                         PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1946         if (!pl08x->pool) {
1947                 ret = -ENOMEM;
1948                 goto out_no_lli_pool;
1949         }
1950
1951         spin_lock_init(&pl08x->lock);
1952
1953         pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1954         if (!pl08x->base) {
1955                 ret = -ENOMEM;
1956                 goto out_no_ioremap;
1957         }
1958
1959         /* Turn on the PL08x */
1960         pl08x_ensure_on(pl08x);
1961
1962         /*
1963          * Attach the interrupt handler
1964          */
1965         writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1966         writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1967
1968         ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1969                           DRIVER_NAME, pl08x);
1970         if (ret) {
1971                 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1972                         __func__, adev->irq[0]);
1973                 goto out_no_irq;
1974         }
1975
1976         /* Initialize physical channels */
1977         pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1978                         GFP_KERNEL);
1979         if (!pl08x->phy_chans) {
1980                 dev_err(&adev->dev, "%s failed to allocate "
1981                         "physical channel holders\n",
1982                         __func__);
1983                 goto out_no_phychans;
1984         }
1985
1986         for (i = 0; i < vd->channels; i++) {
1987                 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1988
1989                 ch->id = i;
1990                 ch->base = pl08x->base + PL080_Cx_BASE(i);
1991                 spin_lock_init(&ch->lock);
1992                 ch->serving = NULL;
1993                 ch->signal = -1;
1994                 dev_info(&adev->dev,
1995                          "physical channel %d is %s\n", i,
1996                          pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1997         }
1998
1999         /* Register as many memcpy channels as there are physical channels */
2000         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
2001                                               pl08x->vd->channels, false);
2002         if (ret <= 0) {
2003                 dev_warn(&pl08x->adev->dev,
2004                          "%s failed to enumerate memcpy channels - %d\n",
2005                          __func__, ret);
2006                 goto out_no_memcpy;
2007         }
2008         pl08x->memcpy.chancnt = ret;
2009
2010         /* Register slave channels */
2011         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2012                                               pl08x->pd->num_slave_channels,
2013                                               true);
2014         if (ret <= 0) {
2015                 dev_warn(&pl08x->adev->dev,
2016                         "%s failed to enumerate slave channels - %d\n",
2017                                 __func__, ret);
2018                 goto out_no_slave;
2019         }
2020         pl08x->slave.chancnt = ret;
2021
2022         ret = dma_async_device_register(&pl08x->memcpy);
2023         if (ret) {
2024                 dev_warn(&pl08x->adev->dev,
2025                         "%s failed to register memcpy as an async device - %d\n",
2026                         __func__, ret);
2027                 goto out_no_memcpy_reg;
2028         }
2029
2030         ret = dma_async_device_register(&pl08x->slave);
2031         if (ret) {
2032                 dev_warn(&pl08x->adev->dev,
2033                         "%s failed to register slave as an async device - %d\n",
2034                         __func__, ret);
2035                 goto out_no_slave_reg;
2036         }
2037
2038         amba_set_drvdata(adev, pl08x);
2039         init_pl08x_debugfs(pl08x);
2040         dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2041                  amba_part(adev), amba_rev(adev),
2042                  (unsigned long long)adev->res.start, adev->irq[0]);
2043         return 0;
2044
2045 out_no_slave_reg:
2046         dma_async_device_unregister(&pl08x->memcpy);
2047 out_no_memcpy_reg:
2048         pl08x_free_virtual_channels(&pl08x->slave);
2049 out_no_slave:
2050         pl08x_free_virtual_channels(&pl08x->memcpy);
2051 out_no_memcpy:
2052         kfree(pl08x->phy_chans);
2053 out_no_phychans:
2054         free_irq(adev->irq[0], pl08x);
2055 out_no_irq:
2056         iounmap(pl08x->base);
2057 out_no_ioremap:
2058         dma_pool_destroy(pl08x->pool);
2059 out_no_lli_pool:
2060 out_no_platdata:
2061         kfree(pl08x);
2062 out_no_pl08x:
2063         amba_release_regions(adev);
2064         return ret;
2065 }
2066
2067 /* PL080 has 8 channels and the PL080 have just 2 */
2068 static struct vendor_data vendor_pl080 = {
2069         .channels = 8,
2070         .dualmaster = true,
2071 };
2072
2073 static struct vendor_data vendor_pl081 = {
2074         .channels = 2,
2075         .dualmaster = false,
2076 };
2077
2078 static struct amba_id pl08x_ids[] = {
2079         /* PL080 */
2080         {
2081                 .id     = 0x00041080,
2082                 .mask   = 0x000fffff,
2083                 .data   = &vendor_pl080,
2084         },
2085         /* PL081 */
2086         {
2087                 .id     = 0x00041081,
2088                 .mask   = 0x000fffff,
2089                 .data   = &vendor_pl081,
2090         },
2091         /* Nomadik 8815 PL080 variant */
2092         {
2093                 .id     = 0x00280880,
2094                 .mask   = 0x00ffffff,
2095                 .data   = &vendor_pl080,
2096         },
2097         { 0, 0 },
2098 };
2099
2100 static struct amba_driver pl08x_amba_driver = {
2101         .drv.name       = DRIVER_NAME,
2102         .id_table       = pl08x_ids,
2103         .probe          = pl08x_probe,
2104 };
2105
2106 static int __init pl08x_init(void)
2107 {
2108         int retval;
2109         retval = amba_driver_register(&pl08x_amba_driver);
2110         if (retval)
2111                 printk(KERN_WARNING DRIVER_NAME
2112                        "failed to register as an AMBA device (%d)\n",
2113                        retval);
2114         return retval;
2115 }
2116 subsys_initcall(pl08x_init);