drivers/dma/amba-pl08x.c

   1 /*
   2  * Copyright (c) 2006 ARM Ltd.
   3  * Copyright (c) 2010 ST-Ericsson SA
   4  *
   5  * Author: Peter Pearse <peter.pearse@arm.com>
   6  * Author: Linus Walleij <linus.walleij@stericsson.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the Free
  10  * Software Foundation; either version 2 of the License, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program; if not, write to the Free Software Foundation, Inc., 59
  20  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  21  *
  22  * The full GNU General Public License is in this distribution in the
  23  * file called COPYING.
  24  *
  25  * Documentation: ARM DDI 0196G == PL080
  26  * Documentation: ARM DDI 0218E == PL081
  27  *
  28  * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
  29  * any channel.
  30  *
  31  * The PL080 has 8 channels available for simultaneous use, and the PL081
  32  * has only two channels. So on these DMA controllers the number of channels
  33  * and the number of incoming DMA signals are two totally different things.
  34  * It is usually not possible to theoretically handle all physical signals,
  35  * so a multiplexing scheme with possible denial of use is necessary.
  36  *
  37  * The PL080 has a dual bus master, PL081 has a single master.
  38  *
  39  * Memory to peripheral transfer may be visualized as
  40  *      Get data from memory to DMAC
  41  *      Until no data left
  42  *              On burst request from peripheral
  43  *                      Destination burst from DMAC to peripheral
  44  *                      Clear burst request
  45  *      Raise terminal count interrupt
  46  *
  47  * For peripherals with a FIFO:
  48  * Source      burst size == half the depth of the peripheral FIFO
  49  * Destination burst size == the depth of the peripheral FIFO
  50  *
  51  * (Bursts are irrelevant for mem to mem transfers - there are no burst
  52  * signals, the DMA controller will simply facilitate its AHB master.)
  53  *
  54  * ASSUMES default (little) endianness for DMA transfers
  55  *
  56  * The PL08x has two flow control settings:
  57  *  - DMAC flow control: the transfer size defines the number of transfers
  58  *    which occur for the current LLI entry, and the DMAC raises TC at the
  59  *    end of every LLI entry.  Observed behaviour shows the DMAC listening
  60  *    to both the BREQ and SREQ signals (contrary to documented),
  61  *    transferring data if either is active.  The LBREQ and LSREQ signals
  62  *    are ignored.
  63  *
  64  *  - Peripheral flow control: the transfer size is ignored (and should be
  65  *    zero).  The data is transferred from the current LLI entry, until
  66  *    after the final transfer signalled by LBREQ or LSREQ.  The DMAC
  67  *    will then move to the next LLI entry.
  68  *
  69  * Only the former works sanely with scatter lists, so we only implement
  70  * the DMAC flow control method.  However, peripherals which use the LBREQ
  71  * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
  72  * these hardware restrictions prevents them from using scatter DMA.
  73  *
  74  * Global TODO:
  75  * - Break out common code from arch/arm/mach-s3c64xx and share
  76  */
  77 #include <linux/device.h>
  78 #include <linux/init.h>
  79 #include <linux/module.h>
  80 #include <linux/interrupt.h>
  81 #include <linux/slab.h>
  82 #include <linux/dmapool.h>
  83 #include <linux/dmaengine.h>
  84 #include <linux/amba/bus.h>
  85 #include <linux/amba/pl08x.h>
  86 #include <linux/debugfs.h>
  87 #include <linux/seq_file.h>
  88
  89 #include <asm/hardware/pl080.h>
  90
  91 #define DRIVER_NAME     "pl08xdmac"
  92
  93 /**
  94  * struct vendor_data - vendor-specific config parameters
  95  * for PL08x derivatives
  96  * @channels: the number of channels available in this variant
  97  * @dualmaster: whether this version supports dual AHB masters
  98  * or not.
  99  */
 100 struct vendor_data {
 101         u8 channels;
 102         bool dualmaster;
 103 };
 104
 105 /*
 106  * PL08X private data structures
 107  * An LLI struct - see PL08x TRM.  Note that next uses bit[0] as a bus bit,
 108  * start & end do not - their bus bit info is in cctl.  Also note that these
 109  * are fixed 32-bit quantities.
 110  */
 111 struct pl08x_lli {
 112         u32 src;
 113         u32 dst;
 114         u32 lli;
 115         u32 cctl;
 116 };
 117
 118 /**
 119  * struct pl08x_driver_data - the local state holder for the PL08x
 120  * @slave: slave engine for this instance
 121  * @memcpy: memcpy engine for this instance
 122  * @base: virtual memory base (remapped) for the PL08x
 123  * @adev: the corresponding AMBA (PrimeCell) bus entry
 124  * @vd: vendor data for this PL08x variant
 125  * @pd: platform data passed in from the platform/machine
 126  * @phy_chans: array of data for the physical channels
 127  * @pool: a pool for the LLI descriptors
 128  * @pool_ctr: counter of LLIs in the pool
 129  * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI fetches
 130  * @mem_buses: set to indicate memory transfers on AHB2.
 131  * @lock: a spinlock for this struct
 132  */
 133 struct pl08x_driver_data {
 134         struct dma_device slave;
 135         struct dma_device memcpy;
 136         void __iomem *base;
 137         struct amba_device *adev;
 138         const struct vendor_data *vd;
 139         struct pl08x_platform_data *pd;
 140         struct pl08x_phy_chan *phy_chans;
 141         struct dma_pool *pool;
 142         int pool_ctr;
 143         u8 lli_buses;
 144         u8 mem_buses;
 145         spinlock_t lock;
 146 };
 147
 148 /*
 149  * PL08X specific defines
 150  */
 151
 152 /*
 153  * Memory boundaries: the manual for PL08x says that the controller
 154  * cannot read past a 1KiB boundary, so these defines are used to
 155  * create transfer LLIs that do not cross such boundaries.
 156  */
 157 #define PL08X_BOUNDARY_SHIFT            (10)    /* 1KB 0x400 */
 158 #define PL08X_BOUNDARY_SIZE             (1 << PL08X_BOUNDARY_SHIFT)
 159
 160 /* Minimum period between work queue runs */
 161 #define PL08X_WQ_PERIODMIN      20
 162
 163 /* Size (bytes) of each LLI buffer allocated for one transfer */
 164 # define PL08X_LLI_TSFR_SIZE    0x2000
 165
 166 /* Maximum times we call dma_pool_alloc on this pool without freeing */
 167 #define PL08X_MAX_ALLOCS        0x40
 168 #define MAX_NUM_TSFR_LLIS       (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
 169 #define PL08X_ALIGN             8
 170
 171 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
 172 {
 173         return container_of(chan, struct pl08x_dma_chan, chan);
 174 }
 175
 176 /*
 177  * Physical channel handling
 178  */
 179
 180 /* Whether a certain channel is busy or not */
 181 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
 182 {
 183         unsigned int val;
 184
 185         val = readl(ch->base + PL080_CH_CONFIG);
 186         return val & PL080_CONFIG_ACTIVE;
 187 }
 188
 189 /*
 190  * Set the initial DMA register values i.e. those for the first LLI
 191  * The next LLI pointer and the configuration interrupt bit have
 192  * been set when the LLIs were constructed.  Poke them into the hardware
 193  * and start the transfer.
 194  */
 195 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
 196         struct pl08x_txd *txd)
 197 {
 198         struct pl08x_driver_data *pl08x = plchan->host;
 199         struct pl08x_phy_chan *phychan = plchan->phychan;
 200         struct pl08x_lli *lli = &txd->llis_va[0];
 201         u32 val;
 202
 203         plchan->at = txd;
 204
 205         /* Wait for channel inactive */
 206         while (pl08x_phy_channel_busy(phychan))
 207                 cpu_relax();
 208
 209         dev_vdbg(&pl08x->adev->dev,
 210                 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
 211                 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
 212                 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
 213                 txd->ccfg);
 214
 215         writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
 216         writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
 217         writel(lli->lli, phychan->base + PL080_CH_LLI);
 218         writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
 219         writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
 220
 221         /* Enable the DMA channel */
 222         /* Do not access config register until channel shows as disabled */
 223         while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
 224                 cpu_relax();
 225
 226         /* Do not access config register until channel shows as inactive */
 227         val = readl(phychan->base + PL080_CH_CONFIG);
 228         while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
 229                 val = readl(phychan->base + PL080_CH_CONFIG);
 230
 231         writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
 232 }
 233
 234 /*
 235  * Overall DMAC remains enabled always.
 236  *
 237  * Disabling individual channels could lose data.
 238  *
 239  * Disable the peripheral DMA after disabling the DMAC
 240  * in order to allow the DMAC FIFO to drain, and
 241  * hence allow the channel to show inactive
 242  *
 243  */
 244 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
 245 {
 246         u32 val;
 247
 248         /* Set the HALT bit and wait for the FIFO to drain */
 249         val = readl(ch->base + PL080_CH_CONFIG);
 250         val |= PL080_CONFIG_HALT;
 251         writel(val, ch->base + PL080_CH_CONFIG);
 252
 253         /* Wait for channel inactive */
 254         while (pl08x_phy_channel_busy(ch))
 255                 cpu_relax();
 256 }
 257
 258 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
 259 {
 260         u32 val;
 261
 262         /* Clear the HALT bit */
 263         val = readl(ch->base + PL080_CH_CONFIG);
 264         val &= ~PL080_CONFIG_HALT;
 265         writel(val, ch->base + PL080_CH_CONFIG);
 266 }
 267
 268
 269 /* Stops the channel */
 270 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
 271 {
 272         u32 val;
 273
 274         pl08x_pause_phy_chan(ch);
 275
 276         /* Disable channel */
 277         val = readl(ch->base + PL080_CH_CONFIG);
 278         val &= ~PL080_CONFIG_ENABLE;
 279         val &= ~PL080_CONFIG_ERR_IRQ_MASK;
 280         val &= ~PL080_CONFIG_TC_IRQ_MASK;
 281         writel(val, ch->base + PL080_CH_CONFIG);
 282 }
 283
 284 static inline u32 get_bytes_in_cctl(u32 cctl)
 285 {
 286         /* The source width defines the number of bytes */
 287         u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
 288
 289         switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 290         case PL080_WIDTH_8BIT:
 291                 break;
 292         case PL080_WIDTH_16BIT:
 293                 bytes *= 2;
 294                 break;
 295         case PL080_WIDTH_32BIT:
 296                 bytes *= 4;
 297                 break;
 298         }
 299         return bytes;
 300 }
 301
 302 /* The channel should be paused when calling this */
 303 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 304 {
 305         struct pl08x_phy_chan *ch;
 306         struct pl08x_txd *txd;
 307         unsigned long flags;
 308         size_t bytes = 0;
 309
 310         spin_lock_irqsave(&plchan->lock, flags);
 311         ch = plchan->phychan;
 312         txd = plchan->at;
 313
 314         /*
 315          * Follow the LLIs to get the number of remaining
 316          * bytes in the currently active transaction.
 317          */
 318         if (ch && txd) {
 319                 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
 320
 321                 /* First get the remaining bytes in the active transfer */
 322                 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
 323
 324                 if (clli) {
 325                         struct pl08x_lli *llis_va = txd->llis_va;
 326                         dma_addr_t llis_bus = txd->llis_bus;
 327                         int index;
 328
 329                         BUG_ON(clli < llis_bus || clli >= llis_bus +
 330                                 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
 331
 332                         /*
 333                          * Locate the next LLI - as this is an array,
 334                          * it's simple maths to find.
 335                          */
 336                         index = (clli - llis_bus) / sizeof(struct pl08x_lli);
 337
 338                         for (; index < MAX_NUM_TSFR_LLIS; index++) {
 339                                 bytes += get_bytes_in_cctl(llis_va[index].cctl);
 340
 341                                 /*
 342                                  * A LLI pointer of 0 terminates the LLI list
 343                                  */
 344                                 if (!llis_va[index].lli)
 345                                         break;
 346                         }
 347                 }
 348         }
 349
 350         /* Sum up all queued transactions */
 351         if (!list_empty(&plchan->desc_list)) {
 352                 struct pl08x_txd *txdi;
 353                 list_for_each_entry(txdi, &plchan->desc_list, node) {
 354                         bytes += txdi->len;
 355                 }
 356         }
 357
 358         spin_unlock_irqrestore(&plchan->lock, flags);
 359
 360         return bytes;
 361 }
 362
 363 /*
 364  * Allocate a physical channel for a virtual channel
 365  */
 366 static struct pl08x_phy_chan *
 367 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
 368                       struct pl08x_dma_chan *virt_chan)
 369 {
 370         struct pl08x_phy_chan *ch = NULL;
 371         unsigned long flags;
 372         int i;
 373
 374         /*
 375          * Try to locate a physical channel to be used for
 376          * this transfer. If all are taken return NULL and
 377          * the requester will have to cope by using some fallback
 378          * PIO mode or retrying later.
 379          */
 380         for (i = 0; i < pl08x->vd->channels; i++) {
 381                 ch = &pl08x->phy_chans[i];
 382
 383                 spin_lock_irqsave(&ch->lock, flags);
 384
 385                 if (!ch->serving) {
 386                         ch->serving = virt_chan;
 387                         ch->signal = -1;
 388                         spin_unlock_irqrestore(&ch->lock, flags);
 389                         break;
 390                 }
 391
 392                 spin_unlock_irqrestore(&ch->lock, flags);
 393         }
 394
 395         if (i == pl08x->vd->channels) {
 396                 /* No physical channel available, cope with it */
 397                 return NULL;
 398         }
 399
 400         return ch;
 401 }
 402
 403 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
 404                                          struct pl08x_phy_chan *ch)
 405 {
 406         unsigned long flags;
 407
 408         /* Stop the channel and clear its interrupts */
 409         pl08x_stop_phy_chan(ch);
 410         writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
 411         writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
 412
 413         /* Mark it as free */
 414         spin_lock_irqsave(&ch->lock, flags);
 415         ch->serving = NULL;
 416         spin_unlock_irqrestore(&ch->lock, flags);
 417 }
 418
 419 /*
 420  * LLI handling
 421  */
 422
 423 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
 424 {
 425         switch (coded) {
 426         case PL080_WIDTH_8BIT:
 427                 return 1;
 428         case PL080_WIDTH_16BIT:
 429                 return 2;
 430         case PL080_WIDTH_32BIT:
 431                 return 4;
 432         default:
 433                 break;
 434         }
 435         BUG();
 436         return 0;
 437 }
 438
 439 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
 440                                   size_t tsize)
 441 {
 442         u32 retbits = cctl;
 443
 444         /* Remove all src, dst and transfer size bits */
 445         retbits &= ~PL080_CONTROL_DWIDTH_MASK;
 446         retbits &= ~PL080_CONTROL_SWIDTH_MASK;
 447         retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
 448
 449         /* Then set the bits according to the parameters */
 450         switch (srcwidth) {
 451         case 1:
 452                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
 453                 break;
 454         case 2:
 455                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
 456                 break;
 457         case 4:
 458                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
 459                 break;
 460         default:
 461                 BUG();
 462                 break;
 463         }
 464
 465         switch (dstwidth) {
 466         case 1:
 467                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
 468                 break;
 469         case 2:
 470                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
 471                 break;
 472         case 4:
 473                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
 474                 break;
 475         default:
 476                 BUG();
 477                 break;
 478         }
 479
 480         retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
 481         return retbits;
 482 }
 483
 484 /*
 485  * Autoselect a master bus to use for the transfer
 486  * this prefers the destination bus if both available
 487  * if fixed address on one bus the other will be chosen
 488  */
 489 static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
 490         struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
 491         struct pl08x_bus_data **sbus, u32 cctl)
 492 {
 493         if (!(cctl & PL080_CONTROL_DST_INCR)) {
 494                 *mbus = src_bus;
 495                 *sbus = dst_bus;
 496         } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
 497                 *mbus = dst_bus;
 498                 *sbus = src_bus;
 499         } else {
 500                 if (dst_bus->buswidth == 4) {
 501                         *mbus = dst_bus;
 502                         *sbus = src_bus;
 503                 } else if (src_bus->buswidth == 4) {
 504                         *mbus = src_bus;
 505                         *sbus = dst_bus;
 506                 } else if (dst_bus->buswidth == 2) {
 507                         *mbus = dst_bus;
 508                         *sbus = src_bus;
 509                 } else if (src_bus->buswidth == 2) {
 510                         *mbus = src_bus;
 511                         *sbus = dst_bus;
 512                 } else {
 513                         /* src_bus->buswidth == 1 */
 514                         *mbus = dst_bus;
 515                         *sbus = src_bus;
 516                 }
 517         }
 518 }
 519
 520 /*
 521  * Fills in one LLI for a certain transfer descriptor
 522  * and advance the counter
 523  */
 524 static int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
 525                             struct pl08x_txd *txd, int num_llis, int len,
 526                             u32 cctl, u32 *remainder)
 527 {
 528         struct pl08x_lli *llis_va = txd->llis_va;
 529         dma_addr_t llis_bus = txd->llis_bus;
 530
 531         BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
 532
 533         llis_va[num_llis].cctl = cctl;
 534         llis_va[num_llis].src = txd->srcbus.addr;
 535         llis_va[num_llis].dst = txd->dstbus.addr;
 536         llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
 537         if (pl08x->lli_buses & PL08X_AHB2)
 538                 llis_va[num_llis].lli |= PL080_LLI_LM_AHB2;
 539
 540         if (cctl & PL080_CONTROL_SRC_INCR)
 541                 txd->srcbus.addr += len;
 542         if (cctl & PL080_CONTROL_DST_INCR)
 543                 txd->dstbus.addr += len;
 544
 545         BUG_ON(*remainder < len);
 546
 547         *remainder -= len;
 548
 549         return num_llis + 1;
 550 }
 551
 552 /*
 553  * Return number of bytes to fill to boundary, or len
 554  */
 555 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
 556 {
 557         u32 boundary;
 558
 559         boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
 560                 << PL08X_BOUNDARY_SHIFT;
 561
 562         if (boundary < addr + len)
 563                 return boundary - addr;
 564         else
 565                 return len;
 566 }
 567
 568 /*
 569  * This fills in the table of LLIs for the transfer descriptor
 570  * Note that we assume we never have to change the burst sizes
 571  * Return 0 for error
 572  */
 573 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 574                               struct pl08x_txd *txd)
 575 {
 576         struct pl08x_bus_data *mbus, *sbus;
 577         size_t remainder;
 578         int num_llis = 0;
 579         u32 cctl;
 580         size_t max_bytes_per_lli;
 581         size_t total_bytes = 0;
 582         struct pl08x_lli *llis_va;
 583
 584         txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
 585                                       &txd->llis_bus);
 586         if (!txd->llis_va) {
 587                 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
 588                 return 0;
 589         }
 590
 591         pl08x->pool_ctr++;
 592
 593         /* Get the default CCTL */
 594         cctl = txd->cctl;
 595
 596         /* Find maximum width of the source bus */
 597         txd->srcbus.maxwidth =
 598                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
 599                                        PL080_CONTROL_SWIDTH_SHIFT);
 600
 601         /* Find maximum width of the destination bus */
 602         txd->dstbus.maxwidth =
 603                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
 604                                        PL080_CONTROL_DWIDTH_SHIFT);
 605
 606         /* Set up the bus widths to the maximum */
 607         txd->srcbus.buswidth = txd->srcbus.maxwidth;
 608         txd->dstbus.buswidth = txd->dstbus.maxwidth;
 609         dev_vdbg(&pl08x->adev->dev,
 610                  "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
 611                  __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
 612
 613
 614         /*
 615          * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
 616          */
 617         max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
 618                 PL080_CONTROL_TRANSFER_SIZE_MASK;
 619         dev_vdbg(&pl08x->adev->dev,
 620                  "%s max bytes per lli = %zu\n",
 621                  __func__, max_bytes_per_lli);
 622
 623         /* We need to count this down to zero */
 624         remainder = txd->len;
 625         dev_vdbg(&pl08x->adev->dev,
 626                  "%s remainder = %zu\n",
 627                  __func__, remainder);
 628
 629         /*
 630          * Choose bus to align to
 631          * - prefers destination bus if both available
 632          * - if fixed address on one bus chooses other
 633          * - modifies cctl to choose an appropriate master
 634          */
 635         pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
 636                                 &mbus, &sbus, cctl);
 637
 638         if (txd->len < mbus->buswidth) {
 639                 /*
 640                  * Less than a bus width available
 641                  * - send as single bytes
 642                  */
 643                 while (remainder) {
 644                         dev_vdbg(&pl08x->adev->dev,
 645                                  "%s single byte LLIs for a transfer of "
 646                                  "less than a bus width (remain 0x%08x)\n",
 647                                  __func__, remainder);
 648                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 649                         num_llis =
 650                                 pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
 651                                         cctl, &remainder);
 652                         total_bytes++;
 653                 }
 654         } else {
 655                 /*
 656                  *  Make one byte LLIs until master bus is aligned
 657                  *  - slave will then be aligned also
 658                  */
 659                 while ((mbus->addr) % (mbus->buswidth)) {
 660                         dev_vdbg(&pl08x->adev->dev,
 661                                 "%s adjustment lli for less than bus width "
 662                                  "(remain 0x%08x)\n",
 663                                  __func__, remainder);
 664                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 665                         num_llis = pl08x_fill_lli_for_desc
 666                                 (pl08x, txd, num_llis, 1, cctl, &remainder);
 667                         total_bytes++;
 668                 }
 669
 670                 /*
 671                  *  Master now aligned
 672                  * - if slave is not then we must set its width down
 673                  */
 674                 if (sbus->addr % sbus->buswidth) {
 675                         dev_dbg(&pl08x->adev->dev,
 676                                 "%s set down bus width to one byte\n",
 677                                  __func__);
 678
 679                         sbus->buswidth = 1;
 680                 }
 681
 682                 /*
 683                  * Make largest possible LLIs until less than one bus
 684                  * width left
 685                  */
 686                 while (remainder > (mbus->buswidth - 1)) {
 687                         size_t lli_len, target_len, tsize, odd_bytes;
 688
 689                         /*
 690                          * If enough left try to send max possible,
 691                          * otherwise try to send the remainder
 692                          */
 693                         target_len = remainder;
 694                         if (remainder > max_bytes_per_lli)
 695                                 target_len = max_bytes_per_lli;
 696
 697                         /*
 698                          * Set bus lengths for incrementing buses
 699                          * to number of bytes which fill to next memory
 700                          * boundary
 701                          */
 702                         if (cctl & PL080_CONTROL_SRC_INCR)
 703                                 txd->srcbus.fill_bytes =
 704                                         pl08x_pre_boundary(
 705                                                 txd->srcbus.addr,
 706                                                 remainder);
 707                         else
 708                                 txd->srcbus.fill_bytes =
 709                                         max_bytes_per_lli;
 710
 711                         if (cctl & PL080_CONTROL_DST_INCR)
 712                                 txd->dstbus.fill_bytes =
 713                                         pl08x_pre_boundary(
 714                                                 txd->dstbus.addr,
 715                                                 remainder);
 716                         else
 717                                 txd->dstbus.fill_bytes =
 718                                                 max_bytes_per_lli;
 719
 720                         /*
 721                          *  Find the nearest
 722                          */
 723                         lli_len = min(txd->srcbus.fill_bytes,
 724                                 txd->dstbus.fill_bytes);
 725
 726                         BUG_ON(lli_len > remainder);
 727
 728                         if (lli_len <= 0) {
 729                                 dev_err(&pl08x->adev->dev,
 730                                         "%s lli_len is %zu, <= 0\n",
 731                                                 __func__, lli_len);
 732                                 return 0;
 733                         }
 734
 735                         if (lli_len == target_len) {
 736                                 /*
 737                                  * Can send what we wanted
 738                                  */
 739                                 /*
 740                                  *  Maintain alignment
 741                                  */
 742                                 lli_len = (lli_len/mbus->buswidth) *
 743                                                         mbus->buswidth;
 744                                 odd_bytes = 0;
 745                         } else {
 746                                 /*
 747                                  * So now we know how many bytes to transfer
 748                                  * to get to the nearest boundary
 749                                  * The next LLI will past the boundary
 750                                  * - however we may be working to a boundary
 751                                  *   on the slave bus
 752                                  *   We need to ensure the master stays aligned
 753                                  */
 754                                 odd_bytes = lli_len % mbus->buswidth;
 755                                 /*
 756                                  * - and that we are working in multiples
 757                                  *   of the bus widths
 758                                  */
 759                                 lli_len -= odd_bytes;
 760
 761                         }
 762
 763                         if (lli_len) {
 764                                 /*
 765                                  * Check against minimum bus alignment:
 766                                  * Calculate actual transfer size in relation
 767                                  * to bus width an get a maximum remainder of
 768                                  * the smallest bus width - 1
 769                                  */
 770                                 /* FIXME: use round_down()? */
 771                                 tsize = lli_len / min(mbus->buswidth,
 772                                                       sbus->buswidth);
 773                                 lli_len = tsize * min(mbus->buswidth,
 774                                                       sbus->buswidth);
 775
 776                                 if (target_len != lli_len) {
 777                                         dev_vdbg(&pl08x->adev->dev,
 778                                         "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
 779                                         __func__, target_len, lli_len, txd->len);
 780                                 }
 781
 782                                 cctl = pl08x_cctl_bits(cctl,
 783                                                        txd->srcbus.buswidth,
 784                                                        txd->dstbus.buswidth,
 785                                                        tsize);
 786
 787                                 dev_vdbg(&pl08x->adev->dev,
 788                                         "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
 789                                         __func__, lli_len, remainder);
 790                                 num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
 791                                                 num_llis, lli_len, cctl,
 792                                                 &remainder);
 793                                 total_bytes += lli_len;
 794                         }
 795
 796
 797                         if (odd_bytes) {
 798                                 /*
 799                                  * Creep past the boundary,
 800                                  * maintaining master alignment
 801                                  */
 802                                 int j;
 803                                 for (j = 0; (j < mbus->buswidth)
 804                                                 && (remainder); j++) {
 805                                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 806                                         dev_vdbg(&pl08x->adev->dev,
 807                                                 "%s align with boundary, single byte (remain 0x%08zx)\n",
 808                                                 __func__, remainder);
 809                                         num_llis =
 810                                                 pl08x_fill_lli_for_desc(pl08x,
 811                                                         txd, num_llis, 1,
 812                                                         cctl, &remainder);
 813                                         total_bytes++;
 814                                 }
 815                         }
 816                 }
 817
 818                 /*
 819                  * Send any odd bytes
 820                  */
 821                 while (remainder) {
 822                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 823                         dev_vdbg(&pl08x->adev->dev,
 824                                 "%s align with boundary, single odd byte (remain %zu)\n",
 825                                 __func__, remainder);
 826                         num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
 827                                         1, cctl, &remainder);
 828                         total_bytes++;
 829                 }
 830         }
 831         if (total_bytes != txd->len) {
 832                 dev_err(&pl08x->adev->dev,
 833                         "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
 834                         __func__, total_bytes, txd->len);
 835                 return 0;
 836         }
 837
 838         if (num_llis >= MAX_NUM_TSFR_LLIS) {
 839                 dev_err(&pl08x->adev->dev,
 840                         "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
 841                         __func__, (u32) MAX_NUM_TSFR_LLIS);
 842                 return 0;
 843         }
 844
 845         llis_va = txd->llis_va;
 846         /*
 847          * The final LLI terminates the LLI.
 848          */
 849         llis_va[num_llis - 1].lli = 0;
 850         /*
 851          * The final LLI element shall also fire an interrupt
 852          */
 853         llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
 854
 855 #ifdef VERBOSE_DEBUG
 856         {
 857                 int i;
 858
 859                 for (i = 0; i < num_llis; i++) {
 860                         dev_vdbg(&pl08x->adev->dev,
 861                                  "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
 862                                  i,
 863                                  &llis_va[i],
 864                                  llis_va[i].src,
 865                                  llis_va[i].dst,
 866                                  llis_va[i].cctl,
 867                                  llis_va[i].lli
 868                                 );
 869                 }
 870         }
 871 #endif
 872
 873         return num_llis;
 874 }
 875
 876 /* You should call this with the struct pl08x lock held */
 877 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
 878                            struct pl08x_txd *txd)
 879 {
 880         /* Free the LLI */
 881         dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
 882
 883         pl08x->pool_ctr--;
 884
 885         kfree(txd);
 886 }
 887
 888 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
 889                                 struct pl08x_dma_chan *plchan)
 890 {
 891         struct pl08x_txd *txdi = NULL;
 892         struct pl08x_txd *next;
 893
 894         if (!list_empty(&plchan->desc_list)) {
 895                 list_for_each_entry_safe(txdi,
 896                                          next, &plchan->desc_list, node) {
 897                         list_del(&txdi->node);
 898                         pl08x_free_txd(pl08x, txdi);
 899                 }
 900
 901         }
 902 }
 903
 904 /*
 905  * The DMA ENGINE API
 906  */
 907 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
 908 {
 909         return 0;
 910 }
 911
 912 static void pl08x_free_chan_resources(struct dma_chan *chan)
 913 {
 914 }
 915
 916 /*
 917  * This should be called with the channel plchan->lock held
 918  */
 919 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
 920                             struct pl08x_txd *txd)
 921 {
 922         struct pl08x_driver_data *pl08x = plchan->host;
 923         struct pl08x_phy_chan *ch;
 924         int ret;
 925
 926         /* Check if we already have a channel */
 927         if (plchan->phychan)
 928                 return 0;
 929
 930         ch = pl08x_get_phy_channel(pl08x, plchan);
 931         if (!ch) {
 932                 /* No physical channel available, cope with it */
 933                 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
 934                 return -EBUSY;
 935         }
 936
 937         /*
 938          * OK we have a physical channel: for memcpy() this is all we
 939          * need, but for slaves the physical signals may be muxed!
 940          * Can the platform allow us to use this channel?
 941          */
 942         if (plchan->slave &&
 943             ch->signal < 0 &&
 944             pl08x->pd->get_signal) {
 945                 ret = pl08x->pd->get_signal(plchan);
 946                 if (ret < 0) {
 947                         dev_dbg(&pl08x->adev->dev,
 948                                 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
 949                                 ch->id, plchan->name);
 950                         /* Release physical channel & return */
 951                         pl08x_put_phy_channel(pl08x, ch);
 952                         return -EBUSY;
 953                 }
 954                 ch->signal = ret;
 955
 956                 /* Assign the flow control signal to this channel */
 957                 if (txd->direction == DMA_TO_DEVICE)
 958                         txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
 959                 else if (txd->direction == DMA_FROM_DEVICE)
 960                         txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
 961         }
 962
 963         dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
 964                  ch->id,
 965                  ch->signal,
 966                  plchan->name);
 967
 968         plchan->phychan = ch;
 969
 970         return 0;
 971 }
 972
 973 static void release_phy_channel(struct pl08x_dma_chan *plchan)
 974 {
 975         struct pl08x_driver_data *pl08x = plchan->host;
 976
 977         if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
 978                 pl08x->pd->put_signal(plchan);
 979                 plchan->phychan->signal = -1;
 980         }
 981         pl08x_put_phy_channel(pl08x, plchan->phychan);
 982         plchan->phychan = NULL;
 983 }
 984
 985 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
 986 {
 987         struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
 988
 989         plchan->chan.cookie += 1;
 990         if (plchan->chan.cookie < 0)
 991                 plchan->chan.cookie = 1;
 992         tx->cookie = plchan->chan.cookie;
 993         /* This unlock follows the lock in the prep() function */
 994         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
 995
 996         return tx->cookie;
 997 }
 998
 999 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1000                 struct dma_chan *chan, unsigned long flags)
1001 {
1002         struct dma_async_tx_descriptor *retval = NULL;
1003
1004         return retval;
1005 }
1006
1007 /*
1008  * Code accessing dma_async_is_complete() in a tight loop
1009  * may give problems - could schedule where indicated.
1010  * If slaves are relying on interrupts to signal completion this
1011  * function must not be called with interrupts disabled
1012  */
1013 static enum dma_status
1014 pl08x_dma_tx_status(struct dma_chan *chan,
1015                     dma_cookie_t cookie,
1016                     struct dma_tx_state *txstate)
1017 {
1018         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1019         dma_cookie_t last_used;
1020         dma_cookie_t last_complete;
1021         enum dma_status ret;
1022         u32 bytesleft = 0;
1023
1024         last_used = plchan->chan.cookie;
1025         last_complete = plchan->lc;
1026
1027         ret = dma_async_is_complete(cookie, last_complete, last_used);
1028         if (ret == DMA_SUCCESS) {
1029                 dma_set_tx_state(txstate, last_complete, last_used, 0);
1030                 return ret;
1031         }
1032
1033         /*
1034          * schedule(); could be inserted here
1035          */
1036
1037         /*
1038          * This cookie not complete yet
1039          */
1040         last_used = plchan->chan.cookie;
1041         last_complete = plchan->lc;
1042
1043         /* Get number of bytes left in the active transactions and queue */
1044         bytesleft = pl08x_getbytes_chan(plchan);
1045
1046         dma_set_tx_state(txstate, last_complete, last_used,
1047                          bytesleft);
1048
1049         if (plchan->state == PL08X_CHAN_PAUSED)
1050                 return DMA_PAUSED;
1051
1052         /* Whether waiting or running, we're in progress */
1053         return DMA_IN_PROGRESS;
1054 }
1055
1056 /* PrimeCell DMA extension */
1057 struct burst_table {
1058         int burstwords;
1059         u32 reg;
1060 };
1061
1062 static const struct burst_table burst_sizes[] = {
1063         {
1064                 .burstwords = 256,
1065                 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1066                         (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1067         },
1068         {
1069                 .burstwords = 128,
1070                 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1071                         (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1072         },
1073         {
1074                 .burstwords = 64,
1075                 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1076                         (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1077         },
1078         {
1079                 .burstwords = 32,
1080                 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1081                         (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1082         },
1083         {
1084                 .burstwords = 16,
1085                 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1086                         (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1087         },
1088         {
1089                 .burstwords = 8,
1090                 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1091                         (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1092         },
1093         {
1094                 .burstwords = 4,
1095                 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1096                         (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1097         },
1098         {
1099                 .burstwords = 1,
1100                 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1101                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1102         },
1103 };
1104
1105 static void dma_set_runtime_config(struct dma_chan *chan,
1106                                struct dma_slave_config *config)
1107 {
1108         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1109         struct pl08x_driver_data *pl08x = plchan->host;
1110         struct pl08x_channel_data *cd = plchan->cd;
1111         enum dma_slave_buswidth addr_width;
1112         u32 maxburst;
1113         u32 cctl = 0;
1114         int i;
1115
1116         /* Transfer direction */
1117         plchan->runtime_direction = config->direction;
1118         if (config->direction == DMA_TO_DEVICE) {
1119                 plchan->runtime_addr = config->dst_addr;
1120                 addr_width = config->dst_addr_width;
1121                 maxburst = config->dst_maxburst;
1122         } else if (config->direction == DMA_FROM_DEVICE) {
1123                 plchan->runtime_addr = config->src_addr;
1124                 addr_width = config->src_addr_width;
1125                 maxburst = config->src_maxburst;
1126         } else {
1127                 dev_err(&pl08x->adev->dev,
1128                         "bad runtime_config: alien transfer direction\n");
1129                 return;
1130         }
1131
1132         switch (addr_width) {
1133         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1134                 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1135                         (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1136                 break;
1137         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1138                 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1139                         (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1140                 break;
1141         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1142                 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1143                         (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1144                 break;
1145         default:
1146                 dev_err(&pl08x->adev->dev,
1147                         "bad runtime_config: alien address width\n");
1148                 return;
1149         }
1150
1151         /*
1152          * Now decide on a maxburst:
1153          * If this channel will only request single transfers, set this
1154          * down to ONE element.  Also select one element if no maxburst
1155          * is specified.
1156          */
1157         if (plchan->cd->single || maxburst == 0) {
1158                 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1159                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1160         } else {
1161                 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1162                         if (burst_sizes[i].burstwords <= maxburst)
1163                                 break;
1164                 cctl |= burst_sizes[i].reg;
1165         }
1166
1167         /* Modify the default channel data to fit PrimeCell request */
1168         cd->cctl = cctl;
1169
1170         dev_dbg(&pl08x->adev->dev,
1171                 "configured channel %s (%s) for %s, data width %d, "
1172                 "maxburst %d words, LE, CCTL=0x%08x\n",
1173                 dma_chan_name(chan), plchan->name,
1174                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1175                 addr_width,
1176                 maxburst,
1177                 cctl);
1178 }
1179
1180 /*
1181  * Slave transactions callback to the slave device to allow
1182  * synchronization of slave DMA signals with the DMAC enable
1183  */
1184 static void pl08x_issue_pending(struct dma_chan *chan)
1185 {
1186         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1187         unsigned long flags;
1188
1189         spin_lock_irqsave(&plchan->lock, flags);
1190         /* Something is already active, or we're waiting for a channel... */
1191         if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1192                 spin_unlock_irqrestore(&plchan->lock, flags);
1193                 return;
1194         }
1195
1196         /* Take the first element in the queue and execute it */
1197         if (!list_empty(&plchan->desc_list)) {
1198                 struct pl08x_txd *next;
1199
1200                 next = list_first_entry(&plchan->desc_list,
1201                                         struct pl08x_txd,
1202                                         node);
1203                 list_del(&next->node);
1204                 plchan->state = PL08X_CHAN_RUNNING;
1205
1206                 pl08x_start_txd(plchan, next);
1207         }
1208
1209         spin_unlock_irqrestore(&plchan->lock, flags);
1210 }
1211
1212 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1213                                         struct pl08x_txd *txd)
1214 {
1215         int num_llis;
1216         struct pl08x_driver_data *pl08x = plchan->host;
1217         int ret;
1218
1219         num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1220         if (!num_llis) {
1221                 kfree(txd);
1222                 return -EINVAL;
1223         }
1224
1225         spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1226
1227         list_add_tail(&txd->node, &plchan->desc_list);
1228
1229         /*
1230          * See if we already have a physical channel allocated,
1231          * else this is the time to try to get one.
1232          */
1233         ret = prep_phy_channel(plchan, txd);
1234         if (ret) {
1235                 /*
1236                  * No physical channel available, we will
1237                  * stack up the memcpy channels until there is a channel
1238                  * available to handle it whereas slave transfers may
1239                  * have been denied due to platform channel muxing restrictions
1240                  * and since there is no guarantee that this will ever be
1241                  * resolved, and since the signal must be acquired AFTER
1242                  * acquiring the physical channel, we will let them be NACK:ed
1243                  * with -EBUSY here. The drivers can alway retry the prep()
1244                  * call if they are eager on doing this using DMA.
1245                  */
1246                 if (plchan->slave) {
1247                         pl08x_free_txd_list(pl08x, plchan);
1248                         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1249                         return -EBUSY;
1250                 }
1251                 /* Do this memcpy whenever there is a channel ready */
1252                 plchan->state = PL08X_CHAN_WAITING;
1253                 plchan->waiting = txd;
1254         } else
1255                 /*
1256                  * Else we're all set, paused and ready to roll,
1257                  * status will switch to PL08X_CHAN_RUNNING when
1258                  * we call issue_pending(). If there is something
1259                  * running on the channel already we don't change
1260                  * its state.
1261                  */
1262                 if (plchan->state == PL08X_CHAN_IDLE)
1263                         plchan->state = PL08X_CHAN_PAUSED;
1264
1265         /*
1266          * Notice that we leave plchan->lock locked on purpose:
1267          * it will be unlocked in the subsequent tx_submit()
1268          * call. This is a consequence of the current API.
1269          */
1270
1271         return 0;
1272 }
1273
1274 /*
1275  * Given the source and destination available bus masks, select which
1276  * will be routed to each port.  We try to have source and destination
1277  * on separate ports, but always respect the allowable settings.
1278  */
1279 static u32 pl08x_select_bus(struct pl08x_driver_data *pl08x, u8 src, u8 dst)
1280 {
1281         u32 cctl = 0;
1282
1283         if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1284                 cctl |= PL080_CONTROL_DST_AHB2;
1285         if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1286                 cctl |= PL080_CONTROL_SRC_AHB2;
1287
1288         return cctl;
1289 }
1290
1291 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1292 {
1293         struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1294
1295         if (txd) {
1296                 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1297                 txd->tx.tx_submit = pl08x_tx_submit;
1298                 INIT_LIST_HEAD(&txd->node);
1299
1300                 /* Always enable error and terminal interrupts */
1301                 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1302                             PL080_CONFIG_TC_IRQ_MASK;
1303         }
1304         return txd;
1305 }
1306
1307 /*
1308  * Initialize a descriptor to be used by memcpy submit
1309  */
1310 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1311                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1312                 size_t len, unsigned long flags)
1313 {
1314         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1315         struct pl08x_driver_data *pl08x = plchan->host;
1316         struct pl08x_txd *txd;
1317         int ret;
1318
1319         txd = pl08x_get_txd(plchan);
1320         if (!txd) {
1321                 dev_err(&pl08x->adev->dev,
1322                         "%s no memory for descriptor\n", __func__);
1323                 return NULL;
1324         }
1325
1326         txd->direction = DMA_NONE;
1327         txd->srcbus.addr = src;
1328         txd->dstbus.addr = dest;
1329         txd->len = len;
1330
1331         /* Set platform data for m2m */
1332         txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1333         txd->cctl = pl08x->pd->memcpy_channel.cctl &
1334                         ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1335
1336         /* Both to be incremented or the code will break */
1337         txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1338
1339         if (pl08x->vd->dualmaster)
1340                 txd->cctl |= pl08x_select_bus(pl08x,
1341                                         pl08x->mem_buses, pl08x->mem_buses);
1342
1343         ret = pl08x_prep_channel_resources(plchan, txd);
1344         if (ret)
1345                 return NULL;
1346         /*
1347          * NB: the channel lock is held at this point so tx_submit()
1348          * must be called in direct succession.
1349          */
1350
1351         return &txd->tx;
1352 }
1353
1354 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1355                 struct dma_chan *chan, struct scatterlist *sgl,
1356                 unsigned int sg_len, enum dma_data_direction direction,
1357                 unsigned long flags)
1358 {
1359         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1360         struct pl08x_driver_data *pl08x = plchan->host;
1361         struct pl08x_txd *txd;
1362         u8 src_buses, dst_buses;
1363         int ret;
1364
1365         /*
1366          * Current implementation ASSUMES only one sg
1367          */
1368         if (sg_len != 1) {
1369                 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1370                         __func__);
1371                 BUG();
1372         }
1373
1374         dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1375                 __func__, sgl->length, plchan->name);
1376
1377         txd = pl08x_get_txd(plchan);
1378         if (!txd) {
1379                 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1380                 return NULL;
1381         }
1382
1383         if (direction != plchan->runtime_direction)
1384                 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1385                         "the direction configured for the PrimeCell\n",
1386                         __func__);
1387
1388         /*
1389          * Set up addresses, the PrimeCell configured address
1390          * will take precedence since this may configure the
1391          * channel target address dynamically at runtime.
1392          */
1393         txd->direction = direction;
1394         txd->len = sgl->length;
1395
1396         txd->cctl = plchan->cd->cctl &
1397                         ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1398                           PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1399                           PL080_CONTROL_PROT_MASK);
1400
1401         /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1402         txd->cctl |= PL080_CONTROL_PROT_SYS;
1403
1404         if (direction == DMA_TO_DEVICE) {
1405                 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1406                 txd->cctl |= PL080_CONTROL_SRC_INCR;
1407                 txd->srcbus.addr = sgl->dma_address;
1408                 if (plchan->runtime_addr)
1409                         txd->dstbus.addr = plchan->runtime_addr;
1410                 else
1411                         txd->dstbus.addr = plchan->cd->addr;
1412                 src_buses = pl08x->mem_buses;
1413                 dst_buses = plchan->cd->periph_buses;
1414         } else if (direction == DMA_FROM_DEVICE) {
1415                 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1416                 txd->cctl |= PL080_CONTROL_DST_INCR;
1417                 if (plchan->runtime_addr)
1418                         txd->srcbus.addr = plchan->runtime_addr;
1419                 else
1420                         txd->srcbus.addr = plchan->cd->addr;
1421                 txd->dstbus.addr = sgl->dma_address;
1422                 src_buses = plchan->cd->periph_buses;
1423                 dst_buses = pl08x->mem_buses;
1424         } else {
1425                 dev_err(&pl08x->adev->dev,
1426                         "%s direction unsupported\n", __func__);
1427                 return NULL;
1428         }
1429
1430         txd->cctl |= pl08x_select_bus(pl08x, src_buses, dst_buses);
1431
1432         ret = pl08x_prep_channel_resources(plchan, txd);
1433         if (ret)
1434                 return NULL;
1435         /*
1436          * NB: the channel lock is held at this point so tx_submit()
1437          * must be called in direct succession.
1438          */
1439
1440         return &txd->tx;
1441 }
1442
1443 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1444                          unsigned long arg)
1445 {
1446         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1447         struct pl08x_driver_data *pl08x = plchan->host;
1448         unsigned long flags;
1449         int ret = 0;
1450
1451         /* Controls applicable to inactive channels */
1452         if (cmd == DMA_SLAVE_CONFIG) {
1453                 dma_set_runtime_config(chan,
1454                                        (struct dma_slave_config *)
1455                                        arg);
1456                 return 0;
1457         }
1458
1459         /*
1460          * Anything succeeds on channels with no physical allocation and
1461          * no queued transfers.
1462          */
1463         spin_lock_irqsave(&plchan->lock, flags);
1464         if (!plchan->phychan && !plchan->at) {
1465                 spin_unlock_irqrestore(&plchan->lock, flags);
1466                 return 0;
1467         }
1468
1469         switch (cmd) {
1470         case DMA_TERMINATE_ALL:
1471                 plchan->state = PL08X_CHAN_IDLE;
1472
1473                 if (plchan->phychan) {
1474                         pl08x_stop_phy_chan(plchan->phychan);
1475
1476                         /*
1477                          * Mark physical channel as free and free any slave
1478                          * signal
1479                          */
1480                         release_phy_channel(plchan);
1481                 }
1482                 /* Dequeue jobs and free LLIs */
1483                 if (plchan->at) {
1484                         pl08x_free_txd(pl08x, plchan->at);
1485                         plchan->at = NULL;
1486                 }
1487                 /* Dequeue jobs not yet fired as well */
1488                 pl08x_free_txd_list(pl08x, plchan);
1489                 break;
1490         case DMA_PAUSE:
1491                 pl08x_pause_phy_chan(plchan->phychan);
1492                 plchan->state = PL08X_CHAN_PAUSED;
1493                 break;
1494         case DMA_RESUME:
1495                 pl08x_resume_phy_chan(plchan->phychan);
1496                 plchan->state = PL08X_CHAN_RUNNING;
1497                 break;
1498         default:
1499                 /* Unknown command */
1500                 ret = -ENXIO;
1501                 break;
1502         }
1503
1504         spin_unlock_irqrestore(&plchan->lock, flags);
1505
1506         return ret;
1507 }
1508
1509 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1510 {
1511         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1512         char *name = chan_id;
1513
1514         /* Check that the channel is not taken! */
1515         if (!strcmp(plchan->name, name))
1516                 return true;
1517
1518         return false;
1519 }
1520
1521 /*
1522  * Just check that the device is there and active
1523  * TODO: turn this bit on/off depending on the number of
1524  * physical channels actually used, if it is zero... well
1525  * shut it off. That will save some power. Cut the clock
1526  * at the same time.
1527  */
1528 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1529 {
1530         u32 val;
1531
1532         val = readl(pl08x->base + PL080_CONFIG);
1533         val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1534         /* We implicitly clear bit 1 and that means little-endian mode */
1535         val |= PL080_CONFIG_ENABLE;
1536         writel(val, pl08x->base + PL080_CONFIG);
1537 }
1538
1539 static void pl08x_tasklet(unsigned long data)
1540 {
1541         struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1542         struct pl08x_driver_data *pl08x = plchan->host;
1543         struct pl08x_txd *txd;
1544         dma_async_tx_callback callback = NULL;
1545         void *callback_param = NULL;
1546         unsigned long flags;
1547
1548         spin_lock_irqsave(&plchan->lock, flags);
1549
1550         txd = plchan->at;
1551         plchan->at = NULL;
1552
1553         if (txd) {
1554                 callback = txd->tx.callback;
1555                 callback_param = txd->tx.callback_param;
1556
1557                 /*
1558                  * Update last completed
1559                  */
1560                 plchan->lc = txd->tx.cookie;
1561
1562                 /*
1563                  * Free the descriptor
1564                  */
1565                 pl08x_free_txd(pl08x, txd);
1566         }
1567         /*
1568          * If a new descriptor is queued, set it up
1569          * plchan->at is NULL here
1570          */
1571         if (!list_empty(&plchan->desc_list)) {
1572                 struct pl08x_txd *next;
1573
1574                 next = list_first_entry(&plchan->desc_list,
1575                                         struct pl08x_txd,
1576                                         node);
1577                 list_del(&next->node);
1578
1579                 pl08x_start_txd(plchan, next);
1580         } else {
1581                 struct pl08x_dma_chan *waiting = NULL;
1582
1583                 /*
1584                  * No more jobs, so free up the physical channel
1585                  * Free any allocated signal on slave transfers too
1586                  */
1587                 release_phy_channel(plchan);
1588                 plchan->state = PL08X_CHAN_IDLE;
1589
1590                 /*
1591                  * And NOW before anyone else can grab that free:d
1592                  * up physical channel, see if there is some memcpy
1593                  * pending that seriously needs to start because of
1594                  * being stacked up while we were choking the
1595                  * physical channels with data.
1596                  */
1597                 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1598                                     chan.device_node) {
1599                   if (waiting->state == PL08X_CHAN_WAITING &&
1600                             waiting->waiting != NULL) {
1601                                 int ret;
1602
1603                                 /* This should REALLY not fail now */
1604                                 ret = prep_phy_channel(waiting,
1605                                                        waiting->waiting);
1606                                 BUG_ON(ret);
1607                                 waiting->state = PL08X_CHAN_RUNNING;
1608                                 waiting->waiting = NULL;
1609                                 pl08x_issue_pending(&waiting->chan);
1610                                 break;
1611                         }
1612                 }
1613         }
1614
1615         spin_unlock_irqrestore(&plchan->lock, flags);
1616
1617         /* Callback to signal completion */
1618         if (callback)
1619                 callback(callback_param);
1620 }
1621
1622 static irqreturn_t pl08x_irq(int irq, void *dev)
1623 {
1624         struct pl08x_driver_data *pl08x = dev;
1625         u32 mask = 0;
1626         u32 val;
1627         int i;
1628
1629         val = readl(pl08x->base + PL080_ERR_STATUS);
1630         if (val) {
1631                 /*
1632                  * An error interrupt (on one or more channels)
1633                  */
1634                 dev_err(&pl08x->adev->dev,
1635                         "%s error interrupt, register value 0x%08x\n",
1636                                 __func__, val);
1637                 /*
1638                  * Simply clear ALL PL08X error interrupts,
1639                  * regardless of channel and cause
1640                  * FIXME: should be 0x00000003 on PL081 really.
1641                  */
1642                 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1643         }
1644         val = readl(pl08x->base + PL080_INT_STATUS);
1645         for (i = 0; i < pl08x->vd->channels; i++) {
1646                 if ((1 << i) & val) {
1647                         /* Locate physical channel */
1648                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1649                         struct pl08x_dma_chan *plchan = phychan->serving;
1650
1651                         /* Schedule tasklet on this channel */
1652                         tasklet_schedule(&plchan->tasklet);
1653
1654                         mask |= (1 << i);
1655                 }
1656         }
1657         /*
1658          * Clear only the terminal interrupts on channels we processed
1659          */
1660         writel(mask, pl08x->base + PL080_TC_CLEAR);
1661
1662         return mask ? IRQ_HANDLED : IRQ_NONE;
1663 }
1664
1665 /*
1666  * Initialise the DMAC memcpy/slave channels.
1667  * Make a local wrapper to hold required data
1668  */
1669 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1670                                            struct dma_device *dmadev,
1671                                            unsigned int channels,
1672                                            bool slave)
1673 {
1674         struct pl08x_dma_chan *chan;
1675         int i;
1676
1677         INIT_LIST_HEAD(&dmadev->channels);
1678         /*
1679          * Register as many many memcpy as we have physical channels,
1680          * we won't always be able to use all but the code will have
1681          * to cope with that situation.
1682          */
1683         for (i = 0; i < channels; i++) {
1684                 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1685                 if (!chan) {
1686                         dev_err(&pl08x->adev->dev,
1687                                 "%s no memory for channel\n", __func__);
1688                         return -ENOMEM;
1689                 }
1690
1691                 chan->host = pl08x;
1692                 chan->state = PL08X_CHAN_IDLE;
1693
1694                 if (slave) {
1695                         chan->slave = true;
1696                         chan->name = pl08x->pd->slave_channels[i].bus_id;
1697                         chan->cd = &pl08x->pd->slave_channels[i];
1698                 } else {
1699                         chan->cd = &pl08x->pd->memcpy_channel;
1700                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1701                         if (!chan->name) {
1702                                 kfree(chan);
1703                                 return -ENOMEM;
1704                         }
1705                 }
1706                 if (chan->cd->circular_buffer) {
1707                         dev_err(&pl08x->adev->dev,
1708                                 "channel %s: circular buffers not supported\n",
1709                                 chan->name);
1710                         kfree(chan);
1711                         continue;
1712                 }
1713                 dev_info(&pl08x->adev->dev,
1714                          "initialize virtual channel \"%s\"\n",
1715                          chan->name);
1716
1717                 chan->chan.device = dmadev;
1718                 chan->chan.cookie = 0;
1719                 chan->lc = 0;
1720
1721                 spin_lock_init(&chan->lock);
1722                 INIT_LIST_HEAD(&chan->desc_list);
1723                 tasklet_init(&chan->tasklet, pl08x_tasklet,
1724                              (unsigned long) chan);
1725
1726                 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1727         }
1728         dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1729                  i, slave ? "slave" : "memcpy");
1730         return i;
1731 }
1732
1733 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1734 {
1735         struct pl08x_dma_chan *chan = NULL;
1736         struct pl08x_dma_chan *next;
1737
1738         list_for_each_entry_safe(chan,
1739                                  next, &dmadev->channels, chan.device_node) {
1740                 list_del(&chan->chan.device_node);
1741                 kfree(chan);
1742         }
1743 }
1744
1745 #ifdef CONFIG_DEBUG_FS
1746 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1747 {
1748         switch (state) {
1749         case PL08X_CHAN_IDLE:
1750                 return "idle";
1751         case PL08X_CHAN_RUNNING:
1752                 return "running";
1753         case PL08X_CHAN_PAUSED:
1754                 return "paused";
1755         case PL08X_CHAN_WAITING:
1756                 return "waiting";
1757         default:
1758                 break;
1759         }
1760         return "UNKNOWN STATE";
1761 }
1762
1763 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1764 {
1765         struct pl08x_driver_data *pl08x = s->private;
1766         struct pl08x_dma_chan *chan;
1767         struct pl08x_phy_chan *ch;
1768         unsigned long flags;
1769         int i;
1770
1771         seq_printf(s, "PL08x physical channels:\n");
1772         seq_printf(s, "CHANNEL:\tUSER:\n");
1773         seq_printf(s, "--------\t-----\n");
1774         for (i = 0; i < pl08x->vd->channels; i++) {
1775                 struct pl08x_dma_chan *virt_chan;
1776
1777                 ch = &pl08x->phy_chans[i];
1778
1779                 spin_lock_irqsave(&ch->lock, flags);
1780                 virt_chan = ch->serving;
1781
1782                 seq_printf(s, "%d\t\t%s\n",
1783                            ch->id, virt_chan ? virt_chan->name : "(none)");
1784
1785                 spin_unlock_irqrestore(&ch->lock, flags);
1786         }
1787
1788         seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1789         seq_printf(s, "CHANNEL:\tSTATE:\n");
1790         seq_printf(s, "--------\t------\n");
1791         list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1792                 seq_printf(s, "%s\t\t%s\n", chan->name,
1793                            pl08x_state_str(chan->state));
1794         }
1795
1796         seq_printf(s, "\nPL08x virtual slave channels:\n");
1797         seq_printf(s, "CHANNEL:\tSTATE:\n");
1798         seq_printf(s, "--------\t------\n");
1799         list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1800                 seq_printf(s, "%s\t\t%s\n", chan->name,
1801                            pl08x_state_str(chan->state));
1802         }
1803
1804         return 0;
1805 }
1806
1807 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1808 {
1809         return single_open(file, pl08x_debugfs_show, inode->i_private);
1810 }
1811
1812 static const struct file_operations pl08x_debugfs_operations = {
1813         .open           = pl08x_debugfs_open,
1814         .read           = seq_read,
1815         .llseek         = seq_lseek,
1816         .release        = single_release,
1817 };
1818
1819 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1820 {
1821         /* Expose a simple debugfs interface to view all clocks */
1822         (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1823                                    NULL, pl08x,
1824                                    &pl08x_debugfs_operations);
1825 }
1826
1827 #else
1828 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1829 {
1830 }
1831 #endif
1832
1833 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1834 {
1835         struct pl08x_driver_data *pl08x;
1836         const struct vendor_data *vd = id->data;
1837         int ret = 0;
1838         int i;
1839
1840         ret = amba_request_regions(adev, NULL);
1841         if (ret)
1842                 return ret;
1843
1844         /* Create the driver state holder */
1845         pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1846         if (!pl08x) {
1847                 ret = -ENOMEM;
1848                 goto out_no_pl08x;
1849         }
1850
1851         /* Initialize memcpy engine */
1852         dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1853         pl08x->memcpy.dev = &adev->dev;
1854         pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1855         pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1856         pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1857         pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1858         pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1859         pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1860         pl08x->memcpy.device_control = pl08x_control;
1861
1862         /* Initialize slave engine */
1863         dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1864         pl08x->slave.dev = &adev->dev;
1865         pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1866         pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1867         pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1868         pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1869         pl08x->slave.device_issue_pending = pl08x_issue_pending;
1870         pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1871         pl08x->slave.device_control = pl08x_control;
1872
1873         /* Get the platform data */
1874         pl08x->pd = dev_get_platdata(&adev->dev);
1875         if (!pl08x->pd) {
1876                 dev_err(&adev->dev, "no platform data supplied\n");
1877                 goto out_no_platdata;
1878         }
1879
1880         /* Assign useful pointers to the driver state */
1881         pl08x->adev = adev;
1882         pl08x->vd = vd;
1883
1884         /* By default, AHB1 only.  If dualmaster, from platform */
1885         pl08x->lli_buses = PL08X_AHB1;
1886         pl08x->mem_buses = PL08X_AHB1;
1887         if (pl08x->vd->dualmaster) {
1888                 pl08x->lli_buses = pl08x->pd->lli_buses;
1889                 pl08x->mem_buses = pl08x->pd->mem_buses;
1890         }
1891
1892         /* A DMA memory pool for LLIs, align on 1-byte boundary */
1893         pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1894                         PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1895         if (!pl08x->pool) {
1896                 ret = -ENOMEM;
1897                 goto out_no_lli_pool;
1898         }
1899
1900         spin_lock_init(&pl08x->lock);
1901
1902         pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1903         if (!pl08x->base) {
1904                 ret = -ENOMEM;
1905                 goto out_no_ioremap;
1906         }
1907
1908         /* Turn on the PL08x */
1909         pl08x_ensure_on(pl08x);
1910
1911         /*
1912          * Attach the interrupt handler
1913          */
1914         writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1915         writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1916
1917         ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1918                           DRIVER_NAME, pl08x);
1919         if (ret) {
1920                 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1921                         __func__, adev->irq[0]);
1922                 goto out_no_irq;
1923         }
1924
1925         /* Initialize physical channels */
1926         pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1927                         GFP_KERNEL);
1928         if (!pl08x->phy_chans) {
1929                 dev_err(&adev->dev, "%s failed to allocate "
1930                         "physical channel holders\n",
1931                         __func__);
1932                 goto out_no_phychans;
1933         }
1934
1935         for (i = 0; i < vd->channels; i++) {
1936                 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1937
1938                 ch->id = i;
1939                 ch->base = pl08x->base + PL080_Cx_BASE(i);
1940                 spin_lock_init(&ch->lock);
1941                 ch->serving = NULL;
1942                 ch->signal = -1;
1943                 dev_info(&adev->dev,
1944                          "physical channel %d is %s\n", i,
1945                          pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1946         }
1947
1948         /* Register as many memcpy channels as there are physical channels */
1949         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1950                                               pl08x->vd->channels, false);
1951         if (ret <= 0) {
1952                 dev_warn(&pl08x->adev->dev,
1953                          "%s failed to enumerate memcpy channels - %d\n",
1954                          __func__, ret);
1955                 goto out_no_memcpy;
1956         }
1957         pl08x->memcpy.chancnt = ret;
1958
1959         /* Register slave channels */
1960         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
1961                                               pl08x->pd->num_slave_channels,
1962                                               true);
1963         if (ret <= 0) {
1964                 dev_warn(&pl08x->adev->dev,
1965                         "%s failed to enumerate slave channels - %d\n",
1966                                 __func__, ret);
1967                 goto out_no_slave;
1968         }
1969         pl08x->slave.chancnt = ret;
1970
1971         ret = dma_async_device_register(&pl08x->memcpy);
1972         if (ret) {
1973                 dev_warn(&pl08x->adev->dev,
1974                         "%s failed to register memcpy as an async device - %d\n",
1975                         __func__, ret);
1976                 goto out_no_memcpy_reg;
1977         }
1978
1979         ret = dma_async_device_register(&pl08x->slave);
1980         if (ret) {
1981                 dev_warn(&pl08x->adev->dev,
1982                         "%s failed to register slave as an async device - %d\n",
1983                         __func__, ret);
1984                 goto out_no_slave_reg;
1985         }
1986
1987         amba_set_drvdata(adev, pl08x);
1988         init_pl08x_debugfs(pl08x);
1989         dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
1990                  amba_part(adev), amba_rev(adev),
1991                  (unsigned long long)adev->res.start, adev->irq[0]);
1992         return 0;
1993
1994 out_no_slave_reg:
1995         dma_async_device_unregister(&pl08x->memcpy);
1996 out_no_memcpy_reg:
1997         pl08x_free_virtual_channels(&pl08x->slave);
1998 out_no_slave:
1999         pl08x_free_virtual_channels(&pl08x->memcpy);
2000 out_no_memcpy:
2001         kfree(pl08x->phy_chans);
2002 out_no_phychans:
2003         free_irq(adev->irq[0], pl08x);
2004 out_no_irq:
2005         iounmap(pl08x->base);
2006 out_no_ioremap:
2007         dma_pool_destroy(pl08x->pool);
2008 out_no_lli_pool:
2009 out_no_platdata:
2010         kfree(pl08x);
2011 out_no_pl08x:
2012         amba_release_regions(adev);
2013         return ret;
2014 }
2015
2016 /* PL080 has 8 channels and the PL080 have just 2 */
2017 static struct vendor_data vendor_pl080 = {
2018         .channels = 8,
2019         .dualmaster = true,
2020 };
2021
2022 static struct vendor_data vendor_pl081 = {
2023         .channels = 2,
2024         .dualmaster = false,
2025 };
2026
2027 static struct amba_id pl08x_ids[] = {
2028         /* PL080 */
2029         {
2030                 .id     = 0x00041080,
2031                 .mask   = 0x000fffff,
2032                 .data   = &vendor_pl080,
2033         },
2034         /* PL081 */
2035         {
2036                 .id     = 0x00041081,
2037                 .mask   = 0x000fffff,
2038                 .data   = &vendor_pl081,
2039         },
2040         /* Nomadik 8815 PL080 variant */
2041         {
2042                 .id     = 0x00280880,
2043                 .mask   = 0x00ffffff,
2044                 .data   = &vendor_pl080,
2045         },
2046         { 0, 0 },
2047 };
2048
2049 static struct amba_driver pl08x_amba_driver = {
2050         .drv.name       = DRIVER_NAME,
2051         .id_table       = pl08x_ids,
2052         .probe          = pl08x_probe,
2053 };
2054
2055 static int __init pl08x_init(void)
2056 {
2057         int retval;
2058         retval = amba_driver_register(&pl08x_amba_driver);
2059         if (retval)
2060                 printk(KERN_WARNING DRIVER_NAME
2061                        "failed to register as an AMBA device (%d)\n",
2062                        retval);
2063         return retval;
2064 }
2065 subsys_initcall(pl08x_init);