2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the
23 * file called COPYING.
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
69 * Only the former works sanely with scatter lists, so we only implement
70 * the DMAC flow control method. However, peripherals which use the LBREQ
71 * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72 * these hardware restrictions prevents them from using scatter DMA.
75 * - Break out common code from arch/arm/mach-s3c64xx and share
77 #include <linux/device.h>
78 #include <linux/init.h>
79 #include <linux/module.h>
80 #include <linux/interrupt.h>
81 #include <linux/slab.h>
82 #include <linux/dmapool.h>
83 #include <linux/dmaengine.h>
84 #include <linux/amba/bus.h>
85 #include <linux/amba/pl08x.h>
86 #include <linux/debugfs.h>
87 #include <linux/seq_file.h>
89 #include <asm/hardware/pl080.h>
91 #define DRIVER_NAME "pl08xdmac"
94 * struct vendor_data - vendor-specific config parameters
95 * for PL08x derivatives
96 * @channels: the number of channels available in this variant
97 * @dualmaster: whether this version supports dual AHB masters
106 * PL08X private data structures
107 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
108 * start & end do not - their bus bit info is in cctl.
118 * struct pl08x_driver_data - the local state holder for the PL08x
119 * @slave: slave engine for this instance
120 * @memcpy: memcpy engine for this instance
121 * @base: virtual memory base (remapped) for the PL08x
122 * @adev: the corresponding AMBA (PrimeCell) bus entry
123 * @vd: vendor data for this PL08x variant
124 * @pd: platform data passed in from the platform/machine
125 * @phy_chans: array of data for the physical channels
126 * @pool: a pool for the LLI descriptors
127 * @pool_ctr: counter of LLIs in the pool
128 * @lock: a spinlock for this struct
130 struct pl08x_driver_data {
131 struct dma_device slave;
132 struct dma_device memcpy;
134 struct amba_device *adev;
135 const struct vendor_data *vd;
136 struct pl08x_platform_data *pd;
137 struct pl08x_phy_chan *phy_chans;
138 struct dma_pool *pool;
144 * PL08X specific defines
148 * Memory boundaries: the manual for PL08x says that the controller
149 * cannot read past a 1KiB boundary, so these defines are used to
150 * create transfer LLIs that do not cross such boundaries.
152 #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
153 #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)
155 /* Minimum period between work queue runs */
156 #define PL08X_WQ_PERIODMIN 20
158 /* Size (bytes) of each LLI buffer allocated for one transfer */
159 # define PL08X_LLI_TSFR_SIZE 0x2000
161 /* Maximum times we call dma_pool_alloc on this pool without freeing */
162 #define PL08X_MAX_ALLOCS 0x40
163 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
164 #define PL08X_ALIGN 8
166 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
168 return container_of(chan, struct pl08x_dma_chan, chan);
172 * Physical channel handling
175 /* Whether a certain channel is busy or not */
176 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
180 val = readl(ch->base + PL080_CH_CONFIG);
181 return val & PL080_CONFIG_ACTIVE;
185 * Set the initial DMA register values i.e. those for the first LLI
186 * The next LLI pointer and the configuration interrupt bit have
187 * been set when the LLIs were constructed
189 static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
190 struct pl08x_phy_chan *ch)
192 /* Wait for channel inactive */
193 while (pl08x_phy_channel_busy(ch))
196 dev_vdbg(&pl08x->adev->dev,
197 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
198 "cctl=0x%08x, clli=0x%08x, ccfg=0x%08x\n",
206 writel(ch->csrc, ch->base + PL080_CH_SRC_ADDR);
207 writel(ch->cdst, ch->base + PL080_CH_DST_ADDR);
208 writel(ch->clli, ch->base + PL080_CH_LLI);
209 writel(ch->cctl, ch->base + PL080_CH_CONTROL);
210 writel(ch->ccfg, ch->base + PL080_CH_CONFIG);
213 static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan *plchan)
215 struct pl08x_channel_data *cd = plchan->cd;
216 struct pl08x_phy_chan *phychan = plchan->phychan;
217 struct pl08x_txd *txd = plchan->at;
219 /* Copy the basic control register calculated at transfer config */
220 phychan->csrc = txd->csrc;
221 phychan->cdst = txd->cdst;
222 phychan->clli = txd->clli;
223 phychan->cctl = txd->cctl;
225 /* Assign the signal to the proper control registers */
226 phychan->ccfg = cd->ccfg;
227 phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
228 phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
229 /* If it wasn't set from AMBA, ignore it */
230 if (txd->direction == DMA_TO_DEVICE)
231 /* Select signal as destination */
233 (phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
234 else if (txd->direction == DMA_FROM_DEVICE)
235 /* Select signal as source */
237 (phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
238 /* Always enable error interrupts */
239 phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
240 /* Always enable terminal interrupts */
241 phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
245 * Enable the DMA channel
246 * Assumes all other configuration bits have been set
247 * as desired before this code is called
249 static void pl08x_enable_phy_chan(struct pl08x_driver_data *pl08x,
250 struct pl08x_phy_chan *ch)
255 * Do not access config register until channel shows as disabled
257 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << ch->id))
261 * Do not access config register until channel shows as inactive
263 val = readl(ch->base + PL080_CH_CONFIG);
264 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
265 val = readl(ch->base + PL080_CH_CONFIG);
267 writel(val | PL080_CONFIG_ENABLE, ch->base + PL080_CH_CONFIG);
271 * Overall DMAC remains enabled always.
273 * Disabling individual channels could lose data.
275 * Disable the peripheral DMA after disabling the DMAC
276 * in order to allow the DMAC FIFO to drain, and
277 * hence allow the channel to show inactive
280 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
284 /* Set the HALT bit and wait for the FIFO to drain */
285 val = readl(ch->base + PL080_CH_CONFIG);
286 val |= PL080_CONFIG_HALT;
287 writel(val, ch->base + PL080_CH_CONFIG);
289 /* Wait for channel inactive */
290 while (pl08x_phy_channel_busy(ch))
294 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
298 /* Clear the HALT bit */
299 val = readl(ch->base + PL080_CH_CONFIG);
300 val &= ~PL080_CONFIG_HALT;
301 writel(val, ch->base + PL080_CH_CONFIG);
305 /* Stops the channel */
306 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
310 pl08x_pause_phy_chan(ch);
312 /* Disable channel */
313 val = readl(ch->base + PL080_CH_CONFIG);
314 val &= ~PL080_CONFIG_ENABLE;
315 val &= ~PL080_CONFIG_ERR_IRQ_MASK;
316 val &= ~PL080_CONFIG_TC_IRQ_MASK;
317 writel(val, ch->base + PL080_CH_CONFIG);
320 static inline u32 get_bytes_in_cctl(u32 cctl)
322 /* The source width defines the number of bytes */
323 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
325 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
326 case PL080_WIDTH_8BIT:
328 case PL080_WIDTH_16BIT:
331 case PL080_WIDTH_32BIT:
338 /* The channel should be paused when calling this */
339 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
341 struct pl08x_phy_chan *ch;
342 struct pl08x_txd *txdi = NULL;
343 struct pl08x_txd *txd;
347 spin_lock_irqsave(&plchan->lock, flags);
349 ch = plchan->phychan;
353 * Next follow the LLIs to get the number of pending bytes in the
354 * currently active transaction.
357 struct pl08x_lli *llis_va = txd->llis_va;
358 struct pl08x_lli *llis_bus = (struct pl08x_lli *) txd->llis_bus;
359 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
361 /* First get the bytes in the current active LLI */
362 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
367 /* Forward to the LLI pointed to by clli */
368 while ((clli != (u32) &(llis_bus[i])) &&
369 (i < MAX_NUM_TSFR_LLIS))
373 bytes += get_bytes_in_cctl(llis_va[i].cctl);
375 * A LLI pointer of 0 terminates the LLI list
377 clli = llis_va[i].next;
383 /* Sum up all queued transactions */
384 if (!list_empty(&plchan->desc_list)) {
385 list_for_each_entry(txdi, &plchan->desc_list, node) {
391 spin_unlock_irqrestore(&plchan->lock, flags);
397 * Allocate a physical channel for a virtual channel
399 static struct pl08x_phy_chan *
400 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
401 struct pl08x_dma_chan *virt_chan)
403 struct pl08x_phy_chan *ch = NULL;
408 * Try to locate a physical channel to be used for
409 * this transfer. If all are taken return NULL and
410 * the requester will have to cope by using some fallback
411 * PIO mode or retrying later.
413 for (i = 0; i < pl08x->vd->channels; i++) {
414 ch = &pl08x->phy_chans[i];
416 spin_lock_irqsave(&ch->lock, flags);
419 ch->serving = virt_chan;
421 spin_unlock_irqrestore(&ch->lock, flags);
425 spin_unlock_irqrestore(&ch->lock, flags);
428 if (i == pl08x->vd->channels) {
429 /* No physical channel available, cope with it */
436 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
437 struct pl08x_phy_chan *ch)
441 /* Stop the channel and clear its interrupts */
442 pl08x_stop_phy_chan(ch);
443 writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
444 writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
446 /* Mark it as free */
447 spin_lock_irqsave(&ch->lock, flags);
449 spin_unlock_irqrestore(&ch->lock, flags);
456 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
459 case PL080_WIDTH_8BIT:
461 case PL080_WIDTH_16BIT:
463 case PL080_WIDTH_32BIT:
472 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
477 /* Remove all src, dst and transfer size bits */
478 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
479 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
480 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
482 /* Then set the bits according to the parameters */
485 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
488 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
491 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
500 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
503 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
506 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
513 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
518 * Autoselect a master bus to use for the transfer
519 * this prefers the destination bus if both available
520 * if fixed address on one bus the other will be chosen
522 static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
523 struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
524 struct pl08x_bus_data **sbus, u32 cctl)
526 if (!(cctl & PL080_CONTROL_DST_INCR)) {
529 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
533 if (dst_bus->buswidth == 4) {
536 } else if (src_bus->buswidth == 4) {
539 } else if (dst_bus->buswidth == 2) {
542 } else if (src_bus->buswidth == 2) {
546 /* src_bus->buswidth == 1 */
554 * Fills in one LLI for a certain transfer descriptor
555 * and advance the counter
557 static int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
558 struct pl08x_txd *txd, int num_llis, int len,
559 u32 cctl, u32 *remainder)
561 struct pl08x_lli *llis_va = txd->llis_va;
562 dma_addr_t llis_bus = txd->llis_bus;
564 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
566 llis_va[num_llis].cctl = cctl;
567 llis_va[num_llis].src = txd->srcbus.addr;
568 llis_va[num_llis].dst = txd->dstbus.addr;
571 * On versions with dual masters, you can optionally AND on
572 * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
573 * in new LLIs with that controller, but we always try to
574 * choose AHB1 to point into memory. The idea is to have AHB2
575 * fixed on the peripheral and AHB1 messing around in the
576 * memory. So we don't manipulate this bit currently.
579 llis_va[num_llis].next = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
581 if (cctl & PL080_CONTROL_SRC_INCR)
582 txd->srcbus.addr += len;
583 if (cctl & PL080_CONTROL_DST_INCR)
584 txd->dstbus.addr += len;
586 BUG_ON(*remainder < len);
594 * Return number of bytes to fill to boundary, or len
596 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
600 boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
601 << PL08X_BOUNDARY_SHIFT;
603 if (boundary < addr + len)
604 return boundary - addr;
610 * This fills in the table of LLIs for the transfer descriptor
611 * Note that we assume we never have to change the burst sizes
614 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
615 struct pl08x_txd *txd)
617 struct pl08x_channel_data *cd = txd->cd;
618 struct pl08x_bus_data *mbus, *sbus;
622 size_t max_bytes_per_lli;
623 size_t total_bytes = 0;
624 struct pl08x_lli *llis_va;
626 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
629 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
636 * Initialize bus values for this transfer
637 * from the passed optimal values
640 dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
644 /* Get the default CCTL from the platform data */
648 * On the PL080 we have two bus masters and we
649 * should select one for source and one for
650 * destination. We try to use AHB2 for the
651 * bus which does not increment (typically the
652 * peripheral) else we just choose something.
654 cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
655 if (pl08x->vd->dualmaster) {
656 if (cctl & PL080_CONTROL_SRC_INCR)
657 /* Source increments, use AHB2 for destination */
658 cctl |= PL080_CONTROL_DST_AHB2;
659 else if (cctl & PL080_CONTROL_DST_INCR)
660 /* Destination increments, use AHB2 for source */
661 cctl |= PL080_CONTROL_SRC_AHB2;
663 /* Just pick something, source AHB1 dest AHB2 */
664 cctl |= PL080_CONTROL_DST_AHB2;
667 /* Find maximum width of the source bus */
668 txd->srcbus.maxwidth =
669 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
670 PL080_CONTROL_SWIDTH_SHIFT);
672 /* Find maximum width of the destination bus */
673 txd->dstbus.maxwidth =
674 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
675 PL080_CONTROL_DWIDTH_SHIFT);
677 /* Set up the bus widths to the maximum */
678 txd->srcbus.buswidth = txd->srcbus.maxwidth;
679 txd->dstbus.buswidth = txd->dstbus.maxwidth;
680 dev_vdbg(&pl08x->adev->dev,
681 "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
682 __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
686 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
688 max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
689 PL080_CONTROL_TRANSFER_SIZE_MASK;
690 dev_vdbg(&pl08x->adev->dev,
691 "%s max bytes per lli = %zu\n",
692 __func__, max_bytes_per_lli);
694 /* We need to count this down to zero */
695 remainder = txd->len;
696 dev_vdbg(&pl08x->adev->dev,
697 "%s remainder = %zu\n",
698 __func__, remainder);
701 * Choose bus to align to
702 * - prefers destination bus if both available
703 * - if fixed address on one bus chooses other
704 * - modifies cctl to choose an appropriate master
706 pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
711 * The lowest bit of the LLI register
712 * is also used to indicate which master to
713 * use for reading the LLIs.
716 if (txd->len < mbus->buswidth) {
718 * Less than a bus width available
719 * - send as single bytes
722 dev_vdbg(&pl08x->adev->dev,
723 "%s single byte LLIs for a transfer of "
724 "less than a bus width (remain 0x%08x)\n",
725 __func__, remainder);
726 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
728 pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
734 * Make one byte LLIs until master bus is aligned
735 * - slave will then be aligned also
737 while ((mbus->addr) % (mbus->buswidth)) {
738 dev_vdbg(&pl08x->adev->dev,
739 "%s adjustment lli for less than bus width "
741 __func__, remainder);
742 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
743 num_llis = pl08x_fill_lli_for_desc
744 (pl08x, txd, num_llis, 1, cctl, &remainder);
750 * - if slave is not then we must set its width down
752 if (sbus->addr % sbus->buswidth) {
753 dev_dbg(&pl08x->adev->dev,
754 "%s set down bus width to one byte\n",
761 * Make largest possible LLIs until less than one bus
764 while (remainder > (mbus->buswidth - 1)) {
765 size_t lli_len, target_len, tsize, odd_bytes;
768 * If enough left try to send max possible,
769 * otherwise try to send the remainder
771 target_len = remainder;
772 if (remainder > max_bytes_per_lli)
773 target_len = max_bytes_per_lli;
776 * Set bus lengths for incrementing buses
777 * to number of bytes which fill to next memory
780 if (cctl & PL080_CONTROL_SRC_INCR)
781 txd->srcbus.fill_bytes =
786 txd->srcbus.fill_bytes =
789 if (cctl & PL080_CONTROL_DST_INCR)
790 txd->dstbus.fill_bytes =
795 txd->dstbus.fill_bytes =
801 lli_len = min(txd->srcbus.fill_bytes,
802 txd->dstbus.fill_bytes);
804 BUG_ON(lli_len > remainder);
807 dev_err(&pl08x->adev->dev,
808 "%s lli_len is %zu, <= 0\n",
813 if (lli_len == target_len) {
815 * Can send what we wanted
820 lli_len = (lli_len/mbus->buswidth) *
825 * So now we know how many bytes to transfer
826 * to get to the nearest boundary
827 * The next LLI will past the boundary
828 * - however we may be working to a boundary
830 * We need to ensure the master stays aligned
832 odd_bytes = lli_len % mbus->buswidth;
834 * - and that we are working in multiples
837 lli_len -= odd_bytes;
843 * Check against minimum bus alignment:
844 * Calculate actual transfer size in relation
845 * to bus width an get a maximum remainder of
846 * the smallest bus width - 1
848 /* FIXME: use round_down()? */
849 tsize = lli_len / min(mbus->buswidth,
851 lli_len = tsize * min(mbus->buswidth,
854 if (target_len != lli_len) {
855 dev_vdbg(&pl08x->adev->dev,
856 "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
857 __func__, target_len, lli_len, txd->len);
860 cctl = pl08x_cctl_bits(cctl,
861 txd->srcbus.buswidth,
862 txd->dstbus.buswidth,
865 dev_vdbg(&pl08x->adev->dev,
866 "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
867 __func__, lli_len, remainder);
868 num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
869 num_llis, lli_len, cctl,
871 total_bytes += lli_len;
877 * Creep past the boundary,
878 * maintaining master alignment
881 for (j = 0; (j < mbus->buswidth)
882 && (remainder); j++) {
883 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
884 dev_vdbg(&pl08x->adev->dev,
885 "%s align with boundary, single byte (remain 0x%08zx)\n",
886 __func__, remainder);
888 pl08x_fill_lli_for_desc(pl08x,
900 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
901 dev_vdbg(&pl08x->adev->dev,
902 "%s align with boundary, single odd byte (remain %zu)\n",
903 __func__, remainder);
904 num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
905 1, cctl, &remainder);
909 if (total_bytes != txd->len) {
910 dev_err(&pl08x->adev->dev,
911 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
912 __func__, total_bytes, txd->len);
916 if (num_llis >= MAX_NUM_TSFR_LLIS) {
917 dev_err(&pl08x->adev->dev,
918 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
919 __func__, (u32) MAX_NUM_TSFR_LLIS);
923 llis_va = txd->llis_va;
925 * The final LLI terminates the LLI.
927 llis_va[num_llis - 1].next = 0;
929 * The final LLI element shall also fire an interrupt
931 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
933 /* Now store the channel register values */
934 txd->csrc = llis_va[0].src;
935 txd->cdst = llis_va[0].dst;
936 txd->clli = llis_va[0].next;
937 txd->cctl = llis_va[0].cctl;
938 /* ccfg will be set at physical channel allocation time */
944 for (i = 0; i < num_llis; i++) {
945 dev_vdbg(&pl08x->adev->dev,
946 "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
961 /* You should call this with the struct pl08x lock held */
962 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
963 struct pl08x_txd *txd)
966 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
973 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
974 struct pl08x_dma_chan *plchan)
976 struct pl08x_txd *txdi = NULL;
977 struct pl08x_txd *next;
979 if (!list_empty(&plchan->desc_list)) {
980 list_for_each_entry_safe(txdi,
981 next, &plchan->desc_list, node) {
982 list_del(&txdi->node);
983 pl08x_free_txd(pl08x, txdi);
992 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
997 static void pl08x_free_chan_resources(struct dma_chan *chan)
1002 * This should be called with the channel plchan->lock held
1004 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
1005 struct pl08x_txd *txd)
1007 struct pl08x_driver_data *pl08x = plchan->host;
1008 struct pl08x_phy_chan *ch;
1011 /* Check if we already have a channel */
1012 if (plchan->phychan)
1015 ch = pl08x_get_phy_channel(pl08x, plchan);
1017 /* No physical channel available, cope with it */
1018 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
1023 * OK we have a physical channel: for memcpy() this is all we
1024 * need, but for slaves the physical signals may be muxed!
1025 * Can the platform allow us to use this channel?
1027 if (plchan->slave &&
1029 pl08x->pd->get_signal) {
1030 ret = pl08x->pd->get_signal(plchan);
1032 dev_dbg(&pl08x->adev->dev,
1033 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1034 ch->id, plchan->name);
1035 /* Release physical channel & return */
1036 pl08x_put_phy_channel(pl08x, ch);
1042 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
1047 plchan->phychan = ch;
1052 static void release_phy_channel(struct pl08x_dma_chan *plchan)
1054 struct pl08x_driver_data *pl08x = plchan->host;
1056 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
1057 pl08x->pd->put_signal(plchan);
1058 plchan->phychan->signal = -1;
1060 pl08x_put_phy_channel(pl08x, plchan->phychan);
1061 plchan->phychan = NULL;
1064 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
1066 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
1068 plchan->chan.cookie += 1;
1069 if (plchan->chan.cookie < 0)
1070 plchan->chan.cookie = 1;
1071 tx->cookie = plchan->chan.cookie;
1072 /* This unlock follows the lock in the prep() function */
1073 spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1078 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1079 struct dma_chan *chan, unsigned long flags)
1081 struct dma_async_tx_descriptor *retval = NULL;
1087 * Code accessing dma_async_is_complete() in a tight loop
1088 * may give problems - could schedule where indicated.
1089 * If slaves are relying on interrupts to signal completion this
1090 * function must not be called with interrupts disabled
1092 static enum dma_status
1093 pl08x_dma_tx_status(struct dma_chan *chan,
1094 dma_cookie_t cookie,
1095 struct dma_tx_state *txstate)
1097 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1098 dma_cookie_t last_used;
1099 dma_cookie_t last_complete;
1100 enum dma_status ret;
1103 last_used = plchan->chan.cookie;
1104 last_complete = plchan->lc;
1106 ret = dma_async_is_complete(cookie, last_complete, last_used);
1107 if (ret == DMA_SUCCESS) {
1108 dma_set_tx_state(txstate, last_complete, last_used, 0);
1113 * schedule(); could be inserted here
1117 * This cookie not complete yet
1119 last_used = plchan->chan.cookie;
1120 last_complete = plchan->lc;
1122 /* Get number of bytes left in the active transactions and queue */
1123 bytesleft = pl08x_getbytes_chan(plchan);
1125 dma_set_tx_state(txstate, last_complete, last_used,
1128 if (plchan->state == PL08X_CHAN_PAUSED)
1131 /* Whether waiting or running, we're in progress */
1132 return DMA_IN_PROGRESS;
1135 /* PrimeCell DMA extension */
1136 struct burst_table {
1141 static const struct burst_table burst_sizes[] = {
1144 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1145 (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1149 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1150 (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1154 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1155 (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1159 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1160 (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1164 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1165 (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1169 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1170 (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1174 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1175 (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1179 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1180 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1184 static void dma_set_runtime_config(struct dma_chan *chan,
1185 struct dma_slave_config *config)
1187 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1188 struct pl08x_driver_data *pl08x = plchan->host;
1189 struct pl08x_channel_data *cd = plchan->cd;
1190 enum dma_slave_buswidth addr_width;
1193 /* Mask out all except src and dst channel */
1194 u32 ccfg = cd->ccfg & 0x000003DEU;
1197 /* Transfer direction */
1198 plchan->runtime_direction = config->direction;
1199 if (config->direction == DMA_TO_DEVICE) {
1200 plchan->runtime_addr = config->dst_addr;
1201 cctl |= PL080_CONTROL_SRC_INCR;
1202 ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1203 addr_width = config->dst_addr_width;
1204 maxburst = config->dst_maxburst;
1205 } else if (config->direction == DMA_FROM_DEVICE) {
1206 plchan->runtime_addr = config->src_addr;
1207 cctl |= PL080_CONTROL_DST_INCR;
1208 ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1209 addr_width = config->src_addr_width;
1210 maxburst = config->src_maxburst;
1212 dev_err(&pl08x->adev->dev,
1213 "bad runtime_config: alien transfer direction\n");
1217 switch (addr_width) {
1218 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1219 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1220 (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1222 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1223 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1224 (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1226 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1227 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1228 (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1231 dev_err(&pl08x->adev->dev,
1232 "bad runtime_config: alien address width\n");
1237 * Now decide on a maxburst:
1238 * If this channel will only request single transfers, set this
1239 * down to ONE element. Also select one element if no maxburst
1242 if (plchan->cd->single || maxburst == 0) {
1243 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1244 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1246 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1247 if (burst_sizes[i].burstwords <= maxburst)
1249 cctl |= burst_sizes[i].reg;
1252 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1253 cctl &= ~PL080_CONTROL_PROT_MASK;
1254 cctl |= PL080_CONTROL_PROT_SYS;
1256 /* Modify the default channel data to fit PrimeCell request */
1260 dev_dbg(&pl08x->adev->dev,
1261 "configured channel %s (%s) for %s, data width %d, "
1262 "maxburst %d words, LE, CCTL=0x%08x, CCFG=0x%08x\n",
1263 dma_chan_name(chan), plchan->name,
1264 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1271 * Slave transactions callback to the slave device to allow
1272 * synchronization of slave DMA signals with the DMAC enable
1274 static void pl08x_issue_pending(struct dma_chan *chan)
1276 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1277 struct pl08x_driver_data *pl08x = plchan->host;
1278 unsigned long flags;
1280 spin_lock_irqsave(&plchan->lock, flags);
1281 /* Something is already active, or we're waiting for a channel... */
1282 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1283 spin_unlock_irqrestore(&plchan->lock, flags);
1287 /* Take the first element in the queue and execute it */
1288 if (!list_empty(&plchan->desc_list)) {
1289 struct pl08x_txd *next;
1291 next = list_first_entry(&plchan->desc_list,
1294 list_del(&next->node);
1296 plchan->state = PL08X_CHAN_RUNNING;
1298 /* Configure the physical channel for the active txd */
1299 pl08x_config_phychan_for_txd(plchan);
1300 pl08x_set_cregs(pl08x, plchan->phychan);
1301 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1304 spin_unlock_irqrestore(&plchan->lock, flags);
1307 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1308 struct pl08x_txd *txd)
1311 struct pl08x_driver_data *pl08x = plchan->host;
1314 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1320 spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1322 list_add_tail(&txd->node, &plchan->desc_list);
1325 * See if we already have a physical channel allocated,
1326 * else this is the time to try to get one.
1328 ret = prep_phy_channel(plchan, txd);
1331 * No physical channel available, we will
1332 * stack up the memcpy channels until there is a channel
1333 * available to handle it whereas slave transfers may
1334 * have been denied due to platform channel muxing restrictions
1335 * and since there is no guarantee that this will ever be
1336 * resolved, and since the signal must be acquired AFTER
1337 * acquiring the physical channel, we will let them be NACK:ed
1338 * with -EBUSY here. The drivers can alway retry the prep()
1339 * call if they are eager on doing this using DMA.
1341 if (plchan->slave) {
1342 pl08x_free_txd_list(pl08x, plchan);
1343 spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1346 /* Do this memcpy whenever there is a channel ready */
1347 plchan->state = PL08X_CHAN_WAITING;
1348 plchan->waiting = txd;
1351 * Else we're all set, paused and ready to roll,
1352 * status will switch to PL08X_CHAN_RUNNING when
1353 * we call issue_pending(). If there is something
1354 * running on the channel already we don't change
1357 if (plchan->state == PL08X_CHAN_IDLE)
1358 plchan->state = PL08X_CHAN_PAUSED;
1361 * Notice that we leave plchan->lock locked on purpose:
1362 * it will be unlocked in the subsequent tx_submit()
1363 * call. This is a consequence of the current API.
1369 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1371 struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1374 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1375 txd->tx.tx_submit = pl08x_tx_submit;
1376 INIT_LIST_HEAD(&txd->node);
1382 * Initialize a descriptor to be used by memcpy submit
1384 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1385 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1386 size_t len, unsigned long flags)
1388 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1389 struct pl08x_driver_data *pl08x = plchan->host;
1390 struct pl08x_txd *txd;
1393 txd = pl08x_get_txd(plchan);
1395 dev_err(&pl08x->adev->dev,
1396 "%s no memory for descriptor\n", __func__);
1400 txd->direction = DMA_NONE;
1401 txd->srcbus.addr = src;
1402 txd->dstbus.addr = dest;
1404 /* Set platform data for m2m */
1405 txd->cd = &pl08x->pd->memcpy_channel;
1406 /* Both to be incremented or the code will break */
1407 txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1410 ret = pl08x_prep_channel_resources(plchan, txd);
1414 * NB: the channel lock is held at this point so tx_submit()
1415 * must be called in direct succession.
1421 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1422 struct dma_chan *chan, struct scatterlist *sgl,
1423 unsigned int sg_len, enum dma_data_direction direction,
1424 unsigned long flags)
1426 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1427 struct pl08x_driver_data *pl08x = plchan->host;
1428 struct pl08x_txd *txd;
1432 * Current implementation ASSUMES only one sg
1435 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1440 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1441 __func__, sgl->length, plchan->name);
1443 txd = pl08x_get_txd(plchan);
1445 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1449 if (direction != plchan->runtime_direction)
1450 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1451 "the direction configured for the PrimeCell\n",
1455 * Set up addresses, the PrimeCell configured address
1456 * will take precedence since this may configure the
1457 * channel target address dynamically at runtime.
1459 txd->direction = direction;
1460 if (direction == DMA_TO_DEVICE) {
1461 txd->srcbus.addr = sgl->dma_address;
1462 if (plchan->runtime_addr)
1463 txd->dstbus.addr = plchan->runtime_addr;
1465 txd->dstbus.addr = plchan->cd->addr;
1466 } else if (direction == DMA_FROM_DEVICE) {
1467 if (plchan->runtime_addr)
1468 txd->srcbus.addr = plchan->runtime_addr;
1470 txd->srcbus.addr = plchan->cd->addr;
1471 txd->dstbus.addr = sgl->dma_address;
1473 dev_err(&pl08x->adev->dev,
1474 "%s direction unsupported\n", __func__);
1477 txd->cd = plchan->cd;
1478 txd->len = sgl->length;
1480 ret = pl08x_prep_channel_resources(plchan, txd);
1484 * NB: the channel lock is held at this point so tx_submit()
1485 * must be called in direct succession.
1491 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1494 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1495 struct pl08x_driver_data *pl08x = plchan->host;
1496 unsigned long flags;
1499 /* Controls applicable to inactive channels */
1500 if (cmd == DMA_SLAVE_CONFIG) {
1501 dma_set_runtime_config(chan,
1502 (struct dma_slave_config *)
1508 * Anything succeeds on channels with no physical allocation and
1509 * no queued transfers.
1511 spin_lock_irqsave(&plchan->lock, flags);
1512 if (!plchan->phychan && !plchan->at) {
1513 spin_unlock_irqrestore(&plchan->lock, flags);
1518 case DMA_TERMINATE_ALL:
1519 plchan->state = PL08X_CHAN_IDLE;
1521 if (plchan->phychan) {
1522 pl08x_stop_phy_chan(plchan->phychan);
1525 * Mark physical channel as free and free any slave
1528 release_phy_channel(plchan);
1530 /* Dequeue jobs and free LLIs */
1532 pl08x_free_txd(pl08x, plchan->at);
1535 /* Dequeue jobs not yet fired as well */
1536 pl08x_free_txd_list(pl08x, plchan);
1539 pl08x_pause_phy_chan(plchan->phychan);
1540 plchan->state = PL08X_CHAN_PAUSED;
1543 pl08x_resume_phy_chan(plchan->phychan);
1544 plchan->state = PL08X_CHAN_RUNNING;
1547 /* Unknown command */
1552 spin_unlock_irqrestore(&plchan->lock, flags);
1557 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1559 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1560 char *name = chan_id;
1562 /* Check that the channel is not taken! */
1563 if (!strcmp(plchan->name, name))
1570 * Just check that the device is there and active
1571 * TODO: turn this bit on/off depending on the number of
1572 * physical channels actually used, if it is zero... well
1573 * shut it off. That will save some power. Cut the clock
1576 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1580 val = readl(pl08x->base + PL080_CONFIG);
1581 val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1582 /* We implicitly clear bit 1 and that means little-endian mode */
1583 val |= PL080_CONFIG_ENABLE;
1584 writel(val, pl08x->base + PL080_CONFIG);
1587 static void pl08x_tasklet(unsigned long data)
1589 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1590 struct pl08x_driver_data *pl08x = plchan->host;
1591 unsigned long flags;
1593 spin_lock_irqsave(&plchan->lock, flags);
1596 dma_async_tx_callback callback =
1597 plchan->at->tx.callback;
1598 void *callback_param =
1599 plchan->at->tx.callback_param;
1602 * Update last completed
1604 plchan->lc = plchan->at->tx.cookie;
1607 * Callback to signal completion
1610 callback(callback_param);
1613 * Free the descriptor
1615 pl08x_free_txd(pl08x, plchan->at);
1619 * If a new descriptor is queued, set it up
1620 * plchan->at is NULL here
1622 if (!list_empty(&plchan->desc_list)) {
1623 struct pl08x_txd *next;
1625 next = list_first_entry(&plchan->desc_list,
1628 list_del(&next->node);
1630 /* Configure the physical channel for the next txd */
1631 pl08x_config_phychan_for_txd(plchan);
1632 pl08x_set_cregs(pl08x, plchan->phychan);
1633 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1635 struct pl08x_dma_chan *waiting = NULL;
1638 * No more jobs, so free up the physical channel
1639 * Free any allocated signal on slave transfers too
1641 release_phy_channel(plchan);
1642 plchan->state = PL08X_CHAN_IDLE;
1645 * And NOW before anyone else can grab that free:d
1646 * up physical channel, see if there is some memcpy
1647 * pending that seriously needs to start because of
1648 * being stacked up while we were choking the
1649 * physical channels with data.
1651 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1653 if (waiting->state == PL08X_CHAN_WAITING &&
1654 waiting->waiting != NULL) {
1657 /* This should REALLY not fail now */
1658 ret = prep_phy_channel(waiting,
1661 waiting->state = PL08X_CHAN_RUNNING;
1662 waiting->waiting = NULL;
1663 pl08x_issue_pending(&waiting->chan);
1669 spin_unlock_irqrestore(&plchan->lock, flags);
1672 static irqreturn_t pl08x_irq(int irq, void *dev)
1674 struct pl08x_driver_data *pl08x = dev;
1679 val = readl(pl08x->base + PL080_ERR_STATUS);
1682 * An error interrupt (on one or more channels)
1684 dev_err(&pl08x->adev->dev,
1685 "%s error interrupt, register value 0x%08x\n",
1688 * Simply clear ALL PL08X error interrupts,
1689 * regardless of channel and cause
1690 * FIXME: should be 0x00000003 on PL081 really.
1692 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1694 val = readl(pl08x->base + PL080_INT_STATUS);
1695 for (i = 0; i < pl08x->vd->channels; i++) {
1696 if ((1 << i) & val) {
1697 /* Locate physical channel */
1698 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1699 struct pl08x_dma_chan *plchan = phychan->serving;
1701 /* Schedule tasklet on this channel */
1702 tasklet_schedule(&plchan->tasklet);
1708 * Clear only the terminal interrupts on channels we processed
1710 writel(mask, pl08x->base + PL080_TC_CLEAR);
1712 return mask ? IRQ_HANDLED : IRQ_NONE;
1716 * Initialise the DMAC memcpy/slave channels.
1717 * Make a local wrapper to hold required data
1719 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1720 struct dma_device *dmadev,
1721 unsigned int channels,
1724 struct pl08x_dma_chan *chan;
1727 INIT_LIST_HEAD(&dmadev->channels);
1729 * Register as many many memcpy as we have physical channels,
1730 * we won't always be able to use all but the code will have
1731 * to cope with that situation.
1733 for (i = 0; i < channels; i++) {
1734 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1736 dev_err(&pl08x->adev->dev,
1737 "%s no memory for channel\n", __func__);
1742 chan->state = PL08X_CHAN_IDLE;
1746 chan->name = pl08x->pd->slave_channels[i].bus_id;
1747 chan->cd = &pl08x->pd->slave_channels[i];
1749 chan->cd = &pl08x->pd->memcpy_channel;
1750 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1756 if (chan->cd->circular_buffer) {
1757 dev_err(&pl08x->adev->dev,
1758 "channel %s: circular buffers not supported\n",
1763 dev_info(&pl08x->adev->dev,
1764 "initialize virtual channel \"%s\"\n",
1767 chan->chan.device = dmadev;
1768 chan->chan.cookie = 0;
1771 spin_lock_init(&chan->lock);
1772 INIT_LIST_HEAD(&chan->desc_list);
1773 tasklet_init(&chan->tasklet, pl08x_tasklet,
1774 (unsigned long) chan);
1776 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1778 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1779 i, slave ? "slave" : "memcpy");
1783 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1785 struct pl08x_dma_chan *chan = NULL;
1786 struct pl08x_dma_chan *next;
1788 list_for_each_entry_safe(chan,
1789 next, &dmadev->channels, chan.device_node) {
1790 list_del(&chan->chan.device_node);
1795 #ifdef CONFIG_DEBUG_FS
1796 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1799 case PL08X_CHAN_IDLE:
1801 case PL08X_CHAN_RUNNING:
1803 case PL08X_CHAN_PAUSED:
1805 case PL08X_CHAN_WAITING:
1810 return "UNKNOWN STATE";
1813 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1815 struct pl08x_driver_data *pl08x = s->private;
1816 struct pl08x_dma_chan *chan;
1817 struct pl08x_phy_chan *ch;
1818 unsigned long flags;
1821 seq_printf(s, "PL08x physical channels:\n");
1822 seq_printf(s, "CHANNEL:\tUSER:\n");
1823 seq_printf(s, "--------\t-----\n");
1824 for (i = 0; i < pl08x->vd->channels; i++) {
1825 struct pl08x_dma_chan *virt_chan;
1827 ch = &pl08x->phy_chans[i];
1829 spin_lock_irqsave(&ch->lock, flags);
1830 virt_chan = ch->serving;
1832 seq_printf(s, "%d\t\t%s\n",
1833 ch->id, virt_chan ? virt_chan->name : "(none)");
1835 spin_unlock_irqrestore(&ch->lock, flags);
1838 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1839 seq_printf(s, "CHANNEL:\tSTATE:\n");
1840 seq_printf(s, "--------\t------\n");
1841 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1842 seq_printf(s, "%s\t\t%s\n", chan->name,
1843 pl08x_state_str(chan->state));
1846 seq_printf(s, "\nPL08x virtual slave channels:\n");
1847 seq_printf(s, "CHANNEL:\tSTATE:\n");
1848 seq_printf(s, "--------\t------\n");
1849 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1850 seq_printf(s, "%s\t\t%s\n", chan->name,
1851 pl08x_state_str(chan->state));
1857 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1859 return single_open(file, pl08x_debugfs_show, inode->i_private);
1862 static const struct file_operations pl08x_debugfs_operations = {
1863 .open = pl08x_debugfs_open,
1865 .llseek = seq_lseek,
1866 .release = single_release,
1869 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1871 /* Expose a simple debugfs interface to view all clocks */
1872 (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1874 &pl08x_debugfs_operations);
1878 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1883 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1885 struct pl08x_driver_data *pl08x;
1886 const struct vendor_data *vd = id->data;
1890 ret = amba_request_regions(adev, NULL);
1894 /* Create the driver state holder */
1895 pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1901 /* Initialize memcpy engine */
1902 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1903 pl08x->memcpy.dev = &adev->dev;
1904 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1905 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1906 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1907 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1908 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1909 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1910 pl08x->memcpy.device_control = pl08x_control;
1912 /* Initialize slave engine */
1913 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1914 pl08x->slave.dev = &adev->dev;
1915 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1916 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1917 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1918 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1919 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1920 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1921 pl08x->slave.device_control = pl08x_control;
1923 /* Get the platform data */
1924 pl08x->pd = dev_get_platdata(&adev->dev);
1926 dev_err(&adev->dev, "no platform data supplied\n");
1927 goto out_no_platdata;
1930 /* Assign useful pointers to the driver state */
1934 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1935 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1936 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1939 goto out_no_lli_pool;
1942 spin_lock_init(&pl08x->lock);
1944 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1947 goto out_no_ioremap;
1950 /* Turn on the PL08x */
1951 pl08x_ensure_on(pl08x);
1954 * Attach the interrupt handler
1956 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1957 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1959 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1960 DRIVER_NAME, pl08x);
1962 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1963 __func__, adev->irq[0]);
1967 /* Initialize physical channels */
1968 pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1970 if (!pl08x->phy_chans) {
1971 dev_err(&adev->dev, "%s failed to allocate "
1972 "physical channel holders\n",
1974 goto out_no_phychans;
1977 for (i = 0; i < vd->channels; i++) {
1978 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1981 ch->base = pl08x->base + PL080_Cx_BASE(i);
1982 spin_lock_init(&ch->lock);
1985 dev_info(&adev->dev,
1986 "physical channel %d is %s\n", i,
1987 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1990 /* Register as many memcpy channels as there are physical channels */
1991 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1992 pl08x->vd->channels, false);
1994 dev_warn(&pl08x->adev->dev,
1995 "%s failed to enumerate memcpy channels - %d\n",
1999 pl08x->memcpy.chancnt = ret;
2001 /* Register slave channels */
2002 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2003 pl08x->pd->num_slave_channels,
2006 dev_warn(&pl08x->adev->dev,
2007 "%s failed to enumerate slave channels - %d\n",
2011 pl08x->slave.chancnt = ret;
2013 ret = dma_async_device_register(&pl08x->memcpy);
2015 dev_warn(&pl08x->adev->dev,
2016 "%s failed to register memcpy as an async device - %d\n",
2018 goto out_no_memcpy_reg;
2021 ret = dma_async_device_register(&pl08x->slave);
2023 dev_warn(&pl08x->adev->dev,
2024 "%s failed to register slave as an async device - %d\n",
2026 goto out_no_slave_reg;
2029 amba_set_drvdata(adev, pl08x);
2030 init_pl08x_debugfs(pl08x);
2031 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2032 amba_part(adev), amba_rev(adev),
2033 (unsigned long long)adev->res.start, adev->irq[0]);
2037 dma_async_device_unregister(&pl08x->memcpy);
2039 pl08x_free_virtual_channels(&pl08x->slave);
2041 pl08x_free_virtual_channels(&pl08x->memcpy);
2043 kfree(pl08x->phy_chans);
2045 free_irq(adev->irq[0], pl08x);
2047 iounmap(pl08x->base);
2049 dma_pool_destroy(pl08x->pool);
2054 amba_release_regions(adev);
2058 /* PL080 has 8 channels and the PL080 have just 2 */
2059 static struct vendor_data vendor_pl080 = {
2064 static struct vendor_data vendor_pl081 = {
2066 .dualmaster = false,
2069 static struct amba_id pl08x_ids[] = {
2074 .data = &vendor_pl080,
2080 .data = &vendor_pl081,
2082 /* Nomadik 8815 PL080 variant */
2086 .data = &vendor_pl080,
2091 static struct amba_driver pl08x_amba_driver = {
2092 .drv.name = DRIVER_NAME,
2093 .id_table = pl08x_ids,
2094 .probe = pl08x_probe,
2097 static int __init pl08x_init(void)
2100 retval = amba_driver_register(&pl08x_amba_driver);
2102 printk(KERN_WARNING DRIVER_NAME
2103 "failed to register as an AMBA device (%d)\n",
2107 subsys_initcall(pl08x_init);