2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the
23 * file called COPYING.
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
69 * Only the former works sanely with scatter lists, so we only implement
70 * the DMAC flow control method. However, peripherals which use the LBREQ
71 * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72 * these hardware restrictions prevents them from using scatter DMA.
75 * - Break out common code from arch/arm/mach-s3c64xx and share
77 #include <linux/device.h>
78 #include <linux/init.h>
79 #include <linux/module.h>
80 #include <linux/interrupt.h>
81 #include <linux/slab.h>
82 #include <linux/dmapool.h>
83 #include <linux/dmaengine.h>
84 #include <linux/amba/bus.h>
85 #include <linux/amba/pl08x.h>
86 #include <linux/debugfs.h>
87 #include <linux/seq_file.h>
89 #include <asm/hardware/pl080.h>
91 #define DRIVER_NAME "pl08xdmac"
94 * struct vendor_data - vendor-specific config parameters
95 * for PL08x derivatives
96 * @channels: the number of channels available in this variant
97 * @dualmaster: whether this version supports dual AHB masters
106 * PL08X private data structures
107 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
108 * start & end do not - their bus bit info is in cctl. Also note that these
109 * are fixed 32-bit quantities.
119 * struct pl08x_driver_data - the local state holder for the PL08x
120 * @slave: slave engine for this instance
121 * @memcpy: memcpy engine for this instance
122 * @base: virtual memory base (remapped) for the PL08x
123 * @adev: the corresponding AMBA (PrimeCell) bus entry
124 * @vd: vendor data for this PL08x variant
125 * @pd: platform data passed in from the platform/machine
126 * @phy_chans: array of data for the physical channels
127 * @pool: a pool for the LLI descriptors
128 * @pool_ctr: counter of LLIs in the pool
129 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI fetches
130 * @mem_buses: set to indicate memory transfers on AHB2.
131 * @lock: a spinlock for this struct
133 struct pl08x_driver_data {
134 struct dma_device slave;
135 struct dma_device memcpy;
137 struct amba_device *adev;
138 const struct vendor_data *vd;
139 struct pl08x_platform_data *pd;
140 struct pl08x_phy_chan *phy_chans;
141 struct dma_pool *pool;
149 * PL08X specific defines
153 * Memory boundaries: the manual for PL08x says that the controller
154 * cannot read past a 1KiB boundary, so these defines are used to
155 * create transfer LLIs that do not cross such boundaries.
157 #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
158 #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)
160 /* Minimum period between work queue runs */
161 #define PL08X_WQ_PERIODMIN 20
163 /* Size (bytes) of each LLI buffer allocated for one transfer */
164 # define PL08X_LLI_TSFR_SIZE 0x2000
166 /* Maximum times we call dma_pool_alloc on this pool without freeing */
167 #define PL08X_MAX_ALLOCS 0x40
168 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
169 #define PL08X_ALIGN 8
171 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
173 return container_of(chan, struct pl08x_dma_chan, chan);
176 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
178 return container_of(tx, struct pl08x_txd, tx);
182 * Physical channel handling
185 /* Whether a certain channel is busy or not */
186 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
190 val = readl(ch->base + PL080_CH_CONFIG);
191 return val & PL080_CONFIG_ACTIVE;
195 * Set the initial DMA register values i.e. those for the first LLI
196 * The next LLI pointer and the configuration interrupt bit have
197 * been set when the LLIs were constructed. Poke them into the hardware
198 * and start the transfer.
200 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
201 struct pl08x_txd *txd)
203 struct pl08x_driver_data *pl08x = plchan->host;
204 struct pl08x_phy_chan *phychan = plchan->phychan;
205 struct pl08x_lli *lli = &txd->llis_va[0];
210 /* Wait for channel inactive */
211 while (pl08x_phy_channel_busy(phychan))
214 dev_vdbg(&pl08x->adev->dev,
215 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
216 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
217 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
220 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
221 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
222 writel(lli->lli, phychan->base + PL080_CH_LLI);
223 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
224 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
226 /* Enable the DMA channel */
227 /* Do not access config register until channel shows as disabled */
228 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
231 /* Do not access config register until channel shows as inactive */
232 val = readl(phychan->base + PL080_CH_CONFIG);
233 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
234 val = readl(phychan->base + PL080_CH_CONFIG);
236 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
240 * Overall DMAC remains enabled always.
242 * Disabling individual channels could lose data.
244 * Disable the peripheral DMA after disabling the DMAC
245 * in order to allow the DMAC FIFO to drain, and
246 * hence allow the channel to show inactive
249 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
253 /* Set the HALT bit and wait for the FIFO to drain */
254 val = readl(ch->base + PL080_CH_CONFIG);
255 val |= PL080_CONFIG_HALT;
256 writel(val, ch->base + PL080_CH_CONFIG);
258 /* Wait for channel inactive */
259 while (pl08x_phy_channel_busy(ch))
263 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
267 /* Clear the HALT bit */
268 val = readl(ch->base + PL080_CH_CONFIG);
269 val &= ~PL080_CONFIG_HALT;
270 writel(val, ch->base + PL080_CH_CONFIG);
274 /* Stops the channel */
275 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
279 pl08x_pause_phy_chan(ch);
281 /* Disable channel */
282 val = readl(ch->base + PL080_CH_CONFIG);
283 val &= ~PL080_CONFIG_ENABLE;
284 val &= ~PL080_CONFIG_ERR_IRQ_MASK;
285 val &= ~PL080_CONFIG_TC_IRQ_MASK;
286 writel(val, ch->base + PL080_CH_CONFIG);
289 static inline u32 get_bytes_in_cctl(u32 cctl)
291 /* The source width defines the number of bytes */
292 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
294 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
295 case PL080_WIDTH_8BIT:
297 case PL080_WIDTH_16BIT:
300 case PL080_WIDTH_32BIT:
307 /* The channel should be paused when calling this */
308 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
310 struct pl08x_phy_chan *ch;
311 struct pl08x_txd *txd;
315 spin_lock_irqsave(&plchan->lock, flags);
316 ch = plchan->phychan;
320 * Follow the LLIs to get the number of remaining
321 * bytes in the currently active transaction.
324 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
326 /* First get the remaining bytes in the active transfer */
327 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
330 struct pl08x_lli *llis_va = txd->llis_va;
331 dma_addr_t llis_bus = txd->llis_bus;
334 BUG_ON(clli < llis_bus || clli >= llis_bus +
335 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
338 * Locate the next LLI - as this is an array,
339 * it's simple maths to find.
341 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
343 for (; index < MAX_NUM_TSFR_LLIS; index++) {
344 bytes += get_bytes_in_cctl(llis_va[index].cctl);
347 * A LLI pointer of 0 terminates the LLI list
349 if (!llis_va[index].lli)
355 /* Sum up all queued transactions */
356 if (!list_empty(&plchan->pend_list)) {
357 struct pl08x_txd *txdi;
358 list_for_each_entry(txdi, &plchan->pend_list, node) {
363 spin_unlock_irqrestore(&plchan->lock, flags);
369 * Allocate a physical channel for a virtual channel
371 static struct pl08x_phy_chan *
372 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
373 struct pl08x_dma_chan *virt_chan)
375 struct pl08x_phy_chan *ch = NULL;
380 * Try to locate a physical channel to be used for
381 * this transfer. If all are taken return NULL and
382 * the requester will have to cope by using some fallback
383 * PIO mode or retrying later.
385 for (i = 0; i < pl08x->vd->channels; i++) {
386 ch = &pl08x->phy_chans[i];
388 spin_lock_irqsave(&ch->lock, flags);
391 ch->serving = virt_chan;
393 spin_unlock_irqrestore(&ch->lock, flags);
397 spin_unlock_irqrestore(&ch->lock, flags);
400 if (i == pl08x->vd->channels) {
401 /* No physical channel available, cope with it */
408 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
409 struct pl08x_phy_chan *ch)
413 /* Stop the channel and clear its interrupts */
414 pl08x_stop_phy_chan(ch);
415 writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
416 writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
418 /* Mark it as free */
419 spin_lock_irqsave(&ch->lock, flags);
421 spin_unlock_irqrestore(&ch->lock, flags);
428 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
431 case PL080_WIDTH_8BIT:
433 case PL080_WIDTH_16BIT:
435 case PL080_WIDTH_32BIT:
444 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
449 /* Remove all src, dst and transfer size bits */
450 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
451 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
452 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
454 /* Then set the bits according to the parameters */
457 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
460 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
463 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
472 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
475 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
478 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
485 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
489 struct pl08x_lli_build_data {
490 struct pl08x_txd *txd;
491 struct pl08x_driver_data *pl08x;
492 struct pl08x_bus_data srcbus;
493 struct pl08x_bus_data dstbus;
498 * Autoselect a master bus to use for the transfer
499 * this prefers the destination bus if both available
500 * if fixed address on one bus the other will be chosen
502 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
503 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
505 if (!(cctl & PL080_CONTROL_DST_INCR)) {
508 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
512 if (bd->dstbus.buswidth == 4) {
515 } else if (bd->srcbus.buswidth == 4) {
518 } else if (bd->dstbus.buswidth == 2) {
521 } else if (bd->srcbus.buswidth == 2) {
525 /* bd->srcbus.buswidth == 1 */
533 * Fills in one LLI for a certain transfer descriptor
534 * and advance the counter
536 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
537 int num_llis, int len, u32 cctl)
539 struct pl08x_lli *llis_va = bd->txd->llis_va;
540 dma_addr_t llis_bus = bd->txd->llis_bus;
542 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
544 llis_va[num_llis].cctl = cctl;
545 llis_va[num_llis].src = bd->srcbus.addr;
546 llis_va[num_llis].dst = bd->dstbus.addr;
547 llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
548 if (bd->pl08x->lli_buses & PL08X_AHB2)
549 llis_va[num_llis].lli |= PL080_LLI_LM_AHB2;
551 if (cctl & PL080_CONTROL_SRC_INCR)
552 bd->srcbus.addr += len;
553 if (cctl & PL080_CONTROL_DST_INCR)
554 bd->dstbus.addr += len;
556 BUG_ON(bd->remainder < len);
558 bd->remainder -= len;
562 * Return number of bytes to fill to boundary, or len.
563 * This calculation works for any value of addr.
565 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
567 size_t boundary_len = PL08X_BOUNDARY_SIZE -
568 (addr & (PL08X_BOUNDARY_SIZE - 1));
570 return min(boundary_len, len);
574 * This fills in the table of LLIs for the transfer descriptor
575 * Note that we assume we never have to change the burst sizes
578 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
579 struct pl08x_txd *txd)
581 struct pl08x_bus_data *mbus, *sbus;
582 struct pl08x_lli_build_data bd;
585 size_t max_bytes_per_lli;
586 size_t total_bytes = 0;
587 struct pl08x_lli *llis_va;
589 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
592 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
598 /* Get the default CCTL */
603 bd.srcbus.addr = txd->src_addr;
604 bd.dstbus.addr = txd->dst_addr;
606 /* Find maximum width of the source bus */
608 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
609 PL080_CONTROL_SWIDTH_SHIFT);
611 /* Find maximum width of the destination bus */
613 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
614 PL080_CONTROL_DWIDTH_SHIFT);
616 /* Set up the bus widths to the maximum */
617 bd.srcbus.buswidth = bd.srcbus.maxwidth;
618 bd.dstbus.buswidth = bd.dstbus.maxwidth;
619 dev_vdbg(&pl08x->adev->dev,
620 "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
621 __func__, bd.srcbus.buswidth, bd.dstbus.buswidth);
625 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
627 max_bytes_per_lli = min(bd.srcbus.buswidth, bd.dstbus.buswidth) *
628 PL080_CONTROL_TRANSFER_SIZE_MASK;
629 dev_vdbg(&pl08x->adev->dev,
630 "%s max bytes per lli = %zu\n",
631 __func__, max_bytes_per_lli);
633 /* We need to count this down to zero */
634 bd.remainder = txd->len;
635 dev_vdbg(&pl08x->adev->dev,
636 "%s remainder = %zu\n",
637 __func__, bd.remainder);
640 * Choose bus to align to
641 * - prefers destination bus if both available
642 * - if fixed address on one bus chooses other
643 * - modifies cctl to choose an appropriate master
645 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
647 if (txd->len < mbus->buswidth) {
649 * Less than a bus width available
650 * - send as single bytes
652 while (bd.remainder) {
653 dev_vdbg(&pl08x->adev->dev,
654 "%s single byte LLIs for a transfer of "
655 "less than a bus width (remain 0x%08x)\n",
656 __func__, bd.remainder);
657 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
658 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
663 * Make one byte LLIs until master bus is aligned
664 * - slave will then be aligned also
666 while ((mbus->addr) % (mbus->buswidth)) {
667 dev_vdbg(&pl08x->adev->dev,
668 "%s adjustment lli for less than bus width "
670 __func__, bd.remainder);
671 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
672 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
678 * - if slave is not then we must set its width down
680 if (sbus->addr % sbus->buswidth) {
681 dev_dbg(&pl08x->adev->dev,
682 "%s set down bus width to one byte\n",
689 * Make largest possible LLIs until less than one bus
692 while (bd.remainder > (mbus->buswidth - 1)) {
693 size_t lli_len, target_len, tsize, odd_bytes;
696 * If enough left try to send max possible,
697 * otherwise try to send the remainder
699 target_len = min(bd.remainder, max_bytes_per_lli);
702 * Set bus lengths for incrementing buses to the
703 * number of bytes which fill to next memory boundary,
704 * limiting on the target length calculated above.
706 if (cctl & PL080_CONTROL_SRC_INCR)
707 bd.srcbus.fill_bytes =
708 pl08x_pre_boundary(bd.srcbus.addr,
711 bd.srcbus.fill_bytes = target_len;
713 if (cctl & PL080_CONTROL_DST_INCR)
714 bd.dstbus.fill_bytes =
715 pl08x_pre_boundary(bd.dstbus.addr,
718 bd.dstbus.fill_bytes = target_len;
720 /* Find the nearest */
721 lli_len = min(bd.srcbus.fill_bytes,
722 bd.dstbus.fill_bytes);
724 BUG_ON(lli_len > bd.remainder);
727 dev_err(&pl08x->adev->dev,
728 "%s lli_len is %zu, <= 0\n",
733 if (lli_len == target_len) {
735 * Can send what we wanted
740 lli_len = (lli_len/mbus->buswidth) *
745 * So now we know how many bytes to transfer
746 * to get to the nearest boundary
747 * The next LLI will past the boundary
748 * - however we may be working to a boundary
750 * We need to ensure the master stays aligned
752 odd_bytes = lli_len % mbus->buswidth;
754 * - and that we are working in multiples
757 lli_len -= odd_bytes;
763 * Check against minimum bus alignment:
764 * Calculate actual transfer size in relation
765 * to bus width an get a maximum remainder of
766 * the smallest bus width - 1
768 /* FIXME: use round_down()? */
769 tsize = lli_len / min(mbus->buswidth,
771 lli_len = tsize * min(mbus->buswidth,
774 if (target_len != lli_len) {
775 dev_vdbg(&pl08x->adev->dev,
776 "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
777 __func__, target_len, lli_len, txd->len);
780 cctl = pl08x_cctl_bits(cctl,
785 dev_vdbg(&pl08x->adev->dev,
786 "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
787 __func__, lli_len, bd.remainder);
788 pl08x_fill_lli_for_desc(&bd, num_llis++,
790 total_bytes += lli_len;
796 * Creep past the boundary,
797 * maintaining master alignment
800 for (j = 0; (j < mbus->buswidth)
801 && (bd.remainder); j++) {
802 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
803 dev_vdbg(&pl08x->adev->dev,
804 "%s align with boundary, single byte (remain 0x%08zx)\n",
805 __func__, bd.remainder);
806 pl08x_fill_lli_for_desc(&bd,
807 num_llis++, 1, cctl);
816 while (bd.remainder) {
817 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
818 dev_vdbg(&pl08x->adev->dev,
819 "%s align with boundary, single odd byte (remain %zu)\n",
820 __func__, bd.remainder);
821 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
825 if (total_bytes != txd->len) {
826 dev_err(&pl08x->adev->dev,
827 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
828 __func__, total_bytes, txd->len);
832 if (num_llis >= MAX_NUM_TSFR_LLIS) {
833 dev_err(&pl08x->adev->dev,
834 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
835 __func__, (u32) MAX_NUM_TSFR_LLIS);
839 llis_va = txd->llis_va;
841 * The final LLI terminates the LLI.
843 llis_va[num_llis - 1].lli = 0;
845 * The final LLI element shall also fire an interrupt
847 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
853 for (i = 0; i < num_llis; i++) {
854 dev_vdbg(&pl08x->adev->dev,
855 "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
870 /* You should call this with the struct pl08x lock held */
871 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
872 struct pl08x_txd *txd)
875 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
882 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
883 struct pl08x_dma_chan *plchan)
885 struct pl08x_txd *txdi = NULL;
886 struct pl08x_txd *next;
888 if (!list_empty(&plchan->pend_list)) {
889 list_for_each_entry_safe(txdi,
890 next, &plchan->pend_list, node) {
891 list_del(&txdi->node);
892 pl08x_free_txd(pl08x, txdi);
901 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
906 static void pl08x_free_chan_resources(struct dma_chan *chan)
911 * This should be called with the channel plchan->lock held
913 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
914 struct pl08x_txd *txd)
916 struct pl08x_driver_data *pl08x = plchan->host;
917 struct pl08x_phy_chan *ch;
920 /* Check if we already have a channel */
924 ch = pl08x_get_phy_channel(pl08x, plchan);
926 /* No physical channel available, cope with it */
927 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
932 * OK we have a physical channel: for memcpy() this is all we
933 * need, but for slaves the physical signals may be muxed!
934 * Can the platform allow us to use this channel?
938 pl08x->pd->get_signal) {
939 ret = pl08x->pd->get_signal(plchan);
941 dev_dbg(&pl08x->adev->dev,
942 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
943 ch->id, plchan->name);
944 /* Release physical channel & return */
945 pl08x_put_phy_channel(pl08x, ch);
950 /* Assign the flow control signal to this channel */
951 if (txd->direction == DMA_TO_DEVICE)
952 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
953 else if (txd->direction == DMA_FROM_DEVICE)
954 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
957 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
962 plchan->phychan = ch;
967 static void release_phy_channel(struct pl08x_dma_chan *plchan)
969 struct pl08x_driver_data *pl08x = plchan->host;
971 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
972 pl08x->pd->put_signal(plchan);
973 plchan->phychan->signal = -1;
975 pl08x_put_phy_channel(pl08x, plchan->phychan);
976 plchan->phychan = NULL;
979 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
981 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
982 struct pl08x_txd *txd = to_pl08x_txd(tx);
984 plchan->chan.cookie += 1;
985 if (plchan->chan.cookie < 0)
986 plchan->chan.cookie = 1;
987 tx->cookie = plchan->chan.cookie;
989 /* Put this onto the pending list */
990 list_add_tail(&txd->node, &plchan->pend_list);
993 * If there was no physical channel available for this memcpy,
994 * stack the request up and indicate that the channel is waiting
995 * for a free physical channel.
997 if (!plchan->slave && !plchan->phychan) {
998 /* Do this memcpy whenever there is a channel ready */
999 plchan->state = PL08X_CHAN_WAITING;
1000 plchan->waiting = txd;
1003 /* This unlock follows the lock in the prep() function */
1004 spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1009 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1010 struct dma_chan *chan, unsigned long flags)
1012 struct dma_async_tx_descriptor *retval = NULL;
1018 * Code accessing dma_async_is_complete() in a tight loop
1019 * may give problems - could schedule where indicated.
1020 * If slaves are relying on interrupts to signal completion this
1021 * function must not be called with interrupts disabled
1023 static enum dma_status
1024 pl08x_dma_tx_status(struct dma_chan *chan,
1025 dma_cookie_t cookie,
1026 struct dma_tx_state *txstate)
1028 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1029 dma_cookie_t last_used;
1030 dma_cookie_t last_complete;
1031 enum dma_status ret;
1034 last_used = plchan->chan.cookie;
1035 last_complete = plchan->lc;
1037 ret = dma_async_is_complete(cookie, last_complete, last_used);
1038 if (ret == DMA_SUCCESS) {
1039 dma_set_tx_state(txstate, last_complete, last_used, 0);
1044 * schedule(); could be inserted here
1048 * This cookie not complete yet
1050 last_used = plchan->chan.cookie;
1051 last_complete = plchan->lc;
1053 /* Get number of bytes left in the active transactions and queue */
1054 bytesleft = pl08x_getbytes_chan(plchan);
1056 dma_set_tx_state(txstate, last_complete, last_used,
1059 if (plchan->state == PL08X_CHAN_PAUSED)
1062 /* Whether waiting or running, we're in progress */
1063 return DMA_IN_PROGRESS;
1066 /* PrimeCell DMA extension */
1067 struct burst_table {
1072 static const struct burst_table burst_sizes[] = {
1075 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1076 (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1080 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1081 (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1085 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1086 (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1090 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1091 (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1095 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1096 (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1100 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1101 (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1105 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1106 (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1110 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1111 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1115 static void dma_set_runtime_config(struct dma_chan *chan,
1116 struct dma_slave_config *config)
1118 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1119 struct pl08x_driver_data *pl08x = plchan->host;
1120 struct pl08x_channel_data *cd = plchan->cd;
1121 enum dma_slave_buswidth addr_width;
1126 /* Transfer direction */
1127 plchan->runtime_direction = config->direction;
1128 if (config->direction == DMA_TO_DEVICE) {
1129 plchan->runtime_addr = config->dst_addr;
1130 addr_width = config->dst_addr_width;
1131 maxburst = config->dst_maxburst;
1132 } else if (config->direction == DMA_FROM_DEVICE) {
1133 plchan->runtime_addr = config->src_addr;
1134 addr_width = config->src_addr_width;
1135 maxburst = config->src_maxburst;
1137 dev_err(&pl08x->adev->dev,
1138 "bad runtime_config: alien transfer direction\n");
1142 switch (addr_width) {
1143 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1144 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1145 (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1147 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1148 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1149 (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1151 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1152 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1153 (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1156 dev_err(&pl08x->adev->dev,
1157 "bad runtime_config: alien address width\n");
1162 * Now decide on a maxburst:
1163 * If this channel will only request single transfers, set this
1164 * down to ONE element. Also select one element if no maxburst
1167 if (plchan->cd->single || maxburst == 0) {
1168 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1169 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1171 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1172 if (burst_sizes[i].burstwords <= maxburst)
1174 cctl |= burst_sizes[i].reg;
1177 /* Modify the default channel data to fit PrimeCell request */
1180 dev_dbg(&pl08x->adev->dev,
1181 "configured channel %s (%s) for %s, data width %d, "
1182 "maxburst %d words, LE, CCTL=0x%08x\n",
1183 dma_chan_name(chan), plchan->name,
1184 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1191 * Slave transactions callback to the slave device to allow
1192 * synchronization of slave DMA signals with the DMAC enable
1194 static void pl08x_issue_pending(struct dma_chan *chan)
1196 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1197 unsigned long flags;
1199 spin_lock_irqsave(&plchan->lock, flags);
1200 /* Something is already active, or we're waiting for a channel... */
1201 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1202 spin_unlock_irqrestore(&plchan->lock, flags);
1206 /* Take the first element in the queue and execute it */
1207 if (!list_empty(&plchan->pend_list)) {
1208 struct pl08x_txd *next;
1210 next = list_first_entry(&plchan->pend_list,
1213 list_del(&next->node);
1214 plchan->state = PL08X_CHAN_RUNNING;
1216 pl08x_start_txd(plchan, next);
1219 spin_unlock_irqrestore(&plchan->lock, flags);
1222 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1223 struct pl08x_txd *txd)
1226 struct pl08x_driver_data *pl08x = plchan->host;
1229 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1235 spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1238 * See if we already have a physical channel allocated,
1239 * else this is the time to try to get one.
1241 ret = prep_phy_channel(plchan, txd);
1244 * No physical channel was available.
1246 * memcpy transfers can be sorted out at submission time.
1248 * Slave transfers may have been denied due to platform
1249 * channel muxing restrictions. Since there is no guarantee
1250 * that this will ever be resolved, and the signal must be
1251 * acquired AFTER acquiring the physical channel, we will let
1252 * them be NACK:ed with -EBUSY here. The drivers can retry
1253 * the prep() call if they are eager on doing this using DMA.
1255 if (plchan->slave) {
1256 pl08x_free_txd_list(pl08x, plchan);
1257 pl08x_free_txd(pl08x, txd);
1258 spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1263 * Else we're all set, paused and ready to roll,
1264 * status will switch to PL08X_CHAN_RUNNING when
1265 * we call issue_pending(). If there is something
1266 * running on the channel already we don't change
1269 if (plchan->state == PL08X_CHAN_IDLE)
1270 plchan->state = PL08X_CHAN_PAUSED;
1273 * Notice that we leave plchan->lock locked on purpose:
1274 * it will be unlocked in the subsequent tx_submit()
1275 * call. This is a consequence of the current API.
1282 * Given the source and destination available bus masks, select which
1283 * will be routed to each port. We try to have source and destination
1284 * on separate ports, but always respect the allowable settings.
1286 static u32 pl08x_select_bus(struct pl08x_driver_data *pl08x, u8 src, u8 dst)
1290 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1291 cctl |= PL080_CONTROL_DST_AHB2;
1292 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1293 cctl |= PL080_CONTROL_SRC_AHB2;
1298 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
1299 unsigned long flags)
1301 struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1304 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1305 txd->tx.flags = flags;
1306 txd->tx.tx_submit = pl08x_tx_submit;
1307 INIT_LIST_HEAD(&txd->node);
1309 /* Always enable error and terminal interrupts */
1310 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1311 PL080_CONFIG_TC_IRQ_MASK;
1317 * Initialize a descriptor to be used by memcpy submit
1319 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1320 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1321 size_t len, unsigned long flags)
1323 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1324 struct pl08x_driver_data *pl08x = plchan->host;
1325 struct pl08x_txd *txd;
1328 txd = pl08x_get_txd(plchan, flags);
1330 dev_err(&pl08x->adev->dev,
1331 "%s no memory for descriptor\n", __func__);
1335 txd->direction = DMA_NONE;
1336 txd->src_addr = src;
1337 txd->dst_addr = dest;
1340 /* Set platform data for m2m */
1341 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1342 txd->cctl = pl08x->pd->memcpy_channel.cctl &
1343 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1345 /* Both to be incremented or the code will break */
1346 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1348 if (pl08x->vd->dualmaster)
1349 txd->cctl |= pl08x_select_bus(pl08x,
1350 pl08x->mem_buses, pl08x->mem_buses);
1352 ret = pl08x_prep_channel_resources(plchan, txd);
1356 * NB: the channel lock is held at this point so tx_submit()
1357 * must be called in direct succession.
1363 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1364 struct dma_chan *chan, struct scatterlist *sgl,
1365 unsigned int sg_len, enum dma_data_direction direction,
1366 unsigned long flags)
1368 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1369 struct pl08x_driver_data *pl08x = plchan->host;
1370 struct pl08x_txd *txd;
1371 u8 src_buses, dst_buses;
1375 * Current implementation ASSUMES only one sg
1378 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1383 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1384 __func__, sgl->length, plchan->name);
1386 txd = pl08x_get_txd(plchan, flags);
1388 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1392 if (direction != plchan->runtime_direction)
1393 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1394 "the direction configured for the PrimeCell\n",
1398 * Set up addresses, the PrimeCell configured address
1399 * will take precedence since this may configure the
1400 * channel target address dynamically at runtime.
1402 txd->direction = direction;
1403 txd->len = sgl->length;
1405 txd->cctl = plchan->cd->cctl &
1406 ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1407 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1408 PL080_CONTROL_PROT_MASK);
1410 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1411 txd->cctl |= PL080_CONTROL_PROT_SYS;
1413 if (direction == DMA_TO_DEVICE) {
1414 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1415 txd->cctl |= PL080_CONTROL_SRC_INCR;
1416 txd->src_addr = sgl->dma_address;
1417 if (plchan->runtime_addr)
1418 txd->dst_addr = plchan->runtime_addr;
1420 txd->dst_addr = plchan->cd->addr;
1421 src_buses = pl08x->mem_buses;
1422 dst_buses = plchan->cd->periph_buses;
1423 } else if (direction == DMA_FROM_DEVICE) {
1424 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1425 txd->cctl |= PL080_CONTROL_DST_INCR;
1426 if (plchan->runtime_addr)
1427 txd->src_addr = plchan->runtime_addr;
1429 txd->src_addr = plchan->cd->addr;
1430 txd->dst_addr = sgl->dma_address;
1431 src_buses = plchan->cd->periph_buses;
1432 dst_buses = pl08x->mem_buses;
1434 dev_err(&pl08x->adev->dev,
1435 "%s direction unsupported\n", __func__);
1439 txd->cctl |= pl08x_select_bus(pl08x, src_buses, dst_buses);
1441 ret = pl08x_prep_channel_resources(plchan, txd);
1445 * NB: the channel lock is held at this point so tx_submit()
1446 * must be called in direct succession.
1452 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1455 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1456 struct pl08x_driver_data *pl08x = plchan->host;
1457 unsigned long flags;
1460 /* Controls applicable to inactive channels */
1461 if (cmd == DMA_SLAVE_CONFIG) {
1462 dma_set_runtime_config(chan,
1463 (struct dma_slave_config *)
1469 * Anything succeeds on channels with no physical allocation and
1470 * no queued transfers.
1472 spin_lock_irqsave(&plchan->lock, flags);
1473 if (!plchan->phychan && !plchan->at) {
1474 spin_unlock_irqrestore(&plchan->lock, flags);
1479 case DMA_TERMINATE_ALL:
1480 plchan->state = PL08X_CHAN_IDLE;
1482 if (plchan->phychan) {
1483 pl08x_stop_phy_chan(plchan->phychan);
1486 * Mark physical channel as free and free any slave
1489 release_phy_channel(plchan);
1491 /* Dequeue jobs and free LLIs */
1493 pl08x_free_txd(pl08x, plchan->at);
1496 /* Dequeue jobs not yet fired as well */
1497 pl08x_free_txd_list(pl08x, plchan);
1500 pl08x_pause_phy_chan(plchan->phychan);
1501 plchan->state = PL08X_CHAN_PAUSED;
1504 pl08x_resume_phy_chan(plchan->phychan);
1505 plchan->state = PL08X_CHAN_RUNNING;
1508 /* Unknown command */
1513 spin_unlock_irqrestore(&plchan->lock, flags);
1518 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1520 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1521 char *name = chan_id;
1523 /* Check that the channel is not taken! */
1524 if (!strcmp(plchan->name, name))
1531 * Just check that the device is there and active
1532 * TODO: turn this bit on/off depending on the number of
1533 * physical channels actually used, if it is zero... well
1534 * shut it off. That will save some power. Cut the clock
1537 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1541 val = readl(pl08x->base + PL080_CONFIG);
1542 val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1543 /* We implicitly clear bit 1 and that means little-endian mode */
1544 val |= PL080_CONFIG_ENABLE;
1545 writel(val, pl08x->base + PL080_CONFIG);
1548 static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1550 struct device *dev = txd->tx.chan->device->dev;
1552 if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1553 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1554 dma_unmap_single(dev, txd->src_addr, txd->len,
1557 dma_unmap_page(dev, txd->src_addr, txd->len,
1560 if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1561 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1562 dma_unmap_single(dev, txd->dst_addr, txd->len,
1565 dma_unmap_page(dev, txd->dst_addr, txd->len,
1570 static void pl08x_tasklet(unsigned long data)
1572 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1573 struct pl08x_driver_data *pl08x = plchan->host;
1574 struct pl08x_txd *txd;
1575 unsigned long flags;
1577 spin_lock_irqsave(&plchan->lock, flags);
1584 * Update last completed
1586 plchan->lc = txd->tx.cookie;
1589 * If a new descriptor is queued, set it up
1590 * plchan->at is NULL here
1592 if (!list_empty(&plchan->pend_list)) {
1593 struct pl08x_txd *next;
1595 next = list_first_entry(&plchan->pend_list,
1598 list_del(&next->node);
1600 pl08x_start_txd(plchan, next);
1602 struct pl08x_dma_chan *waiting = NULL;
1605 * No more jobs, so free up the physical channel
1606 * Free any allocated signal on slave transfers too
1608 release_phy_channel(plchan);
1609 plchan->state = PL08X_CHAN_IDLE;
1612 * And NOW before anyone else can grab that free:d
1613 * up physical channel, see if there is some memcpy
1614 * pending that seriously needs to start because of
1615 * being stacked up while we were choking the
1616 * physical channels with data.
1618 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1620 if (waiting->state == PL08X_CHAN_WAITING &&
1621 waiting->waiting != NULL) {
1624 /* This should REALLY not fail now */
1625 ret = prep_phy_channel(waiting,
1628 waiting->state = PL08X_CHAN_RUNNING;
1629 waiting->waiting = NULL;
1630 pl08x_issue_pending(&waiting->chan);
1636 spin_unlock_irqrestore(&plchan->lock, flags);
1639 dma_async_tx_callback callback = txd->tx.callback;
1640 void *callback_param = txd->tx.callback_param;
1642 /* Don't try to unmap buffers on slave channels */
1644 pl08x_unmap_buffers(txd);
1646 /* Free the descriptor */
1647 spin_lock_irqsave(&plchan->lock, flags);
1648 pl08x_free_txd(pl08x, txd);
1649 spin_unlock_irqrestore(&plchan->lock, flags);
1651 /* Callback to signal completion */
1653 callback(callback_param);
1657 static irqreturn_t pl08x_irq(int irq, void *dev)
1659 struct pl08x_driver_data *pl08x = dev;
1664 val = readl(pl08x->base + PL080_ERR_STATUS);
1667 * An error interrupt (on one or more channels)
1669 dev_err(&pl08x->adev->dev,
1670 "%s error interrupt, register value 0x%08x\n",
1673 * Simply clear ALL PL08X error interrupts,
1674 * regardless of channel and cause
1675 * FIXME: should be 0x00000003 on PL081 really.
1677 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1679 val = readl(pl08x->base + PL080_INT_STATUS);
1680 for (i = 0; i < pl08x->vd->channels; i++) {
1681 if ((1 << i) & val) {
1682 /* Locate physical channel */
1683 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1684 struct pl08x_dma_chan *plchan = phychan->serving;
1686 /* Schedule tasklet on this channel */
1687 tasklet_schedule(&plchan->tasklet);
1693 * Clear only the terminal interrupts on channels we processed
1695 writel(mask, pl08x->base + PL080_TC_CLEAR);
1697 return mask ? IRQ_HANDLED : IRQ_NONE;
1701 * Initialise the DMAC memcpy/slave channels.
1702 * Make a local wrapper to hold required data
1704 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1705 struct dma_device *dmadev,
1706 unsigned int channels,
1709 struct pl08x_dma_chan *chan;
1712 INIT_LIST_HEAD(&dmadev->channels);
1714 * Register as many many memcpy as we have physical channels,
1715 * we won't always be able to use all but the code will have
1716 * to cope with that situation.
1718 for (i = 0; i < channels; i++) {
1719 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1721 dev_err(&pl08x->adev->dev,
1722 "%s no memory for channel\n", __func__);
1727 chan->state = PL08X_CHAN_IDLE;
1731 chan->name = pl08x->pd->slave_channels[i].bus_id;
1732 chan->cd = &pl08x->pd->slave_channels[i];
1734 chan->cd = &pl08x->pd->memcpy_channel;
1735 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1741 if (chan->cd->circular_buffer) {
1742 dev_err(&pl08x->adev->dev,
1743 "channel %s: circular buffers not supported\n",
1748 dev_info(&pl08x->adev->dev,
1749 "initialize virtual channel \"%s\"\n",
1752 chan->chan.device = dmadev;
1753 chan->chan.cookie = 0;
1756 spin_lock_init(&chan->lock);
1757 INIT_LIST_HEAD(&chan->pend_list);
1758 tasklet_init(&chan->tasklet, pl08x_tasklet,
1759 (unsigned long) chan);
1761 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1763 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1764 i, slave ? "slave" : "memcpy");
1768 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1770 struct pl08x_dma_chan *chan = NULL;
1771 struct pl08x_dma_chan *next;
1773 list_for_each_entry_safe(chan,
1774 next, &dmadev->channels, chan.device_node) {
1775 list_del(&chan->chan.device_node);
1780 #ifdef CONFIG_DEBUG_FS
1781 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1784 case PL08X_CHAN_IDLE:
1786 case PL08X_CHAN_RUNNING:
1788 case PL08X_CHAN_PAUSED:
1790 case PL08X_CHAN_WAITING:
1795 return "UNKNOWN STATE";
1798 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1800 struct pl08x_driver_data *pl08x = s->private;
1801 struct pl08x_dma_chan *chan;
1802 struct pl08x_phy_chan *ch;
1803 unsigned long flags;
1806 seq_printf(s, "PL08x physical channels:\n");
1807 seq_printf(s, "CHANNEL:\tUSER:\n");
1808 seq_printf(s, "--------\t-----\n");
1809 for (i = 0; i < pl08x->vd->channels; i++) {
1810 struct pl08x_dma_chan *virt_chan;
1812 ch = &pl08x->phy_chans[i];
1814 spin_lock_irqsave(&ch->lock, flags);
1815 virt_chan = ch->serving;
1817 seq_printf(s, "%d\t\t%s\n",
1818 ch->id, virt_chan ? virt_chan->name : "(none)");
1820 spin_unlock_irqrestore(&ch->lock, flags);
1823 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1824 seq_printf(s, "CHANNEL:\tSTATE:\n");
1825 seq_printf(s, "--------\t------\n");
1826 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1827 seq_printf(s, "%s\t\t%s\n", chan->name,
1828 pl08x_state_str(chan->state));
1831 seq_printf(s, "\nPL08x virtual slave channels:\n");
1832 seq_printf(s, "CHANNEL:\tSTATE:\n");
1833 seq_printf(s, "--------\t------\n");
1834 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1835 seq_printf(s, "%s\t\t%s\n", chan->name,
1836 pl08x_state_str(chan->state));
1842 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1844 return single_open(file, pl08x_debugfs_show, inode->i_private);
1847 static const struct file_operations pl08x_debugfs_operations = {
1848 .open = pl08x_debugfs_open,
1850 .llseek = seq_lseek,
1851 .release = single_release,
1854 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1856 /* Expose a simple debugfs interface to view all clocks */
1857 (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1859 &pl08x_debugfs_operations);
1863 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1868 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1870 struct pl08x_driver_data *pl08x;
1871 const struct vendor_data *vd = id->data;
1875 ret = amba_request_regions(adev, NULL);
1879 /* Create the driver state holder */
1880 pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1886 /* Initialize memcpy engine */
1887 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1888 pl08x->memcpy.dev = &adev->dev;
1889 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1890 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1891 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1892 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1893 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1894 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1895 pl08x->memcpy.device_control = pl08x_control;
1897 /* Initialize slave engine */
1898 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1899 pl08x->slave.dev = &adev->dev;
1900 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1901 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1902 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1903 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1904 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1905 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1906 pl08x->slave.device_control = pl08x_control;
1908 /* Get the platform data */
1909 pl08x->pd = dev_get_platdata(&adev->dev);
1911 dev_err(&adev->dev, "no platform data supplied\n");
1912 goto out_no_platdata;
1915 /* Assign useful pointers to the driver state */
1919 /* By default, AHB1 only. If dualmaster, from platform */
1920 pl08x->lli_buses = PL08X_AHB1;
1921 pl08x->mem_buses = PL08X_AHB1;
1922 if (pl08x->vd->dualmaster) {
1923 pl08x->lli_buses = pl08x->pd->lli_buses;
1924 pl08x->mem_buses = pl08x->pd->mem_buses;
1927 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1928 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1929 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1932 goto out_no_lli_pool;
1935 spin_lock_init(&pl08x->lock);
1937 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1940 goto out_no_ioremap;
1943 /* Turn on the PL08x */
1944 pl08x_ensure_on(pl08x);
1947 * Attach the interrupt handler
1949 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1950 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1952 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1953 DRIVER_NAME, pl08x);
1955 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1956 __func__, adev->irq[0]);
1960 /* Initialize physical channels */
1961 pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1963 if (!pl08x->phy_chans) {
1964 dev_err(&adev->dev, "%s failed to allocate "
1965 "physical channel holders\n",
1967 goto out_no_phychans;
1970 for (i = 0; i < vd->channels; i++) {
1971 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1974 ch->base = pl08x->base + PL080_Cx_BASE(i);
1975 spin_lock_init(&ch->lock);
1978 dev_info(&adev->dev,
1979 "physical channel %d is %s\n", i,
1980 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1983 /* Register as many memcpy channels as there are physical channels */
1984 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1985 pl08x->vd->channels, false);
1987 dev_warn(&pl08x->adev->dev,
1988 "%s failed to enumerate memcpy channels - %d\n",
1992 pl08x->memcpy.chancnt = ret;
1994 /* Register slave channels */
1995 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
1996 pl08x->pd->num_slave_channels,
1999 dev_warn(&pl08x->adev->dev,
2000 "%s failed to enumerate slave channels - %d\n",
2004 pl08x->slave.chancnt = ret;
2006 ret = dma_async_device_register(&pl08x->memcpy);
2008 dev_warn(&pl08x->adev->dev,
2009 "%s failed to register memcpy as an async device - %d\n",
2011 goto out_no_memcpy_reg;
2014 ret = dma_async_device_register(&pl08x->slave);
2016 dev_warn(&pl08x->adev->dev,
2017 "%s failed to register slave as an async device - %d\n",
2019 goto out_no_slave_reg;
2022 amba_set_drvdata(adev, pl08x);
2023 init_pl08x_debugfs(pl08x);
2024 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2025 amba_part(adev), amba_rev(adev),
2026 (unsigned long long)adev->res.start, adev->irq[0]);
2030 dma_async_device_unregister(&pl08x->memcpy);
2032 pl08x_free_virtual_channels(&pl08x->slave);
2034 pl08x_free_virtual_channels(&pl08x->memcpy);
2036 kfree(pl08x->phy_chans);
2038 free_irq(adev->irq[0], pl08x);
2040 iounmap(pl08x->base);
2042 dma_pool_destroy(pl08x->pool);
2047 amba_release_regions(adev);
2051 /* PL080 has 8 channels and the PL080 have just 2 */
2052 static struct vendor_data vendor_pl080 = {
2057 static struct vendor_data vendor_pl081 = {
2059 .dualmaster = false,
2062 static struct amba_id pl08x_ids[] = {
2067 .data = &vendor_pl080,
2073 .data = &vendor_pl081,
2075 /* Nomadik 8815 PL080 variant */
2079 .data = &vendor_pl080,
2084 static struct amba_driver pl08x_amba_driver = {
2085 .drv.name = DRIVER_NAME,
2086 .id_table = pl08x_ids,
2087 .probe = pl08x_probe,
2090 static int __init pl08x_init(void)
2093 retval = amba_driver_register(&pl08x_amba_driver);
2095 printk(KERN_WARNING DRIVER_NAME
2096 "failed to register as an AMBA device (%d)\n",
2100 subsys_initcall(pl08x_init);