2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the
23 * file called COPYING.
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
69 * Only the former works sanely with scatter lists, so we only implement
70 * the DMAC flow control method. However, peripherals which use the LBREQ
71 * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72 * these hardware restrictions prevents them from using scatter DMA.
75 * - Break out common code from arch/arm/mach-s3c64xx and share
77 #include <linux/device.h>
78 #include <linux/init.h>
79 #include <linux/module.h>
80 #include <linux/interrupt.h>
81 #include <linux/slab.h>
82 #include <linux/dmapool.h>
83 #include <linux/dmaengine.h>
84 #include <linux/amba/bus.h>
85 #include <linux/amba/pl08x.h>
86 #include <linux/debugfs.h>
87 #include <linux/seq_file.h>
89 #include <asm/hardware/pl080.h>
91 #define DRIVER_NAME "pl08xdmac"
94 * struct vendor_data - vendor-specific config parameters
95 * for PL08x derivatives
96 * @channels: the number of channels available in this variant
97 * @dualmaster: whether this version supports dual AHB masters
106 * PL08X private data structures
107 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
108 * start & end do not - their bus bit info is in cctl. Also note that these
109 * are fixed 32-bit quantities.
119 * struct pl08x_driver_data - the local state holder for the PL08x
120 * @slave: slave engine for this instance
121 * @memcpy: memcpy engine for this instance
122 * @base: virtual memory base (remapped) for the PL08x
123 * @adev: the corresponding AMBA (PrimeCell) bus entry
124 * @vd: vendor data for this PL08x variant
125 * @pd: platform data passed in from the platform/machine
126 * @phy_chans: array of data for the physical channels
127 * @pool: a pool for the LLI descriptors
128 * @pool_ctr: counter of LLIs in the pool
129 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI fetches
130 * @mem_buses: set to indicate memory transfers on AHB2.
131 * @lock: a spinlock for this struct
133 struct pl08x_driver_data {
134 struct dma_device slave;
135 struct dma_device memcpy;
137 struct amba_device *adev;
138 const struct vendor_data *vd;
139 struct pl08x_platform_data *pd;
140 struct pl08x_phy_chan *phy_chans;
141 struct dma_pool *pool;
149 * PL08X specific defines
153 * Memory boundaries: the manual for PL08x says that the controller
154 * cannot read past a 1KiB boundary, so these defines are used to
155 * create transfer LLIs that do not cross such boundaries.
157 #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
158 #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)
160 /* Minimum period between work queue runs */
161 #define PL08X_WQ_PERIODMIN 20
163 /* Size (bytes) of each LLI buffer allocated for one transfer */
164 # define PL08X_LLI_TSFR_SIZE 0x2000
166 /* Maximum times we call dma_pool_alloc on this pool without freeing */
167 #define PL08X_MAX_ALLOCS 0x40
168 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
169 #define PL08X_ALIGN 8
171 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
173 return container_of(chan, struct pl08x_dma_chan, chan);
177 * Physical channel handling
180 /* Whether a certain channel is busy or not */
181 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
185 val = readl(ch->base + PL080_CH_CONFIG);
186 return val & PL080_CONFIG_ACTIVE;
190 * Set the initial DMA register values i.e. those for the first LLI
191 * The next LLI pointer and the configuration interrupt bit have
192 * been set when the LLIs were constructed. Poke them into the hardware
193 * and start the transfer.
195 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
196 struct pl08x_txd *txd)
198 struct pl08x_driver_data *pl08x = plchan->host;
199 struct pl08x_phy_chan *phychan = plchan->phychan;
200 struct pl08x_lli *lli = &txd->llis_va[0];
205 /* Wait for channel inactive */
206 while (pl08x_phy_channel_busy(phychan))
209 dev_vdbg(&pl08x->adev->dev,
210 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
211 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
212 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
215 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
216 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
217 writel(lli->lli, phychan->base + PL080_CH_LLI);
218 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
219 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
221 /* Enable the DMA channel */
222 /* Do not access config register until channel shows as disabled */
223 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
226 /* Do not access config register until channel shows as inactive */
227 val = readl(phychan->base + PL080_CH_CONFIG);
228 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
229 val = readl(phychan->base + PL080_CH_CONFIG);
231 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
235 * Overall DMAC remains enabled always.
237 * Disabling individual channels could lose data.
239 * Disable the peripheral DMA after disabling the DMAC
240 * in order to allow the DMAC FIFO to drain, and
241 * hence allow the channel to show inactive
244 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
248 /* Set the HALT bit and wait for the FIFO to drain */
249 val = readl(ch->base + PL080_CH_CONFIG);
250 val |= PL080_CONFIG_HALT;
251 writel(val, ch->base + PL080_CH_CONFIG);
253 /* Wait for channel inactive */
254 while (pl08x_phy_channel_busy(ch))
258 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
262 /* Clear the HALT bit */
263 val = readl(ch->base + PL080_CH_CONFIG);
264 val &= ~PL080_CONFIG_HALT;
265 writel(val, ch->base + PL080_CH_CONFIG);
269 /* Stops the channel */
270 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
274 pl08x_pause_phy_chan(ch);
276 /* Disable channel */
277 val = readl(ch->base + PL080_CH_CONFIG);
278 val &= ~PL080_CONFIG_ENABLE;
279 val &= ~PL080_CONFIG_ERR_IRQ_MASK;
280 val &= ~PL080_CONFIG_TC_IRQ_MASK;
281 writel(val, ch->base + PL080_CH_CONFIG);
284 static inline u32 get_bytes_in_cctl(u32 cctl)
286 /* The source width defines the number of bytes */
287 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
289 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
290 case PL080_WIDTH_8BIT:
292 case PL080_WIDTH_16BIT:
295 case PL080_WIDTH_32BIT:
302 /* The channel should be paused when calling this */
303 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
305 struct pl08x_phy_chan *ch;
306 struct pl08x_txd *txd;
310 spin_lock_irqsave(&plchan->lock, flags);
311 ch = plchan->phychan;
315 * Follow the LLIs to get the number of remaining
316 * bytes in the currently active transaction.
319 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
321 /* First get the remaining bytes in the active transfer */
322 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
325 struct pl08x_lli *llis_va = txd->llis_va;
326 dma_addr_t llis_bus = txd->llis_bus;
329 BUG_ON(clli < llis_bus || clli >= llis_bus +
330 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
333 * Locate the next LLI - as this is an array,
334 * it's simple maths to find.
336 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
338 for (; index < MAX_NUM_TSFR_LLIS; index++) {
339 bytes += get_bytes_in_cctl(llis_va[index].cctl);
342 * A LLI pointer of 0 terminates the LLI list
344 if (!llis_va[index].lli)
350 /* Sum up all queued transactions */
351 if (!list_empty(&plchan->desc_list)) {
352 struct pl08x_txd *txdi;
353 list_for_each_entry(txdi, &plchan->desc_list, node) {
358 spin_unlock_irqrestore(&plchan->lock, flags);
364 * Allocate a physical channel for a virtual channel
366 static struct pl08x_phy_chan *
367 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
368 struct pl08x_dma_chan *virt_chan)
370 struct pl08x_phy_chan *ch = NULL;
375 * Try to locate a physical channel to be used for
376 * this transfer. If all are taken return NULL and
377 * the requester will have to cope by using some fallback
378 * PIO mode or retrying later.
380 for (i = 0; i < pl08x->vd->channels; i++) {
381 ch = &pl08x->phy_chans[i];
383 spin_lock_irqsave(&ch->lock, flags);
386 ch->serving = virt_chan;
388 spin_unlock_irqrestore(&ch->lock, flags);
392 spin_unlock_irqrestore(&ch->lock, flags);
395 if (i == pl08x->vd->channels) {
396 /* No physical channel available, cope with it */
403 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
404 struct pl08x_phy_chan *ch)
408 /* Stop the channel and clear its interrupts */
409 pl08x_stop_phy_chan(ch);
410 writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
411 writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
413 /* Mark it as free */
414 spin_lock_irqsave(&ch->lock, flags);
416 spin_unlock_irqrestore(&ch->lock, flags);
423 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
426 case PL080_WIDTH_8BIT:
428 case PL080_WIDTH_16BIT:
430 case PL080_WIDTH_32BIT:
439 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
444 /* Remove all src, dst and transfer size bits */
445 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
446 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
447 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
449 /* Then set the bits according to the parameters */
452 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
455 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
458 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
467 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
470 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
473 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
480 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
485 * Autoselect a master bus to use for the transfer
486 * this prefers the destination bus if both available
487 * if fixed address on one bus the other will be chosen
489 static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
490 struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
491 struct pl08x_bus_data **sbus, u32 cctl)
493 if (!(cctl & PL080_CONTROL_DST_INCR)) {
496 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
500 if (dst_bus->buswidth == 4) {
503 } else if (src_bus->buswidth == 4) {
506 } else if (dst_bus->buswidth == 2) {
509 } else if (src_bus->buswidth == 2) {
513 /* src_bus->buswidth == 1 */
521 * Fills in one LLI for a certain transfer descriptor
522 * and advance the counter
524 static void pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
525 struct pl08x_txd *txd, int num_llis, int len, u32 cctl, u32 *remainder)
527 struct pl08x_lli *llis_va = txd->llis_va;
528 dma_addr_t llis_bus = txd->llis_bus;
530 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
532 llis_va[num_llis].cctl = cctl;
533 llis_va[num_llis].src = txd->srcbus.addr;
534 llis_va[num_llis].dst = txd->dstbus.addr;
535 llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
536 if (pl08x->lli_buses & PL08X_AHB2)
537 llis_va[num_llis].lli |= PL080_LLI_LM_AHB2;
539 if (cctl & PL080_CONTROL_SRC_INCR)
540 txd->srcbus.addr += len;
541 if (cctl & PL080_CONTROL_DST_INCR)
542 txd->dstbus.addr += len;
544 BUG_ON(*remainder < len);
550 * Return number of bytes to fill to boundary, or len.
551 * This calculation works for any value of addr.
553 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
555 size_t boundary_len = PL08X_BOUNDARY_SIZE -
556 (addr & (PL08X_BOUNDARY_SIZE - 1));
558 return min(boundary_len, len);
562 * This fills in the table of LLIs for the transfer descriptor
563 * Note that we assume we never have to change the burst sizes
566 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
567 struct pl08x_txd *txd)
569 struct pl08x_bus_data *mbus, *sbus;
573 size_t max_bytes_per_lli;
574 size_t total_bytes = 0;
575 struct pl08x_lli *llis_va;
577 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
580 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
586 /* Get the default CCTL */
589 /* Find maximum width of the source bus */
590 txd->srcbus.maxwidth =
591 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
592 PL080_CONTROL_SWIDTH_SHIFT);
594 /* Find maximum width of the destination bus */
595 txd->dstbus.maxwidth =
596 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
597 PL080_CONTROL_DWIDTH_SHIFT);
599 /* Set up the bus widths to the maximum */
600 txd->srcbus.buswidth = txd->srcbus.maxwidth;
601 txd->dstbus.buswidth = txd->dstbus.maxwidth;
602 dev_vdbg(&pl08x->adev->dev,
603 "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
604 __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
608 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
610 max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
611 PL080_CONTROL_TRANSFER_SIZE_MASK;
612 dev_vdbg(&pl08x->adev->dev,
613 "%s max bytes per lli = %zu\n",
614 __func__, max_bytes_per_lli);
616 /* We need to count this down to zero */
617 remainder = txd->len;
618 dev_vdbg(&pl08x->adev->dev,
619 "%s remainder = %zu\n",
620 __func__, remainder);
623 * Choose bus to align to
624 * - prefers destination bus if both available
625 * - if fixed address on one bus chooses other
626 * - modifies cctl to choose an appropriate master
628 pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
631 if (txd->len < mbus->buswidth) {
633 * Less than a bus width available
634 * - send as single bytes
637 dev_vdbg(&pl08x->adev->dev,
638 "%s single byte LLIs for a transfer of "
639 "less than a bus width (remain 0x%08x)\n",
640 __func__, remainder);
641 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
642 pl08x_fill_lli_for_desc(pl08x, txd, num_llis++, 1,
648 * Make one byte LLIs until master bus is aligned
649 * - slave will then be aligned also
651 while ((mbus->addr) % (mbus->buswidth)) {
652 dev_vdbg(&pl08x->adev->dev,
653 "%s adjustment lli for less than bus width "
655 __func__, remainder);
656 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
657 pl08x_fill_lli_for_desc(pl08x, txd, num_llis++, 1,
664 * - if slave is not then we must set its width down
666 if (sbus->addr % sbus->buswidth) {
667 dev_dbg(&pl08x->adev->dev,
668 "%s set down bus width to one byte\n",
675 * Make largest possible LLIs until less than one bus
678 while (remainder > (mbus->buswidth - 1)) {
679 size_t lli_len, target_len, tsize, odd_bytes;
682 * If enough left try to send max possible,
683 * otherwise try to send the remainder
685 target_len = min(remainder, max_bytes_per_lli);
688 * Set bus lengths for incrementing buses to the
689 * number of bytes which fill to next memory boundary,
690 * limiting on the target length calculated above.
692 if (cctl & PL080_CONTROL_SRC_INCR)
693 txd->srcbus.fill_bytes =
694 pl08x_pre_boundary(txd->srcbus.addr,
697 txd->srcbus.fill_bytes = target_len;
699 if (cctl & PL080_CONTROL_DST_INCR)
700 txd->dstbus.fill_bytes =
701 pl08x_pre_boundary(txd->dstbus.addr,
704 txd->dstbus.fill_bytes = target_len;
706 /* Find the nearest */
707 lli_len = min(txd->srcbus.fill_bytes,
708 txd->dstbus.fill_bytes);
710 BUG_ON(lli_len > remainder);
713 dev_err(&pl08x->adev->dev,
714 "%s lli_len is %zu, <= 0\n",
719 if (lli_len == target_len) {
721 * Can send what we wanted
726 lli_len = (lli_len/mbus->buswidth) *
731 * So now we know how many bytes to transfer
732 * to get to the nearest boundary
733 * The next LLI will past the boundary
734 * - however we may be working to a boundary
736 * We need to ensure the master stays aligned
738 odd_bytes = lli_len % mbus->buswidth;
740 * - and that we are working in multiples
743 lli_len -= odd_bytes;
749 * Check against minimum bus alignment:
750 * Calculate actual transfer size in relation
751 * to bus width an get a maximum remainder of
752 * the smallest bus width - 1
754 /* FIXME: use round_down()? */
755 tsize = lli_len / min(mbus->buswidth,
757 lli_len = tsize * min(mbus->buswidth,
760 if (target_len != lli_len) {
761 dev_vdbg(&pl08x->adev->dev,
762 "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
763 __func__, target_len, lli_len, txd->len);
766 cctl = pl08x_cctl_bits(cctl,
767 txd->srcbus.buswidth,
768 txd->dstbus.buswidth,
771 dev_vdbg(&pl08x->adev->dev,
772 "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
773 __func__, lli_len, remainder);
774 pl08x_fill_lli_for_desc(pl08x, txd, num_llis++,
775 lli_len, cctl, &remainder);
776 total_bytes += lli_len;
782 * Creep past the boundary,
783 * maintaining master alignment
786 for (j = 0; (j < mbus->buswidth)
787 && (remainder); j++) {
788 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
789 dev_vdbg(&pl08x->adev->dev,
790 "%s align with boundary, single byte (remain 0x%08zx)\n",
791 __func__, remainder);
792 pl08x_fill_lli_for_desc(pl08x, txd,
804 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
805 dev_vdbg(&pl08x->adev->dev,
806 "%s align with boundary, single odd byte (remain %zu)\n",
807 __func__, remainder);
808 pl08x_fill_lli_for_desc(pl08x, txd, num_llis++, 1,
813 if (total_bytes != txd->len) {
814 dev_err(&pl08x->adev->dev,
815 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
816 __func__, total_bytes, txd->len);
820 if (num_llis >= MAX_NUM_TSFR_LLIS) {
821 dev_err(&pl08x->adev->dev,
822 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
823 __func__, (u32) MAX_NUM_TSFR_LLIS);
827 llis_va = txd->llis_va;
829 * The final LLI terminates the LLI.
831 llis_va[num_llis - 1].lli = 0;
833 * The final LLI element shall also fire an interrupt
835 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
841 for (i = 0; i < num_llis; i++) {
842 dev_vdbg(&pl08x->adev->dev,
843 "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
858 /* You should call this with the struct pl08x lock held */
859 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
860 struct pl08x_txd *txd)
863 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
870 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
871 struct pl08x_dma_chan *plchan)
873 struct pl08x_txd *txdi = NULL;
874 struct pl08x_txd *next;
876 if (!list_empty(&plchan->desc_list)) {
877 list_for_each_entry_safe(txdi,
878 next, &plchan->desc_list, node) {
879 list_del(&txdi->node);
880 pl08x_free_txd(pl08x, txdi);
889 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
894 static void pl08x_free_chan_resources(struct dma_chan *chan)
899 * This should be called with the channel plchan->lock held
901 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
902 struct pl08x_txd *txd)
904 struct pl08x_driver_data *pl08x = plchan->host;
905 struct pl08x_phy_chan *ch;
908 /* Check if we already have a channel */
912 ch = pl08x_get_phy_channel(pl08x, plchan);
914 /* No physical channel available, cope with it */
915 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
920 * OK we have a physical channel: for memcpy() this is all we
921 * need, but for slaves the physical signals may be muxed!
922 * Can the platform allow us to use this channel?
926 pl08x->pd->get_signal) {
927 ret = pl08x->pd->get_signal(plchan);
929 dev_dbg(&pl08x->adev->dev,
930 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
931 ch->id, plchan->name);
932 /* Release physical channel & return */
933 pl08x_put_phy_channel(pl08x, ch);
938 /* Assign the flow control signal to this channel */
939 if (txd->direction == DMA_TO_DEVICE)
940 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
941 else if (txd->direction == DMA_FROM_DEVICE)
942 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
945 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
950 plchan->phychan = ch;
955 static void release_phy_channel(struct pl08x_dma_chan *plchan)
957 struct pl08x_driver_data *pl08x = plchan->host;
959 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
960 pl08x->pd->put_signal(plchan);
961 plchan->phychan->signal = -1;
963 pl08x_put_phy_channel(pl08x, plchan->phychan);
964 plchan->phychan = NULL;
967 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
969 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
971 plchan->chan.cookie += 1;
972 if (plchan->chan.cookie < 0)
973 plchan->chan.cookie = 1;
974 tx->cookie = plchan->chan.cookie;
975 /* This unlock follows the lock in the prep() function */
976 spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
981 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
982 struct dma_chan *chan, unsigned long flags)
984 struct dma_async_tx_descriptor *retval = NULL;
990 * Code accessing dma_async_is_complete() in a tight loop
991 * may give problems - could schedule where indicated.
992 * If slaves are relying on interrupts to signal completion this
993 * function must not be called with interrupts disabled
995 static enum dma_status
996 pl08x_dma_tx_status(struct dma_chan *chan,
998 struct dma_tx_state *txstate)
1000 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1001 dma_cookie_t last_used;
1002 dma_cookie_t last_complete;
1003 enum dma_status ret;
1006 last_used = plchan->chan.cookie;
1007 last_complete = plchan->lc;
1009 ret = dma_async_is_complete(cookie, last_complete, last_used);
1010 if (ret == DMA_SUCCESS) {
1011 dma_set_tx_state(txstate, last_complete, last_used, 0);
1016 * schedule(); could be inserted here
1020 * This cookie not complete yet
1022 last_used = plchan->chan.cookie;
1023 last_complete = plchan->lc;
1025 /* Get number of bytes left in the active transactions and queue */
1026 bytesleft = pl08x_getbytes_chan(plchan);
1028 dma_set_tx_state(txstate, last_complete, last_used,
1031 if (plchan->state == PL08X_CHAN_PAUSED)
1034 /* Whether waiting or running, we're in progress */
1035 return DMA_IN_PROGRESS;
1038 /* PrimeCell DMA extension */
1039 struct burst_table {
1044 static const struct burst_table burst_sizes[] = {
1047 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1048 (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1052 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1053 (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1057 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1058 (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1062 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1063 (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1067 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1068 (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1072 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1073 (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1077 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1078 (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1082 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1083 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1087 static void dma_set_runtime_config(struct dma_chan *chan,
1088 struct dma_slave_config *config)
1090 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1091 struct pl08x_driver_data *pl08x = plchan->host;
1092 struct pl08x_channel_data *cd = plchan->cd;
1093 enum dma_slave_buswidth addr_width;
1098 /* Transfer direction */
1099 plchan->runtime_direction = config->direction;
1100 if (config->direction == DMA_TO_DEVICE) {
1101 plchan->runtime_addr = config->dst_addr;
1102 addr_width = config->dst_addr_width;
1103 maxburst = config->dst_maxburst;
1104 } else if (config->direction == DMA_FROM_DEVICE) {
1105 plchan->runtime_addr = config->src_addr;
1106 addr_width = config->src_addr_width;
1107 maxburst = config->src_maxburst;
1109 dev_err(&pl08x->adev->dev,
1110 "bad runtime_config: alien transfer direction\n");
1114 switch (addr_width) {
1115 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1116 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1117 (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1119 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1120 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1121 (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1123 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1124 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1125 (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1128 dev_err(&pl08x->adev->dev,
1129 "bad runtime_config: alien address width\n");
1134 * Now decide on a maxburst:
1135 * If this channel will only request single transfers, set this
1136 * down to ONE element. Also select one element if no maxburst
1139 if (plchan->cd->single || maxburst == 0) {
1140 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1141 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1143 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1144 if (burst_sizes[i].burstwords <= maxburst)
1146 cctl |= burst_sizes[i].reg;
1149 /* Modify the default channel data to fit PrimeCell request */
1152 dev_dbg(&pl08x->adev->dev,
1153 "configured channel %s (%s) for %s, data width %d, "
1154 "maxburst %d words, LE, CCTL=0x%08x\n",
1155 dma_chan_name(chan), plchan->name,
1156 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1163 * Slave transactions callback to the slave device to allow
1164 * synchronization of slave DMA signals with the DMAC enable
1166 static void pl08x_issue_pending(struct dma_chan *chan)
1168 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1169 unsigned long flags;
1171 spin_lock_irqsave(&plchan->lock, flags);
1172 /* Something is already active, or we're waiting for a channel... */
1173 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1174 spin_unlock_irqrestore(&plchan->lock, flags);
1178 /* Take the first element in the queue and execute it */
1179 if (!list_empty(&plchan->desc_list)) {
1180 struct pl08x_txd *next;
1182 next = list_first_entry(&plchan->desc_list,
1185 list_del(&next->node);
1186 plchan->state = PL08X_CHAN_RUNNING;
1188 pl08x_start_txd(plchan, next);
1191 spin_unlock_irqrestore(&plchan->lock, flags);
1194 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1195 struct pl08x_txd *txd)
1198 struct pl08x_driver_data *pl08x = plchan->host;
1201 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1207 spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1209 list_add_tail(&txd->node, &plchan->desc_list);
1212 * See if we already have a physical channel allocated,
1213 * else this is the time to try to get one.
1215 ret = prep_phy_channel(plchan, txd);
1218 * No physical channel available, we will
1219 * stack up the memcpy channels until there is a channel
1220 * available to handle it whereas slave transfers may
1221 * have been denied due to platform channel muxing restrictions
1222 * and since there is no guarantee that this will ever be
1223 * resolved, and since the signal must be acquired AFTER
1224 * acquiring the physical channel, we will let them be NACK:ed
1225 * with -EBUSY here. The drivers can alway retry the prep()
1226 * call if they are eager on doing this using DMA.
1228 if (plchan->slave) {
1229 pl08x_free_txd_list(pl08x, plchan);
1230 spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1233 /* Do this memcpy whenever there is a channel ready */
1234 plchan->state = PL08X_CHAN_WAITING;
1235 plchan->waiting = txd;
1238 * Else we're all set, paused and ready to roll,
1239 * status will switch to PL08X_CHAN_RUNNING when
1240 * we call issue_pending(). If there is something
1241 * running on the channel already we don't change
1244 if (plchan->state == PL08X_CHAN_IDLE)
1245 plchan->state = PL08X_CHAN_PAUSED;
1248 * Notice that we leave plchan->lock locked on purpose:
1249 * it will be unlocked in the subsequent tx_submit()
1250 * call. This is a consequence of the current API.
1257 * Given the source and destination available bus masks, select which
1258 * will be routed to each port. We try to have source and destination
1259 * on separate ports, but always respect the allowable settings.
1261 static u32 pl08x_select_bus(struct pl08x_driver_data *pl08x, u8 src, u8 dst)
1265 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1266 cctl |= PL080_CONTROL_DST_AHB2;
1267 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1268 cctl |= PL080_CONTROL_SRC_AHB2;
1273 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1275 struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1278 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1279 txd->tx.tx_submit = pl08x_tx_submit;
1280 INIT_LIST_HEAD(&txd->node);
1282 /* Always enable error and terminal interrupts */
1283 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1284 PL080_CONFIG_TC_IRQ_MASK;
1290 * Initialize a descriptor to be used by memcpy submit
1292 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1293 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1294 size_t len, unsigned long flags)
1296 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1297 struct pl08x_driver_data *pl08x = plchan->host;
1298 struct pl08x_txd *txd;
1301 txd = pl08x_get_txd(plchan);
1303 dev_err(&pl08x->adev->dev,
1304 "%s no memory for descriptor\n", __func__);
1308 txd->direction = DMA_NONE;
1309 txd->srcbus.addr = src;
1310 txd->dstbus.addr = dest;
1313 /* Set platform data for m2m */
1314 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1315 txd->cctl = pl08x->pd->memcpy_channel.cctl &
1316 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1318 /* Both to be incremented or the code will break */
1319 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1321 if (pl08x->vd->dualmaster)
1322 txd->cctl |= pl08x_select_bus(pl08x,
1323 pl08x->mem_buses, pl08x->mem_buses);
1325 ret = pl08x_prep_channel_resources(plchan, txd);
1329 * NB: the channel lock is held at this point so tx_submit()
1330 * must be called in direct succession.
1336 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1337 struct dma_chan *chan, struct scatterlist *sgl,
1338 unsigned int sg_len, enum dma_data_direction direction,
1339 unsigned long flags)
1341 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1342 struct pl08x_driver_data *pl08x = plchan->host;
1343 struct pl08x_txd *txd;
1344 u8 src_buses, dst_buses;
1348 * Current implementation ASSUMES only one sg
1351 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1356 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1357 __func__, sgl->length, plchan->name);
1359 txd = pl08x_get_txd(plchan);
1361 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1365 if (direction != plchan->runtime_direction)
1366 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1367 "the direction configured for the PrimeCell\n",
1371 * Set up addresses, the PrimeCell configured address
1372 * will take precedence since this may configure the
1373 * channel target address dynamically at runtime.
1375 txd->direction = direction;
1376 txd->len = sgl->length;
1378 txd->cctl = plchan->cd->cctl &
1379 ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1380 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1381 PL080_CONTROL_PROT_MASK);
1383 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1384 txd->cctl |= PL080_CONTROL_PROT_SYS;
1386 if (direction == DMA_TO_DEVICE) {
1387 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1388 txd->cctl |= PL080_CONTROL_SRC_INCR;
1389 txd->srcbus.addr = sgl->dma_address;
1390 if (plchan->runtime_addr)
1391 txd->dstbus.addr = plchan->runtime_addr;
1393 txd->dstbus.addr = plchan->cd->addr;
1394 src_buses = pl08x->mem_buses;
1395 dst_buses = plchan->cd->periph_buses;
1396 } else if (direction == DMA_FROM_DEVICE) {
1397 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1398 txd->cctl |= PL080_CONTROL_DST_INCR;
1399 if (plchan->runtime_addr)
1400 txd->srcbus.addr = plchan->runtime_addr;
1402 txd->srcbus.addr = plchan->cd->addr;
1403 txd->dstbus.addr = sgl->dma_address;
1404 src_buses = plchan->cd->periph_buses;
1405 dst_buses = pl08x->mem_buses;
1407 dev_err(&pl08x->adev->dev,
1408 "%s direction unsupported\n", __func__);
1412 txd->cctl |= pl08x_select_bus(pl08x, src_buses, dst_buses);
1414 ret = pl08x_prep_channel_resources(plchan, txd);
1418 * NB: the channel lock is held at this point so tx_submit()
1419 * must be called in direct succession.
1425 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1428 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1429 struct pl08x_driver_data *pl08x = plchan->host;
1430 unsigned long flags;
1433 /* Controls applicable to inactive channels */
1434 if (cmd == DMA_SLAVE_CONFIG) {
1435 dma_set_runtime_config(chan,
1436 (struct dma_slave_config *)
1442 * Anything succeeds on channels with no physical allocation and
1443 * no queued transfers.
1445 spin_lock_irqsave(&plchan->lock, flags);
1446 if (!plchan->phychan && !plchan->at) {
1447 spin_unlock_irqrestore(&plchan->lock, flags);
1452 case DMA_TERMINATE_ALL:
1453 plchan->state = PL08X_CHAN_IDLE;
1455 if (plchan->phychan) {
1456 pl08x_stop_phy_chan(plchan->phychan);
1459 * Mark physical channel as free and free any slave
1462 release_phy_channel(plchan);
1464 /* Dequeue jobs and free LLIs */
1466 pl08x_free_txd(pl08x, plchan->at);
1469 /* Dequeue jobs not yet fired as well */
1470 pl08x_free_txd_list(pl08x, plchan);
1473 pl08x_pause_phy_chan(plchan->phychan);
1474 plchan->state = PL08X_CHAN_PAUSED;
1477 pl08x_resume_phy_chan(plchan->phychan);
1478 plchan->state = PL08X_CHAN_RUNNING;
1481 /* Unknown command */
1486 spin_unlock_irqrestore(&plchan->lock, flags);
1491 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1493 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1494 char *name = chan_id;
1496 /* Check that the channel is not taken! */
1497 if (!strcmp(plchan->name, name))
1504 * Just check that the device is there and active
1505 * TODO: turn this bit on/off depending on the number of
1506 * physical channels actually used, if it is zero... well
1507 * shut it off. That will save some power. Cut the clock
1510 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1514 val = readl(pl08x->base + PL080_CONFIG);
1515 val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1516 /* We implicitly clear bit 1 and that means little-endian mode */
1517 val |= PL080_CONFIG_ENABLE;
1518 writel(val, pl08x->base + PL080_CONFIG);
1521 static void pl08x_tasklet(unsigned long data)
1523 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1524 struct pl08x_driver_data *pl08x = plchan->host;
1525 struct pl08x_txd *txd;
1526 dma_async_tx_callback callback = NULL;
1527 void *callback_param = NULL;
1528 unsigned long flags;
1530 spin_lock_irqsave(&plchan->lock, flags);
1536 callback = txd->tx.callback;
1537 callback_param = txd->tx.callback_param;
1540 * Update last completed
1542 plchan->lc = txd->tx.cookie;
1545 * Free the descriptor
1547 pl08x_free_txd(pl08x, txd);
1550 * If a new descriptor is queued, set it up
1551 * plchan->at is NULL here
1553 if (!list_empty(&plchan->desc_list)) {
1554 struct pl08x_txd *next;
1556 next = list_first_entry(&plchan->desc_list,
1559 list_del(&next->node);
1561 pl08x_start_txd(plchan, next);
1563 struct pl08x_dma_chan *waiting = NULL;
1566 * No more jobs, so free up the physical channel
1567 * Free any allocated signal on slave transfers too
1569 release_phy_channel(plchan);
1570 plchan->state = PL08X_CHAN_IDLE;
1573 * And NOW before anyone else can grab that free:d
1574 * up physical channel, see if there is some memcpy
1575 * pending that seriously needs to start because of
1576 * being stacked up while we were choking the
1577 * physical channels with data.
1579 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1581 if (waiting->state == PL08X_CHAN_WAITING &&
1582 waiting->waiting != NULL) {
1585 /* This should REALLY not fail now */
1586 ret = prep_phy_channel(waiting,
1589 waiting->state = PL08X_CHAN_RUNNING;
1590 waiting->waiting = NULL;
1591 pl08x_issue_pending(&waiting->chan);
1597 spin_unlock_irqrestore(&plchan->lock, flags);
1599 /* Callback to signal completion */
1601 callback(callback_param);
1604 static irqreturn_t pl08x_irq(int irq, void *dev)
1606 struct pl08x_driver_data *pl08x = dev;
1611 val = readl(pl08x->base + PL080_ERR_STATUS);
1614 * An error interrupt (on one or more channels)
1616 dev_err(&pl08x->adev->dev,
1617 "%s error interrupt, register value 0x%08x\n",
1620 * Simply clear ALL PL08X error interrupts,
1621 * regardless of channel and cause
1622 * FIXME: should be 0x00000003 on PL081 really.
1624 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1626 val = readl(pl08x->base + PL080_INT_STATUS);
1627 for (i = 0; i < pl08x->vd->channels; i++) {
1628 if ((1 << i) & val) {
1629 /* Locate physical channel */
1630 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1631 struct pl08x_dma_chan *plchan = phychan->serving;
1633 /* Schedule tasklet on this channel */
1634 tasklet_schedule(&plchan->tasklet);
1640 * Clear only the terminal interrupts on channels we processed
1642 writel(mask, pl08x->base + PL080_TC_CLEAR);
1644 return mask ? IRQ_HANDLED : IRQ_NONE;
1648 * Initialise the DMAC memcpy/slave channels.
1649 * Make a local wrapper to hold required data
1651 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1652 struct dma_device *dmadev,
1653 unsigned int channels,
1656 struct pl08x_dma_chan *chan;
1659 INIT_LIST_HEAD(&dmadev->channels);
1661 * Register as many many memcpy as we have physical channels,
1662 * we won't always be able to use all but the code will have
1663 * to cope with that situation.
1665 for (i = 0; i < channels; i++) {
1666 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1668 dev_err(&pl08x->adev->dev,
1669 "%s no memory for channel\n", __func__);
1674 chan->state = PL08X_CHAN_IDLE;
1678 chan->name = pl08x->pd->slave_channels[i].bus_id;
1679 chan->cd = &pl08x->pd->slave_channels[i];
1681 chan->cd = &pl08x->pd->memcpy_channel;
1682 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1688 if (chan->cd->circular_buffer) {
1689 dev_err(&pl08x->adev->dev,
1690 "channel %s: circular buffers not supported\n",
1695 dev_info(&pl08x->adev->dev,
1696 "initialize virtual channel \"%s\"\n",
1699 chan->chan.device = dmadev;
1700 chan->chan.cookie = 0;
1703 spin_lock_init(&chan->lock);
1704 INIT_LIST_HEAD(&chan->desc_list);
1705 tasklet_init(&chan->tasklet, pl08x_tasklet,
1706 (unsigned long) chan);
1708 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1710 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1711 i, slave ? "slave" : "memcpy");
1715 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1717 struct pl08x_dma_chan *chan = NULL;
1718 struct pl08x_dma_chan *next;
1720 list_for_each_entry_safe(chan,
1721 next, &dmadev->channels, chan.device_node) {
1722 list_del(&chan->chan.device_node);
1727 #ifdef CONFIG_DEBUG_FS
1728 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1731 case PL08X_CHAN_IDLE:
1733 case PL08X_CHAN_RUNNING:
1735 case PL08X_CHAN_PAUSED:
1737 case PL08X_CHAN_WAITING:
1742 return "UNKNOWN STATE";
1745 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1747 struct pl08x_driver_data *pl08x = s->private;
1748 struct pl08x_dma_chan *chan;
1749 struct pl08x_phy_chan *ch;
1750 unsigned long flags;
1753 seq_printf(s, "PL08x physical channels:\n");
1754 seq_printf(s, "CHANNEL:\tUSER:\n");
1755 seq_printf(s, "--------\t-----\n");
1756 for (i = 0; i < pl08x->vd->channels; i++) {
1757 struct pl08x_dma_chan *virt_chan;
1759 ch = &pl08x->phy_chans[i];
1761 spin_lock_irqsave(&ch->lock, flags);
1762 virt_chan = ch->serving;
1764 seq_printf(s, "%d\t\t%s\n",
1765 ch->id, virt_chan ? virt_chan->name : "(none)");
1767 spin_unlock_irqrestore(&ch->lock, flags);
1770 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1771 seq_printf(s, "CHANNEL:\tSTATE:\n");
1772 seq_printf(s, "--------\t------\n");
1773 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1774 seq_printf(s, "%s\t\t%s\n", chan->name,
1775 pl08x_state_str(chan->state));
1778 seq_printf(s, "\nPL08x virtual slave channels:\n");
1779 seq_printf(s, "CHANNEL:\tSTATE:\n");
1780 seq_printf(s, "--------\t------\n");
1781 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1782 seq_printf(s, "%s\t\t%s\n", chan->name,
1783 pl08x_state_str(chan->state));
1789 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1791 return single_open(file, pl08x_debugfs_show, inode->i_private);
1794 static const struct file_operations pl08x_debugfs_operations = {
1795 .open = pl08x_debugfs_open,
1797 .llseek = seq_lseek,
1798 .release = single_release,
1801 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1803 /* Expose a simple debugfs interface to view all clocks */
1804 (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1806 &pl08x_debugfs_operations);
1810 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1815 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1817 struct pl08x_driver_data *pl08x;
1818 const struct vendor_data *vd = id->data;
1822 ret = amba_request_regions(adev, NULL);
1826 /* Create the driver state holder */
1827 pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1833 /* Initialize memcpy engine */
1834 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1835 pl08x->memcpy.dev = &adev->dev;
1836 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1837 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1838 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1839 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1840 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1841 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1842 pl08x->memcpy.device_control = pl08x_control;
1844 /* Initialize slave engine */
1845 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1846 pl08x->slave.dev = &adev->dev;
1847 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1848 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1849 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1850 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1851 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1852 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1853 pl08x->slave.device_control = pl08x_control;
1855 /* Get the platform data */
1856 pl08x->pd = dev_get_platdata(&adev->dev);
1858 dev_err(&adev->dev, "no platform data supplied\n");
1859 goto out_no_platdata;
1862 /* Assign useful pointers to the driver state */
1866 /* By default, AHB1 only. If dualmaster, from platform */
1867 pl08x->lli_buses = PL08X_AHB1;
1868 pl08x->mem_buses = PL08X_AHB1;
1869 if (pl08x->vd->dualmaster) {
1870 pl08x->lli_buses = pl08x->pd->lli_buses;
1871 pl08x->mem_buses = pl08x->pd->mem_buses;
1874 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1875 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1876 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1879 goto out_no_lli_pool;
1882 spin_lock_init(&pl08x->lock);
1884 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1887 goto out_no_ioremap;
1890 /* Turn on the PL08x */
1891 pl08x_ensure_on(pl08x);
1894 * Attach the interrupt handler
1896 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1897 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1899 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1900 DRIVER_NAME, pl08x);
1902 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1903 __func__, adev->irq[0]);
1907 /* Initialize physical channels */
1908 pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1910 if (!pl08x->phy_chans) {
1911 dev_err(&adev->dev, "%s failed to allocate "
1912 "physical channel holders\n",
1914 goto out_no_phychans;
1917 for (i = 0; i < vd->channels; i++) {
1918 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1921 ch->base = pl08x->base + PL080_Cx_BASE(i);
1922 spin_lock_init(&ch->lock);
1925 dev_info(&adev->dev,
1926 "physical channel %d is %s\n", i,
1927 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1930 /* Register as many memcpy channels as there are physical channels */
1931 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1932 pl08x->vd->channels, false);
1934 dev_warn(&pl08x->adev->dev,
1935 "%s failed to enumerate memcpy channels - %d\n",
1939 pl08x->memcpy.chancnt = ret;
1941 /* Register slave channels */
1942 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
1943 pl08x->pd->num_slave_channels,
1946 dev_warn(&pl08x->adev->dev,
1947 "%s failed to enumerate slave channels - %d\n",
1951 pl08x->slave.chancnt = ret;
1953 ret = dma_async_device_register(&pl08x->memcpy);
1955 dev_warn(&pl08x->adev->dev,
1956 "%s failed to register memcpy as an async device - %d\n",
1958 goto out_no_memcpy_reg;
1961 ret = dma_async_device_register(&pl08x->slave);
1963 dev_warn(&pl08x->adev->dev,
1964 "%s failed to register slave as an async device - %d\n",
1966 goto out_no_slave_reg;
1969 amba_set_drvdata(adev, pl08x);
1970 init_pl08x_debugfs(pl08x);
1971 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
1972 amba_part(adev), amba_rev(adev),
1973 (unsigned long long)adev->res.start, adev->irq[0]);
1977 dma_async_device_unregister(&pl08x->memcpy);
1979 pl08x_free_virtual_channels(&pl08x->slave);
1981 pl08x_free_virtual_channels(&pl08x->memcpy);
1983 kfree(pl08x->phy_chans);
1985 free_irq(adev->irq[0], pl08x);
1987 iounmap(pl08x->base);
1989 dma_pool_destroy(pl08x->pool);
1994 amba_release_regions(adev);
1998 /* PL080 has 8 channels and the PL080 have just 2 */
1999 static struct vendor_data vendor_pl080 = {
2004 static struct vendor_data vendor_pl081 = {
2006 .dualmaster = false,
2009 static struct amba_id pl08x_ids[] = {
2014 .data = &vendor_pl080,
2020 .data = &vendor_pl081,
2022 /* Nomadik 8815 PL080 variant */
2026 .data = &vendor_pl080,
2031 static struct amba_driver pl08x_amba_driver = {
2032 .drv.name = DRIVER_NAME,
2033 .id_table = pl08x_ids,
2034 .probe = pl08x_probe,
2037 static int __init pl08x_init(void)
2040 retval = amba_driver_register(&pl08x_amba_driver);
2042 printk(KERN_WARNING DRIVER_NAME
2043 "failed to register as an AMBA device (%d)\n",
2047 subsys_initcall(pl08x_init);