2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
70 * - Break out common code from arch/arm/mach-s3c64xx and share
72 #include <linux/amba/bus.h>
73 #include <linux/amba/pl08x.h>
74 #include <linux/debugfs.h>
75 #include <linux/delay.h>
76 #include <linux/device.h>
77 #include <linux/dmaengine.h>
78 #include <linux/dmapool.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/interrupt.h>
82 #include <linux/module.h>
83 #include <linux/pm_runtime.h>
84 #include <linux/seq_file.h>
85 #include <linux/slab.h>
86 #include <asm/hardware/pl080.h>
88 #include "dmaengine.h"
90 #define DRIVER_NAME "pl08xdmac"
92 static struct amba_driver pl08x_amba_driver;
93 struct pl08x_driver_data;
96 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
97 * @channels: the number of channels available in this variant
98 * @dualmaster: whether this version supports dual AHB masters or not.
99 * @nomadik: whether the channels have Nomadik security extension bits
100 * that need to be checked for permission before use and some registers are
110 * PL08X private data structures
111 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
112 * start & end do not - their bus bit info is in cctl. Also note that these
113 * are fixed 32-bit quantities.
123 * struct pl08x_bus_data - information of source or destination
124 * busses for a transfer
125 * @addr: current address
126 * @maxwidth: the maximum width of a transfer on this bus
127 * @buswidth: the width of this bus in bytes: 1, 2 or 4
129 struct pl08x_bus_data {
136 * struct pl08x_phy_chan - holder for the physical channels
137 * @id: physical index to this channel
138 * @lock: a lock to use when altering an instance of this struct
139 * @signal: the physical signal (aka channel) serving this physical channel
141 * @serving: the virtual channel currently being served by this physical
144 struct pl08x_phy_chan {
149 struct pl08x_dma_chan *serving;
153 * struct pl08x_sg - structure containing data per sg
154 * @src_addr: src address of sg
155 * @dst_addr: dst address of sg
156 * @len: transfer len in bytes
157 * @node: node for txd's dsg_list
163 struct list_head node;
167 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
168 * @tx: async tx descriptor
169 * @node: node for txd list for channels
170 * @dsg_list: list of children sg's
171 * @direction: direction of transfer
172 * @llis_bus: DMA memory address (physical) start for the LLIs
173 * @llis_va: virtual memory address start for the LLIs
174 * @cctl: control reg values for current txd
175 * @ccfg: config reg values for current txd
178 struct dma_async_tx_descriptor tx;
179 struct list_head node;
180 struct list_head dsg_list;
181 enum dma_transfer_direction direction;
183 struct pl08x_lli *llis_va;
184 /* Default cctl value for LLIs */
187 * Settings to be put into the physical channel when we
188 * trigger this txd. Other registers are in llis_va[0].
194 * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
196 * @PL08X_CHAN_IDLE: the channel is idle
197 * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
198 * channel and is running a transfer on it
199 * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
200 * channel, but the transfer is currently paused
201 * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
202 * channel to become available (only pertains to memcpy channels)
204 enum pl08x_dma_chan_state {
212 * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
213 * @chan: wrappped abstract channel
214 * @phychan: the physical channel utilized by this channel, if there is one
215 * @phychan_hold: if non-zero, hold on to the physical channel even if we
216 * have no pending entries
217 * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
218 * @name: name of channel
219 * @cd: channel platform data
220 * @runtime_addr: address for RX/TX according to the runtime config
221 * @runtime_direction: current direction of this channel according to
223 * @pend_list: queued transactions pending on this channel
224 * @at: active transaction on this channel
225 * @lock: a lock for this channel data
226 * @host: a pointer to the host (internal use)
227 * @state: whether the channel is idle, paused, running etc
228 * @slave: whether this channel is a device (slave) or for memcpy
229 * @waiting: a TX descriptor on this channel which is waiting for a physical
230 * channel to become available
232 struct pl08x_dma_chan {
233 struct dma_chan chan;
234 struct pl08x_phy_chan *phychan;
236 struct tasklet_struct tasklet;
238 const struct pl08x_channel_data *cd;
239 struct dma_slave_config cfg;
242 enum dma_transfer_direction runtime_direction;
243 struct list_head pend_list;
244 struct pl08x_txd *at;
246 struct pl08x_driver_data *host;
247 enum pl08x_dma_chan_state state;
249 struct pl08x_txd *waiting;
253 * struct pl08x_driver_data - the local state holder for the PL08x
254 * @slave: slave engine for this instance
255 * @memcpy: memcpy engine for this instance
256 * @base: virtual memory base (remapped) for the PL08x
257 * @adev: the corresponding AMBA (PrimeCell) bus entry
258 * @vd: vendor data for this PL08x variant
259 * @pd: platform data passed in from the platform/machine
260 * @phy_chans: array of data for the physical channels
261 * @pool: a pool for the LLI descriptors
262 * @pool_ctr: counter of LLIs in the pool
263 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
265 * @mem_buses: set to indicate memory transfers on AHB2.
266 * @lock: a spinlock for this struct
268 struct pl08x_driver_data {
269 struct dma_device slave;
270 struct dma_device memcpy;
272 struct amba_device *adev;
273 const struct vendor_data *vd;
274 struct pl08x_platform_data *pd;
275 struct pl08x_phy_chan *phy_chans;
276 struct dma_pool *pool;
283 * PL08X specific defines
286 /* Size (bytes) of each LLI buffer allocated for one transfer */
287 # define PL08X_LLI_TSFR_SIZE 0x2000
289 /* Maximum times we call dma_pool_alloc on this pool without freeing */
290 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
291 #define PL08X_ALIGN 8
293 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
295 return container_of(chan, struct pl08x_dma_chan, chan);
298 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
300 return container_of(tx, struct pl08x_txd, tx);
304 * Physical channel handling
307 /* Whether a certain channel is busy or not */
308 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
312 val = readl(ch->base + PL080_CH_CONFIG);
313 return val & PL080_CONFIG_ACTIVE;
317 * Set the initial DMA register values i.e. those for the first LLI
318 * The next LLI pointer and the configuration interrupt bit have
319 * been set when the LLIs were constructed. Poke them into the hardware
320 * and start the transfer.
322 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
323 struct pl08x_txd *txd)
325 struct pl08x_driver_data *pl08x = plchan->host;
326 struct pl08x_phy_chan *phychan = plchan->phychan;
327 struct pl08x_lli *lli = &txd->llis_va[0];
332 /* Wait for channel inactive */
333 while (pl08x_phy_channel_busy(phychan))
336 dev_vdbg(&pl08x->adev->dev,
337 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
338 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
339 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
342 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
343 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
344 writel(lli->lli, phychan->base + PL080_CH_LLI);
345 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
346 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
348 /* Enable the DMA channel */
349 /* Do not access config register until channel shows as disabled */
350 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
353 /* Do not access config register until channel shows as inactive */
354 val = readl(phychan->base + PL080_CH_CONFIG);
355 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
356 val = readl(phychan->base + PL080_CH_CONFIG);
358 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
362 * Pause the channel by setting the HALT bit.
364 * For M->P transfers, pause the DMAC first and then stop the peripheral -
365 * the FIFO can only drain if the peripheral is still requesting data.
366 * (note: this can still timeout if the DMAC FIFO never drains of data.)
368 * For P->M transfers, disable the peripheral first to stop it filling
369 * the DMAC FIFO, and then pause the DMAC.
371 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
376 /* Set the HALT bit and wait for the FIFO to drain */
377 val = readl(ch->base + PL080_CH_CONFIG);
378 val |= PL080_CONFIG_HALT;
379 writel(val, ch->base + PL080_CH_CONFIG);
381 /* Wait for channel inactive */
382 for (timeout = 1000; timeout; timeout--) {
383 if (!pl08x_phy_channel_busy(ch))
387 if (pl08x_phy_channel_busy(ch))
388 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
391 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
395 /* Clear the HALT bit */
396 val = readl(ch->base + PL080_CH_CONFIG);
397 val &= ~PL080_CONFIG_HALT;
398 writel(val, ch->base + PL080_CH_CONFIG);
402 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
403 * clears any pending interrupt status. This should not be used for
404 * an on-going transfer, but as a method of shutting down a channel
405 * (eg, when it's no longer used) or terminating a transfer.
407 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
408 struct pl08x_phy_chan *ch)
410 u32 val = readl(ch->base + PL080_CH_CONFIG);
412 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
413 PL080_CONFIG_TC_IRQ_MASK);
415 writel(val, ch->base + PL080_CH_CONFIG);
417 writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
418 writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
421 static inline u32 get_bytes_in_cctl(u32 cctl)
423 /* The source width defines the number of bytes */
424 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
426 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
427 case PL080_WIDTH_8BIT:
429 case PL080_WIDTH_16BIT:
432 case PL080_WIDTH_32BIT:
439 /* The channel should be paused when calling this */
440 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
442 struct pl08x_phy_chan *ch;
443 struct pl08x_txd *txd;
447 spin_lock_irqsave(&plchan->lock, flags);
448 ch = plchan->phychan;
452 * Follow the LLIs to get the number of remaining
453 * bytes in the currently active transaction.
456 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
458 /* First get the remaining bytes in the active transfer */
459 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
462 struct pl08x_lli *llis_va = txd->llis_va;
463 dma_addr_t llis_bus = txd->llis_bus;
466 BUG_ON(clli < llis_bus || clli >= llis_bus +
467 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
470 * Locate the next LLI - as this is an array,
471 * it's simple maths to find.
473 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
475 for (; index < MAX_NUM_TSFR_LLIS; index++) {
476 bytes += get_bytes_in_cctl(llis_va[index].cctl);
479 * A LLI pointer of 0 terminates the LLI list
481 if (!llis_va[index].lli)
487 /* Sum up all queued transactions */
488 if (!list_empty(&plchan->pend_list)) {
489 struct pl08x_txd *txdi;
490 list_for_each_entry(txdi, &plchan->pend_list, node) {
491 struct pl08x_sg *dsg;
492 list_for_each_entry(dsg, &txd->dsg_list, node)
497 spin_unlock_irqrestore(&plchan->lock, flags);
503 * Allocate a physical channel for a virtual channel
505 * Try to locate a physical channel to be used for this transfer. If all
506 * are taken return NULL and the requester will have to cope by using
507 * some fallback PIO mode or retrying later.
509 static struct pl08x_phy_chan *
510 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
511 struct pl08x_dma_chan *virt_chan)
513 struct pl08x_phy_chan *ch = NULL;
517 for (i = 0; i < pl08x->vd->channels; i++) {
518 ch = &pl08x->phy_chans[i];
520 spin_lock_irqsave(&ch->lock, flags);
522 if (!ch->locked && !ch->serving) {
523 ch->serving = virt_chan;
525 spin_unlock_irqrestore(&ch->lock, flags);
529 spin_unlock_irqrestore(&ch->lock, flags);
532 if (i == pl08x->vd->channels) {
533 /* No physical channel available, cope with it */
540 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
541 struct pl08x_phy_chan *ch)
545 spin_lock_irqsave(&ch->lock, flags);
547 /* Stop the channel and clear its interrupts */
548 pl08x_terminate_phy_chan(pl08x, ch);
550 /* Mark it as free */
552 spin_unlock_irqrestore(&ch->lock, flags);
559 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
562 case PL080_WIDTH_8BIT:
564 case PL080_WIDTH_16BIT:
566 case PL080_WIDTH_32BIT:
575 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
580 /* Remove all src, dst and transfer size bits */
581 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
582 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
583 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
585 /* Then set the bits according to the parameters */
588 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
591 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
594 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
603 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
606 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
609 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
616 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
620 struct pl08x_lli_build_data {
621 struct pl08x_txd *txd;
622 struct pl08x_bus_data srcbus;
623 struct pl08x_bus_data dstbus;
629 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
630 * victim in case src & dest are not similarly aligned. i.e. If after aligning
631 * masters address with width requirements of transfer (by sending few byte by
632 * byte data), slave is still not aligned, then its width will be reduced to
634 * - prefers the destination bus if both available
635 * - prefers bus with fixed address (i.e. peripheral)
637 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
638 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
640 if (!(cctl & PL080_CONTROL_DST_INCR)) {
643 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
647 if (bd->dstbus.buswidth >= bd->srcbus.buswidth) {
658 * Fills in one LLI for a certain transfer descriptor and advance the counter
660 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
661 int num_llis, int len, u32 cctl)
663 struct pl08x_lli *llis_va = bd->txd->llis_va;
664 dma_addr_t llis_bus = bd->txd->llis_bus;
666 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
668 llis_va[num_llis].cctl = cctl;
669 llis_va[num_llis].src = bd->srcbus.addr;
670 llis_va[num_llis].dst = bd->dstbus.addr;
671 llis_va[num_llis].lli = llis_bus + (num_llis + 1) *
672 sizeof(struct pl08x_lli);
673 llis_va[num_llis].lli |= bd->lli_bus;
675 if (cctl & PL080_CONTROL_SRC_INCR)
676 bd->srcbus.addr += len;
677 if (cctl & PL080_CONTROL_DST_INCR)
678 bd->dstbus.addr += len;
680 BUG_ON(bd->remainder < len);
682 bd->remainder -= len;
685 static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd,
686 u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
688 *cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
689 pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl);
690 (*total_bytes) += len;
694 * This fills in the table of LLIs for the transfer descriptor
695 * Note that we assume we never have to change the burst sizes
698 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
699 struct pl08x_txd *txd)
701 struct pl08x_bus_data *mbus, *sbus;
702 struct pl08x_lli_build_data bd;
704 u32 cctl, early_bytes = 0;
705 size_t max_bytes_per_lli, total_bytes;
706 struct pl08x_lli *llis_va;
707 struct pl08x_sg *dsg;
709 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
711 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
718 bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
721 /* Find maximum width of the source bus */
723 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
724 PL080_CONTROL_SWIDTH_SHIFT);
726 /* Find maximum width of the destination bus */
728 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
729 PL080_CONTROL_DWIDTH_SHIFT);
731 list_for_each_entry(dsg, &txd->dsg_list, node) {
735 bd.srcbus.addr = dsg->src_addr;
736 bd.dstbus.addr = dsg->dst_addr;
737 bd.remainder = dsg->len;
738 bd.srcbus.buswidth = bd.srcbus.maxwidth;
739 bd.dstbus.buswidth = bd.dstbus.maxwidth;
741 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
743 dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
744 bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
746 bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
749 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
750 mbus == &bd.srcbus ? "src" : "dst",
751 sbus == &bd.srcbus ? "src" : "dst");
754 * Zero length is only allowed if all these requirements are
756 * - flow controller is peripheral.
757 * - src.addr is aligned to src.width
758 * - dst.addr is aligned to dst.width
760 * sg_len == 1 should be true, as there can be two cases here:
762 * - Memory addresses are contiguous and are not scattered.
763 * Here, Only one sg will be passed by user driver, with
764 * memory address and zero length. We pass this to controller
765 * and after the transfer it will receive the last burst
766 * request from peripheral and so transfer finishes.
768 * - Memory addresses are scattered and are not contiguous.
769 * Here, Obviously as DMA controller doesn't know when a lli's
770 * transfer gets over, it can't load next lli. So in this
771 * case, there has to be an assumption that only one lli is
772 * supported. Thus, we can't have scattered addresses.
775 u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >>
776 PL080_CONFIG_FLOW_CONTROL_SHIFT;
777 if (!((fc >= PL080_FLOW_SRC2DST_DST) &&
778 (fc <= PL080_FLOW_SRC2DST_SRC))) {
779 dev_err(&pl08x->adev->dev, "%s sg len can't be zero",
784 if ((bd.srcbus.addr % bd.srcbus.buswidth) ||
785 (bd.dstbus.addr % bd.dstbus.buswidth)) {
786 dev_err(&pl08x->adev->dev,
787 "%s src & dst address must be aligned to src"
788 " & dst width if peripheral is flow controller",
793 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
794 bd.dstbus.buswidth, 0);
795 pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl);
800 * Send byte by byte for following cases
801 * - Less than a bus width available
802 * - until master bus is aligned
804 if (bd.remainder < mbus->buswidth)
805 early_bytes = bd.remainder;
806 else if ((mbus->addr) % (mbus->buswidth)) {
807 early_bytes = mbus->buswidth - (mbus->addr) %
809 if ((bd.remainder - early_bytes) < mbus->buswidth)
810 early_bytes = bd.remainder;
814 dev_vdbg(&pl08x->adev->dev,
815 "%s byte width LLIs (remain 0x%08x)\n",
816 __func__, bd.remainder);
817 prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++,
824 * - if slave is not then we must set its width down
826 if (sbus->addr % sbus->buswidth) {
827 dev_dbg(&pl08x->adev->dev,
828 "%s set down bus width to one byte\n",
835 * Bytes transferred = tsize * src width, not
838 max_bytes_per_lli = bd.srcbus.buswidth *
839 PL080_CONTROL_TRANSFER_SIZE_MASK;
840 dev_vdbg(&pl08x->adev->dev,
841 "%s max bytes per lli = %zu\n",
842 __func__, max_bytes_per_lli);
845 * Make largest possible LLIs until less than one bus
848 while (bd.remainder > (mbus->buswidth - 1)) {
849 size_t lli_len, tsize, width;
852 * If enough left try to send max possible,
853 * otherwise try to send the remainder
855 lli_len = min(bd.remainder, max_bytes_per_lli);
858 * Check against maximum bus alignment:
859 * Calculate actual transfer size in relation to
860 * bus width an get a maximum remainder of the
861 * highest bus width - 1
863 width = max(mbus->buswidth, sbus->buswidth);
864 lli_len = (lli_len / width) * width;
865 tsize = lli_len / bd.srcbus.buswidth;
867 dev_vdbg(&pl08x->adev->dev,
868 "%s fill lli with single lli chunk of "
869 "size 0x%08zx (remainder 0x%08zx)\n",
870 __func__, lli_len, bd.remainder);
872 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
873 bd.dstbus.buswidth, tsize);
874 pl08x_fill_lli_for_desc(&bd, num_llis++,
876 total_bytes += lli_len;
883 dev_vdbg(&pl08x->adev->dev,
884 "%s align with boundary, send odd bytes (remain %zu)\n",
885 __func__, bd.remainder);
886 prep_byte_width_lli(&bd, &cctl, bd.remainder,
887 num_llis++, &total_bytes);
891 if (total_bytes != dsg->len) {
892 dev_err(&pl08x->adev->dev,
893 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
894 __func__, total_bytes, dsg->len);
898 if (num_llis >= MAX_NUM_TSFR_LLIS) {
899 dev_err(&pl08x->adev->dev,
900 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
901 __func__, (u32) MAX_NUM_TSFR_LLIS);
906 llis_va = txd->llis_va;
907 /* The final LLI terminates the LLI. */
908 llis_va[num_llis - 1].lli = 0;
909 /* The final LLI element shall also fire an interrupt. */
910 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
916 dev_vdbg(&pl08x->adev->dev,
917 "%-3s %-9s %-10s %-10s %-10s %s\n",
918 "lli", "", "csrc", "cdst", "clli", "cctl");
919 for (i = 0; i < num_llis; i++) {
920 dev_vdbg(&pl08x->adev->dev,
921 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
922 i, &llis_va[i], llis_va[i].src,
923 llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl
932 /* You should call this with the struct pl08x lock held */
933 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
934 struct pl08x_txd *txd)
936 struct pl08x_sg *dsg, *_dsg;
940 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
944 list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) {
945 list_del(&dsg->node);
952 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
953 struct pl08x_dma_chan *plchan)
955 struct pl08x_txd *txdi = NULL;
956 struct pl08x_txd *next;
958 if (!list_empty(&plchan->pend_list)) {
959 list_for_each_entry_safe(txdi,
960 next, &plchan->pend_list, node) {
961 list_del(&txdi->node);
962 pl08x_free_txd(pl08x, txdi);
970 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
975 static void pl08x_free_chan_resources(struct dma_chan *chan)
980 * This should be called with the channel plchan->lock held
982 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
983 struct pl08x_txd *txd)
985 struct pl08x_driver_data *pl08x = plchan->host;
986 struct pl08x_phy_chan *ch;
989 /* Check if we already have a channel */
990 if (plchan->phychan) {
991 ch = plchan->phychan;
995 ch = pl08x_get_phy_channel(pl08x, plchan);
997 /* No physical channel available, cope with it */
998 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
1003 * OK we have a physical channel: for memcpy() this is all we
1004 * need, but for slaves the physical signals may be muxed!
1005 * Can the platform allow us to use this channel?
1007 if (plchan->slave && pl08x->pd->get_signal) {
1008 ret = pl08x->pd->get_signal(plchan->cd);
1010 dev_dbg(&pl08x->adev->dev,
1011 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1012 ch->id, plchan->name);
1013 /* Release physical channel & return */
1014 pl08x_put_phy_channel(pl08x, ch);
1020 plchan->phychan = ch;
1021 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
1027 /* Assign the flow control signal to this channel */
1028 if (txd->direction == DMA_MEM_TO_DEV)
1029 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
1030 else if (txd->direction == DMA_DEV_TO_MEM)
1031 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
1033 plchan->phychan_hold++;
1038 static void release_phy_channel(struct pl08x_dma_chan *plchan)
1040 struct pl08x_driver_data *pl08x = plchan->host;
1042 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
1043 pl08x->pd->put_signal(plchan->cd, plchan->phychan->signal);
1044 plchan->phychan->signal = -1;
1046 pl08x_put_phy_channel(pl08x, plchan->phychan);
1047 plchan->phychan = NULL;
1050 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
1052 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
1053 struct pl08x_txd *txd = to_pl08x_txd(tx);
1054 unsigned long flags;
1055 dma_cookie_t cookie;
1057 spin_lock_irqsave(&plchan->lock, flags);
1058 cookie = dma_cookie_assign(tx);
1060 /* Put this onto the pending list */
1061 list_add_tail(&txd->node, &plchan->pend_list);
1064 * If there was no physical channel available for this memcpy,
1065 * stack the request up and indicate that the channel is waiting
1066 * for a free physical channel.
1068 if (!plchan->slave && !plchan->phychan) {
1069 /* Do this memcpy whenever there is a channel ready */
1070 plchan->state = PL08X_CHAN_WAITING;
1071 plchan->waiting = txd;
1073 plchan->phychan_hold--;
1076 spin_unlock_irqrestore(&plchan->lock, flags);
1081 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1082 struct dma_chan *chan, unsigned long flags)
1084 struct dma_async_tx_descriptor *retval = NULL;
1090 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1091 * If slaves are relying on interrupts to signal completion this function
1092 * must not be called with interrupts disabled.
1094 static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
1095 dma_cookie_t cookie, struct dma_tx_state *txstate)
1097 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1098 enum dma_status ret;
1100 ret = dma_cookie_status(chan, cookie, txstate);
1101 if (ret == DMA_SUCCESS)
1105 * This cookie not complete yet
1106 * Get number of bytes left in the active transactions and queue
1108 dma_set_residue(txstate, pl08x_getbytes_chan(plchan));
1110 if (plchan->state == PL08X_CHAN_PAUSED)
1113 /* Whether waiting or running, we're in progress */
1114 return DMA_IN_PROGRESS;
1117 /* PrimeCell DMA extension */
1118 struct burst_table {
1123 static const struct burst_table burst_sizes[] = {
1126 .reg = PL080_BSIZE_256,
1130 .reg = PL080_BSIZE_128,
1134 .reg = PL080_BSIZE_64,
1138 .reg = PL080_BSIZE_32,
1142 .reg = PL080_BSIZE_16,
1146 .reg = PL080_BSIZE_8,
1150 .reg = PL080_BSIZE_4,
1154 .reg = PL080_BSIZE_1,
1159 * Given the source and destination available bus masks, select which
1160 * will be routed to each port. We try to have source and destination
1161 * on separate ports, but always respect the allowable settings.
1163 static u32 pl08x_select_bus(u8 src, u8 dst)
1167 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1168 cctl |= PL080_CONTROL_DST_AHB2;
1169 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1170 cctl |= PL080_CONTROL_SRC_AHB2;
1175 static u32 pl08x_cctl(u32 cctl)
1177 cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1178 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1179 PL080_CONTROL_PROT_MASK);
1181 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1182 return cctl | PL080_CONTROL_PROT_SYS;
1185 static u32 pl08x_width(enum dma_slave_buswidth width)
1188 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1189 return PL080_WIDTH_8BIT;
1190 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1191 return PL080_WIDTH_16BIT;
1192 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1193 return PL080_WIDTH_32BIT;
1199 static u32 pl08x_burst(u32 maxburst)
1203 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1204 if (burst_sizes[i].burstwords <= maxburst)
1207 return burst_sizes[i].reg;
1210 static int dma_set_runtime_config(struct dma_chan *chan,
1211 struct dma_slave_config *config)
1213 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1214 struct pl08x_driver_data *pl08x = plchan->host;
1215 enum dma_slave_buswidth addr_width;
1216 u32 width, burst, maxburst;
1222 /* Transfer direction */
1223 plchan->runtime_direction = config->direction;
1224 if (config->direction == DMA_MEM_TO_DEV) {
1225 addr_width = config->dst_addr_width;
1226 maxburst = config->dst_maxburst;
1227 } else if (config->direction == DMA_DEV_TO_MEM) {
1228 addr_width = config->src_addr_width;
1229 maxburst = config->src_maxburst;
1231 dev_err(&pl08x->adev->dev,
1232 "bad runtime_config: alien transfer direction\n");
1236 width = pl08x_width(addr_width);
1238 dev_err(&pl08x->adev->dev,
1239 "bad runtime_config: alien address width\n");
1243 plchan->cfg = *config;
1245 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1246 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1249 * If this channel will only request single transfers, set this
1250 * down to ONE element. Also select one element if no maxburst
1253 if (plchan->cd->single)
1256 burst = pl08x_burst(maxburst);
1257 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1258 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1260 if (plchan->runtime_direction == DMA_DEV_TO_MEM) {
1261 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
1262 pl08x_select_bus(plchan->cd->periph_buses,
1265 plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR |
1266 pl08x_select_bus(pl08x->mem_buses,
1267 plchan->cd->periph_buses);
1270 dev_dbg(&pl08x->adev->dev,
1271 "configured channel %s (%s) for %s, data width %d, "
1272 "maxburst %d words, LE, CCTL=0x%08x\n",
1273 dma_chan_name(chan), plchan->name,
1274 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
1283 * Slave transactions callback to the slave device to allow
1284 * synchronization of slave DMA signals with the DMAC enable
1286 static void pl08x_issue_pending(struct dma_chan *chan)
1288 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1289 unsigned long flags;
1291 spin_lock_irqsave(&plchan->lock, flags);
1292 /* Something is already active, or we're waiting for a channel... */
1293 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1294 spin_unlock_irqrestore(&plchan->lock, flags);
1298 /* Take the first element in the queue and execute it */
1299 if (!list_empty(&plchan->pend_list)) {
1300 struct pl08x_txd *next;
1302 next = list_first_entry(&plchan->pend_list,
1305 list_del(&next->node);
1306 plchan->state = PL08X_CHAN_RUNNING;
1308 pl08x_start_txd(plchan, next);
1311 spin_unlock_irqrestore(&plchan->lock, flags);
1314 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1315 struct pl08x_txd *txd)
1317 struct pl08x_driver_data *pl08x = plchan->host;
1318 unsigned long flags;
1321 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1323 spin_lock_irqsave(&plchan->lock, flags);
1324 pl08x_free_txd(pl08x, txd);
1325 spin_unlock_irqrestore(&plchan->lock, flags);
1329 spin_lock_irqsave(&plchan->lock, flags);
1332 * See if we already have a physical channel allocated,
1333 * else this is the time to try to get one.
1335 ret = prep_phy_channel(plchan, txd);
1338 * No physical channel was available.
1340 * memcpy transfers can be sorted out at submission time.
1342 * Slave transfers may have been denied due to platform
1343 * channel muxing restrictions. Since there is no guarantee
1344 * that this will ever be resolved, and the signal must be
1345 * acquired AFTER acquiring the physical channel, we will let
1346 * them be NACK:ed with -EBUSY here. The drivers can retry
1347 * the prep() call if they are eager on doing this using DMA.
1349 if (plchan->slave) {
1350 pl08x_free_txd_list(pl08x, plchan);
1351 pl08x_free_txd(pl08x, txd);
1352 spin_unlock_irqrestore(&plchan->lock, flags);
1357 * Else we're all set, paused and ready to roll, status
1358 * will switch to PL08X_CHAN_RUNNING when we call
1359 * issue_pending(). If there is something running on the
1360 * channel already we don't change its state.
1362 if (plchan->state == PL08X_CHAN_IDLE)
1363 plchan->state = PL08X_CHAN_PAUSED;
1365 spin_unlock_irqrestore(&plchan->lock, flags);
1370 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
1371 unsigned long flags)
1373 struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
1376 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1377 txd->tx.flags = flags;
1378 txd->tx.tx_submit = pl08x_tx_submit;
1379 INIT_LIST_HEAD(&txd->node);
1380 INIT_LIST_HEAD(&txd->dsg_list);
1382 /* Always enable error and terminal interrupts */
1383 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1384 PL080_CONFIG_TC_IRQ_MASK;
1390 * Initialize a descriptor to be used by memcpy submit
1392 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1393 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1394 size_t len, unsigned long flags)
1396 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1397 struct pl08x_driver_data *pl08x = plchan->host;
1398 struct pl08x_txd *txd;
1399 struct pl08x_sg *dsg;
1402 txd = pl08x_get_txd(plchan, flags);
1404 dev_err(&pl08x->adev->dev,
1405 "%s no memory for descriptor\n", __func__);
1409 dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
1411 pl08x_free_txd(pl08x, txd);
1412 dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n",
1416 list_add_tail(&dsg->node, &txd->dsg_list);
1418 txd->direction = DMA_MEM_TO_MEM;
1419 dsg->src_addr = src;
1420 dsg->dst_addr = dest;
1423 /* Set platform data for m2m */
1424 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1425 txd->cctl = pl08x->pd->memcpy_channel.cctl &
1426 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1428 /* Both to be incremented or the code will break */
1429 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1431 if (pl08x->vd->dualmaster)
1432 txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
1435 ret = pl08x_prep_channel_resources(plchan, txd);
1442 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1443 struct dma_chan *chan, struct scatterlist *sgl,
1444 unsigned int sg_len, enum dma_transfer_direction direction,
1445 unsigned long flags, void *context)
1447 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1448 struct pl08x_driver_data *pl08x = plchan->host;
1449 struct pl08x_txd *txd;
1450 struct pl08x_sg *dsg;
1451 struct scatterlist *sg;
1452 dma_addr_t slave_addr;
1455 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1456 __func__, sg_dma_len(sgl), plchan->name);
1458 txd = pl08x_get_txd(plchan, flags);
1460 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1464 if (direction != plchan->runtime_direction)
1465 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1466 "the direction configured for the PrimeCell\n",
1470 * Set up addresses, the PrimeCell configured address
1471 * will take precedence since this may configure the
1472 * channel target address dynamically at runtime.
1474 txd->direction = direction;
1476 if (direction == DMA_MEM_TO_DEV) {
1477 txd->cctl = plchan->dst_cctl;
1478 slave_addr = plchan->cfg.dst_addr;
1479 } else if (direction == DMA_DEV_TO_MEM) {
1480 txd->cctl = plchan->src_cctl;
1481 slave_addr = plchan->cfg.src_addr;
1483 pl08x_free_txd(pl08x, txd);
1484 dev_err(&pl08x->adev->dev,
1485 "%s direction unsupported\n", __func__);
1489 if (plchan->cfg.device_fc)
1490 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
1491 PL080_FLOW_PER2MEM_PER;
1493 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER :
1496 txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1498 for_each_sg(sgl, sg, sg_len, tmp) {
1499 dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
1501 pl08x_free_txd(pl08x, txd);
1502 dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
1506 list_add_tail(&dsg->node, &txd->dsg_list);
1508 dsg->len = sg_dma_len(sg);
1509 if (direction == DMA_MEM_TO_DEV) {
1510 dsg->src_addr = sg_dma_address(sg);
1511 dsg->dst_addr = slave_addr;
1513 dsg->src_addr = slave_addr;
1514 dsg->dst_addr = sg_dma_address(sg);
1518 ret = pl08x_prep_channel_resources(plchan, txd);
1525 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1528 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1529 struct pl08x_driver_data *pl08x = plchan->host;
1530 unsigned long flags;
1533 /* Controls applicable to inactive channels */
1534 if (cmd == DMA_SLAVE_CONFIG) {
1535 return dma_set_runtime_config(chan,
1536 (struct dma_slave_config *)arg);
1540 * Anything succeeds on channels with no physical allocation and
1541 * no queued transfers.
1543 spin_lock_irqsave(&plchan->lock, flags);
1544 if (!plchan->phychan && !plchan->at) {
1545 spin_unlock_irqrestore(&plchan->lock, flags);
1550 case DMA_TERMINATE_ALL:
1551 plchan->state = PL08X_CHAN_IDLE;
1553 if (plchan->phychan) {
1554 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
1557 * Mark physical channel as free and free any slave
1560 release_phy_channel(plchan);
1561 plchan->phychan_hold = 0;
1563 /* Dequeue jobs and free LLIs */
1565 pl08x_free_txd(pl08x, plchan->at);
1568 /* Dequeue jobs not yet fired as well */
1569 pl08x_free_txd_list(pl08x, plchan);
1572 pl08x_pause_phy_chan(plchan->phychan);
1573 plchan->state = PL08X_CHAN_PAUSED;
1576 pl08x_resume_phy_chan(plchan->phychan);
1577 plchan->state = PL08X_CHAN_RUNNING;
1580 /* Unknown command */
1585 spin_unlock_irqrestore(&plchan->lock, flags);
1590 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1592 struct pl08x_dma_chan *plchan;
1593 char *name = chan_id;
1595 /* Reject channels for devices not bound to this driver */
1596 if (chan->device->dev->driver != &pl08x_amba_driver.drv)
1599 plchan = to_pl08x_chan(chan);
1601 /* Check that the channel is not taken! */
1602 if (!strcmp(plchan->name, name))
1609 * Just check that the device is there and active
1610 * TODO: turn this bit on/off depending on the number of physical channels
1611 * actually used, if it is zero... well shut it off. That will save some
1612 * power. Cut the clock at the same time.
1614 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1616 /* The Nomadik variant does not have the config register */
1617 if (pl08x->vd->nomadik)
1619 writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
1622 static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1624 struct device *dev = txd->tx.chan->device->dev;
1625 struct pl08x_sg *dsg;
1627 if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1628 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1629 list_for_each_entry(dsg, &txd->dsg_list, node)
1630 dma_unmap_single(dev, dsg->src_addr, dsg->len,
1633 list_for_each_entry(dsg, &txd->dsg_list, node)
1634 dma_unmap_page(dev, dsg->src_addr, dsg->len,
1638 if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1639 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1640 list_for_each_entry(dsg, &txd->dsg_list, node)
1641 dma_unmap_single(dev, dsg->dst_addr, dsg->len,
1644 list_for_each_entry(dsg, &txd->dsg_list, node)
1645 dma_unmap_page(dev, dsg->dst_addr, dsg->len,
1650 static void pl08x_tasklet(unsigned long data)
1652 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1653 struct pl08x_driver_data *pl08x = plchan->host;
1654 struct pl08x_txd *txd;
1655 unsigned long flags;
1657 spin_lock_irqsave(&plchan->lock, flags);
1663 /* Update last completed */
1664 dma_cookie_complete(&txd->tx);
1667 /* If a new descriptor is queued, set it up plchan->at is NULL here */
1668 if (!list_empty(&plchan->pend_list)) {
1669 struct pl08x_txd *next;
1671 next = list_first_entry(&plchan->pend_list,
1674 list_del(&next->node);
1676 pl08x_start_txd(plchan, next);
1677 } else if (plchan->phychan_hold) {
1679 * This channel is still in use - we have a new txd being
1680 * prepared and will soon be queued. Don't give up the
1684 struct pl08x_dma_chan *waiting = NULL;
1687 * No more jobs, so free up the physical channel
1688 * Free any allocated signal on slave transfers too
1690 release_phy_channel(plchan);
1691 plchan->state = PL08X_CHAN_IDLE;
1694 * And NOW before anyone else can grab that free:d up
1695 * physical channel, see if there is some memcpy pending
1696 * that seriously needs to start because of being stacked
1697 * up while we were choking the physical channels with data.
1699 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1701 if (waiting->state == PL08X_CHAN_WAITING &&
1702 waiting->waiting != NULL) {
1705 /* This should REALLY not fail now */
1706 ret = prep_phy_channel(waiting,
1709 waiting->phychan_hold--;
1710 waiting->state = PL08X_CHAN_RUNNING;
1711 waiting->waiting = NULL;
1712 pl08x_issue_pending(&waiting->chan);
1718 spin_unlock_irqrestore(&plchan->lock, flags);
1721 dma_async_tx_callback callback = txd->tx.callback;
1722 void *callback_param = txd->tx.callback_param;
1724 /* Don't try to unmap buffers on slave channels */
1726 pl08x_unmap_buffers(txd);
1728 /* Free the descriptor */
1729 spin_lock_irqsave(&plchan->lock, flags);
1730 pl08x_free_txd(pl08x, txd);
1731 spin_unlock_irqrestore(&plchan->lock, flags);
1733 /* Callback to signal completion */
1735 callback(callback_param);
1739 static irqreturn_t pl08x_irq(int irq, void *dev)
1741 struct pl08x_driver_data *pl08x = dev;
1742 u32 mask = 0, err, tc, i;
1744 /* check & clear - ERR & TC interrupts */
1745 err = readl(pl08x->base + PL080_ERR_STATUS);
1747 dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n",
1749 writel(err, pl08x->base + PL080_ERR_CLEAR);
1751 tc = readl(pl08x->base + PL080_TC_STATUS);
1753 writel(tc, pl08x->base + PL080_TC_CLEAR);
1758 for (i = 0; i < pl08x->vd->channels; i++) {
1759 if (((1 << i) & err) || ((1 << i) & tc)) {
1760 /* Locate physical channel */
1761 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1762 struct pl08x_dma_chan *plchan = phychan->serving;
1765 dev_err(&pl08x->adev->dev,
1766 "%s Error TC interrupt on unused channel: 0x%08x\n",
1771 /* Schedule tasklet on this channel */
1772 tasklet_schedule(&plchan->tasklet);
1777 return mask ? IRQ_HANDLED : IRQ_NONE;
1780 static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
1782 u32 cctl = pl08x_cctl(chan->cd->cctl);
1785 chan->name = chan->cd->bus_id;
1786 chan->cfg.src_addr = chan->cd->addr;
1787 chan->cfg.dst_addr = chan->cd->addr;
1788 chan->src_cctl = cctl | PL080_CONTROL_DST_INCR |
1789 pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses);
1790 chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR |
1791 pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses);
1795 * Initialise the DMAC memcpy/slave channels.
1796 * Make a local wrapper to hold required data
1798 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1799 struct dma_device *dmadev, unsigned int channels, bool slave)
1801 struct pl08x_dma_chan *chan;
1804 INIT_LIST_HEAD(&dmadev->channels);
1807 * Register as many many memcpy as we have physical channels,
1808 * we won't always be able to use all but the code will have
1809 * to cope with that situation.
1811 for (i = 0; i < channels; i++) {
1812 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1814 dev_err(&pl08x->adev->dev,
1815 "%s no memory for channel\n", __func__);
1820 chan->state = PL08X_CHAN_IDLE;
1823 chan->cd = &pl08x->pd->slave_channels[i];
1824 pl08x_dma_slave_init(chan);
1826 chan->cd = &pl08x->pd->memcpy_channel;
1827 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1833 dev_dbg(&pl08x->adev->dev,
1834 "initialize virtual channel \"%s\"\n",
1837 chan->chan.device = dmadev;
1838 dma_cookie_init(&chan->chan);
1840 spin_lock_init(&chan->lock);
1841 INIT_LIST_HEAD(&chan->pend_list);
1842 tasklet_init(&chan->tasklet, pl08x_tasklet,
1843 (unsigned long) chan);
1845 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1847 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1848 i, slave ? "slave" : "memcpy");
1852 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1854 struct pl08x_dma_chan *chan = NULL;
1855 struct pl08x_dma_chan *next;
1857 list_for_each_entry_safe(chan,
1858 next, &dmadev->channels, chan.device_node) {
1859 list_del(&chan->chan.device_node);
1864 #ifdef CONFIG_DEBUG_FS
1865 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1868 case PL08X_CHAN_IDLE:
1870 case PL08X_CHAN_RUNNING:
1872 case PL08X_CHAN_PAUSED:
1874 case PL08X_CHAN_WAITING:
1879 return "UNKNOWN STATE";
1882 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1884 struct pl08x_driver_data *pl08x = s->private;
1885 struct pl08x_dma_chan *chan;
1886 struct pl08x_phy_chan *ch;
1887 unsigned long flags;
1890 seq_printf(s, "PL08x physical channels:\n");
1891 seq_printf(s, "CHANNEL:\tUSER:\n");
1892 seq_printf(s, "--------\t-----\n");
1893 for (i = 0; i < pl08x->vd->channels; i++) {
1894 struct pl08x_dma_chan *virt_chan;
1896 ch = &pl08x->phy_chans[i];
1898 spin_lock_irqsave(&ch->lock, flags);
1899 virt_chan = ch->serving;
1901 seq_printf(s, "%d\t\t%s%s\n",
1903 virt_chan ? virt_chan->name : "(none)",
1904 ch->locked ? " LOCKED" : "");
1906 spin_unlock_irqrestore(&ch->lock, flags);
1909 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1910 seq_printf(s, "CHANNEL:\tSTATE:\n");
1911 seq_printf(s, "--------\t------\n");
1912 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1913 seq_printf(s, "%s\t\t%s\n", chan->name,
1914 pl08x_state_str(chan->state));
1917 seq_printf(s, "\nPL08x virtual slave channels:\n");
1918 seq_printf(s, "CHANNEL:\tSTATE:\n");
1919 seq_printf(s, "--------\t------\n");
1920 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1921 seq_printf(s, "%s\t\t%s\n", chan->name,
1922 pl08x_state_str(chan->state));
1928 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1930 return single_open(file, pl08x_debugfs_show, inode->i_private);
1933 static const struct file_operations pl08x_debugfs_operations = {
1934 .open = pl08x_debugfs_open,
1936 .llseek = seq_lseek,
1937 .release = single_release,
1940 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1942 /* Expose a simple debugfs interface to view all clocks */
1943 (void) debugfs_create_file(dev_name(&pl08x->adev->dev),
1944 S_IFREG | S_IRUGO, NULL, pl08x,
1945 &pl08x_debugfs_operations);
1949 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1954 static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
1956 struct pl08x_driver_data *pl08x;
1957 const struct vendor_data *vd = id->data;
1961 ret = amba_request_regions(adev, NULL);
1965 /* Create the driver state holder */
1966 pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL);
1972 /* Initialize memcpy engine */
1973 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1974 pl08x->memcpy.dev = &adev->dev;
1975 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1976 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1977 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1978 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1979 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1980 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1981 pl08x->memcpy.device_control = pl08x_control;
1983 /* Initialize slave engine */
1984 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1985 pl08x->slave.dev = &adev->dev;
1986 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1987 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1988 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1989 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1990 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1991 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1992 pl08x->slave.device_control = pl08x_control;
1994 /* Get the platform data */
1995 pl08x->pd = dev_get_platdata(&adev->dev);
1997 dev_err(&adev->dev, "no platform data supplied\n");
1998 goto out_no_platdata;
2001 /* Assign useful pointers to the driver state */
2005 /* By default, AHB1 only. If dualmaster, from platform */
2006 pl08x->lli_buses = PL08X_AHB1;
2007 pl08x->mem_buses = PL08X_AHB1;
2008 if (pl08x->vd->dualmaster) {
2009 pl08x->lli_buses = pl08x->pd->lli_buses;
2010 pl08x->mem_buses = pl08x->pd->mem_buses;
2013 /* A DMA memory pool for LLIs, align on 1-byte boundary */
2014 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
2015 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
2018 goto out_no_lli_pool;
2021 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
2024 goto out_no_ioremap;
2027 /* Turn on the PL08x */
2028 pl08x_ensure_on(pl08x);
2030 /* Attach the interrupt handler */
2031 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
2032 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
2034 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
2035 DRIVER_NAME, pl08x);
2037 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
2038 __func__, adev->irq[0]);
2042 /* Initialize physical channels */
2043 pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)),
2045 if (!pl08x->phy_chans) {
2046 dev_err(&adev->dev, "%s failed to allocate "
2047 "physical channel holders\n",
2049 goto out_no_phychans;
2052 for (i = 0; i < vd->channels; i++) {
2053 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
2056 ch->base = pl08x->base + PL080_Cx_BASE(i);
2057 spin_lock_init(&ch->lock);
2061 * Nomadik variants can have channels that are locked
2062 * down for the secure world only. Lock up these channels
2063 * by perpetually serving a dummy virtual channel.
2068 val = readl(ch->base + PL080_CH_CONFIG);
2069 if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
2070 dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i);
2075 dev_dbg(&adev->dev, "physical channel %d is %s\n",
2076 i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
2079 /* Register as many memcpy channels as there are physical channels */
2080 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
2081 pl08x->vd->channels, false);
2083 dev_warn(&pl08x->adev->dev,
2084 "%s failed to enumerate memcpy channels - %d\n",
2088 pl08x->memcpy.chancnt = ret;
2090 /* Register slave channels */
2091 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2092 pl08x->pd->num_slave_channels, true);
2094 dev_warn(&pl08x->adev->dev,
2095 "%s failed to enumerate slave channels - %d\n",
2099 pl08x->slave.chancnt = ret;
2101 ret = dma_async_device_register(&pl08x->memcpy);
2103 dev_warn(&pl08x->adev->dev,
2104 "%s failed to register memcpy as an async device - %d\n",
2106 goto out_no_memcpy_reg;
2109 ret = dma_async_device_register(&pl08x->slave);
2111 dev_warn(&pl08x->adev->dev,
2112 "%s failed to register slave as an async device - %d\n",
2114 goto out_no_slave_reg;
2117 amba_set_drvdata(adev, pl08x);
2118 init_pl08x_debugfs(pl08x);
2119 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2120 amba_part(adev), amba_rev(adev),
2121 (unsigned long long)adev->res.start, adev->irq[0]);
2126 dma_async_device_unregister(&pl08x->memcpy);
2128 pl08x_free_virtual_channels(&pl08x->slave);
2130 pl08x_free_virtual_channels(&pl08x->memcpy);
2132 kfree(pl08x->phy_chans);
2134 free_irq(adev->irq[0], pl08x);
2136 iounmap(pl08x->base);
2138 dma_pool_destroy(pl08x->pool);
2143 amba_release_regions(adev);
2147 /* PL080 has 8 channels and the PL080 have just 2 */
2148 static struct vendor_data vendor_pl080 = {
2153 static struct vendor_data vendor_nomadik = {
2159 static struct vendor_data vendor_pl081 = {
2161 .dualmaster = false,
2164 static struct amba_id pl08x_ids[] = {
2169 .data = &vendor_pl080,
2175 .data = &vendor_pl081,
2177 /* Nomadik 8815 PL080 variant */
2181 .data = &vendor_nomadik,
2186 MODULE_DEVICE_TABLE(amba, pl08x_ids);
2188 static struct amba_driver pl08x_amba_driver = {
2189 .drv.name = DRIVER_NAME,
2190 .id_table = pl08x_ids,
2191 .probe = pl08x_probe,
2194 static int __init pl08x_init(void)
2197 retval = amba_driver_register(&pl08x_amba_driver);
2199 printk(KERN_WARNING DRIVER_NAME
2200 "failed to register as an AMBA device (%d)\n",
2204 subsys_initcall(pl08x_init);