drivers/dma/amba-pl08x.c

   1 /*
   2  * Copyright (c) 2006 ARM Ltd.
   3  * Copyright (c) 2010 ST-Ericsson SA
   4  *
   5  * Author: Peter Pearse <peter.pearse@arm.com>
   6  * Author: Linus Walleij <linus.walleij@stericsson.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the Free
  10  * Software Foundation; either version 2 of the License, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program; if not, write to the Free Software Foundation, Inc., 59
  20  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  21  *
  22  * The full GNU General Public License is in this distribution in the
  23  * file called COPYING.
  24  *
  25  * Documentation: ARM DDI 0196G == PL080
  26  * Documentation: ARM DDI 0218E == PL081
  27  *
  28  * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
  29  * any channel.
  30  *
  31  * The PL080 has 8 channels available for simultaneous use, and the PL081
  32  * has only two channels. So on these DMA controllers the number of channels
  33  * and the number of incoming DMA signals are two totally different things.
  34  * It is usually not possible to theoretically handle all physical signals,
  35  * so a multiplexing scheme with possible denial of use is necessary.
  36  *
  37  * The PL080 has a dual bus master, PL081 has a single master.
  38  *
  39  * Memory to peripheral transfer may be visualized as
  40  *      Get data from memory to DMAC
  41  *      Until no data left
  42  *              On burst request from peripheral
  43  *                      Destination burst from DMAC to peripheral
  44  *                      Clear burst request
  45  *      Raise terminal count interrupt
  46  *
  47  * For peripherals with a FIFO:
  48  * Source      burst size == half the depth of the peripheral FIFO
  49  * Destination burst size == the depth of the peripheral FIFO
  50  *
  51  * (Bursts are irrelevant for mem to mem transfers - there are no burst
  52  * signals, the DMA controller will simply facilitate its AHB master.)
  53  *
  54  * ASSUMES default (little) endianness for DMA transfers
  55  *
  56  * The PL08x has two flow control settings:
  57  *  - DMAC flow control: the transfer size defines the number of transfers
  58  *    which occur for the current LLI entry, and the DMAC raises TC at the
  59  *    end of every LLI entry.  Observed behaviour shows the DMAC listening
  60  *    to both the BREQ and SREQ signals (contrary to documented),
  61  *    transferring data if either is active.  The LBREQ and LSREQ signals
  62  *    are ignored.
  63  *
  64  *  - Peripheral flow control: the transfer size is ignored (and should be
  65  *    zero).  The data is transferred from the current LLI entry, until
  66  *    after the final transfer signalled by LBREQ or LSREQ.  The DMAC
  67  *    will then move to the next LLI entry.
  68  *
  69  * Only the former works sanely with scatter lists, so we only implement
  70  * the DMAC flow control method.  However, peripherals which use the LBREQ
  71  * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
  72  * these hardware restrictions prevents them from using scatter DMA.
  73  *
  74  * Global TODO:
  75  * - Break out common code from arch/arm/mach-s3c64xx and share
  76  */
  77 #include <linux/device.h>
  78 #include <linux/init.h>
  79 #include <linux/module.h>
  80 #include <linux/interrupt.h>
  81 #include <linux/slab.h>
  82 #include <linux/dmapool.h>
  83 #include <linux/dmaengine.h>
  84 #include <linux/amba/bus.h>
  85 #include <linux/amba/pl08x.h>
  86 #include <linux/debugfs.h>
  87 #include <linux/seq_file.h>
  88
  89 #include <asm/hardware/pl080.h>
  90
  91 #define DRIVER_NAME     "pl08xdmac"
  92
  93 /**
  94  * struct vendor_data - vendor-specific config parameters
  95  * for PL08x derivatives
  96  * @channels: the number of channels available in this variant
  97  * @dualmaster: whether this version supports dual AHB masters
  98  * or not.
  99  */
 100 struct vendor_data {
 101         u8 channels;
 102         bool dualmaster;
 103 };
 104
 105 /*
 106  * PL08X private data structures
 107  * An LLI struct - see PL08x TRM.  Note that next uses bit[0] as a bus bit,
 108  * start & end do not - their bus bit info is in cctl.  Also note that these
 109  * are fixed 32-bit quantities.
 110  */
 111 struct pl08x_lli {
 112         u32 src;
 113         u32 dst;
 114         u32 lli;
 115         u32 cctl;
 116 };
 117
 118 /**
 119  * struct pl08x_driver_data - the local state holder for the PL08x
 120  * @slave: slave engine for this instance
 121  * @memcpy: memcpy engine for this instance
 122  * @base: virtual memory base (remapped) for the PL08x
 123  * @adev: the corresponding AMBA (PrimeCell) bus entry
 124  * @vd: vendor data for this PL08x variant
 125  * @pd: platform data passed in from the platform/machine
 126  * @phy_chans: array of data for the physical channels
 127  * @pool: a pool for the LLI descriptors
 128  * @pool_ctr: counter of LLIs in the pool
 129  * @lock: a spinlock for this struct
 130  */
 131 struct pl08x_driver_data {
 132         struct dma_device slave;
 133         struct dma_device memcpy;
 134         void __iomem *base;
 135         struct amba_device *adev;
 136         const struct vendor_data *vd;
 137         struct pl08x_platform_data *pd;
 138         struct pl08x_phy_chan *phy_chans;
 139         struct dma_pool *pool;
 140         int pool_ctr;
 141         spinlock_t lock;
 142 };
 143
 144 /*
 145  * PL08X specific defines
 146  */
 147
 148 /*
 149  * Memory boundaries: the manual for PL08x says that the controller
 150  * cannot read past a 1KiB boundary, so these defines are used to
 151  * create transfer LLIs that do not cross such boundaries.
 152  */
 153 #define PL08X_BOUNDARY_SHIFT            (10)    /* 1KB 0x400 */
 154 #define PL08X_BOUNDARY_SIZE             (1 << PL08X_BOUNDARY_SHIFT)
 155
 156 /* Minimum period between work queue runs */
 157 #define PL08X_WQ_PERIODMIN      20
 158
 159 /* Size (bytes) of each LLI buffer allocated for one transfer */
 160 # define PL08X_LLI_TSFR_SIZE    0x2000
 161
 162 /* Maximum times we call dma_pool_alloc on this pool without freeing */
 163 #define PL08X_MAX_ALLOCS        0x40
 164 #define MAX_NUM_TSFR_LLIS       (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
 165 #define PL08X_ALIGN             8
 166
 167 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
 168 {
 169         return container_of(chan, struct pl08x_dma_chan, chan);
 170 }
 171
 172 /*
 173  * Physical channel handling
 174  */
 175
 176 /* Whether a certain channel is busy or not */
 177 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
 178 {
 179         unsigned int val;
 180
 181         val = readl(ch->base + PL080_CH_CONFIG);
 182         return val & PL080_CONFIG_ACTIVE;
 183 }
 184
 185 /*
 186  * Set the initial DMA register values i.e. those for the first LLI
 187  * The next LLI pointer and the configuration interrupt bit have
 188  * been set when the LLIs were constructed.  Poke them into the hardware
 189  * and start the transfer.
 190  */
 191 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
 192         struct pl08x_txd *txd)
 193 {
 194         struct pl08x_driver_data *pl08x = plchan->host;
 195         struct pl08x_phy_chan *phychan = plchan->phychan;
 196         struct pl08x_lli *lli = &txd->llis_va[0];
 197         u32 val;
 198
 199         plchan->at = txd;
 200
 201         /* Wait for channel inactive */
 202         while (pl08x_phy_channel_busy(phychan))
 203                 cpu_relax();
 204
 205         dev_vdbg(&pl08x->adev->dev,
 206                 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
 207                 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
 208                 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
 209                 txd->ccfg);
 210
 211         writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
 212         writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
 213         writel(lli->lli, phychan->base + PL080_CH_LLI);
 214         writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
 215         writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
 216
 217         /* Enable the DMA channel */
 218         /* Do not access config register until channel shows as disabled */
 219         while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
 220                 cpu_relax();
 221
 222         /* Do not access config register until channel shows as inactive */
 223         val = readl(phychan->base + PL080_CH_CONFIG);
 224         while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
 225                 val = readl(phychan->base + PL080_CH_CONFIG);
 226
 227         writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
 228 }
 229
 230 /*
 231  * Overall DMAC remains enabled always.
 232  *
 233  * Disabling individual channels could lose data.
 234  *
 235  * Disable the peripheral DMA after disabling the DMAC
 236  * in order to allow the DMAC FIFO to drain, and
 237  * hence allow the channel to show inactive
 238  *
 239  */
 240 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
 241 {
 242         u32 val;
 243
 244         /* Set the HALT bit and wait for the FIFO to drain */
 245         val = readl(ch->base + PL080_CH_CONFIG);
 246         val |= PL080_CONFIG_HALT;
 247         writel(val, ch->base + PL080_CH_CONFIG);
 248
 249         /* Wait for channel inactive */
 250         while (pl08x_phy_channel_busy(ch))
 251                 cpu_relax();
 252 }
 253
 254 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
 255 {
 256         u32 val;
 257
 258         /* Clear the HALT bit */
 259         val = readl(ch->base + PL080_CH_CONFIG);
 260         val &= ~PL080_CONFIG_HALT;
 261         writel(val, ch->base + PL080_CH_CONFIG);
 262 }
 263
 264
 265 /* Stops the channel */
 266 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
 267 {
 268         u32 val;
 269
 270         pl08x_pause_phy_chan(ch);
 271
 272         /* Disable channel */
 273         val = readl(ch->base + PL080_CH_CONFIG);
 274         val &= ~PL080_CONFIG_ENABLE;
 275         val &= ~PL080_CONFIG_ERR_IRQ_MASK;
 276         val &= ~PL080_CONFIG_TC_IRQ_MASK;
 277         writel(val, ch->base + PL080_CH_CONFIG);
 278 }
 279
 280 static inline u32 get_bytes_in_cctl(u32 cctl)
 281 {
 282         /* The source width defines the number of bytes */
 283         u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
 284
 285         switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 286         case PL080_WIDTH_8BIT:
 287                 break;
 288         case PL080_WIDTH_16BIT:
 289                 bytes *= 2;
 290                 break;
 291         case PL080_WIDTH_32BIT:
 292                 bytes *= 4;
 293                 break;
 294         }
 295         return bytes;
 296 }
 297
 298 /* The channel should be paused when calling this */
 299 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 300 {
 301         struct pl08x_phy_chan *ch;
 302         struct pl08x_txd *txd;
 303         unsigned long flags;
 304         size_t bytes = 0;
 305
 306         spin_lock_irqsave(&plchan->lock, flags);
 307         ch = plchan->phychan;
 308         txd = plchan->at;
 309
 310         /*
 311          * Follow the LLIs to get the number of remaining
 312          * bytes in the currently active transaction.
 313          */
 314         if (ch && txd) {
 315                 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
 316
 317                 /* First get the remaining bytes in the active transfer */
 318                 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
 319
 320                 if (clli) {
 321                         struct pl08x_lli *llis_va = txd->llis_va;
 322                         dma_addr_t llis_bus = txd->llis_bus;
 323                         int index;
 324
 325                         BUG_ON(clli < llis_bus || clli >= llis_bus +
 326                                 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
 327
 328                         /*
 329                          * Locate the next LLI - as this is an array,
 330                          * it's simple maths to find.
 331                          */
 332                         index = (clli - llis_bus) / sizeof(struct pl08x_lli);
 333
 334                         for (; index < MAX_NUM_TSFR_LLIS; index++) {
 335                                 bytes += get_bytes_in_cctl(llis_va[index].cctl);
 336
 337                                 /*
 338                                  * A LLI pointer of 0 terminates the LLI list
 339                                  */
 340                                 if (!llis_va[index].lli)
 341                                         break;
 342                         }
 343                 }
 344         }
 345
 346         /* Sum up all queued transactions */
 347         if (!list_empty(&plchan->desc_list)) {
 348                 struct pl08x_txd *txdi;
 349                 list_for_each_entry(txdi, &plchan->desc_list, node) {
 350                         bytes += txdi->len;
 351                 }
 352         }
 353
 354         spin_unlock_irqrestore(&plchan->lock, flags);
 355
 356         return bytes;
 357 }
 358
 359 /*
 360  * Allocate a physical channel for a virtual channel
 361  */
 362 static struct pl08x_phy_chan *
 363 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
 364                       struct pl08x_dma_chan *virt_chan)
 365 {
 366         struct pl08x_phy_chan *ch = NULL;
 367         unsigned long flags;
 368         int i;
 369
 370         /*
 371          * Try to locate a physical channel to be used for
 372          * this transfer. If all are taken return NULL and
 373          * the requester will have to cope by using some fallback
 374          * PIO mode or retrying later.
 375          */
 376         for (i = 0; i < pl08x->vd->channels; i++) {
 377                 ch = &pl08x->phy_chans[i];
 378
 379                 spin_lock_irqsave(&ch->lock, flags);
 380
 381                 if (!ch->serving) {
 382                         ch->serving = virt_chan;
 383                         ch->signal = -1;
 384                         spin_unlock_irqrestore(&ch->lock, flags);
 385                         break;
 386                 }
 387
 388                 spin_unlock_irqrestore(&ch->lock, flags);
 389         }
 390
 391         if (i == pl08x->vd->channels) {
 392                 /* No physical channel available, cope with it */
 393                 return NULL;
 394         }
 395
 396         return ch;
 397 }
 398
 399 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
 400                                          struct pl08x_phy_chan *ch)
 401 {
 402         unsigned long flags;
 403
 404         /* Stop the channel and clear its interrupts */
 405         pl08x_stop_phy_chan(ch);
 406         writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
 407         writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
 408
 409         /* Mark it as free */
 410         spin_lock_irqsave(&ch->lock, flags);
 411         ch->serving = NULL;
 412         spin_unlock_irqrestore(&ch->lock, flags);
 413 }
 414
 415 /*
 416  * LLI handling
 417  */
 418
 419 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
 420 {
 421         switch (coded) {
 422         case PL080_WIDTH_8BIT:
 423                 return 1;
 424         case PL080_WIDTH_16BIT:
 425                 return 2;
 426         case PL080_WIDTH_32BIT:
 427                 return 4;
 428         default:
 429                 break;
 430         }
 431         BUG();
 432         return 0;
 433 }
 434
 435 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
 436                                   size_t tsize)
 437 {
 438         u32 retbits = cctl;
 439
 440         /* Remove all src, dst and transfer size bits */
 441         retbits &= ~PL080_CONTROL_DWIDTH_MASK;
 442         retbits &= ~PL080_CONTROL_SWIDTH_MASK;
 443         retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
 444
 445         /* Then set the bits according to the parameters */
 446         switch (srcwidth) {
 447         case 1:
 448                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
 449                 break;
 450         case 2:
 451                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
 452                 break;
 453         case 4:
 454                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
 455                 break;
 456         default:
 457                 BUG();
 458                 break;
 459         }
 460
 461         switch (dstwidth) {
 462         case 1:
 463                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
 464                 break;
 465         case 2:
 466                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
 467                 break;
 468         case 4:
 469                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
 470                 break;
 471         default:
 472                 BUG();
 473                 break;
 474         }
 475
 476         retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
 477         return retbits;
 478 }
 479
 480 /*
 481  * Autoselect a master bus to use for the transfer
 482  * this prefers the destination bus if both available
 483  * if fixed address on one bus the other will be chosen
 484  */
 485 static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
 486         struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
 487         struct pl08x_bus_data **sbus, u32 cctl)
 488 {
 489         if (!(cctl & PL080_CONTROL_DST_INCR)) {
 490                 *mbus = src_bus;
 491                 *sbus = dst_bus;
 492         } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
 493                 *mbus = dst_bus;
 494                 *sbus = src_bus;
 495         } else {
 496                 if (dst_bus->buswidth == 4) {
 497                         *mbus = dst_bus;
 498                         *sbus = src_bus;
 499                 } else if (src_bus->buswidth == 4) {
 500                         *mbus = src_bus;
 501                         *sbus = dst_bus;
 502                 } else if (dst_bus->buswidth == 2) {
 503                         *mbus = dst_bus;
 504                         *sbus = src_bus;
 505                 } else if (src_bus->buswidth == 2) {
 506                         *mbus = src_bus;
 507                         *sbus = dst_bus;
 508                 } else {
 509                         /* src_bus->buswidth == 1 */
 510                         *mbus = dst_bus;
 511                         *sbus = src_bus;
 512                 }
 513         }
 514 }
 515
 516 /*
 517  * Fills in one LLI for a certain transfer descriptor
 518  * and advance the counter
 519  */
 520 static int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
 521                             struct pl08x_txd *txd, int num_llis, int len,
 522                             u32 cctl, u32 *remainder)
 523 {
 524         struct pl08x_lli *llis_va = txd->llis_va;
 525         dma_addr_t llis_bus = txd->llis_bus;
 526
 527         BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
 528
 529         llis_va[num_llis].cctl          = cctl;
 530         llis_va[num_llis].src           = txd->srcbus.addr;
 531         llis_va[num_llis].dst           = txd->dstbus.addr;
 532
 533         /*
 534          * On versions with dual masters, you can optionally AND on
 535          * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
 536          * in new LLIs with that controller, but we always try to
 537          * choose AHB1 to point into memory. The idea is to have AHB2
 538          * fixed on the peripheral and AHB1 messing around in the
 539          * memory. So we don't manipulate this bit currently.
 540          */
 541
 542         llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
 543
 544         if (cctl & PL080_CONTROL_SRC_INCR)
 545                 txd->srcbus.addr += len;
 546         if (cctl & PL080_CONTROL_DST_INCR)
 547                 txd->dstbus.addr += len;
 548
 549         BUG_ON(*remainder < len);
 550
 551         *remainder -= len;
 552
 553         return num_llis + 1;
 554 }
 555
 556 /*
 557  * Return number of bytes to fill to boundary, or len
 558  */
 559 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
 560 {
 561         u32 boundary;
 562
 563         boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
 564                 << PL08X_BOUNDARY_SHIFT;
 565
 566         if (boundary < addr + len)
 567                 return boundary - addr;
 568         else
 569                 return len;
 570 }
 571
 572 /*
 573  * This fills in the table of LLIs for the transfer descriptor
 574  * Note that we assume we never have to change the burst sizes
 575  * Return 0 for error
 576  */
 577 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 578                               struct pl08x_txd *txd)
 579 {
 580         struct pl08x_bus_data *mbus, *sbus;
 581         size_t remainder;
 582         int num_llis = 0;
 583         u32 cctl;
 584         size_t max_bytes_per_lli;
 585         size_t total_bytes = 0;
 586         struct pl08x_lli *llis_va;
 587
 588         txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
 589                                       &txd->llis_bus);
 590         if (!txd->llis_va) {
 591                 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
 592                 return 0;
 593         }
 594
 595         pl08x->pool_ctr++;
 596
 597         /* Get the default CCTL */
 598         cctl = txd->cctl;
 599
 600         /* Find maximum width of the source bus */
 601         txd->srcbus.maxwidth =
 602                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
 603                                        PL080_CONTROL_SWIDTH_SHIFT);
 604
 605         /* Find maximum width of the destination bus */
 606         txd->dstbus.maxwidth =
 607                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
 608                                        PL080_CONTROL_DWIDTH_SHIFT);
 609
 610         /* Set up the bus widths to the maximum */
 611         txd->srcbus.buswidth = txd->srcbus.maxwidth;
 612         txd->dstbus.buswidth = txd->dstbus.maxwidth;
 613         dev_vdbg(&pl08x->adev->dev,
 614                  "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
 615                  __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
 616
 617
 618         /*
 619          * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
 620          */
 621         max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
 622                 PL080_CONTROL_TRANSFER_SIZE_MASK;
 623         dev_vdbg(&pl08x->adev->dev,
 624                  "%s max bytes per lli = %zu\n",
 625                  __func__, max_bytes_per_lli);
 626
 627         /* We need to count this down to zero */
 628         remainder = txd->len;
 629         dev_vdbg(&pl08x->adev->dev,
 630                  "%s remainder = %zu\n",
 631                  __func__, remainder);
 632
 633         /*
 634          * Choose bus to align to
 635          * - prefers destination bus if both available
 636          * - if fixed address on one bus chooses other
 637          * - modifies cctl to choose an appropriate master
 638          */
 639         pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
 640                                 &mbus, &sbus, cctl);
 641
 642
 643         /*
 644          * The lowest bit of the LLI register
 645          * is also used to indicate which master to
 646          * use for reading the LLIs.
 647          */
 648
 649         if (txd->len < mbus->buswidth) {
 650                 /*
 651                  * Less than a bus width available
 652                  * - send as single bytes
 653                  */
 654                 while (remainder) {
 655                         dev_vdbg(&pl08x->adev->dev,
 656                                  "%s single byte LLIs for a transfer of "
 657                                  "less than a bus width (remain 0x%08x)\n",
 658                                  __func__, remainder);
 659                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 660                         num_llis =
 661                                 pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
 662                                         cctl, &remainder);
 663                         total_bytes++;
 664                 }
 665         } else {
 666                 /*
 667                  *  Make one byte LLIs until master bus is aligned
 668                  *  - slave will then be aligned also
 669                  */
 670                 while ((mbus->addr) % (mbus->buswidth)) {
 671                         dev_vdbg(&pl08x->adev->dev,
 672                                 "%s adjustment lli for less than bus width "
 673                                  "(remain 0x%08x)\n",
 674                                  __func__, remainder);
 675                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 676                         num_llis = pl08x_fill_lli_for_desc
 677                                 (pl08x, txd, num_llis, 1, cctl, &remainder);
 678                         total_bytes++;
 679                 }
 680
 681                 /*
 682                  *  Master now aligned
 683                  * - if slave is not then we must set its width down
 684                  */
 685                 if (sbus->addr % sbus->buswidth) {
 686                         dev_dbg(&pl08x->adev->dev,
 687                                 "%s set down bus width to one byte\n",
 688                                  __func__);
 689
 690                         sbus->buswidth = 1;
 691                 }
 692
 693                 /*
 694                  * Make largest possible LLIs until less than one bus
 695                  * width left
 696                  */
 697                 while (remainder > (mbus->buswidth - 1)) {
 698                         size_t lli_len, target_len, tsize, odd_bytes;
 699
 700                         /*
 701                          * If enough left try to send max possible,
 702                          * otherwise try to send the remainder
 703                          */
 704                         target_len = remainder;
 705                         if (remainder > max_bytes_per_lli)
 706                                 target_len = max_bytes_per_lli;
 707
 708                         /*
 709                          * Set bus lengths for incrementing buses
 710                          * to number of bytes which fill to next memory
 711                          * boundary
 712                          */
 713                         if (cctl & PL080_CONTROL_SRC_INCR)
 714                                 txd->srcbus.fill_bytes =
 715                                         pl08x_pre_boundary(
 716                                                 txd->srcbus.addr,
 717                                                 remainder);
 718                         else
 719                                 txd->srcbus.fill_bytes =
 720                                         max_bytes_per_lli;
 721
 722                         if (cctl & PL080_CONTROL_DST_INCR)
 723                                 txd->dstbus.fill_bytes =
 724                                         pl08x_pre_boundary(
 725                                                 txd->dstbus.addr,
 726                                                 remainder);
 727                         else
 728                                 txd->dstbus.fill_bytes =
 729                                                 max_bytes_per_lli;
 730
 731                         /*
 732                          *  Find the nearest
 733                          */
 734                         lli_len = min(txd->srcbus.fill_bytes,
 735                                 txd->dstbus.fill_bytes);
 736
 737                         BUG_ON(lli_len > remainder);
 738
 739                         if (lli_len <= 0) {
 740                                 dev_err(&pl08x->adev->dev,
 741                                         "%s lli_len is %zu, <= 0\n",
 742                                                 __func__, lli_len);
 743                                 return 0;
 744                         }
 745
 746                         if (lli_len == target_len) {
 747                                 /*
 748                                  * Can send what we wanted
 749                                  */
 750                                 /*
 751                                  *  Maintain alignment
 752                                  */
 753                                 lli_len = (lli_len/mbus->buswidth) *
 754                                                         mbus->buswidth;
 755                                 odd_bytes = 0;
 756                         } else {
 757                                 /*
 758                                  * So now we know how many bytes to transfer
 759                                  * to get to the nearest boundary
 760                                  * The next LLI will past the boundary
 761                                  * - however we may be working to a boundary
 762                                  *   on the slave bus
 763                                  *   We need to ensure the master stays aligned
 764                                  */
 765                                 odd_bytes = lli_len % mbus->buswidth;
 766                                 /*
 767                                  * - and that we are working in multiples
 768                                  *   of the bus widths
 769                                  */
 770                                 lli_len -= odd_bytes;
 771
 772                         }
 773
 774                         if (lli_len) {
 775                                 /*
 776                                  * Check against minimum bus alignment:
 777                                  * Calculate actual transfer size in relation
 778                                  * to bus width an get a maximum remainder of
 779                                  * the smallest bus width - 1
 780                                  */
 781                                 /* FIXME: use round_down()? */
 782                                 tsize = lli_len / min(mbus->buswidth,
 783                                                       sbus->buswidth);
 784                                 lli_len = tsize * min(mbus->buswidth,
 785                                                       sbus->buswidth);
 786
 787                                 if (target_len != lli_len) {
 788                                         dev_vdbg(&pl08x->adev->dev,
 789                                         "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
 790                                         __func__, target_len, lli_len, txd->len);
 791                                 }
 792
 793                                 cctl = pl08x_cctl_bits(cctl,
 794                                                        txd->srcbus.buswidth,
 795                                                        txd->dstbus.buswidth,
 796                                                        tsize);
 797
 798                                 dev_vdbg(&pl08x->adev->dev,
 799                                         "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
 800                                         __func__, lli_len, remainder);
 801                                 num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
 802                                                 num_llis, lli_len, cctl,
 803                                                 &remainder);
 804                                 total_bytes += lli_len;
 805                         }
 806
 807
 808                         if (odd_bytes) {
 809                                 /*
 810                                  * Creep past the boundary,
 811                                  * maintaining master alignment
 812                                  */
 813                                 int j;
 814                                 for (j = 0; (j < mbus->buswidth)
 815                                                 && (remainder); j++) {
 816                                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 817                                         dev_vdbg(&pl08x->adev->dev,
 818                                                 "%s align with boundary, single byte (remain 0x%08zx)\n",
 819                                                 __func__, remainder);
 820                                         num_llis =
 821                                                 pl08x_fill_lli_for_desc(pl08x,
 822                                                         txd, num_llis, 1,
 823                                                         cctl, &remainder);
 824                                         total_bytes++;
 825                                 }
 826                         }
 827                 }
 828
 829                 /*
 830                  * Send any odd bytes
 831                  */
 832                 while (remainder) {
 833                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 834                         dev_vdbg(&pl08x->adev->dev,
 835                                 "%s align with boundary, single odd byte (remain %zu)\n",
 836                                 __func__, remainder);
 837                         num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
 838                                         1, cctl, &remainder);
 839                         total_bytes++;
 840                 }
 841         }
 842         if (total_bytes != txd->len) {
 843                 dev_err(&pl08x->adev->dev,
 844                         "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
 845                         __func__, total_bytes, txd->len);
 846                 return 0;
 847         }
 848
 849         if (num_llis >= MAX_NUM_TSFR_LLIS) {
 850                 dev_err(&pl08x->adev->dev,
 851                         "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
 852                         __func__, (u32) MAX_NUM_TSFR_LLIS);
 853                 return 0;
 854         }
 855
 856         llis_va = txd->llis_va;
 857         /*
 858          * The final LLI terminates the LLI.
 859          */
 860         llis_va[num_llis - 1].lli = 0;
 861         /*
 862          * The final LLI element shall also fire an interrupt
 863          */
 864         llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
 865
 866 #ifdef VERBOSE_DEBUG
 867         {
 868                 int i;
 869
 870                 for (i = 0; i < num_llis; i++) {
 871                         dev_vdbg(&pl08x->adev->dev,
 872                                  "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
 873                                  i,
 874                                  &llis_va[i],
 875                                  llis_va[i].src,
 876                                  llis_va[i].dst,
 877                                  llis_va[i].cctl,
 878                                  llis_va[i].lli
 879                                 );
 880                 }
 881         }
 882 #endif
 883
 884         return num_llis;
 885 }
 886
 887 /* You should call this with the struct pl08x lock held */
 888 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
 889                            struct pl08x_txd *txd)
 890 {
 891         /* Free the LLI */
 892         dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
 893
 894         pl08x->pool_ctr--;
 895
 896         kfree(txd);
 897 }
 898
 899 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
 900                                 struct pl08x_dma_chan *plchan)
 901 {
 902         struct pl08x_txd *txdi = NULL;
 903         struct pl08x_txd *next;
 904
 905         if (!list_empty(&plchan->desc_list)) {
 906                 list_for_each_entry_safe(txdi,
 907                                          next, &plchan->desc_list, node) {
 908                         list_del(&txdi->node);
 909                         pl08x_free_txd(pl08x, txdi);
 910                 }
 911
 912         }
 913 }
 914
 915 /*
 916  * The DMA ENGINE API
 917  */
 918 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
 919 {
 920         return 0;
 921 }
 922
 923 static void pl08x_free_chan_resources(struct dma_chan *chan)
 924 {
 925 }
 926
 927 /*
 928  * This should be called with the channel plchan->lock held
 929  */
 930 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
 931                             struct pl08x_txd *txd)
 932 {
 933         struct pl08x_driver_data *pl08x = plchan->host;
 934         struct pl08x_phy_chan *ch;
 935         int ret;
 936
 937         /* Check if we already have a channel */
 938         if (plchan->phychan)
 939                 return 0;
 940
 941         ch = pl08x_get_phy_channel(pl08x, plchan);
 942         if (!ch) {
 943                 /* No physical channel available, cope with it */
 944                 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
 945                 return -EBUSY;
 946         }
 947
 948         /*
 949          * OK we have a physical channel: for memcpy() this is all we
 950          * need, but for slaves the physical signals may be muxed!
 951          * Can the platform allow us to use this channel?
 952          */
 953         if (plchan->slave &&
 954             ch->signal < 0 &&
 955             pl08x->pd->get_signal) {
 956                 ret = pl08x->pd->get_signal(plchan);
 957                 if (ret < 0) {
 958                         dev_dbg(&pl08x->adev->dev,
 959                                 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
 960                                 ch->id, plchan->name);
 961                         /* Release physical channel & return */
 962                         pl08x_put_phy_channel(pl08x, ch);
 963                         return -EBUSY;
 964                 }
 965                 ch->signal = ret;
 966
 967                 /* Assign the flow control signal to this channel */
 968                 if (txd->direction == DMA_TO_DEVICE)
 969                         txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
 970                 else if (txd->direction == DMA_FROM_DEVICE)
 971                         txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
 972         }
 973
 974         dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
 975                  ch->id,
 976                  ch->signal,
 977                  plchan->name);
 978
 979         plchan->phychan = ch;
 980
 981         return 0;
 982 }
 983
 984 static void release_phy_channel(struct pl08x_dma_chan *plchan)
 985 {
 986         struct pl08x_driver_data *pl08x = plchan->host;
 987
 988         if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
 989                 pl08x->pd->put_signal(plchan);
 990                 plchan->phychan->signal = -1;
 991         }
 992         pl08x_put_phy_channel(pl08x, plchan->phychan);
 993         plchan->phychan = NULL;
 994 }
 995
 996 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
 997 {
 998         struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
 999
1000         plchan->chan.cookie += 1;
1001         if (plchan->chan.cookie < 0)
1002                 plchan->chan.cookie = 1;
1003         tx->cookie = plchan->chan.cookie;
1004         /* This unlock follows the lock in the prep() function */
1005         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1006
1007         return tx->cookie;
1008 }
1009
1010 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1011                 struct dma_chan *chan, unsigned long flags)
1012 {
1013         struct dma_async_tx_descriptor *retval = NULL;
1014
1015         return retval;
1016 }
1017
1018 /*
1019  * Code accessing dma_async_is_complete() in a tight loop
1020  * may give problems - could schedule where indicated.
1021  * If slaves are relying on interrupts to signal completion this
1022  * function must not be called with interrupts disabled
1023  */
1024 static enum dma_status
1025 pl08x_dma_tx_status(struct dma_chan *chan,
1026                     dma_cookie_t cookie,
1027                     struct dma_tx_state *txstate)
1028 {
1029         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1030         dma_cookie_t last_used;
1031         dma_cookie_t last_complete;
1032         enum dma_status ret;
1033         u32 bytesleft = 0;
1034
1035         last_used = plchan->chan.cookie;
1036         last_complete = plchan->lc;
1037
1038         ret = dma_async_is_complete(cookie, last_complete, last_used);
1039         if (ret == DMA_SUCCESS) {
1040                 dma_set_tx_state(txstate, last_complete, last_used, 0);
1041                 return ret;
1042         }
1043
1044         /*
1045          * schedule(); could be inserted here
1046          */
1047
1048         /*
1049          * This cookie not complete yet
1050          */
1051         last_used = plchan->chan.cookie;
1052         last_complete = plchan->lc;
1053
1054         /* Get number of bytes left in the active transactions and queue */
1055         bytesleft = pl08x_getbytes_chan(plchan);
1056
1057         dma_set_tx_state(txstate, last_complete, last_used,
1058                          bytesleft);
1059
1060         if (plchan->state == PL08X_CHAN_PAUSED)
1061                 return DMA_PAUSED;
1062
1063         /* Whether waiting or running, we're in progress */
1064         return DMA_IN_PROGRESS;
1065 }
1066
1067 /* PrimeCell DMA extension */
1068 struct burst_table {
1069         int burstwords;
1070         u32 reg;
1071 };
1072
1073 static const struct burst_table burst_sizes[] = {
1074         {
1075                 .burstwords = 256,
1076                 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1077                         (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1078         },
1079         {
1080                 .burstwords = 128,
1081                 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1082                         (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1083         },
1084         {
1085                 .burstwords = 64,
1086                 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1087                         (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1088         },
1089         {
1090                 .burstwords = 32,
1091                 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1092                         (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1093         },
1094         {
1095                 .burstwords = 16,
1096                 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1097                         (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1098         },
1099         {
1100                 .burstwords = 8,
1101                 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1102                         (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1103         },
1104         {
1105                 .burstwords = 4,
1106                 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1107                         (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1108         },
1109         {
1110                 .burstwords = 1,
1111                 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1112                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1113         },
1114 };
1115
1116 static void dma_set_runtime_config(struct dma_chan *chan,
1117                                struct dma_slave_config *config)
1118 {
1119         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1120         struct pl08x_driver_data *pl08x = plchan->host;
1121         struct pl08x_channel_data *cd = plchan->cd;
1122         enum dma_slave_buswidth addr_width;
1123         u32 maxburst;
1124         u32 cctl = 0;
1125         int i;
1126
1127         /* Transfer direction */
1128         plchan->runtime_direction = config->direction;
1129         if (config->direction == DMA_TO_DEVICE) {
1130                 plchan->runtime_addr = config->dst_addr;
1131                 addr_width = config->dst_addr_width;
1132                 maxburst = config->dst_maxburst;
1133         } else if (config->direction == DMA_FROM_DEVICE) {
1134                 plchan->runtime_addr = config->src_addr;
1135                 addr_width = config->src_addr_width;
1136                 maxburst = config->src_maxburst;
1137         } else {
1138                 dev_err(&pl08x->adev->dev,
1139                         "bad runtime_config: alien transfer direction\n");
1140                 return;
1141         }
1142
1143         switch (addr_width) {
1144         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1145                 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1146                         (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1147                 break;
1148         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1149                 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1150                         (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1151                 break;
1152         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1153                 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1154                         (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1155                 break;
1156         default:
1157                 dev_err(&pl08x->adev->dev,
1158                         "bad runtime_config: alien address width\n");
1159                 return;
1160         }
1161
1162         /*
1163          * Now decide on a maxburst:
1164          * If this channel will only request single transfers, set this
1165          * down to ONE element.  Also select one element if no maxburst
1166          * is specified.
1167          */
1168         if (plchan->cd->single || maxburst == 0) {
1169                 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1170                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1171         } else {
1172                 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1173                         if (burst_sizes[i].burstwords <= maxburst)
1174                                 break;
1175                 cctl |= burst_sizes[i].reg;
1176         }
1177
1178         /* Modify the default channel data to fit PrimeCell request */
1179         cd->cctl = cctl;
1180
1181         dev_dbg(&pl08x->adev->dev,
1182                 "configured channel %s (%s) for %s, data width %d, "
1183                 "maxburst %d words, LE, CCTL=0x%08x\n",
1184                 dma_chan_name(chan), plchan->name,
1185                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1186                 addr_width,
1187                 maxburst,
1188                 cctl);
1189 }
1190
1191 /*
1192  * Slave transactions callback to the slave device to allow
1193  * synchronization of slave DMA signals with the DMAC enable
1194  */
1195 static void pl08x_issue_pending(struct dma_chan *chan)
1196 {
1197         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1198         unsigned long flags;
1199
1200         spin_lock_irqsave(&plchan->lock, flags);
1201         /* Something is already active, or we're waiting for a channel... */
1202         if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1203                 spin_unlock_irqrestore(&plchan->lock, flags);
1204                 return;
1205         }
1206
1207         /* Take the first element in the queue and execute it */
1208         if (!list_empty(&plchan->desc_list)) {
1209                 struct pl08x_txd *next;
1210
1211                 next = list_first_entry(&plchan->desc_list,
1212                                         struct pl08x_txd,
1213                                         node);
1214                 list_del(&next->node);
1215                 plchan->state = PL08X_CHAN_RUNNING;
1216
1217                 pl08x_start_txd(plchan, next);
1218         }
1219
1220         spin_unlock_irqrestore(&plchan->lock, flags);
1221 }
1222
1223 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1224                                         struct pl08x_txd *txd)
1225 {
1226         int num_llis;
1227         struct pl08x_driver_data *pl08x = plchan->host;
1228         int ret;
1229
1230         num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1231         if (!num_llis) {
1232                 kfree(txd);
1233                 return -EINVAL;
1234         }
1235
1236         spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1237
1238         list_add_tail(&txd->node, &plchan->desc_list);
1239
1240         /*
1241          * See if we already have a physical channel allocated,
1242          * else this is the time to try to get one.
1243          */
1244         ret = prep_phy_channel(plchan, txd);
1245         if (ret) {
1246                 /*
1247                  * No physical channel available, we will
1248                  * stack up the memcpy channels until there is a channel
1249                  * available to handle it whereas slave transfers may
1250                  * have been denied due to platform channel muxing restrictions
1251                  * and since there is no guarantee that this will ever be
1252                  * resolved, and since the signal must be acquired AFTER
1253                  * acquiring the physical channel, we will let them be NACK:ed
1254                  * with -EBUSY here. The drivers can alway retry the prep()
1255                  * call if they are eager on doing this using DMA.
1256                  */
1257                 if (plchan->slave) {
1258                         pl08x_free_txd_list(pl08x, plchan);
1259                         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1260                         return -EBUSY;
1261                 }
1262                 /* Do this memcpy whenever there is a channel ready */
1263                 plchan->state = PL08X_CHAN_WAITING;
1264                 plchan->waiting = txd;
1265         } else
1266                 /*
1267                  * Else we're all set, paused and ready to roll,
1268                  * status will switch to PL08X_CHAN_RUNNING when
1269                  * we call issue_pending(). If there is something
1270                  * running on the channel already we don't change
1271                  * its state.
1272                  */
1273                 if (plchan->state == PL08X_CHAN_IDLE)
1274                         plchan->state = PL08X_CHAN_PAUSED;
1275
1276         /*
1277          * Notice that we leave plchan->lock locked on purpose:
1278          * it will be unlocked in the subsequent tx_submit()
1279          * call. This is a consequence of the current API.
1280          */
1281
1282         return 0;
1283 }
1284
1285 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1286 {
1287         struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1288
1289         if (txd) {
1290                 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1291                 txd->tx.tx_submit = pl08x_tx_submit;
1292                 INIT_LIST_HEAD(&txd->node);
1293
1294                 /* Always enable error and terminal interrupts */
1295                 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1296                             PL080_CONFIG_TC_IRQ_MASK;
1297         }
1298         return txd;
1299 }
1300
1301 /*
1302  * Initialize a descriptor to be used by memcpy submit
1303  */
1304 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1305                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1306                 size_t len, unsigned long flags)
1307 {
1308         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1309         struct pl08x_driver_data *pl08x = plchan->host;
1310         struct pl08x_txd *txd;
1311         int ret;
1312
1313         txd = pl08x_get_txd(plchan);
1314         if (!txd) {
1315                 dev_err(&pl08x->adev->dev,
1316                         "%s no memory for descriptor\n", __func__);
1317                 return NULL;
1318         }
1319
1320         txd->direction = DMA_NONE;
1321         txd->srcbus.addr = src;
1322         txd->dstbus.addr = dest;
1323         txd->len = len;
1324
1325         /* Set platform data for m2m */
1326         txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1327         txd->cctl = pl08x->pd->memcpy_channel.cctl &
1328                         ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1329
1330         /* Both to be incremented or the code will break */
1331         txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1332
1333         /*
1334          * On the PL080 we have two bus masters and we should select one for
1335          * source and one for destination. We try to use AHB2 for the bus
1336          * which does not increment (typically the peripheral) else we just
1337          * choose something.
1338          */
1339         if (pl08x->vd->dualmaster)
1340                 /* Source increments, use AHB2 for destination */
1341                 txd->cctl |= PL080_CONTROL_DST_AHB2;
1342
1343         ret = pl08x_prep_channel_resources(plchan, txd);
1344         if (ret)
1345                 return NULL;
1346         /*
1347          * NB: the channel lock is held at this point so tx_submit()
1348          * must be called in direct succession.
1349          */
1350
1351         return &txd->tx;
1352 }
1353
1354 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1355                 struct dma_chan *chan, struct scatterlist *sgl,
1356                 unsigned int sg_len, enum dma_data_direction direction,
1357                 unsigned long flags)
1358 {
1359         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1360         struct pl08x_driver_data *pl08x = plchan->host;
1361         struct pl08x_txd *txd;
1362         int ret;
1363
1364         /*
1365          * Current implementation ASSUMES only one sg
1366          */
1367         if (sg_len != 1) {
1368                 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1369                         __func__);
1370                 BUG();
1371         }
1372
1373         dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1374                 __func__, sgl->length, plchan->name);
1375
1376         txd = pl08x_get_txd(plchan);
1377         if (!txd) {
1378                 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1379                 return NULL;
1380         }
1381
1382         if (direction != plchan->runtime_direction)
1383                 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1384                         "the direction configured for the PrimeCell\n",
1385                         __func__);
1386
1387         /*
1388          * Set up addresses, the PrimeCell configured address
1389          * will take precedence since this may configure the
1390          * channel target address dynamically at runtime.
1391          */
1392         txd->direction = direction;
1393         txd->len = sgl->length;
1394
1395         txd->cctl = plchan->cd->cctl &
1396                         ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1397                           PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1398                           PL080_CONTROL_PROT_MASK);
1399
1400         /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1401         txd->cctl |= PL080_CONTROL_PROT_SYS;
1402
1403         if (direction == DMA_TO_DEVICE) {
1404                 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1405                 txd->cctl |= PL080_CONTROL_SRC_INCR;
1406                 if (pl08x->vd->dualmaster)
1407                         /* Source increments, use AHB2 for destination */
1408                         txd->cctl |= PL080_CONTROL_DST_AHB2;
1409                 txd->srcbus.addr = sgl->dma_address;
1410                 if (plchan->runtime_addr)
1411                         txd->dstbus.addr = plchan->runtime_addr;
1412                 else
1413                         txd->dstbus.addr = plchan->cd->addr;
1414         } else if (direction == DMA_FROM_DEVICE) {
1415                 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1416                 txd->cctl |= PL080_CONTROL_DST_INCR;
1417                 if (pl08x->vd->dualmaster)
1418                         /* Destination increments, use AHB2 for source */
1419                         txd->cctl |= PL080_CONTROL_SRC_AHB2;
1420                 if (plchan->runtime_addr)
1421                         txd->srcbus.addr = plchan->runtime_addr;
1422                 else
1423                         txd->srcbus.addr = plchan->cd->addr;
1424                 txd->dstbus.addr = sgl->dma_address;
1425         } else {
1426                 dev_err(&pl08x->adev->dev,
1427                         "%s direction unsupported\n", __func__);
1428                 return NULL;
1429         }
1430
1431         ret = pl08x_prep_channel_resources(plchan, txd);
1432         if (ret)
1433                 return NULL;
1434         /*
1435          * NB: the channel lock is held at this point so tx_submit()
1436          * must be called in direct succession.
1437          */
1438
1439         return &txd->tx;
1440 }
1441
1442 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1443                          unsigned long arg)
1444 {
1445         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1446         struct pl08x_driver_data *pl08x = plchan->host;
1447         unsigned long flags;
1448         int ret = 0;
1449
1450         /* Controls applicable to inactive channels */
1451         if (cmd == DMA_SLAVE_CONFIG) {
1452                 dma_set_runtime_config(chan,
1453                                        (struct dma_slave_config *)
1454                                        arg);
1455                 return 0;
1456         }
1457
1458         /*
1459          * Anything succeeds on channels with no physical allocation and
1460          * no queued transfers.
1461          */
1462         spin_lock_irqsave(&plchan->lock, flags);
1463         if (!plchan->phychan && !plchan->at) {
1464                 spin_unlock_irqrestore(&plchan->lock, flags);
1465                 return 0;
1466         }
1467
1468         switch (cmd) {
1469         case DMA_TERMINATE_ALL:
1470                 plchan->state = PL08X_CHAN_IDLE;
1471
1472                 if (plchan->phychan) {
1473                         pl08x_stop_phy_chan(plchan->phychan);
1474
1475                         /*
1476                          * Mark physical channel as free and free any slave
1477                          * signal
1478                          */
1479                         release_phy_channel(plchan);
1480                 }
1481                 /* Dequeue jobs and free LLIs */
1482                 if (plchan->at) {
1483                         pl08x_free_txd(pl08x, plchan->at);
1484                         plchan->at = NULL;
1485                 }
1486                 /* Dequeue jobs not yet fired as well */
1487                 pl08x_free_txd_list(pl08x, plchan);
1488                 break;
1489         case DMA_PAUSE:
1490                 pl08x_pause_phy_chan(plchan->phychan);
1491                 plchan->state = PL08X_CHAN_PAUSED;
1492                 break;
1493         case DMA_RESUME:
1494                 pl08x_resume_phy_chan(plchan->phychan);
1495                 plchan->state = PL08X_CHAN_RUNNING;
1496                 break;
1497         default:
1498                 /* Unknown command */
1499                 ret = -ENXIO;
1500                 break;
1501         }
1502
1503         spin_unlock_irqrestore(&plchan->lock, flags);
1504
1505         return ret;
1506 }
1507
1508 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1509 {
1510         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1511         char *name = chan_id;
1512
1513         /* Check that the channel is not taken! */
1514         if (!strcmp(plchan->name, name))
1515                 return true;
1516
1517         return false;
1518 }
1519
1520 /*
1521  * Just check that the device is there and active
1522  * TODO: turn this bit on/off depending on the number of
1523  * physical channels actually used, if it is zero... well
1524  * shut it off. That will save some power. Cut the clock
1525  * at the same time.
1526  */
1527 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1528 {
1529         u32 val;
1530
1531         val = readl(pl08x->base + PL080_CONFIG);
1532         val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1533         /* We implicitly clear bit 1 and that means little-endian mode */
1534         val |= PL080_CONFIG_ENABLE;
1535         writel(val, pl08x->base + PL080_CONFIG);
1536 }
1537
1538 static void pl08x_tasklet(unsigned long data)
1539 {
1540         struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1541         struct pl08x_driver_data *pl08x = plchan->host;
1542         unsigned long flags;
1543
1544         spin_lock_irqsave(&plchan->lock, flags);
1545
1546         if (plchan->at) {
1547                 dma_async_tx_callback callback =
1548                         plchan->at->tx.callback;
1549                 void *callback_param =
1550                         plchan->at->tx.callback_param;
1551
1552                 /*
1553                  * Update last completed
1554                  */
1555                 plchan->lc = plchan->at->tx.cookie;
1556
1557                 /*
1558                  * Callback to signal completion
1559                  */
1560                 if (callback)
1561                         callback(callback_param);
1562
1563                 /*
1564                  * Free the descriptor
1565                  */
1566                 pl08x_free_txd(pl08x, plchan->at);
1567                 plchan->at = NULL;
1568         }
1569         /*
1570          * If a new descriptor is queued, set it up
1571          * plchan->at is NULL here
1572          */
1573         if (!list_empty(&plchan->desc_list)) {
1574                 struct pl08x_txd *next;
1575
1576                 next = list_first_entry(&plchan->desc_list,
1577                                         struct pl08x_txd,
1578                                         node);
1579                 list_del(&next->node);
1580
1581                 pl08x_start_txd(plchan, next);
1582         } else {
1583                 struct pl08x_dma_chan *waiting = NULL;
1584
1585                 /*
1586                  * No more jobs, so free up the physical channel
1587                  * Free any allocated signal on slave transfers too
1588                  */
1589                 release_phy_channel(plchan);
1590                 plchan->state = PL08X_CHAN_IDLE;
1591
1592                 /*
1593                  * And NOW before anyone else can grab that free:d
1594                  * up physical channel, see if there is some memcpy
1595                  * pending that seriously needs to start because of
1596                  * being stacked up while we were choking the
1597                  * physical channels with data.
1598                  */
1599                 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1600                                     chan.device_node) {
1601                   if (waiting->state == PL08X_CHAN_WAITING &&
1602                             waiting->waiting != NULL) {
1603                                 int ret;
1604
1605                                 /* This should REALLY not fail now */
1606                                 ret = prep_phy_channel(waiting,
1607                                                        waiting->waiting);
1608                                 BUG_ON(ret);
1609                                 waiting->state = PL08X_CHAN_RUNNING;
1610                                 waiting->waiting = NULL;
1611                                 pl08x_issue_pending(&waiting->chan);
1612                                 break;
1613                         }
1614                 }
1615         }
1616
1617         spin_unlock_irqrestore(&plchan->lock, flags);
1618 }
1619
1620 static irqreturn_t pl08x_irq(int irq, void *dev)
1621 {
1622         struct pl08x_driver_data *pl08x = dev;
1623         u32 mask = 0;
1624         u32 val;
1625         int i;
1626
1627         val = readl(pl08x->base + PL080_ERR_STATUS);
1628         if (val) {
1629                 /*
1630                  * An error interrupt (on one or more channels)
1631                  */
1632                 dev_err(&pl08x->adev->dev,
1633                         "%s error interrupt, register value 0x%08x\n",
1634                                 __func__, val);
1635                 /*
1636                  * Simply clear ALL PL08X error interrupts,
1637                  * regardless of channel and cause
1638                  * FIXME: should be 0x00000003 on PL081 really.
1639                  */
1640                 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1641         }
1642         val = readl(pl08x->base + PL080_INT_STATUS);
1643         for (i = 0; i < pl08x->vd->channels; i++) {
1644                 if ((1 << i) & val) {
1645                         /* Locate physical channel */
1646                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1647                         struct pl08x_dma_chan *plchan = phychan->serving;
1648
1649                         /* Schedule tasklet on this channel */
1650                         tasklet_schedule(&plchan->tasklet);
1651
1652                         mask |= (1 << i);
1653                 }
1654         }
1655         /*
1656          * Clear only the terminal interrupts on channels we processed
1657          */
1658         writel(mask, pl08x->base + PL080_TC_CLEAR);
1659
1660         return mask ? IRQ_HANDLED : IRQ_NONE;
1661 }
1662
1663 /*
1664  * Initialise the DMAC memcpy/slave channels.
1665  * Make a local wrapper to hold required data
1666  */
1667 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1668                                            struct dma_device *dmadev,
1669                                            unsigned int channels,
1670                                            bool slave)
1671 {
1672         struct pl08x_dma_chan *chan;
1673         int i;
1674
1675         INIT_LIST_HEAD(&dmadev->channels);
1676         /*
1677          * Register as many many memcpy as we have physical channels,
1678          * we won't always be able to use all but the code will have
1679          * to cope with that situation.
1680          */
1681         for (i = 0; i < channels; i++) {
1682                 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1683                 if (!chan) {
1684                         dev_err(&pl08x->adev->dev,
1685                                 "%s no memory for channel\n", __func__);
1686                         return -ENOMEM;
1687                 }
1688
1689                 chan->host = pl08x;
1690                 chan->state = PL08X_CHAN_IDLE;
1691
1692                 if (slave) {
1693                         chan->slave = true;
1694                         chan->name = pl08x->pd->slave_channels[i].bus_id;
1695                         chan->cd = &pl08x->pd->slave_channels[i];
1696                 } else {
1697                         chan->cd = &pl08x->pd->memcpy_channel;
1698                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1699                         if (!chan->name) {
1700                                 kfree(chan);
1701                                 return -ENOMEM;
1702                         }
1703                 }
1704                 if (chan->cd->circular_buffer) {
1705                         dev_err(&pl08x->adev->dev,
1706                                 "channel %s: circular buffers not supported\n",
1707                                 chan->name);
1708                         kfree(chan);
1709                         continue;
1710                 }
1711                 dev_info(&pl08x->adev->dev,
1712                          "initialize virtual channel \"%s\"\n",
1713                          chan->name);
1714
1715                 chan->chan.device = dmadev;
1716                 chan->chan.cookie = 0;
1717                 chan->lc = 0;
1718
1719                 spin_lock_init(&chan->lock);
1720                 INIT_LIST_HEAD(&chan->desc_list);
1721                 tasklet_init(&chan->tasklet, pl08x_tasklet,
1722                              (unsigned long) chan);
1723
1724                 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1725         }
1726         dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1727                  i, slave ? "slave" : "memcpy");
1728         return i;
1729 }
1730
1731 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1732 {
1733         struct pl08x_dma_chan *chan = NULL;
1734         struct pl08x_dma_chan *next;
1735
1736         list_for_each_entry_safe(chan,
1737                                  next, &dmadev->channels, chan.device_node) {
1738                 list_del(&chan->chan.device_node);
1739                 kfree(chan);
1740         }
1741 }
1742
1743 #ifdef CONFIG_DEBUG_FS
1744 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1745 {
1746         switch (state) {
1747         case PL08X_CHAN_IDLE:
1748                 return "idle";
1749         case PL08X_CHAN_RUNNING:
1750                 return "running";
1751         case PL08X_CHAN_PAUSED:
1752                 return "paused";
1753         case PL08X_CHAN_WAITING:
1754                 return "waiting";
1755         default:
1756                 break;
1757         }
1758         return "UNKNOWN STATE";
1759 }
1760
1761 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1762 {
1763         struct pl08x_driver_data *pl08x = s->private;
1764         struct pl08x_dma_chan *chan;
1765         struct pl08x_phy_chan *ch;
1766         unsigned long flags;
1767         int i;
1768
1769         seq_printf(s, "PL08x physical channels:\n");
1770         seq_printf(s, "CHANNEL:\tUSER:\n");
1771         seq_printf(s, "--------\t-----\n");
1772         for (i = 0; i < pl08x->vd->channels; i++) {
1773                 struct pl08x_dma_chan *virt_chan;
1774
1775                 ch = &pl08x->phy_chans[i];
1776
1777                 spin_lock_irqsave(&ch->lock, flags);
1778                 virt_chan = ch->serving;
1779
1780                 seq_printf(s, "%d\t\t%s\n",
1781                            ch->id, virt_chan ? virt_chan->name : "(none)");
1782
1783                 spin_unlock_irqrestore(&ch->lock, flags);
1784         }
1785
1786         seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1787         seq_printf(s, "CHANNEL:\tSTATE:\n");
1788         seq_printf(s, "--------\t------\n");
1789         list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1790                 seq_printf(s, "%s\t\t%s\n", chan->name,
1791                            pl08x_state_str(chan->state));
1792         }
1793
1794         seq_printf(s, "\nPL08x virtual slave channels:\n");
1795         seq_printf(s, "CHANNEL:\tSTATE:\n");
1796         seq_printf(s, "--------\t------\n");
1797         list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1798                 seq_printf(s, "%s\t\t%s\n", chan->name,
1799                            pl08x_state_str(chan->state));
1800         }
1801
1802         return 0;
1803 }
1804
1805 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1806 {
1807         return single_open(file, pl08x_debugfs_show, inode->i_private);
1808 }
1809
1810 static const struct file_operations pl08x_debugfs_operations = {
1811         .open           = pl08x_debugfs_open,
1812         .read           = seq_read,
1813         .llseek         = seq_lseek,
1814         .release        = single_release,
1815 };
1816
1817 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1818 {
1819         /* Expose a simple debugfs interface to view all clocks */
1820         (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1821                                    NULL, pl08x,
1822                                    &pl08x_debugfs_operations);
1823 }
1824
1825 #else
1826 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1827 {
1828 }
1829 #endif
1830
1831 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1832 {
1833         struct pl08x_driver_data *pl08x;
1834         const struct vendor_data *vd = id->data;
1835         int ret = 0;
1836         int i;
1837
1838         ret = amba_request_regions(adev, NULL);
1839         if (ret)
1840                 return ret;
1841
1842         /* Create the driver state holder */
1843         pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1844         if (!pl08x) {
1845                 ret = -ENOMEM;
1846                 goto out_no_pl08x;
1847         }
1848
1849         /* Initialize memcpy engine */
1850         dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1851         pl08x->memcpy.dev = &adev->dev;
1852         pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1853         pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1854         pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1855         pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1856         pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1857         pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1858         pl08x->memcpy.device_control = pl08x_control;
1859
1860         /* Initialize slave engine */
1861         dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1862         pl08x->slave.dev = &adev->dev;
1863         pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1864         pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1865         pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1866         pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1867         pl08x->slave.device_issue_pending = pl08x_issue_pending;
1868         pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1869         pl08x->slave.device_control = pl08x_control;
1870
1871         /* Get the platform data */
1872         pl08x->pd = dev_get_platdata(&adev->dev);
1873         if (!pl08x->pd) {
1874                 dev_err(&adev->dev, "no platform data supplied\n");
1875                 goto out_no_platdata;
1876         }
1877
1878         /* Assign useful pointers to the driver state */
1879         pl08x->adev = adev;
1880         pl08x->vd = vd;
1881
1882         /* A DMA memory pool for LLIs, align on 1-byte boundary */
1883         pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1884                         PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1885         if (!pl08x->pool) {
1886                 ret = -ENOMEM;
1887                 goto out_no_lli_pool;
1888         }
1889
1890         spin_lock_init(&pl08x->lock);
1891
1892         pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1893         if (!pl08x->base) {
1894                 ret = -ENOMEM;
1895                 goto out_no_ioremap;
1896         }
1897
1898         /* Turn on the PL08x */
1899         pl08x_ensure_on(pl08x);
1900
1901         /*
1902          * Attach the interrupt handler
1903          */
1904         writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1905         writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1906
1907         ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1908                           DRIVER_NAME, pl08x);
1909         if (ret) {
1910                 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1911                         __func__, adev->irq[0]);
1912                 goto out_no_irq;
1913         }
1914
1915         /* Initialize physical channels */
1916         pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1917                         GFP_KERNEL);
1918         if (!pl08x->phy_chans) {
1919                 dev_err(&adev->dev, "%s failed to allocate "
1920                         "physical channel holders\n",
1921                         __func__);
1922                 goto out_no_phychans;
1923         }
1924
1925         for (i = 0; i < vd->channels; i++) {
1926                 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1927
1928                 ch->id = i;
1929                 ch->base = pl08x->base + PL080_Cx_BASE(i);
1930                 spin_lock_init(&ch->lock);
1931                 ch->serving = NULL;
1932                 ch->signal = -1;
1933                 dev_info(&adev->dev,
1934                          "physical channel %d is %s\n", i,
1935                          pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1936         }
1937
1938         /* Register as many memcpy channels as there are physical channels */
1939         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1940                                               pl08x->vd->channels, false);
1941         if (ret <= 0) {
1942                 dev_warn(&pl08x->adev->dev,
1943                          "%s failed to enumerate memcpy channels - %d\n",
1944                          __func__, ret);
1945                 goto out_no_memcpy;
1946         }
1947         pl08x->memcpy.chancnt = ret;
1948
1949         /* Register slave channels */
1950         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
1951                                               pl08x->pd->num_slave_channels,
1952                                               true);
1953         if (ret <= 0) {
1954                 dev_warn(&pl08x->adev->dev,
1955                         "%s failed to enumerate slave channels - %d\n",
1956                                 __func__, ret);
1957                 goto out_no_slave;
1958         }
1959         pl08x->slave.chancnt = ret;
1960
1961         ret = dma_async_device_register(&pl08x->memcpy);
1962         if (ret) {
1963                 dev_warn(&pl08x->adev->dev,
1964                         "%s failed to register memcpy as an async device - %d\n",
1965                         __func__, ret);
1966                 goto out_no_memcpy_reg;
1967         }
1968
1969         ret = dma_async_device_register(&pl08x->slave);
1970         if (ret) {
1971                 dev_warn(&pl08x->adev->dev,
1972                         "%s failed to register slave as an async device - %d\n",
1973                         __func__, ret);
1974                 goto out_no_slave_reg;
1975         }
1976
1977         amba_set_drvdata(adev, pl08x);
1978         init_pl08x_debugfs(pl08x);
1979         dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
1980                  amba_part(adev), amba_rev(adev),
1981                  (unsigned long long)adev->res.start, adev->irq[0]);
1982         return 0;
1983
1984 out_no_slave_reg:
1985         dma_async_device_unregister(&pl08x->memcpy);
1986 out_no_memcpy_reg:
1987         pl08x_free_virtual_channels(&pl08x->slave);
1988 out_no_slave:
1989         pl08x_free_virtual_channels(&pl08x->memcpy);
1990 out_no_memcpy:
1991         kfree(pl08x->phy_chans);
1992 out_no_phychans:
1993         free_irq(adev->irq[0], pl08x);
1994 out_no_irq:
1995         iounmap(pl08x->base);
1996 out_no_ioremap:
1997         dma_pool_destroy(pl08x->pool);
1998 out_no_lli_pool:
1999 out_no_platdata:
2000         kfree(pl08x);
2001 out_no_pl08x:
2002         amba_release_regions(adev);
2003         return ret;
2004 }
2005
2006 /* PL080 has 8 channels and the PL080 have just 2 */
2007 static struct vendor_data vendor_pl080 = {
2008         .channels = 8,
2009         .dualmaster = true,
2010 };
2011
2012 static struct vendor_data vendor_pl081 = {
2013         .channels = 2,
2014         .dualmaster = false,
2015 };
2016
2017 static struct amba_id pl08x_ids[] = {
2018         /* PL080 */
2019         {
2020                 .id     = 0x00041080,
2021                 .mask   = 0x000fffff,
2022                 .data   = &vendor_pl080,
2023         },
2024         /* PL081 */
2025         {
2026                 .id     = 0x00041081,
2027                 .mask   = 0x000fffff,
2028                 .data   = &vendor_pl081,
2029         },
2030         /* Nomadik 8815 PL080 variant */
2031         {
2032                 .id     = 0x00280880,
2033                 .mask   = 0x00ffffff,
2034                 .data   = &vendor_pl080,
2035         },
2036         { 0, 0 },
2037 };
2038
2039 static struct amba_driver pl08x_amba_driver = {
2040         .drv.name       = DRIVER_NAME,
2041         .id_table       = pl08x_ids,
2042         .probe          = pl08x_probe,
2043 };
2044
2045 static int __init pl08x_init(void)
2046 {
2047         int retval;
2048         retval = amba_driver_register(&pl08x_amba_driver);
2049         if (retval)
2050                 printk(KERN_WARNING DRIVER_NAME
2051                        "failed to register as an AMBA device (%d)\n",
2052                        retval);
2053         return retval;
2054 }
2055 subsys_initcall(pl08x_init);