drivers/dma/amba-pl08x.c

   1 /*
   2  * Copyright (c) 2006 ARM Ltd.
   3  * Copyright (c) 2010 ST-Ericsson SA
   4  *
   5  * Author: Peter Pearse <peter.pearse@arm.com>
   6  * Author: Linus Walleij <linus.walleij@stericsson.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the Free
  10  * Software Foundation; either version 2 of the License, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program; if not, write to the Free Software Foundation, Inc., 59
  20  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  21  *
  22  * The full GNU General Public License is in this distribution in the
  23  * file called COPYING.
  24  *
  25  * Documentation: ARM DDI 0196G == PL080
  26  * Documentation: ARM DDI 0218E == PL081
  27  *
  28  * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
  29  * any channel.
  30  *
  31  * The PL080 has 8 channels available for simultaneous use, and the PL081
  32  * has only two channels. So on these DMA controllers the number of channels
  33  * and the number of incoming DMA signals are two totally different things.
  34  * It is usually not possible to theoretically handle all physical signals,
  35  * so a multiplexing scheme with possible denial of use is necessary.
  36  *
  37  * The PL080 has a dual bus master, PL081 has a single master.
  38  *
  39  * Memory to peripheral transfer may be visualized as
  40  *      Get data from memory to DMAC
  41  *      Until no data left
  42  *              On burst request from peripheral
  43  *                      Destination burst from DMAC to peripheral
  44  *                      Clear burst request
  45  *      Raise terminal count interrupt
  46  *
  47  * For peripherals with a FIFO:
  48  * Source      burst size == half the depth of the peripheral FIFO
  49  * Destination burst size == the depth of the peripheral FIFO
  50  *
  51  * (Bursts are irrelevant for mem to mem transfers - there are no burst
  52  * signals, the DMA controller will simply facilitate its AHB master.)
  53  *
  54  * ASSUMES default (little) endianness for DMA transfers
  55  *
  56  * The PL08x has two flow control settings:
  57  *  - DMAC flow control: the transfer size defines the number of transfers
  58  *    which occur for the current LLI entry, and the DMAC raises TC at the
  59  *    end of every LLI entry.  Observed behaviour shows the DMAC listening
  60  *    to both the BREQ and SREQ signals (contrary to documented),
  61  *    transferring data if either is active.  The LBREQ and LSREQ signals
  62  *    are ignored.
  63  *
  64  *  - Peripheral flow control: the transfer size is ignored (and should be
  65  *    zero).  The data is transferred from the current LLI entry, until
  66  *    after the final transfer signalled by LBREQ or LSREQ.  The DMAC
  67  *    will then move to the next LLI entry.
  68  *
  69  * Only the former works sanely with scatter lists, so we only implement
  70  * the DMAC flow control method.  However, peripherals which use the LBREQ
  71  * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
  72  * these hardware restrictions prevents them from using scatter DMA.
  73  *
  74  * Global TODO:
  75  * - Break out common code from arch/arm/mach-s3c64xx and share
  76  */
  77 #include <linux/device.h>
  78 #include <linux/init.h>
  79 #include <linux/module.h>
  80 #include <linux/interrupt.h>
  81 #include <linux/slab.h>
  82 #include <linux/dmapool.h>
  83 #include <linux/dmaengine.h>
  84 #include <linux/amba/bus.h>
  85 #include <linux/amba/pl08x.h>
  86 #include <linux/debugfs.h>
  87 #include <linux/seq_file.h>
  88
  89 #include <asm/hardware/pl080.h>
  90
  91 #define DRIVER_NAME     "pl08xdmac"
  92
  93 /**
  94  * struct vendor_data - vendor-specific config parameters
  95  * for PL08x derivatives
  96  * @channels: the number of channels available in this variant
  97  * @dualmaster: whether this version supports dual AHB masters
  98  * or not.
  99  */
 100 struct vendor_data {
 101         u8 channels;
 102         bool dualmaster;
 103 };
 104
 105 /*
 106  * PL08X private data structures
 107  * An LLI struct - see PL08x TRM.  Note that next uses bit[0] as a bus bit,
 108  * start & end do not - their bus bit info is in cctl.  Also note that these
 109  * are fixed 32-bit quantities.
 110  */
 111 struct pl08x_lli {
 112         u32 src;
 113         u32 dst;
 114         u32 lli;
 115         u32 cctl;
 116 };
 117
 118 /**
 119  * struct pl08x_driver_data - the local state holder for the PL08x
 120  * @slave: slave engine for this instance
 121  * @memcpy: memcpy engine for this instance
 122  * @base: virtual memory base (remapped) for the PL08x
 123  * @adev: the corresponding AMBA (PrimeCell) bus entry
 124  * @vd: vendor data for this PL08x variant
 125  * @pd: platform data passed in from the platform/machine
 126  * @phy_chans: array of data for the physical channels
 127  * @pool: a pool for the LLI descriptors
 128  * @pool_ctr: counter of LLIs in the pool
 129  * @lock: a spinlock for this struct
 130  */
 131 struct pl08x_driver_data {
 132         struct dma_device slave;
 133         struct dma_device memcpy;
 134         void __iomem *base;
 135         struct amba_device *adev;
 136         const struct vendor_data *vd;
 137         struct pl08x_platform_data *pd;
 138         struct pl08x_phy_chan *phy_chans;
 139         struct dma_pool *pool;
 140         int pool_ctr;
 141         spinlock_t lock;
 142 };
 143
 144 /*
 145  * PL08X specific defines
 146  */
 147
 148 /*
 149  * Memory boundaries: the manual for PL08x says that the controller
 150  * cannot read past a 1KiB boundary, so these defines are used to
 151  * create transfer LLIs that do not cross such boundaries.
 152  */
 153 #define PL08X_BOUNDARY_SHIFT            (10)    /* 1KB 0x400 */
 154 #define PL08X_BOUNDARY_SIZE             (1 << PL08X_BOUNDARY_SHIFT)
 155
 156 /* Minimum period between work queue runs */
 157 #define PL08X_WQ_PERIODMIN      20
 158
 159 /* Size (bytes) of each LLI buffer allocated for one transfer */
 160 # define PL08X_LLI_TSFR_SIZE    0x2000
 161
 162 /* Maximum times we call dma_pool_alloc on this pool without freeing */
 163 #define PL08X_MAX_ALLOCS        0x40
 164 #define MAX_NUM_TSFR_LLIS       (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
 165 #define PL08X_ALIGN             8
 166
 167 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
 168 {
 169         return container_of(chan, struct pl08x_dma_chan, chan);
 170 }
 171
 172 /*
 173  * Physical channel handling
 174  */
 175
 176 /* Whether a certain channel is busy or not */
 177 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
 178 {
 179         unsigned int val;
 180
 181         val = readl(ch->base + PL080_CH_CONFIG);
 182         return val & PL080_CONFIG_ACTIVE;
 183 }
 184
 185 /*
 186  * Set the initial DMA register values i.e. those for the first LLI
 187  * The next LLI pointer and the configuration interrupt bit have
 188  * been set when the LLIs were constructed.  Poke them into the hardware
 189  * and start the transfer.
 190  */
 191 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
 192         struct pl08x_txd *txd)
 193 {
 194         struct pl08x_driver_data *pl08x = plchan->host;
 195         struct pl08x_phy_chan *phychan = plchan->phychan;
 196         u32 val;
 197
 198         plchan->at = txd;
 199
 200         /* Copy the basic control register calculated at transfer config */
 201         phychan->csrc = txd->csrc;
 202         phychan->cdst = txd->cdst;
 203         phychan->clli = txd->clli;
 204         phychan->cctl = txd->cctl;
 205
 206         /* Assign the signal to the proper control registers */
 207         phychan->ccfg = plchan->cd->ccfg;
 208         phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
 209         phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
 210         /* If it wasn't set from AMBA, ignore it */
 211         if (txd->direction == DMA_TO_DEVICE)
 212                 /* Select signal as destination */
 213                 phychan->ccfg |=
 214                         (phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
 215         else if (txd->direction == DMA_FROM_DEVICE)
 216                 /* Select signal as source */
 217                 phychan->ccfg |=
 218                         (phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
 219         /* Always enable error interrupts */
 220         phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
 221         /* Always enable terminal interrupts */
 222         phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
 223
 224         /* Wait for channel inactive */
 225         while (pl08x_phy_channel_busy(phychan))
 226                 cpu_relax();
 227
 228         dev_vdbg(&pl08x->adev->dev,
 229                 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
 230                  "cctl=0x%08x, clli=0x%08x, ccfg=0x%08x\n",
 231                 phychan->id,
 232                 phychan->csrc,
 233                 phychan->cdst,
 234                 phychan->cctl,
 235                 phychan->clli,
 236                 phychan->ccfg);
 237
 238         writel(phychan->csrc, phychan->base + PL080_CH_SRC_ADDR);
 239         writel(phychan->cdst, phychan->base + PL080_CH_DST_ADDR);
 240         writel(phychan->clli, phychan->base + PL080_CH_LLI);
 241         writel(phychan->cctl, phychan->base + PL080_CH_CONTROL);
 242         writel(phychan->ccfg, phychan->base + PL080_CH_CONFIG);
 243
 244         /* Enable the DMA channel */
 245         /* Do not access config register until channel shows as disabled */
 246         while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
 247                 cpu_relax();
 248
 249         /* Do not access config register until channel shows as inactive */
 250         val = readl(phychan->base + PL080_CH_CONFIG);
 251         while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
 252                 val = readl(phychan->base + PL080_CH_CONFIG);
 253
 254         writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
 255 }
 256
 257 /*
 258  * Overall DMAC remains enabled always.
 259  *
 260  * Disabling individual channels could lose data.
 261  *
 262  * Disable the peripheral DMA after disabling the DMAC
 263  * in order to allow the DMAC FIFO to drain, and
 264  * hence allow the channel to show inactive
 265  *
 266  */
 267 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
 268 {
 269         u32 val;
 270
 271         /* Set the HALT bit and wait for the FIFO to drain */
 272         val = readl(ch->base + PL080_CH_CONFIG);
 273         val |= PL080_CONFIG_HALT;
 274         writel(val, ch->base + PL080_CH_CONFIG);
 275
 276         /* Wait for channel inactive */
 277         while (pl08x_phy_channel_busy(ch))
 278                 cpu_relax();
 279 }
 280
 281 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
 282 {
 283         u32 val;
 284
 285         /* Clear the HALT bit */
 286         val = readl(ch->base + PL080_CH_CONFIG);
 287         val &= ~PL080_CONFIG_HALT;
 288         writel(val, ch->base + PL080_CH_CONFIG);
 289 }
 290
 291
 292 /* Stops the channel */
 293 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
 294 {
 295         u32 val;
 296
 297         pl08x_pause_phy_chan(ch);
 298
 299         /* Disable channel */
 300         val = readl(ch->base + PL080_CH_CONFIG);
 301         val &= ~PL080_CONFIG_ENABLE;
 302         val &= ~PL080_CONFIG_ERR_IRQ_MASK;
 303         val &= ~PL080_CONFIG_TC_IRQ_MASK;
 304         writel(val, ch->base + PL080_CH_CONFIG);
 305 }
 306
 307 static inline u32 get_bytes_in_cctl(u32 cctl)
 308 {
 309         /* The source width defines the number of bytes */
 310         u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
 311
 312         switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 313         case PL080_WIDTH_8BIT:
 314                 break;
 315         case PL080_WIDTH_16BIT:
 316                 bytes *= 2;
 317                 break;
 318         case PL080_WIDTH_32BIT:
 319                 bytes *= 4;
 320                 break;
 321         }
 322         return bytes;
 323 }
 324
 325 /* The channel should be paused when calling this */
 326 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 327 {
 328         struct pl08x_phy_chan *ch;
 329         struct pl08x_txd *txd;
 330         unsigned long flags;
 331         size_t bytes = 0;
 332
 333         spin_lock_irqsave(&plchan->lock, flags);
 334         ch = plchan->phychan;
 335         txd = plchan->at;
 336
 337         /*
 338          * Follow the LLIs to get the number of remaining
 339          * bytes in the currently active transaction.
 340          */
 341         if (ch && txd) {
 342                 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
 343
 344                 /* First get the remaining bytes in the active transfer */
 345                 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
 346
 347                 if (clli) {
 348                         struct pl08x_lli *llis_va = txd->llis_va;
 349                         dma_addr_t llis_bus = txd->llis_bus;
 350                         int index;
 351
 352                         BUG_ON(clli < llis_bus || clli >= llis_bus +
 353                                 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
 354
 355                         /*
 356                          * Locate the next LLI - as this is an array,
 357                          * it's simple maths to find.
 358                          */
 359                         index = (clli - llis_bus) / sizeof(struct pl08x_lli);
 360
 361                         for (; index < MAX_NUM_TSFR_LLIS; index++) {
 362                                 bytes += get_bytes_in_cctl(llis_va[index].cctl);
 363
 364                                 /*
 365                                  * A LLI pointer of 0 terminates the LLI list
 366                                  */
 367                                 if (!llis_va[index].lli)
 368                                         break;
 369                         }
 370                 }
 371         }
 372
 373         /* Sum up all queued transactions */
 374         if (!list_empty(&plchan->desc_list)) {
 375                 struct pl08x_txd *txdi;
 376                 list_for_each_entry(txdi, &plchan->desc_list, node) {
 377                         bytes += txdi->len;
 378                 }
 379         }
 380
 381         spin_unlock_irqrestore(&plchan->lock, flags);
 382
 383         return bytes;
 384 }
 385
 386 /*
 387  * Allocate a physical channel for a virtual channel
 388  */
 389 static struct pl08x_phy_chan *
 390 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
 391                       struct pl08x_dma_chan *virt_chan)
 392 {
 393         struct pl08x_phy_chan *ch = NULL;
 394         unsigned long flags;
 395         int i;
 396
 397         /*
 398          * Try to locate a physical channel to be used for
 399          * this transfer. If all are taken return NULL and
 400          * the requester will have to cope by using some fallback
 401          * PIO mode or retrying later.
 402          */
 403         for (i = 0; i < pl08x->vd->channels; i++) {
 404                 ch = &pl08x->phy_chans[i];
 405
 406                 spin_lock_irqsave(&ch->lock, flags);
 407
 408                 if (!ch->serving) {
 409                         ch->serving = virt_chan;
 410                         ch->signal = -1;
 411                         spin_unlock_irqrestore(&ch->lock, flags);
 412                         break;
 413                 }
 414
 415                 spin_unlock_irqrestore(&ch->lock, flags);
 416         }
 417
 418         if (i == pl08x->vd->channels) {
 419                 /* No physical channel available, cope with it */
 420                 return NULL;
 421         }
 422
 423         return ch;
 424 }
 425
 426 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
 427                                          struct pl08x_phy_chan *ch)
 428 {
 429         unsigned long flags;
 430
 431         /* Stop the channel and clear its interrupts */
 432         pl08x_stop_phy_chan(ch);
 433         writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
 434         writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
 435
 436         /* Mark it as free */
 437         spin_lock_irqsave(&ch->lock, flags);
 438         ch->serving = NULL;
 439         spin_unlock_irqrestore(&ch->lock, flags);
 440 }
 441
 442 /*
 443  * LLI handling
 444  */
 445
 446 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
 447 {
 448         switch (coded) {
 449         case PL080_WIDTH_8BIT:
 450                 return 1;
 451         case PL080_WIDTH_16BIT:
 452                 return 2;
 453         case PL080_WIDTH_32BIT:
 454                 return 4;
 455         default:
 456                 break;
 457         }
 458         BUG();
 459         return 0;
 460 }
 461
 462 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
 463                                   size_t tsize)
 464 {
 465         u32 retbits = cctl;
 466
 467         /* Remove all src, dst and transfer size bits */
 468         retbits &= ~PL080_CONTROL_DWIDTH_MASK;
 469         retbits &= ~PL080_CONTROL_SWIDTH_MASK;
 470         retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
 471
 472         /* Then set the bits according to the parameters */
 473         switch (srcwidth) {
 474         case 1:
 475                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
 476                 break;
 477         case 2:
 478                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
 479                 break;
 480         case 4:
 481                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
 482                 break;
 483         default:
 484                 BUG();
 485                 break;
 486         }
 487
 488         switch (dstwidth) {
 489         case 1:
 490                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
 491                 break;
 492         case 2:
 493                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
 494                 break;
 495         case 4:
 496                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
 497                 break;
 498         default:
 499                 BUG();
 500                 break;
 501         }
 502
 503         retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
 504         return retbits;
 505 }
 506
 507 /*
 508  * Autoselect a master bus to use for the transfer
 509  * this prefers the destination bus if both available
 510  * if fixed address on one bus the other will be chosen
 511  */
 512 static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
 513         struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
 514         struct pl08x_bus_data **sbus, u32 cctl)
 515 {
 516         if (!(cctl & PL080_CONTROL_DST_INCR)) {
 517                 *mbus = src_bus;
 518                 *sbus = dst_bus;
 519         } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
 520                 *mbus = dst_bus;
 521                 *sbus = src_bus;
 522         } else {
 523                 if (dst_bus->buswidth == 4) {
 524                         *mbus = dst_bus;
 525                         *sbus = src_bus;
 526                 } else if (src_bus->buswidth == 4) {
 527                         *mbus = src_bus;
 528                         *sbus = dst_bus;
 529                 } else if (dst_bus->buswidth == 2) {
 530                         *mbus = dst_bus;
 531                         *sbus = src_bus;
 532                 } else if (src_bus->buswidth == 2) {
 533                         *mbus = src_bus;
 534                         *sbus = dst_bus;
 535                 } else {
 536                         /* src_bus->buswidth == 1 */
 537                         *mbus = dst_bus;
 538                         *sbus = src_bus;
 539                 }
 540         }
 541 }
 542
 543 /*
 544  * Fills in one LLI for a certain transfer descriptor
 545  * and advance the counter
 546  */
 547 static int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
 548                             struct pl08x_txd *txd, int num_llis, int len,
 549                             u32 cctl, u32 *remainder)
 550 {
 551         struct pl08x_lli *llis_va = txd->llis_va;
 552         dma_addr_t llis_bus = txd->llis_bus;
 553
 554         BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
 555
 556         llis_va[num_llis].cctl          = cctl;
 557         llis_va[num_llis].src           = txd->srcbus.addr;
 558         llis_va[num_llis].dst           = txd->dstbus.addr;
 559
 560         /*
 561          * On versions with dual masters, you can optionally AND on
 562          * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
 563          * in new LLIs with that controller, but we always try to
 564          * choose AHB1 to point into memory. The idea is to have AHB2
 565          * fixed on the peripheral and AHB1 messing around in the
 566          * memory. So we don't manipulate this bit currently.
 567          */
 568
 569         llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
 570
 571         if (cctl & PL080_CONTROL_SRC_INCR)
 572                 txd->srcbus.addr += len;
 573         if (cctl & PL080_CONTROL_DST_INCR)
 574                 txd->dstbus.addr += len;
 575
 576         BUG_ON(*remainder < len);
 577
 578         *remainder -= len;
 579
 580         return num_llis + 1;
 581 }
 582
 583 /*
 584  * Return number of bytes to fill to boundary, or len
 585  */
 586 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
 587 {
 588         u32 boundary;
 589
 590         boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
 591                 << PL08X_BOUNDARY_SHIFT;
 592
 593         if (boundary < addr + len)
 594                 return boundary - addr;
 595         else
 596                 return len;
 597 }
 598
 599 /*
 600  * This fills in the table of LLIs for the transfer descriptor
 601  * Note that we assume we never have to change the burst sizes
 602  * Return 0 for error
 603  */
 604 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 605                               struct pl08x_txd *txd)
 606 {
 607         struct pl08x_channel_data *cd = txd->cd;
 608         struct pl08x_bus_data *mbus, *sbus;
 609         size_t remainder;
 610         int num_llis = 0;
 611         u32 cctl;
 612         size_t max_bytes_per_lli;
 613         size_t total_bytes = 0;
 614         struct pl08x_lli *llis_va;
 615
 616         txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
 617                                       &txd->llis_bus);
 618         if (!txd->llis_va) {
 619                 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
 620                 return 0;
 621         }
 622
 623         pl08x->pool_ctr++;
 624
 625         /*
 626          * Initialize bus values for this transfer
 627          * from the passed optimal values
 628          */
 629         if (!cd) {
 630                 dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
 631                 return 0;
 632         }
 633
 634         /* Get the default CCTL from the platform data */
 635         cctl = cd->cctl;
 636
 637         /*
 638          * On the PL080 we have two bus masters and we
 639          * should select one for source and one for
 640          * destination. We try to use AHB2 for the
 641          * bus which does not increment (typically the
 642          * peripheral) else we just choose something.
 643          */
 644         cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
 645         if (pl08x->vd->dualmaster) {
 646                 if (cctl & PL080_CONTROL_SRC_INCR)
 647                         /* Source increments, use AHB2 for destination */
 648                         cctl |= PL080_CONTROL_DST_AHB2;
 649                 else if (cctl & PL080_CONTROL_DST_INCR)
 650                         /* Destination increments, use AHB2 for source */
 651                         cctl |= PL080_CONTROL_SRC_AHB2;
 652                 else
 653                         /* Just pick something, source AHB1 dest AHB2 */
 654                         cctl |= PL080_CONTROL_DST_AHB2;
 655         }
 656
 657         /* Find maximum width of the source bus */
 658         txd->srcbus.maxwidth =
 659                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
 660                                        PL080_CONTROL_SWIDTH_SHIFT);
 661
 662         /* Find maximum width of the destination bus */
 663         txd->dstbus.maxwidth =
 664                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
 665                                        PL080_CONTROL_DWIDTH_SHIFT);
 666
 667         /* Set up the bus widths to the maximum */
 668         txd->srcbus.buswidth = txd->srcbus.maxwidth;
 669         txd->dstbus.buswidth = txd->dstbus.maxwidth;
 670         dev_vdbg(&pl08x->adev->dev,
 671                  "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
 672                  __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
 673
 674
 675         /*
 676          * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
 677          */
 678         max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
 679                 PL080_CONTROL_TRANSFER_SIZE_MASK;
 680         dev_vdbg(&pl08x->adev->dev,
 681                  "%s max bytes per lli = %zu\n",
 682                  __func__, max_bytes_per_lli);
 683
 684         /* We need to count this down to zero */
 685         remainder = txd->len;
 686         dev_vdbg(&pl08x->adev->dev,
 687                  "%s remainder = %zu\n",
 688                  __func__, remainder);
 689
 690         /*
 691          * Choose bus to align to
 692          * - prefers destination bus if both available
 693          * - if fixed address on one bus chooses other
 694          * - modifies cctl to choose an appropriate master
 695          */
 696         pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
 697                                 &mbus, &sbus, cctl);
 698
 699
 700         /*
 701          * The lowest bit of the LLI register
 702          * is also used to indicate which master to
 703          * use for reading the LLIs.
 704          */
 705
 706         if (txd->len < mbus->buswidth) {
 707                 /*
 708                  * Less than a bus width available
 709                  * - send as single bytes
 710                  */
 711                 while (remainder) {
 712                         dev_vdbg(&pl08x->adev->dev,
 713                                  "%s single byte LLIs for a transfer of "
 714                                  "less than a bus width (remain 0x%08x)\n",
 715                                  __func__, remainder);
 716                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 717                         num_llis =
 718                                 pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
 719                                         cctl, &remainder);
 720                         total_bytes++;
 721                 }
 722         } else {
 723                 /*
 724                  *  Make one byte LLIs until master bus is aligned
 725                  *  - slave will then be aligned also
 726                  */
 727                 while ((mbus->addr) % (mbus->buswidth)) {
 728                         dev_vdbg(&pl08x->adev->dev,
 729                                 "%s adjustment lli for less than bus width "
 730                                  "(remain 0x%08x)\n",
 731                                  __func__, remainder);
 732                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 733                         num_llis = pl08x_fill_lli_for_desc
 734                                 (pl08x, txd, num_llis, 1, cctl, &remainder);
 735                         total_bytes++;
 736                 }
 737
 738                 /*
 739                  *  Master now aligned
 740                  * - if slave is not then we must set its width down
 741                  */
 742                 if (sbus->addr % sbus->buswidth) {
 743                         dev_dbg(&pl08x->adev->dev,
 744                                 "%s set down bus width to one byte\n",
 745                                  __func__);
 746
 747                         sbus->buswidth = 1;
 748                 }
 749
 750                 /*
 751                  * Make largest possible LLIs until less than one bus
 752                  * width left
 753                  */
 754                 while (remainder > (mbus->buswidth - 1)) {
 755                         size_t lli_len, target_len, tsize, odd_bytes;
 756
 757                         /*
 758                          * If enough left try to send max possible,
 759                          * otherwise try to send the remainder
 760                          */
 761                         target_len = remainder;
 762                         if (remainder > max_bytes_per_lli)
 763                                 target_len = max_bytes_per_lli;
 764
 765                         /*
 766                          * Set bus lengths for incrementing buses
 767                          * to number of bytes which fill to next memory
 768                          * boundary
 769                          */
 770                         if (cctl & PL080_CONTROL_SRC_INCR)
 771                                 txd->srcbus.fill_bytes =
 772                                         pl08x_pre_boundary(
 773                                                 txd->srcbus.addr,
 774                                                 remainder);
 775                         else
 776                                 txd->srcbus.fill_bytes =
 777                                         max_bytes_per_lli;
 778
 779                         if (cctl & PL080_CONTROL_DST_INCR)
 780                                 txd->dstbus.fill_bytes =
 781                                         pl08x_pre_boundary(
 782                                                 txd->dstbus.addr,
 783                                                 remainder);
 784                         else
 785                                 txd->dstbus.fill_bytes =
 786                                                 max_bytes_per_lli;
 787
 788                         /*
 789                          *  Find the nearest
 790                          */
 791                         lli_len = min(txd->srcbus.fill_bytes,
 792                                 txd->dstbus.fill_bytes);
 793
 794                         BUG_ON(lli_len > remainder);
 795
 796                         if (lli_len <= 0) {
 797                                 dev_err(&pl08x->adev->dev,
 798                                         "%s lli_len is %zu, <= 0\n",
 799                                                 __func__, lli_len);
 800                                 return 0;
 801                         }
 802
 803                         if (lli_len == target_len) {
 804                                 /*
 805                                  * Can send what we wanted
 806                                  */
 807                                 /*
 808                                  *  Maintain alignment
 809                                  */
 810                                 lli_len = (lli_len/mbus->buswidth) *
 811                                                         mbus->buswidth;
 812                                 odd_bytes = 0;
 813                         } else {
 814                                 /*
 815                                  * So now we know how many bytes to transfer
 816                                  * to get to the nearest boundary
 817                                  * The next LLI will past the boundary
 818                                  * - however we may be working to a boundary
 819                                  *   on the slave bus
 820                                  *   We need to ensure the master stays aligned
 821                                  */
 822                                 odd_bytes = lli_len % mbus->buswidth;
 823                                 /*
 824                                  * - and that we are working in multiples
 825                                  *   of the bus widths
 826                                  */
 827                                 lli_len -= odd_bytes;
 828
 829                         }
 830
 831                         if (lli_len) {
 832                                 /*
 833                                  * Check against minimum bus alignment:
 834                                  * Calculate actual transfer size in relation
 835                                  * to bus width an get a maximum remainder of
 836                                  * the smallest bus width - 1
 837                                  */
 838                                 /* FIXME: use round_down()? */
 839                                 tsize = lli_len / min(mbus->buswidth,
 840                                                       sbus->buswidth);
 841                                 lli_len = tsize * min(mbus->buswidth,
 842                                                       sbus->buswidth);
 843
 844                                 if (target_len != lli_len) {
 845                                         dev_vdbg(&pl08x->adev->dev,
 846                                         "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
 847                                         __func__, target_len, lli_len, txd->len);
 848                                 }
 849
 850                                 cctl = pl08x_cctl_bits(cctl,
 851                                                        txd->srcbus.buswidth,
 852                                                        txd->dstbus.buswidth,
 853                                                        tsize);
 854
 855                                 dev_vdbg(&pl08x->adev->dev,
 856                                         "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
 857                                         __func__, lli_len, remainder);
 858                                 num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
 859                                                 num_llis, lli_len, cctl,
 860                                                 &remainder);
 861                                 total_bytes += lli_len;
 862                         }
 863
 864
 865                         if (odd_bytes) {
 866                                 /*
 867                                  * Creep past the boundary,
 868                                  * maintaining master alignment
 869                                  */
 870                                 int j;
 871                                 for (j = 0; (j < mbus->buswidth)
 872                                                 && (remainder); j++) {
 873                                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 874                                         dev_vdbg(&pl08x->adev->dev,
 875                                                 "%s align with boundary, single byte (remain 0x%08zx)\n",
 876                                                 __func__, remainder);
 877                                         num_llis =
 878                                                 pl08x_fill_lli_for_desc(pl08x,
 879                                                         txd, num_llis, 1,
 880                                                         cctl, &remainder);
 881                                         total_bytes++;
 882                                 }
 883                         }
 884                 }
 885
 886                 /*
 887                  * Send any odd bytes
 888                  */
 889                 while (remainder) {
 890                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 891                         dev_vdbg(&pl08x->adev->dev,
 892                                 "%s align with boundary, single odd byte (remain %zu)\n",
 893                                 __func__, remainder);
 894                         num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
 895                                         1, cctl, &remainder);
 896                         total_bytes++;
 897                 }
 898         }
 899         if (total_bytes != txd->len) {
 900                 dev_err(&pl08x->adev->dev,
 901                         "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
 902                         __func__, total_bytes, txd->len);
 903                 return 0;
 904         }
 905
 906         if (num_llis >= MAX_NUM_TSFR_LLIS) {
 907                 dev_err(&pl08x->adev->dev,
 908                         "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
 909                         __func__, (u32) MAX_NUM_TSFR_LLIS);
 910                 return 0;
 911         }
 912
 913         llis_va = txd->llis_va;
 914         /*
 915          * The final LLI terminates the LLI.
 916          */
 917         llis_va[num_llis - 1].lli = 0;
 918         /*
 919          * The final LLI element shall also fire an interrupt
 920          */
 921         llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
 922
 923         /* Now store the channel register values */
 924         txd->csrc = llis_va[0].src;
 925         txd->cdst = llis_va[0].dst;
 926         txd->clli = llis_va[0].lli;
 927         txd->cctl = llis_va[0].cctl;
 928         /* ccfg will be set at physical channel allocation time */
 929
 930 #ifdef VERBOSE_DEBUG
 931         {
 932                 int i;
 933
 934                 for (i = 0; i < num_llis; i++) {
 935                         dev_vdbg(&pl08x->adev->dev,
 936                                  "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
 937                                  i,
 938                                  &llis_va[i],
 939                                  llis_va[i].src,
 940                                  llis_va[i].dst,
 941                                  llis_va[i].cctl,
 942                                  llis_va[i].lli
 943                                 );
 944                 }
 945         }
 946 #endif
 947
 948         return num_llis;
 949 }
 950
 951 /* You should call this with the struct pl08x lock held */
 952 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
 953                            struct pl08x_txd *txd)
 954 {
 955         /* Free the LLI */
 956         dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
 957
 958         pl08x->pool_ctr--;
 959
 960         kfree(txd);
 961 }
 962
 963 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
 964                                 struct pl08x_dma_chan *plchan)
 965 {
 966         struct pl08x_txd *txdi = NULL;
 967         struct pl08x_txd *next;
 968
 969         if (!list_empty(&plchan->desc_list)) {
 970                 list_for_each_entry_safe(txdi,
 971                                          next, &plchan->desc_list, node) {
 972                         list_del(&txdi->node);
 973                         pl08x_free_txd(pl08x, txdi);
 974                 }
 975
 976         }
 977 }
 978
 979 /*
 980  * The DMA ENGINE API
 981  */
 982 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
 983 {
 984         return 0;
 985 }
 986
 987 static void pl08x_free_chan_resources(struct dma_chan *chan)
 988 {
 989 }
 990
 991 /*
 992  * This should be called with the channel plchan->lock held
 993  */
 994 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
 995                             struct pl08x_txd *txd)
 996 {
 997         struct pl08x_driver_data *pl08x = plchan->host;
 998         struct pl08x_phy_chan *ch;
 999         int ret;
1000
1001         /* Check if we already have a channel */
1002         if (plchan->phychan)
1003                 return 0;
1004
1005         ch = pl08x_get_phy_channel(pl08x, plchan);
1006         if (!ch) {
1007                 /* No physical channel available, cope with it */
1008                 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
1009                 return -EBUSY;
1010         }
1011
1012         /*
1013          * OK we have a physical channel: for memcpy() this is all we
1014          * need, but for slaves the physical signals may be muxed!
1015          * Can the platform allow us to use this channel?
1016          */
1017         if (plchan->slave &&
1018             ch->signal < 0 &&
1019             pl08x->pd->get_signal) {
1020                 ret = pl08x->pd->get_signal(plchan);
1021                 if (ret < 0) {
1022                         dev_dbg(&pl08x->adev->dev,
1023                                 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1024                                 ch->id, plchan->name);
1025                         /* Release physical channel & return */
1026                         pl08x_put_phy_channel(pl08x, ch);
1027                         return -EBUSY;
1028                 }
1029                 ch->signal = ret;
1030         }
1031
1032         dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
1033                  ch->id,
1034                  ch->signal,
1035                  plchan->name);
1036
1037         plchan->phychan = ch;
1038
1039         return 0;
1040 }
1041
1042 static void release_phy_channel(struct pl08x_dma_chan *plchan)
1043 {
1044         struct pl08x_driver_data *pl08x = plchan->host;
1045
1046         if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
1047                 pl08x->pd->put_signal(plchan);
1048                 plchan->phychan->signal = -1;
1049         }
1050         pl08x_put_phy_channel(pl08x, plchan->phychan);
1051         plchan->phychan = NULL;
1052 }
1053
1054 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
1055 {
1056         struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
1057
1058         plchan->chan.cookie += 1;
1059         if (plchan->chan.cookie < 0)
1060                 plchan->chan.cookie = 1;
1061         tx->cookie = plchan->chan.cookie;
1062         /* This unlock follows the lock in the prep() function */
1063         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1064
1065         return tx->cookie;
1066 }
1067
1068 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1069                 struct dma_chan *chan, unsigned long flags)
1070 {
1071         struct dma_async_tx_descriptor *retval = NULL;
1072
1073         return retval;
1074 }
1075
1076 /*
1077  * Code accessing dma_async_is_complete() in a tight loop
1078  * may give problems - could schedule where indicated.
1079  * If slaves are relying on interrupts to signal completion this
1080  * function must not be called with interrupts disabled
1081  */
1082 static enum dma_status
1083 pl08x_dma_tx_status(struct dma_chan *chan,
1084                     dma_cookie_t cookie,
1085                     struct dma_tx_state *txstate)
1086 {
1087         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1088         dma_cookie_t last_used;
1089         dma_cookie_t last_complete;
1090         enum dma_status ret;
1091         u32 bytesleft = 0;
1092
1093         last_used = plchan->chan.cookie;
1094         last_complete = plchan->lc;
1095
1096         ret = dma_async_is_complete(cookie, last_complete, last_used);
1097         if (ret == DMA_SUCCESS) {
1098                 dma_set_tx_state(txstate, last_complete, last_used, 0);
1099                 return ret;
1100         }
1101
1102         /*
1103          * schedule(); could be inserted here
1104          */
1105
1106         /*
1107          * This cookie not complete yet
1108          */
1109         last_used = plchan->chan.cookie;
1110         last_complete = plchan->lc;
1111
1112         /* Get number of bytes left in the active transactions and queue */
1113         bytesleft = pl08x_getbytes_chan(plchan);
1114
1115         dma_set_tx_state(txstate, last_complete, last_used,
1116                          bytesleft);
1117
1118         if (plchan->state == PL08X_CHAN_PAUSED)
1119                 return DMA_PAUSED;
1120
1121         /* Whether waiting or running, we're in progress */
1122         return DMA_IN_PROGRESS;
1123 }
1124
1125 /* PrimeCell DMA extension */
1126 struct burst_table {
1127         int burstwords;
1128         u32 reg;
1129 };
1130
1131 static const struct burst_table burst_sizes[] = {
1132         {
1133                 .burstwords = 256,
1134                 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1135                         (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1136         },
1137         {
1138                 .burstwords = 128,
1139                 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1140                         (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1141         },
1142         {
1143                 .burstwords = 64,
1144                 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1145                         (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1146         },
1147         {
1148                 .burstwords = 32,
1149                 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1150                         (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1151         },
1152         {
1153                 .burstwords = 16,
1154                 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1155                         (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1156         },
1157         {
1158                 .burstwords = 8,
1159                 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1160                         (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1161         },
1162         {
1163                 .burstwords = 4,
1164                 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1165                         (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1166         },
1167         {
1168                 .burstwords = 1,
1169                 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1170                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1171         },
1172 };
1173
1174 static void dma_set_runtime_config(struct dma_chan *chan,
1175                                struct dma_slave_config *config)
1176 {
1177         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1178         struct pl08x_driver_data *pl08x = plchan->host;
1179         struct pl08x_channel_data *cd = plchan->cd;
1180         enum dma_slave_buswidth addr_width;
1181         u32 maxburst;
1182         u32 cctl = 0;
1183         /* Mask out all except src and dst channel */
1184         u32 ccfg = cd->ccfg & 0x000003DEU;
1185         int i;
1186
1187         /* Transfer direction */
1188         plchan->runtime_direction = config->direction;
1189         if (config->direction == DMA_TO_DEVICE) {
1190                 plchan->runtime_addr = config->dst_addr;
1191                 cctl |= PL080_CONTROL_SRC_INCR;
1192                 ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1193                 addr_width = config->dst_addr_width;
1194                 maxburst = config->dst_maxburst;
1195         } else if (config->direction == DMA_FROM_DEVICE) {
1196                 plchan->runtime_addr = config->src_addr;
1197                 cctl |= PL080_CONTROL_DST_INCR;
1198                 ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1199                 addr_width = config->src_addr_width;
1200                 maxburst = config->src_maxburst;
1201         } else {
1202                 dev_err(&pl08x->adev->dev,
1203                         "bad runtime_config: alien transfer direction\n");
1204                 return;
1205         }
1206
1207         switch (addr_width) {
1208         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1209                 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1210                         (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1211                 break;
1212         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1213                 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1214                         (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1215                 break;
1216         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1217                 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1218                         (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1219                 break;
1220         default:
1221                 dev_err(&pl08x->adev->dev,
1222                         "bad runtime_config: alien address width\n");
1223                 return;
1224         }
1225
1226         /*
1227          * Now decide on a maxburst:
1228          * If this channel will only request single transfers, set this
1229          * down to ONE element.  Also select one element if no maxburst
1230          * is specified.
1231          */
1232         if (plchan->cd->single || maxburst == 0) {
1233                 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1234                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1235         } else {
1236                 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1237                         if (burst_sizes[i].burstwords <= maxburst)
1238                                 break;
1239                 cctl |= burst_sizes[i].reg;
1240         }
1241
1242         /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1243         cctl &= ~PL080_CONTROL_PROT_MASK;
1244         cctl |= PL080_CONTROL_PROT_SYS;
1245
1246         /* Modify the default channel data to fit PrimeCell request */
1247         cd->cctl = cctl;
1248         cd->ccfg = ccfg;
1249
1250         dev_dbg(&pl08x->adev->dev,
1251                 "configured channel %s (%s) for %s, data width %d, "
1252                 "maxburst %d words, LE, CCTL=0x%08x, CCFG=0x%08x\n",
1253                 dma_chan_name(chan), plchan->name,
1254                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1255                 addr_width,
1256                 maxburst,
1257                 cctl, ccfg);
1258 }
1259
1260 /*
1261  * Slave transactions callback to the slave device to allow
1262  * synchronization of slave DMA signals with the DMAC enable
1263  */
1264 static void pl08x_issue_pending(struct dma_chan *chan)
1265 {
1266         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1267         unsigned long flags;
1268
1269         spin_lock_irqsave(&plchan->lock, flags);
1270         /* Something is already active, or we're waiting for a channel... */
1271         if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1272                 spin_unlock_irqrestore(&plchan->lock, flags);
1273                 return;
1274         }
1275
1276         /* Take the first element in the queue and execute it */
1277         if (!list_empty(&plchan->desc_list)) {
1278                 struct pl08x_txd *next;
1279
1280                 next = list_first_entry(&plchan->desc_list,
1281                                         struct pl08x_txd,
1282                                         node);
1283                 list_del(&next->node);
1284                 plchan->state = PL08X_CHAN_RUNNING;
1285
1286                 pl08x_start_txd(plchan, next);
1287         }
1288
1289         spin_unlock_irqrestore(&plchan->lock, flags);
1290 }
1291
1292 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1293                                         struct pl08x_txd *txd)
1294 {
1295         int num_llis;
1296         struct pl08x_driver_data *pl08x = plchan->host;
1297         int ret;
1298
1299         num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1300         if (!num_llis) {
1301                 kfree(txd);
1302                 return -EINVAL;
1303         }
1304
1305         spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1306
1307         list_add_tail(&txd->node, &plchan->desc_list);
1308
1309         /*
1310          * See if we already have a physical channel allocated,
1311          * else this is the time to try to get one.
1312          */
1313         ret = prep_phy_channel(plchan, txd);
1314         if (ret) {
1315                 /*
1316                  * No physical channel available, we will
1317                  * stack up the memcpy channels until there is a channel
1318                  * available to handle it whereas slave transfers may
1319                  * have been denied due to platform channel muxing restrictions
1320                  * and since there is no guarantee that this will ever be
1321                  * resolved, and since the signal must be acquired AFTER
1322                  * acquiring the physical channel, we will let them be NACK:ed
1323                  * with -EBUSY here. The drivers can alway retry the prep()
1324                  * call if they are eager on doing this using DMA.
1325                  */
1326                 if (plchan->slave) {
1327                         pl08x_free_txd_list(pl08x, plchan);
1328                         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1329                         return -EBUSY;
1330                 }
1331                 /* Do this memcpy whenever there is a channel ready */
1332                 plchan->state = PL08X_CHAN_WAITING;
1333                 plchan->waiting = txd;
1334         } else
1335                 /*
1336                  * Else we're all set, paused and ready to roll,
1337                  * status will switch to PL08X_CHAN_RUNNING when
1338                  * we call issue_pending(). If there is something
1339                  * running on the channel already we don't change
1340                  * its state.
1341                  */
1342                 if (plchan->state == PL08X_CHAN_IDLE)
1343                         plchan->state = PL08X_CHAN_PAUSED;
1344
1345         /*
1346          * Notice that we leave plchan->lock locked on purpose:
1347          * it will be unlocked in the subsequent tx_submit()
1348          * call. This is a consequence of the current API.
1349          */
1350
1351         return 0;
1352 }
1353
1354 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1355 {
1356         struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1357
1358         if (txd) {
1359                 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1360                 txd->tx.tx_submit = pl08x_tx_submit;
1361                 INIT_LIST_HEAD(&txd->node);
1362         }
1363         return txd;
1364 }
1365
1366 /*
1367  * Initialize a descriptor to be used by memcpy submit
1368  */
1369 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1370                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1371                 size_t len, unsigned long flags)
1372 {
1373         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1374         struct pl08x_driver_data *pl08x = plchan->host;
1375         struct pl08x_txd *txd;
1376         int ret;
1377
1378         txd = pl08x_get_txd(plchan);
1379         if (!txd) {
1380                 dev_err(&pl08x->adev->dev,
1381                         "%s no memory for descriptor\n", __func__);
1382                 return NULL;
1383         }
1384
1385         txd->direction = DMA_NONE;
1386         txd->srcbus.addr = src;
1387         txd->dstbus.addr = dest;
1388
1389         /* Set platform data for m2m */
1390         txd->cd = &pl08x->pd->memcpy_channel;
1391         /* Both to be incremented or the code will break */
1392         txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1393         txd->len = len;
1394
1395         ret = pl08x_prep_channel_resources(plchan, txd);
1396         if (ret)
1397                 return NULL;
1398         /*
1399          * NB: the channel lock is held at this point so tx_submit()
1400          * must be called in direct succession.
1401          */
1402
1403         return &txd->tx;
1404 }
1405
1406 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1407                 struct dma_chan *chan, struct scatterlist *sgl,
1408                 unsigned int sg_len, enum dma_data_direction direction,
1409                 unsigned long flags)
1410 {
1411         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1412         struct pl08x_driver_data *pl08x = plchan->host;
1413         struct pl08x_txd *txd;
1414         int ret;
1415
1416         /*
1417          * Current implementation ASSUMES only one sg
1418          */
1419         if (sg_len != 1) {
1420                 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1421                         __func__);
1422                 BUG();
1423         }
1424
1425         dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1426                 __func__, sgl->length, plchan->name);
1427
1428         txd = pl08x_get_txd(plchan);
1429         if (!txd) {
1430                 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1431                 return NULL;
1432         }
1433
1434         if (direction != plchan->runtime_direction)
1435                 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1436                         "the direction configured for the PrimeCell\n",
1437                         __func__);
1438
1439         /*
1440          * Set up addresses, the PrimeCell configured address
1441          * will take precedence since this may configure the
1442          * channel target address dynamically at runtime.
1443          */
1444         txd->direction = direction;
1445         if (direction == DMA_TO_DEVICE) {
1446                 txd->srcbus.addr = sgl->dma_address;
1447                 if (plchan->runtime_addr)
1448                         txd->dstbus.addr = plchan->runtime_addr;
1449                 else
1450                         txd->dstbus.addr = plchan->cd->addr;
1451         } else if (direction == DMA_FROM_DEVICE) {
1452                 if (plchan->runtime_addr)
1453                         txd->srcbus.addr = plchan->runtime_addr;
1454                 else
1455                         txd->srcbus.addr = plchan->cd->addr;
1456                 txd->dstbus.addr = sgl->dma_address;
1457         } else {
1458                 dev_err(&pl08x->adev->dev,
1459                         "%s direction unsupported\n", __func__);
1460                 return NULL;
1461         }
1462         txd->cd = plchan->cd;
1463         txd->len = sgl->length;
1464
1465         ret = pl08x_prep_channel_resources(plchan, txd);
1466         if (ret)
1467                 return NULL;
1468         /*
1469          * NB: the channel lock is held at this point so tx_submit()
1470          * must be called in direct succession.
1471          */
1472
1473         return &txd->tx;
1474 }
1475
1476 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1477                          unsigned long arg)
1478 {
1479         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1480         struct pl08x_driver_data *pl08x = plchan->host;
1481         unsigned long flags;
1482         int ret = 0;
1483
1484         /* Controls applicable to inactive channels */
1485         if (cmd == DMA_SLAVE_CONFIG) {
1486                 dma_set_runtime_config(chan,
1487                                        (struct dma_slave_config *)
1488                                        arg);
1489                 return 0;
1490         }
1491
1492         /*
1493          * Anything succeeds on channels with no physical allocation and
1494          * no queued transfers.
1495          */
1496         spin_lock_irqsave(&plchan->lock, flags);
1497         if (!plchan->phychan && !plchan->at) {
1498                 spin_unlock_irqrestore(&plchan->lock, flags);
1499                 return 0;
1500         }
1501
1502         switch (cmd) {
1503         case DMA_TERMINATE_ALL:
1504                 plchan->state = PL08X_CHAN_IDLE;
1505
1506                 if (plchan->phychan) {
1507                         pl08x_stop_phy_chan(plchan->phychan);
1508
1509                         /*
1510                          * Mark physical channel as free and free any slave
1511                          * signal
1512                          */
1513                         release_phy_channel(plchan);
1514                 }
1515                 /* Dequeue jobs and free LLIs */
1516                 if (plchan->at) {
1517                         pl08x_free_txd(pl08x, plchan->at);
1518                         plchan->at = NULL;
1519                 }
1520                 /* Dequeue jobs not yet fired as well */
1521                 pl08x_free_txd_list(pl08x, plchan);
1522                 break;
1523         case DMA_PAUSE:
1524                 pl08x_pause_phy_chan(plchan->phychan);
1525                 plchan->state = PL08X_CHAN_PAUSED;
1526                 break;
1527         case DMA_RESUME:
1528                 pl08x_resume_phy_chan(plchan->phychan);
1529                 plchan->state = PL08X_CHAN_RUNNING;
1530                 break;
1531         default:
1532                 /* Unknown command */
1533                 ret = -ENXIO;
1534                 break;
1535         }
1536
1537         spin_unlock_irqrestore(&plchan->lock, flags);
1538
1539         return ret;
1540 }
1541
1542 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1543 {
1544         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1545         char *name = chan_id;
1546
1547         /* Check that the channel is not taken! */
1548         if (!strcmp(plchan->name, name))
1549                 return true;
1550
1551         return false;
1552 }
1553
1554 /*
1555  * Just check that the device is there and active
1556  * TODO: turn this bit on/off depending on the number of
1557  * physical channels actually used, if it is zero... well
1558  * shut it off. That will save some power. Cut the clock
1559  * at the same time.
1560  */
1561 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1562 {
1563         u32 val;
1564
1565         val = readl(pl08x->base + PL080_CONFIG);
1566         val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1567         /* We implicitly clear bit 1 and that means little-endian mode */
1568         val |= PL080_CONFIG_ENABLE;
1569         writel(val, pl08x->base + PL080_CONFIG);
1570 }
1571
1572 static void pl08x_tasklet(unsigned long data)
1573 {
1574         struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1575         struct pl08x_driver_data *pl08x = plchan->host;
1576         unsigned long flags;
1577
1578         spin_lock_irqsave(&plchan->lock, flags);
1579
1580         if (plchan->at) {
1581                 dma_async_tx_callback callback =
1582                         plchan->at->tx.callback;
1583                 void *callback_param =
1584                         plchan->at->tx.callback_param;
1585
1586                 /*
1587                  * Update last completed
1588                  */
1589                 plchan->lc = plchan->at->tx.cookie;
1590
1591                 /*
1592                  * Callback to signal completion
1593                  */
1594                 if (callback)
1595                         callback(callback_param);
1596
1597                 /*
1598                  * Free the descriptor
1599                  */
1600                 pl08x_free_txd(pl08x, plchan->at);
1601                 plchan->at = NULL;
1602         }
1603         /*
1604          * If a new descriptor is queued, set it up
1605          * plchan->at is NULL here
1606          */
1607         if (!list_empty(&plchan->desc_list)) {
1608                 struct pl08x_txd *next;
1609
1610                 next = list_first_entry(&plchan->desc_list,
1611                                         struct pl08x_txd,
1612                                         node);
1613                 list_del(&next->node);
1614
1615                 pl08x_start_txd(plchan, next);
1616         } else {
1617                 struct pl08x_dma_chan *waiting = NULL;
1618
1619                 /*
1620                  * No more jobs, so free up the physical channel
1621                  * Free any allocated signal on slave transfers too
1622                  */
1623                 release_phy_channel(plchan);
1624                 plchan->state = PL08X_CHAN_IDLE;
1625
1626                 /*
1627                  * And NOW before anyone else can grab that free:d
1628                  * up physical channel, see if there is some memcpy
1629                  * pending that seriously needs to start because of
1630                  * being stacked up while we were choking the
1631                  * physical channels with data.
1632                  */
1633                 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1634                                     chan.device_node) {
1635                   if (waiting->state == PL08X_CHAN_WAITING &&
1636                             waiting->waiting != NULL) {
1637                                 int ret;
1638
1639                                 /* This should REALLY not fail now */
1640                                 ret = prep_phy_channel(waiting,
1641                                                        waiting->waiting);
1642                                 BUG_ON(ret);
1643                                 waiting->state = PL08X_CHAN_RUNNING;
1644                                 waiting->waiting = NULL;
1645                                 pl08x_issue_pending(&waiting->chan);
1646                                 break;
1647                         }
1648                 }
1649         }
1650
1651         spin_unlock_irqrestore(&plchan->lock, flags);
1652 }
1653
1654 static irqreturn_t pl08x_irq(int irq, void *dev)
1655 {
1656         struct pl08x_driver_data *pl08x = dev;
1657         u32 mask = 0;
1658         u32 val;
1659         int i;
1660
1661         val = readl(pl08x->base + PL080_ERR_STATUS);
1662         if (val) {
1663                 /*
1664                  * An error interrupt (on one or more channels)
1665                  */
1666                 dev_err(&pl08x->adev->dev,
1667                         "%s error interrupt, register value 0x%08x\n",
1668                                 __func__, val);
1669                 /*
1670                  * Simply clear ALL PL08X error interrupts,
1671                  * regardless of channel and cause
1672                  * FIXME: should be 0x00000003 on PL081 really.
1673                  */
1674                 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1675         }
1676         val = readl(pl08x->base + PL080_INT_STATUS);
1677         for (i = 0; i < pl08x->vd->channels; i++) {
1678                 if ((1 << i) & val) {
1679                         /* Locate physical channel */
1680                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1681                         struct pl08x_dma_chan *plchan = phychan->serving;
1682
1683                         /* Schedule tasklet on this channel */
1684                         tasklet_schedule(&plchan->tasklet);
1685
1686                         mask |= (1 << i);
1687                 }
1688         }
1689         /*
1690          * Clear only the terminal interrupts on channels we processed
1691          */
1692         writel(mask, pl08x->base + PL080_TC_CLEAR);
1693
1694         return mask ? IRQ_HANDLED : IRQ_NONE;
1695 }
1696
1697 /*
1698  * Initialise the DMAC memcpy/slave channels.
1699  * Make a local wrapper to hold required data
1700  */
1701 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1702                                            struct dma_device *dmadev,
1703                                            unsigned int channels,
1704                                            bool slave)
1705 {
1706         struct pl08x_dma_chan *chan;
1707         int i;
1708
1709         INIT_LIST_HEAD(&dmadev->channels);
1710         /*
1711          * Register as many many memcpy as we have physical channels,
1712          * we won't always be able to use all but the code will have
1713          * to cope with that situation.
1714          */
1715         for (i = 0; i < channels; i++) {
1716                 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1717                 if (!chan) {
1718                         dev_err(&pl08x->adev->dev,
1719                                 "%s no memory for channel\n", __func__);
1720                         return -ENOMEM;
1721                 }
1722
1723                 chan->host = pl08x;
1724                 chan->state = PL08X_CHAN_IDLE;
1725
1726                 if (slave) {
1727                         chan->slave = true;
1728                         chan->name = pl08x->pd->slave_channels[i].bus_id;
1729                         chan->cd = &pl08x->pd->slave_channels[i];
1730                 } else {
1731                         chan->cd = &pl08x->pd->memcpy_channel;
1732                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1733                         if (!chan->name) {
1734                                 kfree(chan);
1735                                 return -ENOMEM;
1736                         }
1737                 }
1738                 if (chan->cd->circular_buffer) {
1739                         dev_err(&pl08x->adev->dev,
1740                                 "channel %s: circular buffers not supported\n",
1741                                 chan->name);
1742                         kfree(chan);
1743                         continue;
1744                 }
1745                 dev_info(&pl08x->adev->dev,
1746                          "initialize virtual channel \"%s\"\n",
1747                          chan->name);
1748
1749                 chan->chan.device = dmadev;
1750                 chan->chan.cookie = 0;
1751                 chan->lc = 0;
1752
1753                 spin_lock_init(&chan->lock);
1754                 INIT_LIST_HEAD(&chan->desc_list);
1755                 tasklet_init(&chan->tasklet, pl08x_tasklet,
1756                              (unsigned long) chan);
1757
1758                 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1759         }
1760         dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1761                  i, slave ? "slave" : "memcpy");
1762         return i;
1763 }
1764
1765 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1766 {
1767         struct pl08x_dma_chan *chan = NULL;
1768         struct pl08x_dma_chan *next;
1769
1770         list_for_each_entry_safe(chan,
1771                                  next, &dmadev->channels, chan.device_node) {
1772                 list_del(&chan->chan.device_node);
1773                 kfree(chan);
1774         }
1775 }
1776
1777 #ifdef CONFIG_DEBUG_FS
1778 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1779 {
1780         switch (state) {
1781         case PL08X_CHAN_IDLE:
1782                 return "idle";
1783         case PL08X_CHAN_RUNNING:
1784                 return "running";
1785         case PL08X_CHAN_PAUSED:
1786                 return "paused";
1787         case PL08X_CHAN_WAITING:
1788                 return "waiting";
1789         default:
1790                 break;
1791         }
1792         return "UNKNOWN STATE";
1793 }
1794
1795 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1796 {
1797         struct pl08x_driver_data *pl08x = s->private;
1798         struct pl08x_dma_chan *chan;
1799         struct pl08x_phy_chan *ch;
1800         unsigned long flags;
1801         int i;
1802
1803         seq_printf(s, "PL08x physical channels:\n");
1804         seq_printf(s, "CHANNEL:\tUSER:\n");
1805         seq_printf(s, "--------\t-----\n");
1806         for (i = 0; i < pl08x->vd->channels; i++) {
1807                 struct pl08x_dma_chan *virt_chan;
1808
1809                 ch = &pl08x->phy_chans[i];
1810
1811                 spin_lock_irqsave(&ch->lock, flags);
1812                 virt_chan = ch->serving;
1813
1814                 seq_printf(s, "%d\t\t%s\n",
1815                            ch->id, virt_chan ? virt_chan->name : "(none)");
1816
1817                 spin_unlock_irqrestore(&ch->lock, flags);
1818         }
1819
1820         seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1821         seq_printf(s, "CHANNEL:\tSTATE:\n");
1822         seq_printf(s, "--------\t------\n");
1823         list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1824                 seq_printf(s, "%s\t\t%s\n", chan->name,
1825                            pl08x_state_str(chan->state));
1826         }
1827
1828         seq_printf(s, "\nPL08x virtual slave channels:\n");
1829         seq_printf(s, "CHANNEL:\tSTATE:\n");
1830         seq_printf(s, "--------\t------\n");
1831         list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1832                 seq_printf(s, "%s\t\t%s\n", chan->name,
1833                            pl08x_state_str(chan->state));
1834         }
1835
1836         return 0;
1837 }
1838
1839 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1840 {
1841         return single_open(file, pl08x_debugfs_show, inode->i_private);
1842 }
1843
1844 static const struct file_operations pl08x_debugfs_operations = {
1845         .open           = pl08x_debugfs_open,
1846         .read           = seq_read,
1847         .llseek         = seq_lseek,
1848         .release        = single_release,
1849 };
1850
1851 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1852 {
1853         /* Expose a simple debugfs interface to view all clocks */
1854         (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1855                                    NULL, pl08x,
1856                                    &pl08x_debugfs_operations);
1857 }
1858
1859 #else
1860 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1861 {
1862 }
1863 #endif
1864
1865 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1866 {
1867         struct pl08x_driver_data *pl08x;
1868         const struct vendor_data *vd = id->data;
1869         int ret = 0;
1870         int i;
1871
1872         ret = amba_request_regions(adev, NULL);
1873         if (ret)
1874                 return ret;
1875
1876         /* Create the driver state holder */
1877         pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1878         if (!pl08x) {
1879                 ret = -ENOMEM;
1880                 goto out_no_pl08x;
1881         }
1882
1883         /* Initialize memcpy engine */
1884         dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1885         pl08x->memcpy.dev = &adev->dev;
1886         pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1887         pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1888         pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1889         pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1890         pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1891         pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1892         pl08x->memcpy.device_control = pl08x_control;
1893
1894         /* Initialize slave engine */
1895         dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1896         pl08x->slave.dev = &adev->dev;
1897         pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1898         pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1899         pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1900         pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1901         pl08x->slave.device_issue_pending = pl08x_issue_pending;
1902         pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1903         pl08x->slave.device_control = pl08x_control;
1904
1905         /* Get the platform data */
1906         pl08x->pd = dev_get_platdata(&adev->dev);
1907         if (!pl08x->pd) {
1908                 dev_err(&adev->dev, "no platform data supplied\n");
1909                 goto out_no_platdata;
1910         }
1911
1912         /* Assign useful pointers to the driver state */
1913         pl08x->adev = adev;
1914         pl08x->vd = vd;
1915
1916         /* A DMA memory pool for LLIs, align on 1-byte boundary */
1917         pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1918                         PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1919         if (!pl08x->pool) {
1920                 ret = -ENOMEM;
1921                 goto out_no_lli_pool;
1922         }
1923
1924         spin_lock_init(&pl08x->lock);
1925
1926         pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1927         if (!pl08x->base) {
1928                 ret = -ENOMEM;
1929                 goto out_no_ioremap;
1930         }
1931
1932         /* Turn on the PL08x */
1933         pl08x_ensure_on(pl08x);
1934
1935         /*
1936          * Attach the interrupt handler
1937          */
1938         writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1939         writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1940
1941         ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1942                           DRIVER_NAME, pl08x);
1943         if (ret) {
1944                 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1945                         __func__, adev->irq[0]);
1946                 goto out_no_irq;
1947         }
1948
1949         /* Initialize physical channels */
1950         pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1951                         GFP_KERNEL);
1952         if (!pl08x->phy_chans) {
1953                 dev_err(&adev->dev, "%s failed to allocate "
1954                         "physical channel holders\n",
1955                         __func__);
1956                 goto out_no_phychans;
1957         }
1958
1959         for (i = 0; i < vd->channels; i++) {
1960                 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1961
1962                 ch->id = i;
1963                 ch->base = pl08x->base + PL080_Cx_BASE(i);
1964                 spin_lock_init(&ch->lock);
1965                 ch->serving = NULL;
1966                 ch->signal = -1;
1967                 dev_info(&adev->dev,
1968                          "physical channel %d is %s\n", i,
1969                          pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1970         }
1971
1972         /* Register as many memcpy channels as there are physical channels */
1973         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1974                                               pl08x->vd->channels, false);
1975         if (ret <= 0) {
1976                 dev_warn(&pl08x->adev->dev,
1977                          "%s failed to enumerate memcpy channels - %d\n",
1978                          __func__, ret);
1979                 goto out_no_memcpy;
1980         }
1981         pl08x->memcpy.chancnt = ret;
1982
1983         /* Register slave channels */
1984         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
1985                                               pl08x->pd->num_slave_channels,
1986                                               true);
1987         if (ret <= 0) {
1988                 dev_warn(&pl08x->adev->dev,
1989                         "%s failed to enumerate slave channels - %d\n",
1990                                 __func__, ret);
1991                 goto out_no_slave;
1992         }
1993         pl08x->slave.chancnt = ret;
1994
1995         ret = dma_async_device_register(&pl08x->memcpy);
1996         if (ret) {
1997                 dev_warn(&pl08x->adev->dev,
1998                         "%s failed to register memcpy as an async device - %d\n",
1999                         __func__, ret);
2000                 goto out_no_memcpy_reg;
2001         }
2002
2003         ret = dma_async_device_register(&pl08x->slave);
2004         if (ret) {
2005                 dev_warn(&pl08x->adev->dev,
2006                         "%s failed to register slave as an async device - %d\n",
2007                         __func__, ret);
2008                 goto out_no_slave_reg;
2009         }
2010
2011         amba_set_drvdata(adev, pl08x);
2012         init_pl08x_debugfs(pl08x);
2013         dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2014                  amba_part(adev), amba_rev(adev),
2015                  (unsigned long long)adev->res.start, adev->irq[0]);
2016         return 0;
2017
2018 out_no_slave_reg:
2019         dma_async_device_unregister(&pl08x->memcpy);
2020 out_no_memcpy_reg:
2021         pl08x_free_virtual_channels(&pl08x->slave);
2022 out_no_slave:
2023         pl08x_free_virtual_channels(&pl08x->memcpy);
2024 out_no_memcpy:
2025         kfree(pl08x->phy_chans);
2026 out_no_phychans:
2027         free_irq(adev->irq[0], pl08x);
2028 out_no_irq:
2029         iounmap(pl08x->base);
2030 out_no_ioremap:
2031         dma_pool_destroy(pl08x->pool);
2032 out_no_lli_pool:
2033 out_no_platdata:
2034         kfree(pl08x);
2035 out_no_pl08x:
2036         amba_release_regions(adev);
2037         return ret;
2038 }
2039
2040 /* PL080 has 8 channels and the PL080 have just 2 */
2041 static struct vendor_data vendor_pl080 = {
2042         .channels = 8,
2043         .dualmaster = true,
2044 };
2045
2046 static struct vendor_data vendor_pl081 = {
2047         .channels = 2,
2048         .dualmaster = false,
2049 };
2050
2051 static struct amba_id pl08x_ids[] = {
2052         /* PL080 */
2053         {
2054                 .id     = 0x00041080,
2055                 .mask   = 0x000fffff,
2056                 .data   = &vendor_pl080,
2057         },
2058         /* PL081 */
2059         {
2060                 .id     = 0x00041081,
2061                 .mask   = 0x000fffff,
2062                 .data   = &vendor_pl081,
2063         },
2064         /* Nomadik 8815 PL080 variant */
2065         {
2066                 .id     = 0x00280880,
2067                 .mask   = 0x00ffffff,
2068                 .data   = &vendor_pl080,
2069         },
2070         { 0, 0 },
2071 };
2072
2073 static struct amba_driver pl08x_amba_driver = {
2074         .drv.name       = DRIVER_NAME,
2075         .id_table       = pl08x_ids,
2076         .probe          = pl08x_probe,
2077 };
2078
2079 static int __init pl08x_init(void)
2080 {
2081         int retval;
2082         retval = amba_driver_register(&pl08x_amba_driver);
2083         if (retval)
2084                 printk(KERN_WARNING DRIVER_NAME
2085                        "failed to register as an AMBA device (%d)\n",
2086                        retval);
2087         return retval;
2088 }
2089 subsys_initcall(pl08x_init);