drivers/dma/amba-pl08x.c

   1 /*
   2  * Copyright (c) 2006 ARM Ltd.
   3  * Copyright (c) 2010 ST-Ericsson SA
   4  *
   5  * Author: Peter Pearse <peter.pearse@arm.com>
   6  * Author: Linus Walleij <linus.walleij@stericsson.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the Free
  10  * Software Foundation; either version 2 of the License, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program; if not, write to the Free Software Foundation, Inc., 59
  20  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  21  *
  22  * The full GNU General Public License is in this distribution in the
  23  * file called COPYING.
  24  *
  25  * Documentation: ARM DDI 0196G == PL080
  26  * Documentation: ARM DDI 0218E == PL081
  27  *
  28  * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
  29  * any channel.
  30  *
  31  * The PL080 has 8 channels available for simultaneous use, and the PL081
  32  * has only two channels. So on these DMA controllers the number of channels
  33  * and the number of incoming DMA signals are two totally different things.
  34  * It is usually not possible to theoretically handle all physical signals,
  35  * so a multiplexing scheme with possible denial of use is necessary.
  36  *
  37  * The PL080 has a dual bus master, PL081 has a single master.
  38  *
  39  * Memory to peripheral transfer may be visualized as
  40  *      Get data from memory to DMAC
  41  *      Until no data left
  42  *              On burst request from peripheral
  43  *                      Destination burst from DMAC to peripheral
  44  *                      Clear burst request
  45  *      Raise terminal count interrupt
  46  *
  47  * For peripherals with a FIFO:
  48  * Source      burst size == half the depth of the peripheral FIFO
  49  * Destination burst size == the depth of the peripheral FIFO
  50  *
  51  * (Bursts are irrelevant for mem to mem transfers - there are no burst
  52  * signals, the DMA controller will simply facilitate its AHB master.)
  53  *
  54  * ASSUMES default (little) endianness for DMA transfers
  55  *
  56  * The PL08x has two flow control settings:
  57  *  - DMAC flow control: the transfer size defines the number of transfers
  58  *    which occur for the current LLI entry, and the DMAC raises TC at the
  59  *    end of every LLI entry.  Observed behaviour shows the DMAC listening
  60  *    to both the BREQ and SREQ signals (contrary to documented),
  61  *    transferring data if either is active.  The LBREQ and LSREQ signals
  62  *    are ignored.
  63  *
  64  *  - Peripheral flow control: the transfer size is ignored (and should be
  65  *    zero).  The data is transferred from the current LLI entry, until
  66  *    after the final transfer signalled by LBREQ or LSREQ.  The DMAC
  67  *    will then move to the next LLI entry.
  68  *
  69  * Only the former works sanely with scatter lists, so we only implement
  70  * the DMAC flow control method.  However, peripherals which use the LBREQ
  71  * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
  72  * these hardware restrictions prevents them from using scatter DMA.
  73  *
  74  * Global TODO:
  75  * - Break out common code from arch/arm/mach-s3c64xx and share
  76  */
  77 #include <linux/device.h>
  78 #include <linux/init.h>
  79 #include <linux/module.h>
  80 #include <linux/interrupt.h>
  81 #include <linux/slab.h>
  82 #include <linux/dmapool.h>
  83 #include <linux/dmaengine.h>
  84 #include <linux/amba/bus.h>
  85 #include <linux/amba/pl08x.h>
  86 #include <linux/debugfs.h>
  87 #include <linux/seq_file.h>
  88
  89 #include <asm/hardware/pl080.h>
  90
  91 #define DRIVER_NAME     "pl08xdmac"
  92
  93 /**
  94  * struct vendor_data - vendor-specific config parameters
  95  * for PL08x derivatives
  96  * @channels: the number of channels available in this variant
  97  * @dualmaster: whether this version supports dual AHB masters
  98  * or not.
  99  */
 100 struct vendor_data {
 101         u8 channels;
 102         bool dualmaster;
 103 };
 104
 105 /*
 106  * PL08X private data structures
 107  * An LLI struct - see PL08x TRM.  Note that next uses bit[0] as a bus bit,
 108  * start & end do not - their bus bit info is in cctl.  Also note that these
 109  * are fixed 32-bit quantities.
 110  */
 111 struct pl08x_lli {
 112         u32 src;
 113         u32 dst;
 114         u32 lli;
 115         u32 cctl;
 116 };
 117
 118 /**
 119  * struct pl08x_driver_data - the local state holder for the PL08x
 120  * @slave: slave engine for this instance
 121  * @memcpy: memcpy engine for this instance
 122  * @base: virtual memory base (remapped) for the PL08x
 123  * @adev: the corresponding AMBA (PrimeCell) bus entry
 124  * @vd: vendor data for this PL08x variant
 125  * @pd: platform data passed in from the platform/machine
 126  * @phy_chans: array of data for the physical channels
 127  * @pool: a pool for the LLI descriptors
 128  * @pool_ctr: counter of LLIs in the pool
 129  * @lock: a spinlock for this struct
 130  */
 131 struct pl08x_driver_data {
 132         struct dma_device slave;
 133         struct dma_device memcpy;
 134         void __iomem *base;
 135         struct amba_device *adev;
 136         const struct vendor_data *vd;
 137         struct pl08x_platform_data *pd;
 138         struct pl08x_phy_chan *phy_chans;
 139         struct dma_pool *pool;
 140         int pool_ctr;
 141         spinlock_t lock;
 142 };
 143
 144 /*
 145  * PL08X specific defines
 146  */
 147
 148 /*
 149  * Memory boundaries: the manual for PL08x says that the controller
 150  * cannot read past a 1KiB boundary, so these defines are used to
 151  * create transfer LLIs that do not cross such boundaries.
 152  */
 153 #define PL08X_BOUNDARY_SHIFT            (10)    /* 1KB 0x400 */
 154 #define PL08X_BOUNDARY_SIZE             (1 << PL08X_BOUNDARY_SHIFT)
 155
 156 /* Minimum period between work queue runs */
 157 #define PL08X_WQ_PERIODMIN      20
 158
 159 /* Size (bytes) of each LLI buffer allocated for one transfer */
 160 # define PL08X_LLI_TSFR_SIZE    0x2000
 161
 162 /* Maximum times we call dma_pool_alloc on this pool without freeing */
 163 #define PL08X_MAX_ALLOCS        0x40
 164 #define MAX_NUM_TSFR_LLIS       (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
 165 #define PL08X_ALIGN             8
 166
 167 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
 168 {
 169         return container_of(chan, struct pl08x_dma_chan, chan);
 170 }
 171
 172 /*
 173  * Physical channel handling
 174  */
 175
 176 /* Whether a certain channel is busy or not */
 177 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
 178 {
 179         unsigned int val;
 180
 181         val = readl(ch->base + PL080_CH_CONFIG);
 182         return val & PL080_CONFIG_ACTIVE;
 183 }
 184
 185 /*
 186  * Set the initial DMA register values i.e. those for the first LLI
 187  * The next LLI pointer and the configuration interrupt bit have
 188  * been set when the LLIs were constructed
 189  */
 190 static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
 191                             struct pl08x_phy_chan *ch)
 192 {
 193         /* Wait for channel inactive */
 194         while (pl08x_phy_channel_busy(ch))
 195                 cpu_relax();
 196
 197         dev_vdbg(&pl08x->adev->dev,
 198                 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
 199                  "cctl=0x%08x, clli=0x%08x, ccfg=0x%08x\n",
 200                 ch->id,
 201                 ch->csrc,
 202                 ch->cdst,
 203                 ch->cctl,
 204                 ch->clli,
 205                 ch->ccfg);
 206
 207         writel(ch->csrc, ch->base + PL080_CH_SRC_ADDR);
 208         writel(ch->cdst, ch->base + PL080_CH_DST_ADDR);
 209         writel(ch->clli, ch->base + PL080_CH_LLI);
 210         writel(ch->cctl, ch->base + PL080_CH_CONTROL);
 211         writel(ch->ccfg, ch->base + PL080_CH_CONFIG);
 212 }
 213
 214 static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan *plchan)
 215 {
 216         struct pl08x_channel_data *cd = plchan->cd;
 217         struct pl08x_phy_chan *phychan = plchan->phychan;
 218         struct pl08x_txd *txd = plchan->at;
 219
 220         /* Copy the basic control register calculated at transfer config */
 221         phychan->csrc = txd->csrc;
 222         phychan->cdst = txd->cdst;
 223         phychan->clli = txd->clli;
 224         phychan->cctl = txd->cctl;
 225
 226         /* Assign the signal to the proper control registers */
 227         phychan->ccfg = cd->ccfg;
 228         phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
 229         phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
 230         /* If it wasn't set from AMBA, ignore it */
 231         if (txd->direction == DMA_TO_DEVICE)
 232                 /* Select signal as destination */
 233                 phychan->ccfg |=
 234                         (phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
 235         else if (txd->direction == DMA_FROM_DEVICE)
 236                 /* Select signal as source */
 237                 phychan->ccfg |=
 238                         (phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
 239         /* Always enable error interrupts */
 240         phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
 241         /* Always enable terminal interrupts */
 242         phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
 243 }
 244
 245 /*
 246  * Enable the DMA channel
 247  * Assumes all other configuration bits have been set
 248  * as desired before this code is called
 249  */
 250 static void pl08x_enable_phy_chan(struct pl08x_driver_data *pl08x,
 251                                   struct pl08x_phy_chan *ch)
 252 {
 253         u32 val;
 254
 255         /*
 256          * Do not access config register until channel shows as disabled
 257          */
 258         while (readl(pl08x->base + PL080_EN_CHAN) & (1 << ch->id))
 259                 cpu_relax();
 260
 261         /*
 262          * Do not access config register until channel shows as inactive
 263          */
 264         val = readl(ch->base + PL080_CH_CONFIG);
 265         while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
 266                 val = readl(ch->base + PL080_CH_CONFIG);
 267
 268         writel(val | PL080_CONFIG_ENABLE, ch->base + PL080_CH_CONFIG);
 269 }
 270
 271 /*
 272  * Overall DMAC remains enabled always.
 273  *
 274  * Disabling individual channels could lose data.
 275  *
 276  * Disable the peripheral DMA after disabling the DMAC
 277  * in order to allow the DMAC FIFO to drain, and
 278  * hence allow the channel to show inactive
 279  *
 280  */
 281 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
 282 {
 283         u32 val;
 284
 285         /* Set the HALT bit and wait for the FIFO to drain */
 286         val = readl(ch->base + PL080_CH_CONFIG);
 287         val |= PL080_CONFIG_HALT;
 288         writel(val, ch->base + PL080_CH_CONFIG);
 289
 290         /* Wait for channel inactive */
 291         while (pl08x_phy_channel_busy(ch))
 292                 cpu_relax();
 293 }
 294
 295 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
 296 {
 297         u32 val;
 298
 299         /* Clear the HALT bit */
 300         val = readl(ch->base + PL080_CH_CONFIG);
 301         val &= ~PL080_CONFIG_HALT;
 302         writel(val, ch->base + PL080_CH_CONFIG);
 303 }
 304
 305
 306 /* Stops the channel */
 307 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
 308 {
 309         u32 val;
 310
 311         pl08x_pause_phy_chan(ch);
 312
 313         /* Disable channel */
 314         val = readl(ch->base + PL080_CH_CONFIG);
 315         val &= ~PL080_CONFIG_ENABLE;
 316         val &= ~PL080_CONFIG_ERR_IRQ_MASK;
 317         val &= ~PL080_CONFIG_TC_IRQ_MASK;
 318         writel(val, ch->base + PL080_CH_CONFIG);
 319 }
 320
 321 static inline u32 get_bytes_in_cctl(u32 cctl)
 322 {
 323         /* The source width defines the number of bytes */
 324         u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
 325
 326         switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 327         case PL080_WIDTH_8BIT:
 328                 break;
 329         case PL080_WIDTH_16BIT:
 330                 bytes *= 2;
 331                 break;
 332         case PL080_WIDTH_32BIT:
 333                 bytes *= 4;
 334                 break;
 335         }
 336         return bytes;
 337 }
 338
 339 /* The channel should be paused when calling this */
 340 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 341 {
 342         struct pl08x_phy_chan *ch;
 343         struct pl08x_txd *txd;
 344         unsigned long flags;
 345         size_t bytes = 0;
 346
 347         spin_lock_irqsave(&plchan->lock, flags);
 348         ch = plchan->phychan;
 349         txd = plchan->at;
 350
 351         /*
 352          * Follow the LLIs to get the number of remaining
 353          * bytes in the currently active transaction.
 354          */
 355         if (ch && txd) {
 356                 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
 357
 358                 /* First get the remaining bytes in the active transfer */
 359                 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
 360
 361                 if (clli) {
 362                         struct pl08x_lli *llis_va = txd->llis_va;
 363                         dma_addr_t llis_bus = txd->llis_bus;
 364                         int index;
 365
 366                         BUG_ON(clli < llis_bus || clli >= llis_bus +
 367                                 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
 368
 369                         /*
 370                          * Locate the next LLI - as this is an array,
 371                          * it's simple maths to find.
 372                          */
 373                         index = (clli - llis_bus) / sizeof(struct pl08x_lli);
 374
 375                         for (; index < MAX_NUM_TSFR_LLIS; index++) {
 376                                 bytes += get_bytes_in_cctl(llis_va[index].cctl);
 377
 378                                 /*
 379                                  * A LLI pointer of 0 terminates the LLI list
 380                                  */
 381                                 if (!llis_va[index].lli)
 382                                         break;
 383                         }
 384                 }
 385         }
 386
 387         /* Sum up all queued transactions */
 388         if (!list_empty(&plchan->desc_list)) {
 389                 struct pl08x_txd *txdi;
 390                 list_for_each_entry(txdi, &plchan->desc_list, node) {
 391                         bytes += txdi->len;
 392                 }
 393         }
 394
 395         spin_unlock_irqrestore(&plchan->lock, flags);
 396
 397         return bytes;
 398 }
 399
 400 /*
 401  * Allocate a physical channel for a virtual channel
 402  */
 403 static struct pl08x_phy_chan *
 404 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
 405                       struct pl08x_dma_chan *virt_chan)
 406 {
 407         struct pl08x_phy_chan *ch = NULL;
 408         unsigned long flags;
 409         int i;
 410
 411         /*
 412          * Try to locate a physical channel to be used for
 413          * this transfer. If all are taken return NULL and
 414          * the requester will have to cope by using some fallback
 415          * PIO mode or retrying later.
 416          */
 417         for (i = 0; i < pl08x->vd->channels; i++) {
 418                 ch = &pl08x->phy_chans[i];
 419
 420                 spin_lock_irqsave(&ch->lock, flags);
 421
 422                 if (!ch->serving) {
 423                         ch->serving = virt_chan;
 424                         ch->signal = -1;
 425                         spin_unlock_irqrestore(&ch->lock, flags);
 426                         break;
 427                 }
 428
 429                 spin_unlock_irqrestore(&ch->lock, flags);
 430         }
 431
 432         if (i == pl08x->vd->channels) {
 433                 /* No physical channel available, cope with it */
 434                 return NULL;
 435         }
 436
 437         return ch;
 438 }
 439
 440 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
 441                                          struct pl08x_phy_chan *ch)
 442 {
 443         unsigned long flags;
 444
 445         /* Stop the channel and clear its interrupts */
 446         pl08x_stop_phy_chan(ch);
 447         writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
 448         writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
 449
 450         /* Mark it as free */
 451         spin_lock_irqsave(&ch->lock, flags);
 452         ch->serving = NULL;
 453         spin_unlock_irqrestore(&ch->lock, flags);
 454 }
 455
 456 /*
 457  * LLI handling
 458  */
 459
 460 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
 461 {
 462         switch (coded) {
 463         case PL080_WIDTH_8BIT:
 464                 return 1;
 465         case PL080_WIDTH_16BIT:
 466                 return 2;
 467         case PL080_WIDTH_32BIT:
 468                 return 4;
 469         default:
 470                 break;
 471         }
 472         BUG();
 473         return 0;
 474 }
 475
 476 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
 477                                   size_t tsize)
 478 {
 479         u32 retbits = cctl;
 480
 481         /* Remove all src, dst and transfer size bits */
 482         retbits &= ~PL080_CONTROL_DWIDTH_MASK;
 483         retbits &= ~PL080_CONTROL_SWIDTH_MASK;
 484         retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
 485
 486         /* Then set the bits according to the parameters */
 487         switch (srcwidth) {
 488         case 1:
 489                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
 490                 break;
 491         case 2:
 492                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
 493                 break;
 494         case 4:
 495                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
 496                 break;
 497         default:
 498                 BUG();
 499                 break;
 500         }
 501
 502         switch (dstwidth) {
 503         case 1:
 504                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
 505                 break;
 506         case 2:
 507                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
 508                 break;
 509         case 4:
 510                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
 511                 break;
 512         default:
 513                 BUG();
 514                 break;
 515         }
 516
 517         retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
 518         return retbits;
 519 }
 520
 521 /*
 522  * Autoselect a master bus to use for the transfer
 523  * this prefers the destination bus if both available
 524  * if fixed address on one bus the other will be chosen
 525  */
 526 static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
 527         struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
 528         struct pl08x_bus_data **sbus, u32 cctl)
 529 {
 530         if (!(cctl & PL080_CONTROL_DST_INCR)) {
 531                 *mbus = src_bus;
 532                 *sbus = dst_bus;
 533         } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
 534                 *mbus = dst_bus;
 535                 *sbus = src_bus;
 536         } else {
 537                 if (dst_bus->buswidth == 4) {
 538                         *mbus = dst_bus;
 539                         *sbus = src_bus;
 540                 } else if (src_bus->buswidth == 4) {
 541                         *mbus = src_bus;
 542                         *sbus = dst_bus;
 543                 } else if (dst_bus->buswidth == 2) {
 544                         *mbus = dst_bus;
 545                         *sbus = src_bus;
 546                 } else if (src_bus->buswidth == 2) {
 547                         *mbus = src_bus;
 548                         *sbus = dst_bus;
 549                 } else {
 550                         /* src_bus->buswidth == 1 */
 551                         *mbus = dst_bus;
 552                         *sbus = src_bus;
 553                 }
 554         }
 555 }
 556
 557 /*
 558  * Fills in one LLI for a certain transfer descriptor
 559  * and advance the counter
 560  */
 561 static int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
 562                             struct pl08x_txd *txd, int num_llis, int len,
 563                             u32 cctl, u32 *remainder)
 564 {
 565         struct pl08x_lli *llis_va = txd->llis_va;
 566         dma_addr_t llis_bus = txd->llis_bus;
 567
 568         BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
 569
 570         llis_va[num_llis].cctl          = cctl;
 571         llis_va[num_llis].src           = txd->srcbus.addr;
 572         llis_va[num_llis].dst           = txd->dstbus.addr;
 573
 574         /*
 575          * On versions with dual masters, you can optionally AND on
 576          * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
 577          * in new LLIs with that controller, but we always try to
 578          * choose AHB1 to point into memory. The idea is to have AHB2
 579          * fixed on the peripheral and AHB1 messing around in the
 580          * memory. So we don't manipulate this bit currently.
 581          */
 582
 583         llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
 584
 585         if (cctl & PL080_CONTROL_SRC_INCR)
 586                 txd->srcbus.addr += len;
 587         if (cctl & PL080_CONTROL_DST_INCR)
 588                 txd->dstbus.addr += len;
 589
 590         BUG_ON(*remainder < len);
 591
 592         *remainder -= len;
 593
 594         return num_llis + 1;
 595 }
 596
 597 /*
 598  * Return number of bytes to fill to boundary, or len
 599  */
 600 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
 601 {
 602         u32 boundary;
 603
 604         boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
 605                 << PL08X_BOUNDARY_SHIFT;
 606
 607         if (boundary < addr + len)
 608                 return boundary - addr;
 609         else
 610                 return len;
 611 }
 612
 613 /*
 614  * This fills in the table of LLIs for the transfer descriptor
 615  * Note that we assume we never have to change the burst sizes
 616  * Return 0 for error
 617  */
 618 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 619                               struct pl08x_txd *txd)
 620 {
 621         struct pl08x_channel_data *cd = txd->cd;
 622         struct pl08x_bus_data *mbus, *sbus;
 623         size_t remainder;
 624         int num_llis = 0;
 625         u32 cctl;
 626         size_t max_bytes_per_lli;
 627         size_t total_bytes = 0;
 628         struct pl08x_lli *llis_va;
 629
 630         txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
 631                                       &txd->llis_bus);
 632         if (!txd->llis_va) {
 633                 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
 634                 return 0;
 635         }
 636
 637         pl08x->pool_ctr++;
 638
 639         /*
 640          * Initialize bus values for this transfer
 641          * from the passed optimal values
 642          */
 643         if (!cd) {
 644                 dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
 645                 return 0;
 646         }
 647
 648         /* Get the default CCTL from the platform data */
 649         cctl = cd->cctl;
 650
 651         /*
 652          * On the PL080 we have two bus masters and we
 653          * should select one for source and one for
 654          * destination. We try to use AHB2 for the
 655          * bus which does not increment (typically the
 656          * peripheral) else we just choose something.
 657          */
 658         cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
 659         if (pl08x->vd->dualmaster) {
 660                 if (cctl & PL080_CONTROL_SRC_INCR)
 661                         /* Source increments, use AHB2 for destination */
 662                         cctl |= PL080_CONTROL_DST_AHB2;
 663                 else if (cctl & PL080_CONTROL_DST_INCR)
 664                         /* Destination increments, use AHB2 for source */
 665                         cctl |= PL080_CONTROL_SRC_AHB2;
 666                 else
 667                         /* Just pick something, source AHB1 dest AHB2 */
 668                         cctl |= PL080_CONTROL_DST_AHB2;
 669         }
 670
 671         /* Find maximum width of the source bus */
 672         txd->srcbus.maxwidth =
 673                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
 674                                        PL080_CONTROL_SWIDTH_SHIFT);
 675
 676         /* Find maximum width of the destination bus */
 677         txd->dstbus.maxwidth =
 678                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
 679                                        PL080_CONTROL_DWIDTH_SHIFT);
 680
 681         /* Set up the bus widths to the maximum */
 682         txd->srcbus.buswidth = txd->srcbus.maxwidth;
 683         txd->dstbus.buswidth = txd->dstbus.maxwidth;
 684         dev_vdbg(&pl08x->adev->dev,
 685                  "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
 686                  __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
 687
 688
 689         /*
 690          * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
 691          */
 692         max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
 693                 PL080_CONTROL_TRANSFER_SIZE_MASK;
 694         dev_vdbg(&pl08x->adev->dev,
 695                  "%s max bytes per lli = %zu\n",
 696                  __func__, max_bytes_per_lli);
 697
 698         /* We need to count this down to zero */
 699         remainder = txd->len;
 700         dev_vdbg(&pl08x->adev->dev,
 701                  "%s remainder = %zu\n",
 702                  __func__, remainder);
 703
 704         /*
 705          * Choose bus to align to
 706          * - prefers destination bus if both available
 707          * - if fixed address on one bus chooses other
 708          * - modifies cctl to choose an appropriate master
 709          */
 710         pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
 711                                 &mbus, &sbus, cctl);
 712
 713
 714         /*
 715          * The lowest bit of the LLI register
 716          * is also used to indicate which master to
 717          * use for reading the LLIs.
 718          */
 719
 720         if (txd->len < mbus->buswidth) {
 721                 /*
 722                  * Less than a bus width available
 723                  * - send as single bytes
 724                  */
 725                 while (remainder) {
 726                         dev_vdbg(&pl08x->adev->dev,
 727                                  "%s single byte LLIs for a transfer of "
 728                                  "less than a bus width (remain 0x%08x)\n",
 729                                  __func__, remainder);
 730                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 731                         num_llis =
 732                                 pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
 733                                         cctl, &remainder);
 734                         total_bytes++;
 735                 }
 736         } else {
 737                 /*
 738                  *  Make one byte LLIs until master bus is aligned
 739                  *  - slave will then be aligned also
 740                  */
 741                 while ((mbus->addr) % (mbus->buswidth)) {
 742                         dev_vdbg(&pl08x->adev->dev,
 743                                 "%s adjustment lli for less than bus width "
 744                                  "(remain 0x%08x)\n",
 745                                  __func__, remainder);
 746                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 747                         num_llis = pl08x_fill_lli_for_desc
 748                                 (pl08x, txd, num_llis, 1, cctl, &remainder);
 749                         total_bytes++;
 750                 }
 751
 752                 /*
 753                  *  Master now aligned
 754                  * - if slave is not then we must set its width down
 755                  */
 756                 if (sbus->addr % sbus->buswidth) {
 757                         dev_dbg(&pl08x->adev->dev,
 758                                 "%s set down bus width to one byte\n",
 759                                  __func__);
 760
 761                         sbus->buswidth = 1;
 762                 }
 763
 764                 /*
 765                  * Make largest possible LLIs until less than one bus
 766                  * width left
 767                  */
 768                 while (remainder > (mbus->buswidth - 1)) {
 769                         size_t lli_len, target_len, tsize, odd_bytes;
 770
 771                         /*
 772                          * If enough left try to send max possible,
 773                          * otherwise try to send the remainder
 774                          */
 775                         target_len = remainder;
 776                         if (remainder > max_bytes_per_lli)
 777                                 target_len = max_bytes_per_lli;
 778
 779                         /*
 780                          * Set bus lengths for incrementing buses
 781                          * to number of bytes which fill to next memory
 782                          * boundary
 783                          */
 784                         if (cctl & PL080_CONTROL_SRC_INCR)
 785                                 txd->srcbus.fill_bytes =
 786                                         pl08x_pre_boundary(
 787                                                 txd->srcbus.addr,
 788                                                 remainder);
 789                         else
 790                                 txd->srcbus.fill_bytes =
 791                                         max_bytes_per_lli;
 792
 793                         if (cctl & PL080_CONTROL_DST_INCR)
 794                                 txd->dstbus.fill_bytes =
 795                                         pl08x_pre_boundary(
 796                                                 txd->dstbus.addr,
 797                                                 remainder);
 798                         else
 799                                 txd->dstbus.fill_bytes =
 800                                                 max_bytes_per_lli;
 801
 802                         /*
 803                          *  Find the nearest
 804                          */
 805                         lli_len = min(txd->srcbus.fill_bytes,
 806                                 txd->dstbus.fill_bytes);
 807
 808                         BUG_ON(lli_len > remainder);
 809
 810                         if (lli_len <= 0) {
 811                                 dev_err(&pl08x->adev->dev,
 812                                         "%s lli_len is %zu, <= 0\n",
 813                                                 __func__, lli_len);
 814                                 return 0;
 815                         }
 816
 817                         if (lli_len == target_len) {
 818                                 /*
 819                                  * Can send what we wanted
 820                                  */
 821                                 /*
 822                                  *  Maintain alignment
 823                                  */
 824                                 lli_len = (lli_len/mbus->buswidth) *
 825                                                         mbus->buswidth;
 826                                 odd_bytes = 0;
 827                         } else {
 828                                 /*
 829                                  * So now we know how many bytes to transfer
 830                                  * to get to the nearest boundary
 831                                  * The next LLI will past the boundary
 832                                  * - however we may be working to a boundary
 833                                  *   on the slave bus
 834                                  *   We need to ensure the master stays aligned
 835                                  */
 836                                 odd_bytes = lli_len % mbus->buswidth;
 837                                 /*
 838                                  * - and that we are working in multiples
 839                                  *   of the bus widths
 840                                  */
 841                                 lli_len -= odd_bytes;
 842
 843                         }
 844
 845                         if (lli_len) {
 846                                 /*
 847                                  * Check against minimum bus alignment:
 848                                  * Calculate actual transfer size in relation
 849                                  * to bus width an get a maximum remainder of
 850                                  * the smallest bus width - 1
 851                                  */
 852                                 /* FIXME: use round_down()? */
 853                                 tsize = lli_len / min(mbus->buswidth,
 854                                                       sbus->buswidth);
 855                                 lli_len = tsize * min(mbus->buswidth,
 856                                                       sbus->buswidth);
 857
 858                                 if (target_len != lli_len) {
 859                                         dev_vdbg(&pl08x->adev->dev,
 860                                         "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
 861                                         __func__, target_len, lli_len, txd->len);
 862                                 }
 863
 864                                 cctl = pl08x_cctl_bits(cctl,
 865                                                        txd->srcbus.buswidth,
 866                                                        txd->dstbus.buswidth,
 867                                                        tsize);
 868
 869                                 dev_vdbg(&pl08x->adev->dev,
 870                                         "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
 871                                         __func__, lli_len, remainder);
 872                                 num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
 873                                                 num_llis, lli_len, cctl,
 874                                                 &remainder);
 875                                 total_bytes += lli_len;
 876                         }
 877
 878
 879                         if (odd_bytes) {
 880                                 /*
 881                                  * Creep past the boundary,
 882                                  * maintaining master alignment
 883                                  */
 884                                 int j;
 885                                 for (j = 0; (j < mbus->buswidth)
 886                                                 && (remainder); j++) {
 887                                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 888                                         dev_vdbg(&pl08x->adev->dev,
 889                                                 "%s align with boundary, single byte (remain 0x%08zx)\n",
 890                                                 __func__, remainder);
 891                                         num_llis =
 892                                                 pl08x_fill_lli_for_desc(pl08x,
 893                                                         txd, num_llis, 1,
 894                                                         cctl, &remainder);
 895                                         total_bytes++;
 896                                 }
 897                         }
 898                 }
 899
 900                 /*
 901                  * Send any odd bytes
 902                  */
 903                 while (remainder) {
 904                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
 905                         dev_vdbg(&pl08x->adev->dev,
 906                                 "%s align with boundary, single odd byte (remain %zu)\n",
 907                                 __func__, remainder);
 908                         num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
 909                                         1, cctl, &remainder);
 910                         total_bytes++;
 911                 }
 912         }
 913         if (total_bytes != txd->len) {
 914                 dev_err(&pl08x->adev->dev,
 915                         "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
 916                         __func__, total_bytes, txd->len);
 917                 return 0;
 918         }
 919
 920         if (num_llis >= MAX_NUM_TSFR_LLIS) {
 921                 dev_err(&pl08x->adev->dev,
 922                         "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
 923                         __func__, (u32) MAX_NUM_TSFR_LLIS);
 924                 return 0;
 925         }
 926
 927         llis_va = txd->llis_va;
 928         /*
 929          * The final LLI terminates the LLI.
 930          */
 931         llis_va[num_llis - 1].lli = 0;
 932         /*
 933          * The final LLI element shall also fire an interrupt
 934          */
 935         llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
 936
 937         /* Now store the channel register values */
 938         txd->csrc = llis_va[0].src;
 939         txd->cdst = llis_va[0].dst;
 940         txd->clli = llis_va[0].lli;
 941         txd->cctl = llis_va[0].cctl;
 942         /* ccfg will be set at physical channel allocation time */
 943
 944 #ifdef VERBOSE_DEBUG
 945         {
 946                 int i;
 947
 948                 for (i = 0; i < num_llis; i++) {
 949                         dev_vdbg(&pl08x->adev->dev,
 950                                  "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
 951                                  i,
 952                                  &llis_va[i],
 953                                  llis_va[i].src,
 954                                  llis_va[i].dst,
 955                                  llis_va[i].cctl,
 956                                  llis_va[i].lli
 957                                 );
 958                 }
 959         }
 960 #endif
 961
 962         return num_llis;
 963 }
 964
 965 /* You should call this with the struct pl08x lock held */
 966 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
 967                            struct pl08x_txd *txd)
 968 {
 969         /* Free the LLI */
 970         dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
 971
 972         pl08x->pool_ctr--;
 973
 974         kfree(txd);
 975 }
 976
 977 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
 978                                 struct pl08x_dma_chan *plchan)
 979 {
 980         struct pl08x_txd *txdi = NULL;
 981         struct pl08x_txd *next;
 982
 983         if (!list_empty(&plchan->desc_list)) {
 984                 list_for_each_entry_safe(txdi,
 985                                          next, &plchan->desc_list, node) {
 986                         list_del(&txdi->node);
 987                         pl08x_free_txd(pl08x, txdi);
 988                 }
 989
 990         }
 991 }
 992
 993 /*
 994  * The DMA ENGINE API
 995  */
 996 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
 997 {
 998         return 0;
 999 }
1000
1001 static void pl08x_free_chan_resources(struct dma_chan *chan)
1002 {
1003 }
1004
1005 /*
1006  * This should be called with the channel plchan->lock held
1007  */
1008 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
1009                             struct pl08x_txd *txd)
1010 {
1011         struct pl08x_driver_data *pl08x = plchan->host;
1012         struct pl08x_phy_chan *ch;
1013         int ret;
1014
1015         /* Check if we already have a channel */
1016         if (plchan->phychan)
1017                 return 0;
1018
1019         ch = pl08x_get_phy_channel(pl08x, plchan);
1020         if (!ch) {
1021                 /* No physical channel available, cope with it */
1022                 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
1023                 return -EBUSY;
1024         }
1025
1026         /*
1027          * OK we have a physical channel: for memcpy() this is all we
1028          * need, but for slaves the physical signals may be muxed!
1029          * Can the platform allow us to use this channel?
1030          */
1031         if (plchan->slave &&
1032             ch->signal < 0 &&
1033             pl08x->pd->get_signal) {
1034                 ret = pl08x->pd->get_signal(plchan);
1035                 if (ret < 0) {
1036                         dev_dbg(&pl08x->adev->dev,
1037                                 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1038                                 ch->id, plchan->name);
1039                         /* Release physical channel & return */
1040                         pl08x_put_phy_channel(pl08x, ch);
1041                         return -EBUSY;
1042                 }
1043                 ch->signal = ret;
1044         }
1045
1046         dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
1047                  ch->id,
1048                  ch->signal,
1049                  plchan->name);
1050
1051         plchan->phychan = ch;
1052
1053         return 0;
1054 }
1055
1056 static void release_phy_channel(struct pl08x_dma_chan *plchan)
1057 {
1058         struct pl08x_driver_data *pl08x = plchan->host;
1059
1060         if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
1061                 pl08x->pd->put_signal(plchan);
1062                 plchan->phychan->signal = -1;
1063         }
1064         pl08x_put_phy_channel(pl08x, plchan->phychan);
1065         plchan->phychan = NULL;
1066 }
1067
1068 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
1069 {
1070         struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
1071
1072         plchan->chan.cookie += 1;
1073         if (plchan->chan.cookie < 0)
1074                 plchan->chan.cookie = 1;
1075         tx->cookie = plchan->chan.cookie;
1076         /* This unlock follows the lock in the prep() function */
1077         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1078
1079         return tx->cookie;
1080 }
1081
1082 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1083                 struct dma_chan *chan, unsigned long flags)
1084 {
1085         struct dma_async_tx_descriptor *retval = NULL;
1086
1087         return retval;
1088 }
1089
1090 /*
1091  * Code accessing dma_async_is_complete() in a tight loop
1092  * may give problems - could schedule where indicated.
1093  * If slaves are relying on interrupts to signal completion this
1094  * function must not be called with interrupts disabled
1095  */
1096 static enum dma_status
1097 pl08x_dma_tx_status(struct dma_chan *chan,
1098                     dma_cookie_t cookie,
1099                     struct dma_tx_state *txstate)
1100 {
1101         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1102         dma_cookie_t last_used;
1103         dma_cookie_t last_complete;
1104         enum dma_status ret;
1105         u32 bytesleft = 0;
1106
1107         last_used = plchan->chan.cookie;
1108         last_complete = plchan->lc;
1109
1110         ret = dma_async_is_complete(cookie, last_complete, last_used);
1111         if (ret == DMA_SUCCESS) {
1112                 dma_set_tx_state(txstate, last_complete, last_used, 0);
1113                 return ret;
1114         }
1115
1116         /*
1117          * schedule(); could be inserted here
1118          */
1119
1120         /*
1121          * This cookie not complete yet
1122          */
1123         last_used = plchan->chan.cookie;
1124         last_complete = plchan->lc;
1125
1126         /* Get number of bytes left in the active transactions and queue */
1127         bytesleft = pl08x_getbytes_chan(plchan);
1128
1129         dma_set_tx_state(txstate, last_complete, last_used,
1130                          bytesleft);
1131
1132         if (plchan->state == PL08X_CHAN_PAUSED)
1133                 return DMA_PAUSED;
1134
1135         /* Whether waiting or running, we're in progress */
1136         return DMA_IN_PROGRESS;
1137 }
1138
1139 /* PrimeCell DMA extension */
1140 struct burst_table {
1141         int burstwords;
1142         u32 reg;
1143 };
1144
1145 static const struct burst_table burst_sizes[] = {
1146         {
1147                 .burstwords = 256,
1148                 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1149                         (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1150         },
1151         {
1152                 .burstwords = 128,
1153                 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1154                         (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1155         },
1156         {
1157                 .burstwords = 64,
1158                 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1159                         (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1160         },
1161         {
1162                 .burstwords = 32,
1163                 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1164                         (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1165         },
1166         {
1167                 .burstwords = 16,
1168                 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1169                         (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1170         },
1171         {
1172                 .burstwords = 8,
1173                 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1174                         (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1175         },
1176         {
1177                 .burstwords = 4,
1178                 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1179                         (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1180         },
1181         {
1182                 .burstwords = 1,
1183                 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1184                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1185         },
1186 };
1187
1188 static void dma_set_runtime_config(struct dma_chan *chan,
1189                                struct dma_slave_config *config)
1190 {
1191         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1192         struct pl08x_driver_data *pl08x = plchan->host;
1193         struct pl08x_channel_data *cd = plchan->cd;
1194         enum dma_slave_buswidth addr_width;
1195         u32 maxburst;
1196         u32 cctl = 0;
1197         /* Mask out all except src and dst channel */
1198         u32 ccfg = cd->ccfg & 0x000003DEU;
1199         int i;
1200
1201         /* Transfer direction */
1202         plchan->runtime_direction = config->direction;
1203         if (config->direction == DMA_TO_DEVICE) {
1204                 plchan->runtime_addr = config->dst_addr;
1205                 cctl |= PL080_CONTROL_SRC_INCR;
1206                 ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1207                 addr_width = config->dst_addr_width;
1208                 maxburst = config->dst_maxburst;
1209         } else if (config->direction == DMA_FROM_DEVICE) {
1210                 plchan->runtime_addr = config->src_addr;
1211                 cctl |= PL080_CONTROL_DST_INCR;
1212                 ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1213                 addr_width = config->src_addr_width;
1214                 maxburst = config->src_maxburst;
1215         } else {
1216                 dev_err(&pl08x->adev->dev,
1217                         "bad runtime_config: alien transfer direction\n");
1218                 return;
1219         }
1220
1221         switch (addr_width) {
1222         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1223                 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1224                         (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1225                 break;
1226         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1227                 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1228                         (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1229                 break;
1230         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1231                 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1232                         (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1233                 break;
1234         default:
1235                 dev_err(&pl08x->adev->dev,
1236                         "bad runtime_config: alien address width\n");
1237                 return;
1238         }
1239
1240         /*
1241          * Now decide on a maxburst:
1242          * If this channel will only request single transfers, set this
1243          * down to ONE element.  Also select one element if no maxburst
1244          * is specified.
1245          */
1246         if (plchan->cd->single || maxburst == 0) {
1247                 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1248                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1249         } else {
1250                 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1251                         if (burst_sizes[i].burstwords <= maxburst)
1252                                 break;
1253                 cctl |= burst_sizes[i].reg;
1254         }
1255
1256         /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1257         cctl &= ~PL080_CONTROL_PROT_MASK;
1258         cctl |= PL080_CONTROL_PROT_SYS;
1259
1260         /* Modify the default channel data to fit PrimeCell request */
1261         cd->cctl = cctl;
1262         cd->ccfg = ccfg;
1263
1264         dev_dbg(&pl08x->adev->dev,
1265                 "configured channel %s (%s) for %s, data width %d, "
1266                 "maxburst %d words, LE, CCTL=0x%08x, CCFG=0x%08x\n",
1267                 dma_chan_name(chan), plchan->name,
1268                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1269                 addr_width,
1270                 maxburst,
1271                 cctl, ccfg);
1272 }
1273
1274 /*
1275  * Slave transactions callback to the slave device to allow
1276  * synchronization of slave DMA signals with the DMAC enable
1277  */
1278 static void pl08x_issue_pending(struct dma_chan *chan)
1279 {
1280         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1281         struct pl08x_driver_data *pl08x = plchan->host;
1282         unsigned long flags;
1283
1284         spin_lock_irqsave(&plchan->lock, flags);
1285         /* Something is already active, or we're waiting for a channel... */
1286         if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1287                 spin_unlock_irqrestore(&plchan->lock, flags);
1288                 return;
1289         }
1290
1291         /* Take the first element in the queue and execute it */
1292         if (!list_empty(&plchan->desc_list)) {
1293                 struct pl08x_txd *next;
1294
1295                 next = list_first_entry(&plchan->desc_list,
1296                                         struct pl08x_txd,
1297                                         node);
1298                 list_del(&next->node);
1299                 plchan->at = next;
1300                 plchan->state = PL08X_CHAN_RUNNING;
1301
1302                 /* Configure the physical channel for the active txd */
1303                 pl08x_config_phychan_for_txd(plchan);
1304                 pl08x_set_cregs(pl08x, plchan->phychan);
1305                 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1306         }
1307
1308         spin_unlock_irqrestore(&plchan->lock, flags);
1309 }
1310
1311 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1312                                         struct pl08x_txd *txd)
1313 {
1314         int num_llis;
1315         struct pl08x_driver_data *pl08x = plchan->host;
1316         int ret;
1317
1318         num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1319         if (!num_llis) {
1320                 kfree(txd);
1321                 return -EINVAL;
1322         }
1323
1324         spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1325
1326         list_add_tail(&txd->node, &plchan->desc_list);
1327
1328         /*
1329          * See if we already have a physical channel allocated,
1330          * else this is the time to try to get one.
1331          */
1332         ret = prep_phy_channel(plchan, txd);
1333         if (ret) {
1334                 /*
1335                  * No physical channel available, we will
1336                  * stack up the memcpy channels until there is a channel
1337                  * available to handle it whereas slave transfers may
1338                  * have been denied due to platform channel muxing restrictions
1339                  * and since there is no guarantee that this will ever be
1340                  * resolved, and since the signal must be acquired AFTER
1341                  * acquiring the physical channel, we will let them be NACK:ed
1342                  * with -EBUSY here. The drivers can alway retry the prep()
1343                  * call if they are eager on doing this using DMA.
1344                  */
1345                 if (plchan->slave) {
1346                         pl08x_free_txd_list(pl08x, plchan);
1347                         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1348                         return -EBUSY;
1349                 }
1350                 /* Do this memcpy whenever there is a channel ready */
1351                 plchan->state = PL08X_CHAN_WAITING;
1352                 plchan->waiting = txd;
1353         } else
1354                 /*
1355                  * Else we're all set, paused and ready to roll,
1356                  * status will switch to PL08X_CHAN_RUNNING when
1357                  * we call issue_pending(). If there is something
1358                  * running on the channel already we don't change
1359                  * its state.
1360                  */
1361                 if (plchan->state == PL08X_CHAN_IDLE)
1362                         plchan->state = PL08X_CHAN_PAUSED;
1363
1364         /*
1365          * Notice that we leave plchan->lock locked on purpose:
1366          * it will be unlocked in the subsequent tx_submit()
1367          * call. This is a consequence of the current API.
1368          */
1369
1370         return 0;
1371 }
1372
1373 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1374 {
1375         struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1376
1377         if (txd) {
1378                 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1379                 txd->tx.tx_submit = pl08x_tx_submit;
1380                 INIT_LIST_HEAD(&txd->node);
1381         }
1382         return txd;
1383 }
1384
1385 /*
1386  * Initialize a descriptor to be used by memcpy submit
1387  */
1388 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1389                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1390                 size_t len, unsigned long flags)
1391 {
1392         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1393         struct pl08x_driver_data *pl08x = plchan->host;
1394         struct pl08x_txd *txd;
1395         int ret;
1396
1397         txd = pl08x_get_txd(plchan);
1398         if (!txd) {
1399                 dev_err(&pl08x->adev->dev,
1400                         "%s no memory for descriptor\n", __func__);
1401                 return NULL;
1402         }
1403
1404         txd->direction = DMA_NONE;
1405         txd->srcbus.addr = src;
1406         txd->dstbus.addr = dest;
1407
1408         /* Set platform data for m2m */
1409         txd->cd = &pl08x->pd->memcpy_channel;
1410         /* Both to be incremented or the code will break */
1411         txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1412         txd->len = len;
1413
1414         ret = pl08x_prep_channel_resources(plchan, txd);
1415         if (ret)
1416                 return NULL;
1417         /*
1418          * NB: the channel lock is held at this point so tx_submit()
1419          * must be called in direct succession.
1420          */
1421
1422         return &txd->tx;
1423 }
1424
1425 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1426                 struct dma_chan *chan, struct scatterlist *sgl,
1427                 unsigned int sg_len, enum dma_data_direction direction,
1428                 unsigned long flags)
1429 {
1430         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1431         struct pl08x_driver_data *pl08x = plchan->host;
1432         struct pl08x_txd *txd;
1433         int ret;
1434
1435         /*
1436          * Current implementation ASSUMES only one sg
1437          */
1438         if (sg_len != 1) {
1439                 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1440                         __func__);
1441                 BUG();
1442         }
1443
1444         dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1445                 __func__, sgl->length, plchan->name);
1446
1447         txd = pl08x_get_txd(plchan);
1448         if (!txd) {
1449                 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1450                 return NULL;
1451         }
1452
1453         if (direction != plchan->runtime_direction)
1454                 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1455                         "the direction configured for the PrimeCell\n",
1456                         __func__);
1457
1458         /*
1459          * Set up addresses, the PrimeCell configured address
1460          * will take precedence since this may configure the
1461          * channel target address dynamically at runtime.
1462          */
1463         txd->direction = direction;
1464         if (direction == DMA_TO_DEVICE) {
1465                 txd->srcbus.addr = sgl->dma_address;
1466                 if (plchan->runtime_addr)
1467                         txd->dstbus.addr = plchan->runtime_addr;
1468                 else
1469                         txd->dstbus.addr = plchan->cd->addr;
1470         } else if (direction == DMA_FROM_DEVICE) {
1471                 if (plchan->runtime_addr)
1472                         txd->srcbus.addr = plchan->runtime_addr;
1473                 else
1474                         txd->srcbus.addr = plchan->cd->addr;
1475                 txd->dstbus.addr = sgl->dma_address;
1476         } else {
1477                 dev_err(&pl08x->adev->dev,
1478                         "%s direction unsupported\n", __func__);
1479                 return NULL;
1480         }
1481         txd->cd = plchan->cd;
1482         txd->len = sgl->length;
1483
1484         ret = pl08x_prep_channel_resources(plchan, txd);
1485         if (ret)
1486                 return NULL;
1487         /*
1488          * NB: the channel lock is held at this point so tx_submit()
1489          * must be called in direct succession.
1490          */
1491
1492         return &txd->tx;
1493 }
1494
1495 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1496                          unsigned long arg)
1497 {
1498         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1499         struct pl08x_driver_data *pl08x = plchan->host;
1500         unsigned long flags;
1501         int ret = 0;
1502
1503         /* Controls applicable to inactive channels */
1504         if (cmd == DMA_SLAVE_CONFIG) {
1505                 dma_set_runtime_config(chan,
1506                                        (struct dma_slave_config *)
1507                                        arg);
1508                 return 0;
1509         }
1510
1511         /*
1512          * Anything succeeds on channels with no physical allocation and
1513          * no queued transfers.
1514          */
1515         spin_lock_irqsave(&plchan->lock, flags);
1516         if (!plchan->phychan && !plchan->at) {
1517                 spin_unlock_irqrestore(&plchan->lock, flags);
1518                 return 0;
1519         }
1520
1521         switch (cmd) {
1522         case DMA_TERMINATE_ALL:
1523                 plchan->state = PL08X_CHAN_IDLE;
1524
1525                 if (plchan->phychan) {
1526                         pl08x_stop_phy_chan(plchan->phychan);
1527
1528                         /*
1529                          * Mark physical channel as free and free any slave
1530                          * signal
1531                          */
1532                         release_phy_channel(plchan);
1533                 }
1534                 /* Dequeue jobs and free LLIs */
1535                 if (plchan->at) {
1536                         pl08x_free_txd(pl08x, plchan->at);
1537                         plchan->at = NULL;
1538                 }
1539                 /* Dequeue jobs not yet fired as well */
1540                 pl08x_free_txd_list(pl08x, plchan);
1541                 break;
1542         case DMA_PAUSE:
1543                 pl08x_pause_phy_chan(plchan->phychan);
1544                 plchan->state = PL08X_CHAN_PAUSED;
1545                 break;
1546         case DMA_RESUME:
1547                 pl08x_resume_phy_chan(plchan->phychan);
1548                 plchan->state = PL08X_CHAN_RUNNING;
1549                 break;
1550         default:
1551                 /* Unknown command */
1552                 ret = -ENXIO;
1553                 break;
1554         }
1555
1556         spin_unlock_irqrestore(&plchan->lock, flags);
1557
1558         return ret;
1559 }
1560
1561 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1562 {
1563         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1564         char *name = chan_id;
1565
1566         /* Check that the channel is not taken! */
1567         if (!strcmp(plchan->name, name))
1568                 return true;
1569
1570         return false;
1571 }
1572
1573 /*
1574  * Just check that the device is there and active
1575  * TODO: turn this bit on/off depending on the number of
1576  * physical channels actually used, if it is zero... well
1577  * shut it off. That will save some power. Cut the clock
1578  * at the same time.
1579  */
1580 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1581 {
1582         u32 val;
1583
1584         val = readl(pl08x->base + PL080_CONFIG);
1585         val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1586         /* We implicitly clear bit 1 and that means little-endian mode */
1587         val |= PL080_CONFIG_ENABLE;
1588         writel(val, pl08x->base + PL080_CONFIG);
1589 }
1590
1591 static void pl08x_tasklet(unsigned long data)
1592 {
1593         struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1594         struct pl08x_driver_data *pl08x = plchan->host;
1595         unsigned long flags;
1596
1597         spin_lock_irqsave(&plchan->lock, flags);
1598
1599         if (plchan->at) {
1600                 dma_async_tx_callback callback =
1601                         plchan->at->tx.callback;
1602                 void *callback_param =
1603                         plchan->at->tx.callback_param;
1604
1605                 /*
1606                  * Update last completed
1607                  */
1608                 plchan->lc = plchan->at->tx.cookie;
1609
1610                 /*
1611                  * Callback to signal completion
1612                  */
1613                 if (callback)
1614                         callback(callback_param);
1615
1616                 /*
1617                  * Free the descriptor
1618                  */
1619                 pl08x_free_txd(pl08x, plchan->at);
1620                 plchan->at = NULL;
1621         }
1622         /*
1623          * If a new descriptor is queued, set it up
1624          * plchan->at is NULL here
1625          */
1626         if (!list_empty(&plchan->desc_list)) {
1627                 struct pl08x_txd *next;
1628
1629                 next = list_first_entry(&plchan->desc_list,
1630                                         struct pl08x_txd,
1631                                         node);
1632                 list_del(&next->node);
1633                 plchan->at = next;
1634                 /* Configure the physical channel for the next txd */
1635                 pl08x_config_phychan_for_txd(plchan);
1636                 pl08x_set_cregs(pl08x, plchan->phychan);
1637                 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1638         } else {
1639                 struct pl08x_dma_chan *waiting = NULL;
1640
1641                 /*
1642                  * No more jobs, so free up the physical channel
1643                  * Free any allocated signal on slave transfers too
1644                  */
1645                 release_phy_channel(plchan);
1646                 plchan->state = PL08X_CHAN_IDLE;
1647
1648                 /*
1649                  * And NOW before anyone else can grab that free:d
1650                  * up physical channel, see if there is some memcpy
1651                  * pending that seriously needs to start because of
1652                  * being stacked up while we were choking the
1653                  * physical channels with data.
1654                  */
1655                 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1656                                     chan.device_node) {
1657                   if (waiting->state == PL08X_CHAN_WAITING &&
1658                             waiting->waiting != NULL) {
1659                                 int ret;
1660
1661                                 /* This should REALLY not fail now */
1662                                 ret = prep_phy_channel(waiting,
1663                                                        waiting->waiting);
1664                                 BUG_ON(ret);
1665                                 waiting->state = PL08X_CHAN_RUNNING;
1666                                 waiting->waiting = NULL;
1667                                 pl08x_issue_pending(&waiting->chan);
1668                                 break;
1669                         }
1670                 }
1671         }
1672
1673         spin_unlock_irqrestore(&plchan->lock, flags);
1674 }
1675
1676 static irqreturn_t pl08x_irq(int irq, void *dev)
1677 {
1678         struct pl08x_driver_data *pl08x = dev;
1679         u32 mask = 0;
1680         u32 val;
1681         int i;
1682
1683         val = readl(pl08x->base + PL080_ERR_STATUS);
1684         if (val) {
1685                 /*
1686                  * An error interrupt (on one or more channels)
1687                  */
1688                 dev_err(&pl08x->adev->dev,
1689                         "%s error interrupt, register value 0x%08x\n",
1690                                 __func__, val);
1691                 /*
1692                  * Simply clear ALL PL08X error interrupts,
1693                  * regardless of channel and cause
1694                  * FIXME: should be 0x00000003 on PL081 really.
1695                  */
1696                 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1697         }
1698         val = readl(pl08x->base + PL080_INT_STATUS);
1699         for (i = 0; i < pl08x->vd->channels; i++) {
1700                 if ((1 << i) & val) {
1701                         /* Locate physical channel */
1702                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1703                         struct pl08x_dma_chan *plchan = phychan->serving;
1704
1705                         /* Schedule tasklet on this channel */
1706                         tasklet_schedule(&plchan->tasklet);
1707
1708                         mask |= (1 << i);
1709                 }
1710         }
1711         /*
1712          * Clear only the terminal interrupts on channels we processed
1713          */
1714         writel(mask, pl08x->base + PL080_TC_CLEAR);
1715
1716         return mask ? IRQ_HANDLED : IRQ_NONE;
1717 }
1718
1719 /*
1720  * Initialise the DMAC memcpy/slave channels.
1721  * Make a local wrapper to hold required data
1722  */
1723 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1724                                            struct dma_device *dmadev,
1725                                            unsigned int channels,
1726                                            bool slave)
1727 {
1728         struct pl08x_dma_chan *chan;
1729         int i;
1730
1731         INIT_LIST_HEAD(&dmadev->channels);
1732         /*
1733          * Register as many many memcpy as we have physical channels,
1734          * we won't always be able to use all but the code will have
1735          * to cope with that situation.
1736          */
1737         for (i = 0; i < channels; i++) {
1738                 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1739                 if (!chan) {
1740                         dev_err(&pl08x->adev->dev,
1741                                 "%s no memory for channel\n", __func__);
1742                         return -ENOMEM;
1743                 }
1744
1745                 chan->host = pl08x;
1746                 chan->state = PL08X_CHAN_IDLE;
1747
1748                 if (slave) {
1749                         chan->slave = true;
1750                         chan->name = pl08x->pd->slave_channels[i].bus_id;
1751                         chan->cd = &pl08x->pd->slave_channels[i];
1752                 } else {
1753                         chan->cd = &pl08x->pd->memcpy_channel;
1754                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1755                         if (!chan->name) {
1756                                 kfree(chan);
1757                                 return -ENOMEM;
1758                         }
1759                 }
1760                 if (chan->cd->circular_buffer) {
1761                         dev_err(&pl08x->adev->dev,
1762                                 "channel %s: circular buffers not supported\n",
1763                                 chan->name);
1764                         kfree(chan);
1765                         continue;
1766                 }
1767                 dev_info(&pl08x->adev->dev,
1768                          "initialize virtual channel \"%s\"\n",
1769                          chan->name);
1770
1771                 chan->chan.device = dmadev;
1772                 chan->chan.cookie = 0;
1773                 chan->lc = 0;
1774
1775                 spin_lock_init(&chan->lock);
1776                 INIT_LIST_HEAD(&chan->desc_list);
1777                 tasklet_init(&chan->tasklet, pl08x_tasklet,
1778                              (unsigned long) chan);
1779
1780                 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1781         }
1782         dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1783                  i, slave ? "slave" : "memcpy");
1784         return i;
1785 }
1786
1787 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1788 {
1789         struct pl08x_dma_chan *chan = NULL;
1790         struct pl08x_dma_chan *next;
1791
1792         list_for_each_entry_safe(chan,
1793                                  next, &dmadev->channels, chan.device_node) {
1794                 list_del(&chan->chan.device_node);
1795                 kfree(chan);
1796         }
1797 }
1798
1799 #ifdef CONFIG_DEBUG_FS
1800 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1801 {
1802         switch (state) {
1803         case PL08X_CHAN_IDLE:
1804                 return "idle";
1805         case PL08X_CHAN_RUNNING:
1806                 return "running";
1807         case PL08X_CHAN_PAUSED:
1808                 return "paused";
1809         case PL08X_CHAN_WAITING:
1810                 return "waiting";
1811         default:
1812                 break;
1813         }
1814         return "UNKNOWN STATE";
1815 }
1816
1817 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1818 {
1819         struct pl08x_driver_data *pl08x = s->private;
1820         struct pl08x_dma_chan *chan;
1821         struct pl08x_phy_chan *ch;
1822         unsigned long flags;
1823         int i;
1824
1825         seq_printf(s, "PL08x physical channels:\n");
1826         seq_printf(s, "CHANNEL:\tUSER:\n");
1827         seq_printf(s, "--------\t-----\n");
1828         for (i = 0; i < pl08x->vd->channels; i++) {
1829                 struct pl08x_dma_chan *virt_chan;
1830
1831                 ch = &pl08x->phy_chans[i];
1832
1833                 spin_lock_irqsave(&ch->lock, flags);
1834                 virt_chan = ch->serving;
1835
1836                 seq_printf(s, "%d\t\t%s\n",
1837                            ch->id, virt_chan ? virt_chan->name : "(none)");
1838
1839                 spin_unlock_irqrestore(&ch->lock, flags);
1840         }
1841
1842         seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1843         seq_printf(s, "CHANNEL:\tSTATE:\n");
1844         seq_printf(s, "--------\t------\n");
1845         list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1846                 seq_printf(s, "%s\t\t%s\n", chan->name,
1847                            pl08x_state_str(chan->state));
1848         }
1849
1850         seq_printf(s, "\nPL08x virtual slave channels:\n");
1851         seq_printf(s, "CHANNEL:\tSTATE:\n");
1852         seq_printf(s, "--------\t------\n");
1853         list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1854                 seq_printf(s, "%s\t\t%s\n", chan->name,
1855                            pl08x_state_str(chan->state));
1856         }
1857
1858         return 0;
1859 }
1860
1861 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1862 {
1863         return single_open(file, pl08x_debugfs_show, inode->i_private);
1864 }
1865
1866 static const struct file_operations pl08x_debugfs_operations = {
1867         .open           = pl08x_debugfs_open,
1868         .read           = seq_read,
1869         .llseek         = seq_lseek,
1870         .release        = single_release,
1871 };
1872
1873 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1874 {
1875         /* Expose a simple debugfs interface to view all clocks */
1876         (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1877                                    NULL, pl08x,
1878                                    &pl08x_debugfs_operations);
1879 }
1880
1881 #else
1882 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1883 {
1884 }
1885 #endif
1886
1887 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1888 {
1889         struct pl08x_driver_data *pl08x;
1890         const struct vendor_data *vd = id->data;
1891         int ret = 0;
1892         int i;
1893
1894         ret = amba_request_regions(adev, NULL);
1895         if (ret)
1896                 return ret;
1897
1898         /* Create the driver state holder */
1899         pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1900         if (!pl08x) {
1901                 ret = -ENOMEM;
1902                 goto out_no_pl08x;
1903         }
1904
1905         /* Initialize memcpy engine */
1906         dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1907         pl08x->memcpy.dev = &adev->dev;
1908         pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1909         pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1910         pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1911         pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1912         pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1913         pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1914         pl08x->memcpy.device_control = pl08x_control;
1915
1916         /* Initialize slave engine */
1917         dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1918         pl08x->slave.dev = &adev->dev;
1919         pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1920         pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1921         pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1922         pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1923         pl08x->slave.device_issue_pending = pl08x_issue_pending;
1924         pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1925         pl08x->slave.device_control = pl08x_control;
1926
1927         /* Get the platform data */
1928         pl08x->pd = dev_get_platdata(&adev->dev);
1929         if (!pl08x->pd) {
1930                 dev_err(&adev->dev, "no platform data supplied\n");
1931                 goto out_no_platdata;
1932         }
1933
1934         /* Assign useful pointers to the driver state */
1935         pl08x->adev = adev;
1936         pl08x->vd = vd;
1937
1938         /* A DMA memory pool for LLIs, align on 1-byte boundary */
1939         pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1940                         PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1941         if (!pl08x->pool) {
1942                 ret = -ENOMEM;
1943                 goto out_no_lli_pool;
1944         }
1945
1946         spin_lock_init(&pl08x->lock);
1947
1948         pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1949         if (!pl08x->base) {
1950                 ret = -ENOMEM;
1951                 goto out_no_ioremap;
1952         }
1953
1954         /* Turn on the PL08x */
1955         pl08x_ensure_on(pl08x);
1956
1957         /*
1958          * Attach the interrupt handler
1959          */
1960         writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1961         writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1962
1963         ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1964                           DRIVER_NAME, pl08x);
1965         if (ret) {
1966                 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1967                         __func__, adev->irq[0]);
1968                 goto out_no_irq;
1969         }
1970
1971         /* Initialize physical channels */
1972         pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1973                         GFP_KERNEL);
1974         if (!pl08x->phy_chans) {
1975                 dev_err(&adev->dev, "%s failed to allocate "
1976                         "physical channel holders\n",
1977                         __func__);
1978                 goto out_no_phychans;
1979         }
1980
1981         for (i = 0; i < vd->channels; i++) {
1982                 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1983
1984                 ch->id = i;
1985                 ch->base = pl08x->base + PL080_Cx_BASE(i);
1986                 spin_lock_init(&ch->lock);
1987                 ch->serving = NULL;
1988                 ch->signal = -1;
1989                 dev_info(&adev->dev,
1990                          "physical channel %d is %s\n", i,
1991                          pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1992         }
1993
1994         /* Register as many memcpy channels as there are physical channels */
1995         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1996                                               pl08x->vd->channels, false);
1997         if (ret <= 0) {
1998                 dev_warn(&pl08x->adev->dev,
1999                          "%s failed to enumerate memcpy channels - %d\n",
2000                          __func__, ret);
2001                 goto out_no_memcpy;
2002         }
2003         pl08x->memcpy.chancnt = ret;
2004
2005         /* Register slave channels */
2006         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2007                                               pl08x->pd->num_slave_channels,
2008                                               true);
2009         if (ret <= 0) {
2010                 dev_warn(&pl08x->adev->dev,
2011                         "%s failed to enumerate slave channels - %d\n",
2012                                 __func__, ret);
2013                 goto out_no_slave;
2014         }
2015         pl08x->slave.chancnt = ret;
2016
2017         ret = dma_async_device_register(&pl08x->memcpy);
2018         if (ret) {
2019                 dev_warn(&pl08x->adev->dev,
2020                         "%s failed to register memcpy as an async device - %d\n",
2021                         __func__, ret);
2022                 goto out_no_memcpy_reg;
2023         }
2024
2025         ret = dma_async_device_register(&pl08x->slave);
2026         if (ret) {
2027                 dev_warn(&pl08x->adev->dev,
2028                         "%s failed to register slave as an async device - %d\n",
2029                         __func__, ret);
2030                 goto out_no_slave_reg;
2031         }
2032
2033         amba_set_drvdata(adev, pl08x);
2034         init_pl08x_debugfs(pl08x);
2035         dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2036                  amba_part(adev), amba_rev(adev),
2037                  (unsigned long long)adev->res.start, adev->irq[0]);
2038         return 0;
2039
2040 out_no_slave_reg:
2041         dma_async_device_unregister(&pl08x->memcpy);
2042 out_no_memcpy_reg:
2043         pl08x_free_virtual_channels(&pl08x->slave);
2044 out_no_slave:
2045         pl08x_free_virtual_channels(&pl08x->memcpy);
2046 out_no_memcpy:
2047         kfree(pl08x->phy_chans);
2048 out_no_phychans:
2049         free_irq(adev->irq[0], pl08x);
2050 out_no_irq:
2051         iounmap(pl08x->base);
2052 out_no_ioremap:
2053         dma_pool_destroy(pl08x->pool);
2054 out_no_lli_pool:
2055 out_no_platdata:
2056         kfree(pl08x);
2057 out_no_pl08x:
2058         amba_release_regions(adev);
2059         return ret;
2060 }
2061
2062 /* PL080 has 8 channels and the PL080 have just 2 */
2063 static struct vendor_data vendor_pl080 = {
2064         .channels = 8,
2065         .dualmaster = true,
2066 };
2067
2068 static struct vendor_data vendor_pl081 = {
2069         .channels = 2,
2070         .dualmaster = false,
2071 };
2072
2073 static struct amba_id pl08x_ids[] = {
2074         /* PL080 */
2075         {
2076                 .id     = 0x00041080,
2077                 .mask   = 0x000fffff,
2078                 .data   = &vendor_pl080,
2079         },
2080         /* PL081 */
2081         {
2082                 .id     = 0x00041081,
2083                 .mask   = 0x000fffff,
2084                 .data   = &vendor_pl081,
2085         },
2086         /* Nomadik 8815 PL080 variant */
2087         {
2088                 .id     = 0x00280880,
2089                 .mask   = 0x00ffffff,
2090                 .data   = &vendor_pl080,
2091         },
2092         { 0, 0 },
2093 };
2094
2095 static struct amba_driver pl08x_amba_driver = {
2096         .drv.name       = DRIVER_NAME,
2097         .id_table       = pl08x_ids,
2098         .probe          = pl08x_probe,
2099 };
2100
2101 static int __init pl08x_init(void)
2102 {
2103         int retval;
2104         retval = amba_driver_register(&pl08x_amba_driver);
2105         if (retval)
2106                 printk(KERN_WARNING DRIVER_NAME
2107                        "failed to register as an AMBA device (%d)\n",
2108                        retval);
2109         return retval;
2110 }
2111 subsys_initcall(pl08x_init);