2 * Freescale i.MX28 APBH DMA driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/list.h>
17 #include <asm/errno.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/imx-common/dma.h>
23 #include <asm/imx-common/regs-apbh.h>
25 static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
26 static struct mxs_apbh_regs *apbh_regs = (struct mxs_apbh_regs *)MXS_APBH_BASE;
29 * Test is the DMA channel is valid channel
31 int mxs_dma_validate_chan(int channel)
33 struct mxs_dma_chan *pchan;
35 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) {
36 printf("Invalid DMA channel %d\n", channel);
40 pchan = mxs_dma_channels + channel;
41 if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) {
42 printf("DMA channel %d not allocated\n", channel);
50 * Return the address of the command within a descriptor.
52 static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
54 return desc->address + offsetof(struct mxs_dma_desc, cmd);
58 * Read a DMA channel's hardware semaphore.
60 * As used by the MXS platform's DMA software, the DMA channel's hardware
61 * semaphore reflects the number of DMA commands the hardware will process, but
62 * has not yet finished. This is a volatile value read directly from hardware,
63 * so it must be be viewed as immediately stale.
65 * If the channel is not marked busy, or has finished processing all its
66 * commands, this value should be zero.
68 * See mxs_dma_append() for details on how DMA command blocks must be configured
69 * to maintain the expected behavior of the semaphore's value.
71 static int mxs_dma_read_semaphore(int channel)
76 ret = mxs_dma_validate_chan(channel);
80 tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema);
82 tmp &= APBH_CHn_SEMA_PHORE_MASK;
83 tmp >>= APBH_CHn_SEMA_PHORE_OFFSET;
88 #ifndef CONFIG_SYS_DCACHE_OFF
89 static void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
94 addr = (uint32_t)desc;
95 size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
97 flush_dcache_range(addr, addr + size);
100 static inline void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
106 * Enable a DMA channel.
108 * If the given channel has any DMA descriptors on its active list, this
109 * function causes the DMA hardware to begin processing them.
111 * This function marks the DMA channel as "busy," whether or not there are any
112 * descriptors to process.
114 static int mxs_dma_enable(int channel)
117 struct mxs_dma_chan *pchan;
118 struct mxs_dma_desc *pdesc;
121 ret = mxs_dma_validate_chan(channel);
125 pchan = mxs_dma_channels + channel;
127 if (pchan->pending_num == 0) {
128 pchan->flags |= MXS_DMA_FLAGS_BUSY;
132 pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
136 if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
137 if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
140 sem = mxs_dma_read_semaphore(channel);
145 pdesc = list_entry(pdesc->node.next,
146 struct mxs_dma_desc, node);
147 writel(mxs_dma_cmd_address(pdesc),
148 &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
150 writel(pchan->pending_num,
151 &apbh_regs->ch[channel].hw_apbh_ch_sema);
152 pchan->active_num += pchan->pending_num;
153 pchan->pending_num = 0;
155 pchan->active_num += pchan->pending_num;
156 pchan->pending_num = 0;
157 writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
158 &apbh_regs->hw_apbh_ctrl0_clr);
159 writel(mxs_dma_cmd_address(pdesc),
160 &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
161 writel(pchan->active_num,
162 &apbh_regs->ch[channel].hw_apbh_ch_sema);
165 pchan->flags |= MXS_DMA_FLAGS_BUSY;
170 * Disable a DMA channel.
172 * This function shuts down a DMA channel and marks it as "not busy." Any
173 * descriptors on the active list are immediately moved to the head of the
174 * "done" list, whether or not they have actually been processed by the
175 * hardware. The "ready" flags of these descriptors are NOT cleared, so they
176 * still appear to be active.
178 * This function immediately shuts down a DMA channel's hardware, aborting any
179 * I/O that may be in progress, potentially leaving I/O hardware in an undefined
180 * state. It is unwise to call this function if there is ANY chance the hardware
181 * is still processing a command.
183 static int mxs_dma_disable(int channel)
185 struct mxs_dma_chan *pchan;
188 ret = mxs_dma_validate_chan(channel);
192 pchan = mxs_dma_channels + channel;
194 if ((pchan->flags & MXS_DMA_FLAGS_BUSY)) {
195 printf("%s: DMA channel %d busy\n", __func__, channel);
198 writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
199 &apbh_regs->hw_apbh_ctrl0_set);
200 pchan->active_num = 0;
201 pchan->pending_num = 0;
202 list_splice_init(&pchan->active, &pchan->done);
208 * Resets the DMA channel hardware.
210 static int mxs_dma_reset(int channel)
213 #if defined(CONFIG_SOC_MX23)
214 uint32_t *setreg = &apbh_regs->hw_apbh_ctrl0_set;
215 uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
216 #elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_SOC_MX6))
217 uint32_t *setreg = &apbh_regs->hw_apbh_channel_ctrl_set;
218 uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
221 ret = mxs_dma_validate_chan(channel);
225 writel(1 << (channel + offset), setreg);
231 * Enable or disable DMA interrupt.
233 * This function enables the given DMA channel to interrupt the CPU.
235 static int mxs_dma_enable_irq(int channel, int enable)
239 ret = mxs_dma_validate_chan(channel);
244 writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
245 &apbh_regs->hw_apbh_ctrl1_set);
247 writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
248 &apbh_regs->hw_apbh_ctrl1_clr);
254 * Clear DMA interrupt.
256 * The software that is using the DMA channel must register to receive its
257 * interrupts and, when they arrive, must call this function to clear them.
259 static int mxs_dma_ack_irq(int channel)
263 ret = mxs_dma_validate_chan(channel);
267 writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr);
268 writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr);
274 * Request to reserve a DMA channel
276 static int mxs_dma_request(int channel)
278 struct mxs_dma_chan *pchan;
280 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
283 pchan = mxs_dma_channels + channel;
284 if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID)
287 if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED)
290 pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;
291 pchan->active_num = 0;
292 pchan->pending_num = 0;
293 pchan->timeout = 10000000;
295 INIT_LIST_HEAD(&pchan->active);
296 INIT_LIST_HEAD(&pchan->done);
302 * Release a DMA channel.
304 * This function releases a DMA channel from its current owner.
306 * The channel will NOT be released if it's marked "busy" (see
309 int mxs_dma_release(int channel)
311 struct mxs_dma_chan *pchan;
314 ret = mxs_dma_validate_chan(channel);
318 pchan = mxs_dma_channels + channel;
320 if (pchan->flags & MXS_DMA_FLAGS_BUSY)
324 pchan->active_num = 0;
325 pchan->pending_num = 0;
326 pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;
332 * Set the timeout for any DMA operation started with mxs_dma_go()
333 * The timeout value given is in milliseconds
335 int mxs_dma_set_timeout(int channel, unsigned long timeout)
338 struct mxs_dma_chan *pchan;
340 ret = mxs_dma_validate_chan(channel);
344 pchan = &mxs_dma_channels[channel];
346 if (pchan->flags & MXS_DMA_FLAGS_BUSY)
349 if (timeout > ~0UL / 1000)
352 pchan->timeout = timeout;
356 unsigned long mxs_dma_get_timeout(int channel)
359 struct mxs_dma_chan *pchan;
361 ret = mxs_dma_validate_chan(channel);
365 pchan = &mxs_dma_channels[channel];
366 return pchan->timeout;
370 * Allocate DMA descriptor
372 struct mxs_dma_desc *mxs_dma_desc_alloc(void)
374 struct mxs_dma_desc *pdesc;
377 size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
378 pdesc = memalign(MXS_DMA_ALIGNMENT, size);
383 memset(pdesc, 0, sizeof(*pdesc));
384 pdesc->address = (dma_addr_t)pdesc;
390 * Free DMA descriptor
392 void mxs_dma_desc_free(struct mxs_dma_desc *pdesc)
401 * Add a DMA descriptor to a channel.
403 * If the descriptor list for this channel is not empty, this function sets the
404 * CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so
405 * it will chain to the new descriptor's command.
407 * Then, this function marks the new descriptor as "ready," adds it to the end
408 * of the active descriptor list, and increments the count of pending
411 * The MXS platform DMA software imposes some rules on DMA commands to maintain
412 * important invariants. These rules are NOT checked, but they must be carefully
413 * applied by software that uses MXS DMA channels.
416 * The DMA channel's hardware semaphore must reflect the number of DMA
417 * commands the hardware will process, but has not yet finished.
420 * A DMA channel begins processing commands when its hardware semaphore is
421 * written with a value greater than zero, and it stops processing commands
422 * when the semaphore returns to zero.
424 * When a channel finishes a DMA command, it will decrement its semaphore if
425 * the DECREMENT_SEMAPHORE bit is set in that command's flags bits.
427 * In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set,
428 * unless it suits the purposes of the software. For example, one could
429 * construct a series of five DMA commands, with the DECREMENT_SEMAPHORE
430 * bit set only in the last one. Then, setting the DMA channel's hardware
431 * semaphore to one would cause the entire series of five commands to be
432 * processed. However, this example would violate the invariant given above.
435 * ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA
436 * channel's hardware semaphore will be decremented EVERY time a command is
439 int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)
441 struct mxs_dma_chan *pchan;
442 struct mxs_dma_desc *last;
445 ret = mxs_dma_validate_chan(channel);
449 pchan = mxs_dma_channels + channel;
451 pdesc->cmd.next = mxs_dma_cmd_address(pdesc);
452 pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST;
454 if (!list_empty(&pchan->active)) {
455 last = list_entry(pchan->active.prev, struct mxs_dma_desc,
458 pdesc->flags &= ~MXS_DMA_DESC_FIRST;
459 last->flags &= ~MXS_DMA_DESC_LAST;
461 last->cmd.next = mxs_dma_cmd_address(pdesc);
462 last->cmd.data |= MXS_DMA_DESC_CHAIN;
464 mxs_dma_flush_desc(last);
466 pdesc->flags |= MXS_DMA_DESC_READY;
467 if (pdesc->flags & MXS_DMA_DESC_FIRST)
468 pchan->pending_num++;
469 list_add_tail(&pdesc->node, &pchan->active);
471 mxs_dma_flush_desc(pdesc);
477 * Clean up processed DMA descriptors.
479 * This function removes processed DMA descriptors from the "active" list. Pass
480 * in a non-NULL list head to get the descriptors moved to your list. Pass NULL
481 * to get the descriptors moved to the channel's "done" list. Descriptors on
482 * the "done" list can be retrieved with mxs_dma_get_finished().
484 * This function marks the DMA channel as "not busy" if no unprocessed
485 * descriptors remain on the "active" list.
487 static int mxs_dma_finish(int channel, struct list_head *head)
490 struct mxs_dma_chan *pchan;
491 struct list_head *p, *q;
492 struct mxs_dma_desc *pdesc;
495 ret = mxs_dma_validate_chan(channel);
499 pchan = mxs_dma_channels + channel;
501 sem = mxs_dma_read_semaphore(channel);
505 if (sem == pchan->active_num)
508 list_for_each_safe(p, q, &pchan->active) {
509 if ((pchan->active_num) <= sem)
512 pdesc = list_entry(p, struct mxs_dma_desc, node);
513 pdesc->flags &= ~MXS_DMA_DESC_READY;
516 list_move_tail(p, head);
518 list_move_tail(p, &pchan->done);
520 if (pdesc->flags & MXS_DMA_DESC_LAST)
525 pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
531 * Wait for DMA channel to complete
533 static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
537 ret = mxs_dma_validate_chan(chan);
541 if (mxs_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
542 1 << chan, timeout)) {
551 * Execute the DMA channel
553 int mxs_dma_go(int chan)
556 struct mxs_dma_chan *pchan;
557 LIST_HEAD(tmp_desc_list);
559 ret = mxs_dma_validate_chan(chan);
563 pchan = &mxs_dma_channels[chan];
565 mxs_dma_enable_irq(chan, 1);
566 ret = mxs_dma_enable(chan);
568 mxs_dma_enable_irq(chan, 0);
572 /* Wait for DMA to finish. */
573 ret = mxs_dma_wait_complete(pchan->timeout * 1000, chan);
575 /* Clear out the descriptors we just ran. */
576 mxs_dma_finish(chan, &tmp_desc_list);
578 /* Shut the DMA channel down. */
579 mxs_dma_ack_irq(chan);
581 mxs_dma_enable_irq(chan, 0);
582 mxs_dma_disable(chan);
588 * Execute a continuously running circular DMA descriptor.
589 * NOTE: This is not intended for general use, but rather
590 * for the LCD driver in Smart-LCD mode. It allows
591 * continuous triggering of the RUN bit there.
593 void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc)
595 struct mxs_apbh_regs *apbh_regs =
596 (struct mxs_apbh_regs *)MXS_APBH_BASE;
598 mxs_dma_flush_desc(pdesc);
600 mxs_dma_enable_irq(chan, 1);
602 writel(mxs_dma_cmd_address(pdesc),
603 &apbh_regs->ch[chan].hw_apbh_ch_nxtcmdar);
604 writel(1, &apbh_regs->ch[chan].hw_apbh_ch_sema);
605 writel(1 << (chan + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
606 &apbh_regs->hw_apbh_ctrl0_clr);
610 * Initialize the DMA hardware
612 void mxs_dma_init(void)
614 mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
616 #ifdef CONFIG_APBH_DMA_BURST8
617 writel(APBH_CTRL0_AHB_BURST8_EN,
618 &apbh_regs->hw_apbh_ctrl0_set);
620 writel(APBH_CTRL0_AHB_BURST8_EN,
621 &apbh_regs->hw_apbh_ctrl0_clr);
624 #ifdef CONFIG_APBH_DMA_BURST
625 writel(APBH_CTRL0_APB_BURST_EN,
626 &apbh_regs->hw_apbh_ctrl0_set);
628 writel(APBH_CTRL0_APB_BURST_EN,
629 &apbh_regs->hw_apbh_ctrl0_clr);
633 int mxs_dma_init_channel(int channel)
635 struct mxs_dma_chan *pchan;
638 pchan = mxs_dma_channels + channel;
639 pchan->flags = MXS_DMA_FLAGS_VALID;
641 ret = mxs_dma_request(channel);
644 printf("MXS DMA: Can't acquire DMA channel %i\n",
649 mxs_dma_reset(channel);
650 mxs_dma_ack_irq(channel);