2 * driver/dma/coh901318.c
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 * DMA driver for COH 901 318
7 * Author: Per Friden <per.friden@stericsson.com>
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h> /* printk() */
13 #include <linux/fs.h> /* everything... */
14 #include <linux/slab.h> /* kmalloc() */
15 #include <linux/dmaengine.h>
16 #include <linux/platform_device.h>
17 #include <linux/device.h>
18 #include <linux/irqreturn.h>
19 #include <linux/interrupt.h>
21 #include <linux/uaccess.h>
22 #include <linux/debugfs.h>
23 #include <mach/coh901318.h>
25 #include "coh901318_lli.h"
27 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
30 #define COH_DBG(x) ({ if (1) x; 0; })
32 #define COH_DBG(x) ({ if (0) x; 0; })
35 struct coh901318_desc {
36 struct dma_async_tx_descriptor desc;
37 struct list_head node;
38 struct scatterlist *sg;
40 struct coh901318_lli *lli;
41 enum dma_data_direction dir;
45 struct coh901318_base {
47 void __iomem *virtbase;
48 struct coh901318_pool pool;
50 struct dma_device dma_slave;
51 struct dma_device dma_memcpy;
52 struct coh901318_chan *chans;
53 struct coh901318_platform *platform;
56 struct coh901318_chan {
63 struct work_struct free_work;
66 struct tasklet_struct tasklet;
68 struct list_head active;
69 struct list_head queue;
70 struct list_head free;
72 unsigned long nbr_active_done;
78 struct coh901318_base *base;
81 static void coh901318_list_print(struct coh901318_chan *cohc,
82 struct coh901318_lli *lli)
84 struct coh901318_lli *l = lli;
88 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
89 ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
90 i, l, l->control, l->src_addr, l->dst_addr,
91 l->link_addr, l->virt_link_addr);
93 l = l->virt_link_addr;
97 #ifdef CONFIG_DEBUG_FS
99 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
101 static struct coh901318_base *debugfs_dma_base;
102 static struct dentry *dma_dentry;
104 static int coh901318_debugfs_open(struct inode *inode, struct file *file)
107 file->private_data = inode->i_private;
111 static int coh901318_debugfs_read(struct file *file, char __user *buf,
112 size_t count, loff_t *f_pos)
114 u64 started_channels = debugfs_dma_base->pm.started_channels;
115 int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
122 dev_buf = kmalloc(4*1024, GFP_KERNEL);
127 tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
129 for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
130 if (started_channels & (1 << i))
131 tmp += sprintf(tmp, "channel %d\n", i);
133 tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
134 dev_size = tmp - dev_buf;
136 /* No more to read if offset != 0 */
137 if (*f_pos > dev_size)
140 if (count > dev_size - *f_pos)
141 count = dev_size - *f_pos;
143 if (copy_to_user(buf, dev_buf + *f_pos, count))
156 static const struct file_operations coh901318_debugfs_status_operations = {
157 .owner = THIS_MODULE,
158 .open = coh901318_debugfs_open,
159 .read = coh901318_debugfs_read,
163 static int __init init_coh901318_debugfs(void)
166 dma_dentry = debugfs_create_dir("dma", NULL);
168 (void) debugfs_create_file("status",
171 &coh901318_debugfs_status_operations);
175 static void __exit exit_coh901318_debugfs(void)
177 debugfs_remove_recursive(dma_dentry);
180 module_init(init_coh901318_debugfs);
181 module_exit(exit_coh901318_debugfs);
184 #define COH901318_DEBUGFS_ASSIGN(x, y)
186 #endif /* CONFIG_DEBUG_FS */
188 static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
190 return container_of(chan, struct coh901318_chan, chan);
193 static inline dma_addr_t
194 cohc_dev_addr(struct coh901318_chan *cohc)
196 /* Runtime supplied address will take precedence */
197 if (cohc->runtime_addr)
198 return cohc->runtime_addr;
199 return cohc->base->platform->chan_conf[cohc->id].dev_addr;
202 static inline const struct coh901318_params *
203 cohc_chan_param(struct coh901318_chan *cohc)
205 return &cohc->base->platform->chan_conf[cohc->id].param;
208 static inline const struct coh_dma_channel *
209 cohc_chan_conf(struct coh901318_chan *cohc)
211 return &cohc->base->platform->chan_conf[cohc->id];
214 static void enable_powersave(struct coh901318_chan *cohc)
217 struct powersave *pm = &cohc->base->pm;
219 spin_lock_irqsave(&pm->lock, flags);
221 pm->started_channels &= ~(1ULL << cohc->id);
223 if (!pm->started_channels) {
224 /* DMA no longer intends to access memory */
225 cohc->base->platform->access_memory_state(cohc->base->dev,
229 spin_unlock_irqrestore(&pm->lock, flags);
231 static void disable_powersave(struct coh901318_chan *cohc)
234 struct powersave *pm = &cohc->base->pm;
236 spin_lock_irqsave(&pm->lock, flags);
238 if (!pm->started_channels) {
239 /* DMA intends to access memory */
240 cohc->base->platform->access_memory_state(cohc->base->dev,
244 pm->started_channels |= (1ULL << cohc->id);
246 spin_unlock_irqrestore(&pm->lock, flags);
249 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
251 int channel = cohc->id;
252 void __iomem *virtbase = cohc->base->virtbase;
255 virtbase + COH901318_CX_CTRL +
256 COH901318_CX_CTRL_SPACING * channel);
260 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
262 int channel = cohc->id;
263 void __iomem *virtbase = cohc->base->virtbase;
266 virtbase + COH901318_CX_CFG +
267 COH901318_CX_CFG_SPACING*channel);
272 static int coh901318_start(struct coh901318_chan *cohc)
275 int channel = cohc->id;
276 void __iomem *virtbase = cohc->base->virtbase;
278 disable_powersave(cohc);
280 val = readl(virtbase + COH901318_CX_CFG +
281 COH901318_CX_CFG_SPACING * channel);
284 val |= COH901318_CX_CFG_CH_ENABLE;
285 writel(val, virtbase + COH901318_CX_CFG +
286 COH901318_CX_CFG_SPACING * channel);
291 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
292 struct coh901318_lli *lli)
294 int channel = cohc->id;
295 void __iomem *virtbase = cohc->base->virtbase;
297 BUG_ON(readl(virtbase + COH901318_CX_STAT +
298 COH901318_CX_STAT_SPACING*channel) &
299 COH901318_CX_STAT_ACTIVE);
301 writel(lli->src_addr,
302 virtbase + COH901318_CX_SRC_ADDR +
303 COH901318_CX_SRC_ADDR_SPACING * channel);
305 writel(lli->dst_addr, virtbase +
306 COH901318_CX_DST_ADDR +
307 COH901318_CX_DST_ADDR_SPACING * channel);
309 writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
310 COH901318_CX_LNK_ADDR_SPACING * channel);
312 writel(lli->control, virtbase + COH901318_CX_CTRL +
313 COH901318_CX_CTRL_SPACING * channel);
318 coh901318_assign_cookie(struct coh901318_chan *cohc,
319 struct coh901318_desc *cohd)
321 dma_cookie_t cookie = cohc->chan.cookie;
326 cohc->chan.cookie = cookie;
327 cohd->desc.cookie = cookie;
332 static struct coh901318_desc *
333 coh901318_desc_get(struct coh901318_chan *cohc)
335 struct coh901318_desc *desc;
337 if (list_empty(&cohc->free)) {
338 /* alloc new desc because we're out of used ones
339 * TODO: alloc a pile of descs instead of just one,
340 * avoid many small allocations.
342 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
345 INIT_LIST_HEAD(&desc->node);
346 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
348 /* Reuse an old desc. */
349 desc = list_first_entry(&cohc->free,
350 struct coh901318_desc,
352 list_del(&desc->node);
353 /* Initialize it a bit so it's not insane */
356 desc->desc.callback = NULL;
357 desc->desc.callback_param = NULL;
365 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
367 list_add_tail(&cohd->node, &cohc->free);
370 /* call with irq lock held */
372 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
374 list_add_tail(&desc->node, &cohc->active);
377 static struct coh901318_desc *
378 coh901318_first_active_get(struct coh901318_chan *cohc)
380 struct coh901318_desc *d;
382 if (list_empty(&cohc->active))
385 d = list_first_entry(&cohc->active,
386 struct coh901318_desc,
392 coh901318_desc_remove(struct coh901318_desc *cohd)
394 list_del(&cohd->node);
398 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
400 list_add_tail(&desc->node, &cohc->queue);
403 static struct coh901318_desc *
404 coh901318_first_queued(struct coh901318_chan *cohc)
406 struct coh901318_desc *d;
408 if (list_empty(&cohc->queue))
411 d = list_first_entry(&cohc->queue,
412 struct coh901318_desc,
417 static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
419 struct coh901318_lli *lli = in_lli;
423 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
424 lli = lli->virt_link_addr;
430 * Get the number of bytes left to transfer on this channel,
431 * it is unwise to call this before stopping the channel for
432 * absolute measures, but for a rough guess you can still call
435 static u32 coh901318_get_bytes_left(struct dma_chan *chan)
437 struct coh901318_chan *cohc = to_coh901318_chan(chan);
438 struct coh901318_desc *cohd;
439 struct list_head *pos;
444 spin_lock_irqsave(&cohc->lock, flags);
447 * If there are many queued jobs, we iterate and add the
448 * size of them all. We take a special look on the first
449 * job though, since it is probably active.
451 list_for_each(pos, &cohc->active) {
453 * The first job in the list will be working on the
454 * hardware. The job can be stopped but still active,
455 * so that the transfer counter is somewhere inside
458 cohd = list_entry(pos, struct coh901318_desc, node);
461 struct coh901318_lli *lli;
464 /* Read current transfer count value */
465 left = readl(cohc->base->virtbase +
467 COH901318_CX_CTRL_SPACING * cohc->id) &
468 COH901318_CX_CTRL_TC_VALUE_MASK;
470 /* See if the transfer is linked... */
471 ladd = readl(cohc->base->virtbase +
472 COH901318_CX_LNK_ADDR +
473 COH901318_CX_LNK_ADDR_SPACING *
475 ~COH901318_CX_LNK_LINK_IMMEDIATE;
476 /* Single transaction */
481 * Linked transaction, follow the lli, find the
482 * currently processing lli, and proceed to the next
485 while (lli && lli->link_addr != ladd)
486 lli = lli->virt_link_addr;
489 lli = lli->virt_link_addr;
492 * Follow remaining lli links around to count the total
493 * number of bytes left
495 left += coh901318_get_bytes_in_lli(lli);
497 left += coh901318_get_bytes_in_lli(cohd->lli);
502 /* Also count bytes in the queued jobs */
503 list_for_each(pos, &cohc->queue) {
504 cohd = list_entry(pos, struct coh901318_desc, node);
505 left += coh901318_get_bytes_in_lli(cohd->lli);
508 spin_unlock_irqrestore(&cohc->lock, flags);
514 * Pauses a transfer without losing data. Enables power save.
515 * Use this function in conjunction with coh901318_resume.
517 static void coh901318_pause(struct dma_chan *chan)
521 struct coh901318_chan *cohc = to_coh901318_chan(chan);
522 int channel = cohc->id;
523 void __iomem *virtbase = cohc->base->virtbase;
525 spin_lock_irqsave(&cohc->lock, flags);
527 /* Disable channel in HW */
528 val = readl(virtbase + COH901318_CX_CFG +
529 COH901318_CX_CFG_SPACING * channel);
531 /* Stopping infinit transfer */
532 if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
533 (val & COH901318_CX_CFG_CH_ENABLE))
537 val &= ~COH901318_CX_CFG_CH_ENABLE;
538 /* Enable twice, HW bug work around */
539 writel(val, virtbase + COH901318_CX_CFG +
540 COH901318_CX_CFG_SPACING * channel);
541 writel(val, virtbase + COH901318_CX_CFG +
542 COH901318_CX_CFG_SPACING * channel);
544 /* Spin-wait for it to actually go inactive */
545 while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
546 channel) & COH901318_CX_STAT_ACTIVE)
549 /* Check if we stopped an active job */
550 if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
551 channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
554 enable_powersave(cohc);
556 spin_unlock_irqrestore(&cohc->lock, flags);
559 /* Resumes a transfer that has been stopped via 300_dma_stop(..).
560 Power save is handled.
562 static void coh901318_resume(struct dma_chan *chan)
566 struct coh901318_chan *cohc = to_coh901318_chan(chan);
567 int channel = cohc->id;
569 spin_lock_irqsave(&cohc->lock, flags);
571 disable_powersave(cohc);
574 /* Enable channel in HW */
575 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
576 COH901318_CX_CFG_SPACING * channel);
578 val |= COH901318_CX_CFG_CH_ENABLE;
580 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
581 COH901318_CX_CFG_SPACING*channel);
586 spin_unlock_irqrestore(&cohc->lock, flags);
589 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
591 unsigned int ch_nr = (unsigned int) chan_id;
593 if (ch_nr == to_coh901318_chan(chan)->id)
598 EXPORT_SYMBOL(coh901318_filter_id);
601 * DMA channel allocation
603 static int coh901318_config(struct coh901318_chan *cohc,
604 struct coh901318_params *param)
607 const struct coh901318_params *p;
608 int channel = cohc->id;
609 void __iomem *virtbase = cohc->base->virtbase;
611 spin_lock_irqsave(&cohc->lock, flags);
616 p = &cohc->base->platform->chan_conf[channel].param;
618 /* Clear any pending BE or TC interrupt */
620 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
621 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
623 writel(1 << (channel - 32), virtbase +
624 COH901318_BE_INT_CLEAR2);
625 writel(1 << (channel - 32), virtbase +
626 COH901318_TC_INT_CLEAR2);
629 coh901318_set_conf(cohc, p->config);
630 coh901318_set_ctrl(cohc, p->ctrl_lli_last);
632 spin_unlock_irqrestore(&cohc->lock, flags);
637 /* must lock when calling this function
638 * start queued jobs, if any
639 * TODO: start all queued jobs in one go
641 * Returns descriptor if queued job is started otherwise NULL.
642 * If the queue is empty NULL is returned.
644 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
646 struct coh901318_desc *cohd;
649 * start queued jobs, if any
650 * TODO: transmit all queued jobs in one go
652 cohd = coh901318_first_queued(cohc);
655 /* Remove from queue */
656 coh901318_desc_remove(cohd);
657 /* initiate DMA job */
660 coh901318_desc_submit(cohc, cohd);
662 coh901318_prep_linked_list(cohc, cohd->lli);
664 /* start dma job on this channel */
665 coh901318_start(cohc);
673 * This tasklet is called from the interrupt handler to
674 * handle each descriptor (DMA job) that is sent to a channel.
676 static void dma_tasklet(unsigned long data)
678 struct coh901318_chan *cohc = (struct coh901318_chan *) data;
679 struct coh901318_desc *cohd_fin;
681 dma_async_tx_callback callback;
682 void *callback_param;
684 dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
685 " nbr_active_done %ld\n", __func__,
686 cohc->id, cohc->nbr_active_done);
688 spin_lock_irqsave(&cohc->lock, flags);
690 /* get first active descriptor entry from list */
691 cohd_fin = coh901318_first_active_get(cohc);
693 if (cohd_fin == NULL)
696 /* locate callback to client */
697 callback = cohd_fin->desc.callback;
698 callback_param = cohd_fin->desc.callback_param;
700 /* sign this job as completed on the channel */
701 cohc->completed = cohd_fin->desc.cookie;
703 /* release the lli allocation and remove the descriptor */
704 coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
706 /* return desc to free-list */
707 coh901318_desc_remove(cohd_fin);
708 coh901318_desc_free(cohc, cohd_fin);
710 spin_unlock_irqrestore(&cohc->lock, flags);
712 /* Call the callback when we're done */
714 callback(callback_param);
716 spin_lock_irqsave(&cohc->lock, flags);
719 * If another interrupt fired while the tasklet was scheduling,
720 * we don't get called twice, so we have this number of active
721 * counter that keep track of the number of IRQs expected to
722 * be handled for this channel. If there happen to be more than
723 * one IRQ to be ack:ed, we simply schedule this tasklet again.
725 cohc->nbr_active_done--;
726 if (cohc->nbr_active_done) {
727 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
728 "came in while we were scheduling this tasklet\n");
729 if (cohc_chan_conf(cohc)->priority_high)
730 tasklet_hi_schedule(&cohc->tasklet);
732 tasklet_schedule(&cohc->tasklet);
735 spin_unlock_irqrestore(&cohc->lock, flags);
740 spin_unlock_irqrestore(&cohc->lock, flags);
741 dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
745 /* called from interrupt context */
746 static void dma_tc_handle(struct coh901318_chan *cohc)
749 * If the channel is not allocated, then we shouldn't have
750 * any TC interrupts on it.
752 if (!cohc->allocated) {
753 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
754 "unallocated channel\n");
758 spin_lock(&cohc->lock);
761 * When we reach this point, at least one queue item
762 * should have been moved over from cohc->queue to
763 * cohc->active and run to completion, that is why we're
764 * getting a terminal count interrupt is it not?
765 * If you get this BUG() the most probable cause is that
766 * the individual nodes in the lli chain have IRQ enabled,
767 * so check your platform config for lli chain ctrl.
769 BUG_ON(list_empty(&cohc->active));
771 cohc->nbr_active_done++;
774 * This attempt to take a job from cohc->queue, put it
775 * into cohc->active and start it.
777 if (coh901318_queue_start(cohc) == NULL)
780 spin_unlock(&cohc->lock);
783 * This tasklet will remove items from cohc->active
784 * and thus terminates them.
786 if (cohc_chan_conf(cohc)->priority_high)
787 tasklet_hi_schedule(&cohc->tasklet);
789 tasklet_schedule(&cohc->tasklet);
793 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
799 struct coh901318_base *base = dev_id;
800 struct coh901318_chan *cohc;
801 void __iomem *virtbase = base->virtbase;
803 status1 = readl(virtbase + COH901318_INT_STATUS1);
804 status2 = readl(virtbase + COH901318_INT_STATUS2);
806 if (unlikely(status1 == 0 && status2 == 0)) {
807 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
811 /* TODO: consider handle IRQ in tasklet here to
812 * minimize interrupt latency */
814 /* Check the first 32 DMA channels for IRQ */
816 /* Find first bit set, return as a number. */
817 i = ffs(status1) - 1;
820 cohc = &base->chans[ch];
821 spin_lock(&cohc->lock);
823 /* Mask off this bit */
824 status1 &= ~(1 << i);
825 /* Check the individual channel bits */
826 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
827 dev_crit(COHC_2_DEV(cohc),
828 "DMA bus error on channel %d!\n", ch);
830 /* Clear BE interrupt */
831 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
833 /* Caused by TC, really? */
834 if (unlikely(!test_bit(i, virtbase +
835 COH901318_TC_INT_STATUS1))) {
836 dev_warn(COHC_2_DEV(cohc),
837 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
838 /* Clear TC interrupt */
840 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
842 /* Enable powersave if transfer has finished */
843 if (!(readl(virtbase + COH901318_CX_STAT +
844 COH901318_CX_STAT_SPACING*ch) &
845 COH901318_CX_STAT_ENABLED)) {
846 enable_powersave(cohc);
849 /* Must clear TC interrupt before calling
851 * in case tc_handle initate a new dma job
853 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
858 spin_unlock(&cohc->lock);
861 /* Check the remaining 32 DMA channels for IRQ */
863 /* Find first bit set, return as a number. */
864 i = ffs(status2) - 1;
866 cohc = &base->chans[ch];
867 spin_lock(&cohc->lock);
869 /* Mask off this bit */
870 status2 &= ~(1 << i);
871 /* Check the individual channel bits */
872 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
873 dev_crit(COHC_2_DEV(cohc),
874 "DMA bus error on channel %d!\n", ch);
875 /* Clear BE interrupt */
877 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
879 /* Caused by TC, really? */
880 if (unlikely(!test_bit(i, virtbase +
881 COH901318_TC_INT_STATUS2))) {
882 dev_warn(COHC_2_DEV(cohc),
883 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
884 /* Clear TC interrupt */
885 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
888 /* Enable powersave if transfer has finished */
889 if (!(readl(virtbase + COH901318_CX_STAT +
890 COH901318_CX_STAT_SPACING*ch) &
891 COH901318_CX_STAT_ENABLED)) {
892 enable_powersave(cohc);
894 /* Must clear TC interrupt before calling
896 * in case tc_handle initate a new dma job
898 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
903 spin_unlock(&cohc->lock);
909 static int coh901318_alloc_chan_resources(struct dma_chan *chan)
911 struct coh901318_chan *cohc = to_coh901318_chan(chan);
914 dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
917 if (chan->client_count > 1)
920 spin_lock_irqsave(&cohc->lock, flags);
922 coh901318_config(cohc, NULL);
925 cohc->completed = chan->cookie = 1;
927 spin_unlock_irqrestore(&cohc->lock, flags);
933 coh901318_free_chan_resources(struct dma_chan *chan)
935 struct coh901318_chan *cohc = to_coh901318_chan(chan);
936 int channel = cohc->id;
939 spin_lock_irqsave(&cohc->lock, flags);
942 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
943 COH901318_CX_CFG_SPACING*channel);
944 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
945 COH901318_CX_CTRL_SPACING*channel);
949 spin_unlock_irqrestore(&cohc->lock, flags);
951 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
956 coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
958 struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
960 struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
963 spin_lock_irqsave(&cohc->lock, flags);
965 tx->cookie = coh901318_assign_cookie(cohc, cohd);
967 coh901318_desc_queue(cohc, cohd);
969 spin_unlock_irqrestore(&cohc->lock, flags);
974 static struct dma_async_tx_descriptor *
975 coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
976 size_t size, unsigned long flags)
978 struct coh901318_lli *lli;
979 struct coh901318_desc *cohd;
981 struct coh901318_chan *cohc = to_coh901318_chan(chan);
983 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
986 spin_lock_irqsave(&cohc->lock, flg);
988 dev_vdbg(COHC_2_DEV(cohc),
989 "[%s] channel %d src 0x%x dest 0x%x size %d\n",
990 __func__, cohc->id, src, dest, size);
992 if (flags & DMA_PREP_INTERRUPT)
993 /* Trigger interrupt after last lli */
994 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
996 lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
997 if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1000 lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
1005 ret = coh901318_lli_fill_memcpy(
1006 &cohc->base->pool, lli, src, size, dest,
1007 cohc_chan_param(cohc)->ctrl_lli_chained,
1012 COH_DBG(coh901318_list_print(cohc, lli));
1014 /* Pick a descriptor to handle this transfer */
1015 cohd = coh901318_desc_get(cohc);
1017 cohd->flags = flags;
1018 cohd->desc.tx_submit = coh901318_tx_submit;
1020 spin_unlock_irqrestore(&cohc->lock, flg);
1024 spin_unlock_irqrestore(&cohc->lock, flg);
1028 static struct dma_async_tx_descriptor *
1029 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1030 unsigned int sg_len, enum dma_data_direction direction,
1031 unsigned long flags)
1033 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1034 struct coh901318_lli *lli;
1035 struct coh901318_desc *cohd;
1036 const struct coh901318_params *params;
1037 struct scatterlist *sg;
1041 u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
1042 u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
1043 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
1050 if (sgl->length == 0)
1053 spin_lock_irqsave(&cohc->lock, flg);
1055 dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
1056 __func__, sg_len, direction);
1058 if (flags & DMA_PREP_INTERRUPT)
1059 /* Trigger interrupt after last lli */
1060 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
1062 params = cohc_chan_param(cohc);
1063 config = params->config;
1065 * Add runtime-specific control on top, make
1066 * sure the bits you set per peripheral channel are
1067 * cleared in the default config from the platform.
1069 ctrl_chained |= cohc->runtime_ctrl;
1070 ctrl_last |= cohc->runtime_ctrl;
1071 ctrl |= cohc->runtime_ctrl;
1073 if (direction == DMA_TO_DEVICE) {
1074 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
1075 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
1077 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
1078 ctrl_chained |= tx_flags;
1079 ctrl_last |= tx_flags;
1081 } else if (direction == DMA_FROM_DEVICE) {
1082 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
1083 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
1085 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
1086 ctrl_chained |= rx_flags;
1087 ctrl_last |= rx_flags;
1092 coh901318_set_conf(cohc, config);
1094 /* The dma only supports transmitting packages up to
1095 * MAX_DMA_PACKET_SIZE. Calculate to total number of
1096 * dma elemts required to send the entire sg list
1098 for_each_sg(sgl, sg, sg_len, i) {
1099 unsigned int factor;
1100 size = sg_dma_len(sg);
1102 if (size <= MAX_DMA_PACKET_SIZE) {
1107 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
1108 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1114 pr_debug("Allocate %d lli:s for this transfer\n", len);
1115 lli = coh901318_lli_alloc(&cohc->base->pool, len);
1120 /* initiate allocated lli list */
1121 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
1122 cohc_dev_addr(cohc),
1126 direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
1131 * Set the default ctrl for the channel to the one from the lli,
1132 * things may have changed due to odd buffer alignment etc.
1134 coh901318_set_ctrl(cohc, lli->control);
1136 COH_DBG(coh901318_list_print(cohc, lli));
1138 /* Pick a descriptor to handle this transfer */
1139 cohd = coh901318_desc_get(cohc);
1140 cohd->dir = direction;
1141 cohd->flags = flags;
1142 cohd->desc.tx_submit = coh901318_tx_submit;
1145 spin_unlock_irqrestore(&cohc->lock, flg);
1151 spin_unlock_irqrestore(&cohc->lock, flg);
1156 static enum dma_status
1157 coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1158 struct dma_tx_state *txstate)
1160 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1161 dma_cookie_t last_used;
1162 dma_cookie_t last_complete;
1165 last_complete = cohc->completed;
1166 last_used = chan->cookie;
1168 ret = dma_async_is_complete(cookie, last_complete, last_used);
1170 dma_set_tx_state(txstate, last_complete, last_used,
1171 coh901318_get_bytes_left(chan));
1172 if (ret == DMA_IN_PROGRESS && cohc->stopped)
1179 coh901318_issue_pending(struct dma_chan *chan)
1181 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1182 unsigned long flags;
1184 spin_lock_irqsave(&cohc->lock, flags);
1187 * Busy means that pending jobs are already being processed,
1188 * and then there is no point in starting the queue: the
1189 * terminal count interrupt on the channel will take the next
1190 * job on the queue and execute it anyway.
1193 coh901318_queue_start(cohc);
1195 spin_unlock_irqrestore(&cohc->lock, flags);
1199 * Here we wrap in the runtime dma control interface
1201 struct burst_table {
1208 static const struct burst_table burst_sizes[] = {
1213 .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
1219 .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
1225 .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
1231 .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
1237 .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
1243 .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
1249 .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
1255 .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
1259 static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1260 struct dma_slave_config *config)
1262 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1264 enum dma_slave_buswidth addr_width;
1266 u32 runtime_ctrl = 0;
1269 /* We only support mem to per or per to mem transfers */
1270 if (config->direction == DMA_FROM_DEVICE) {
1271 addr = config->src_addr;
1272 addr_width = config->src_addr_width;
1273 maxburst = config->src_maxburst;
1274 } else if (config->direction == DMA_TO_DEVICE) {
1275 addr = config->dst_addr;
1276 addr_width = config->dst_addr_width;
1277 maxburst = config->dst_maxburst;
1279 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
1283 dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
1285 switch (addr_width) {
1286 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1288 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
1289 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
1291 while (i < ARRAY_SIZE(burst_sizes)) {
1292 if (burst_sizes[i].burst_8bit <= maxburst)
1298 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1300 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
1301 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
1303 while (i < ARRAY_SIZE(burst_sizes)) {
1304 if (burst_sizes[i].burst_16bit <= maxburst)
1310 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1311 /* Direction doesn't matter here, it's 32/32 bits */
1313 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1314 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
1316 while (i < ARRAY_SIZE(burst_sizes)) {
1317 if (burst_sizes[i].burst_32bit <= maxburst)
1324 dev_err(COHC_2_DEV(cohc),
1325 "bad runtimeconfig: alien address width\n");
1329 runtime_ctrl |= burst_sizes[i].reg;
1330 dev_dbg(COHC_2_DEV(cohc),
1331 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
1332 burst_sizes[i].burst_8bit, addr_width, maxburst);
1334 cohc->runtime_addr = addr;
1335 cohc->runtime_ctrl = runtime_ctrl;
1339 coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1342 unsigned long flags;
1343 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1344 struct coh901318_desc *cohd;
1345 void __iomem *virtbase = cohc->base->virtbase;
1347 if (cmd == DMA_SLAVE_CONFIG) {
1348 struct dma_slave_config *config =
1349 (struct dma_slave_config *) arg;
1351 coh901318_dma_set_runtimeconfig(chan, config);
1355 if (cmd == DMA_PAUSE) {
1356 coh901318_pause(chan);
1360 if (cmd == DMA_RESUME) {
1361 coh901318_resume(chan);
1365 if (cmd != DMA_TERMINATE_ALL)
1368 /* The remainder of this function terminates the transfer */
1369 coh901318_pause(chan);
1370 spin_lock_irqsave(&cohc->lock, flags);
1372 /* Clear any pending BE or TC interrupt */
1373 if (cohc->id < 32) {
1374 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1375 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1377 writel(1 << (cohc->id - 32), virtbase +
1378 COH901318_BE_INT_CLEAR2);
1379 writel(1 << (cohc->id - 32), virtbase +
1380 COH901318_TC_INT_CLEAR2);
1383 enable_powersave(cohc);
1385 while ((cohd = coh901318_first_active_get(cohc))) {
1386 /* release the lli allocation*/
1387 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1389 /* return desc to free-list */
1390 coh901318_desc_remove(cohd);
1391 coh901318_desc_free(cohc, cohd);
1394 while ((cohd = coh901318_first_queued(cohc))) {
1395 /* release the lli allocation*/
1396 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1398 /* return desc to free-list */
1399 coh901318_desc_remove(cohd);
1400 coh901318_desc_free(cohc, cohd);
1404 cohc->nbr_active_done = 0;
1407 spin_unlock_irqrestore(&cohc->lock, flags);
1412 void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1413 struct coh901318_base *base)
1417 struct coh901318_chan *cohc;
1419 INIT_LIST_HEAD(&dma->channels);
1421 for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
1422 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
1423 cohc = &base->chans[i];
1426 cohc->chan.device = dma;
1429 /* TODO: do we really need this lock if only one
1430 * client is connected to each channel?
1433 spin_lock_init(&cohc->lock);
1435 cohc->nbr_active_done = 0;
1437 INIT_LIST_HEAD(&cohc->free);
1438 INIT_LIST_HEAD(&cohc->active);
1439 INIT_LIST_HEAD(&cohc->queue);
1441 tasklet_init(&cohc->tasklet, dma_tasklet,
1442 (unsigned long) cohc);
1444 list_add_tail(&cohc->chan.device_node,
1450 static int __init coh901318_probe(struct platform_device *pdev)
1453 struct coh901318_platform *pdata;
1454 struct coh901318_base *base;
1456 struct resource *io;
1458 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1460 goto err_get_resource;
1462 /* Map DMA controller registers to virtual memory */
1463 if (request_mem_region(io->start,
1465 pdev->dev.driver->name) == NULL) {
1467 goto err_request_mem;
1470 pdata = pdev->dev.platform_data;
1472 goto err_no_platformdata;
1474 base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
1475 pdata->max_channels *
1476 sizeof(struct coh901318_chan),
1479 goto err_alloc_coh_dma_channels;
1481 base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
1483 base->virtbase = ioremap(io->start, resource_size(io));
1484 if (!base->virtbase) {
1486 goto err_no_ioremap;
1489 base->dev = &pdev->dev;
1490 base->platform = pdata;
1491 spin_lock_init(&base->pm.lock);
1492 base->pm.started_channels = 0;
1494 COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
1496 platform_set_drvdata(pdev, base);
1498 irq = platform_get_irq(pdev, 0);
1502 err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
1505 dev_crit(&pdev->dev,
1506 "Cannot allocate IRQ for DMA controller!\n");
1507 goto err_request_irq;
1510 err = coh901318_pool_create(&base->pool, &pdev->dev,
1511 sizeof(struct coh901318_lli),
1514 goto err_pool_create;
1516 /* init channels for device transfers */
1517 coh901318_base_init(&base->dma_slave, base->platform->chans_slave,
1520 dma_cap_zero(base->dma_slave.cap_mask);
1521 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
1523 base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1524 base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
1525 base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
1526 base->dma_slave.device_tx_status = coh901318_tx_status;
1527 base->dma_slave.device_issue_pending = coh901318_issue_pending;
1528 base->dma_slave.device_control = coh901318_control;
1529 base->dma_slave.dev = &pdev->dev;
1531 err = dma_async_device_register(&base->dma_slave);
1534 goto err_register_slave;
1536 /* init channels for memcpy */
1537 coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
1540 dma_cap_zero(base->dma_memcpy.cap_mask);
1541 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
1543 base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1544 base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
1545 base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
1546 base->dma_memcpy.device_tx_status = coh901318_tx_status;
1547 base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
1548 base->dma_memcpy.device_control = coh901318_control;
1549 base->dma_memcpy.dev = &pdev->dev;
1551 * This controller can only access address at even 32bit boundaries,
1554 base->dma_memcpy.copy_align = 2;
1555 err = dma_async_device_register(&base->dma_memcpy);
1558 goto err_register_memcpy;
1560 dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
1561 (u32) base->virtbase);
1565 err_register_memcpy:
1566 dma_async_device_unregister(&base->dma_slave);
1568 coh901318_pool_destroy(&base->pool);
1570 free_irq(platform_get_irq(pdev, 0), base);
1573 iounmap(base->virtbase);
1576 err_alloc_coh_dma_channels:
1577 err_no_platformdata:
1578 release_mem_region(pdev->resource->start,
1579 resource_size(pdev->resource));
1585 static int __exit coh901318_remove(struct platform_device *pdev)
1587 struct coh901318_base *base = platform_get_drvdata(pdev);
1589 dma_async_device_unregister(&base->dma_memcpy);
1590 dma_async_device_unregister(&base->dma_slave);
1591 coh901318_pool_destroy(&base->pool);
1592 free_irq(platform_get_irq(pdev, 0), base);
1593 iounmap(base->virtbase);
1595 release_mem_region(pdev->resource->start,
1596 resource_size(pdev->resource));
1601 static struct platform_driver coh901318_driver = {
1602 .remove = __exit_p(coh901318_remove),
1604 .name = "coh901318",
1608 int __init coh901318_init(void)
1610 return platform_driver_probe(&coh901318_driver, coh901318_probe);
1612 subsys_initcall(coh901318_init);
1614 void __exit coh901318_exit(void)
1616 platform_driver_unregister(&coh901318_driver);
1618 module_exit(coh901318_exit);
1620 MODULE_LICENSE("GPL");
1621 MODULE_AUTHOR("Per Friden");