1 #include <linux/delay.h>
2 #include <linux/dmaengine.h>
3 #include <linux/dma-mapping.h>
4 #include <linux/platform_device.h>
5 #include <linux/module.h>
7 #include <linux/slab.h>
8 #include <linux/of_dma.h>
9 #include <linux/of_irq.h>
10 #include <linux/dmapool.h>
11 #include <linux/interrupt.h>
12 #include <linux/of_address.h>
13 #include <linux/pm_runtime.h>
14 #include "dmaengine.h"
17 #define DESC_TYPE_HOST 0x10
18 #define DESC_TYPE_TEARD 0x13
20 #define TD_DESC_IS_RX (1 << 16)
21 #define TD_DESC_DMA_NUM 10
23 #define DESC_LENGTH_BITS_NUM 21
25 #define DESC_TYPE_USB (5 << 26)
26 #define DESC_PD_COMPLETE (1 << 31)
30 #define DMA_TXGCR(x) (0x800 + (x) * 0x20)
31 #define DMA_RXGCR(x) (0x808 + (x) * 0x20)
34 #define GCR_CHAN_ENABLE (1 << 31)
35 #define GCR_TEARDOWN (1 << 30)
36 #define GCR_STARV_RETRY (1 << 24)
37 #define GCR_DESC_TYPE_HOST (1 << 14)
40 #define DMA_SCHED_CTRL 0
41 #define DMA_SCHED_CTRL_EN (1 << 31)
42 #define DMA_SCHED_WORD(x) ((x) * 4 + 0x800)
44 #define SCHED_ENTRY0_CHAN(x) ((x) << 0)
45 #define SCHED_ENTRY0_IS_RX (1 << 7)
47 #define SCHED_ENTRY1_CHAN(x) ((x) << 8)
48 #define SCHED_ENTRY1_IS_RX (1 << 15)
50 #define SCHED_ENTRY2_CHAN(x) ((x) << 16)
51 #define SCHED_ENTRY2_IS_RX (1 << 23)
53 #define SCHED_ENTRY3_CHAN(x) ((x) << 24)
54 #define SCHED_ENTRY3_IS_RX (1 << 31)
57 /* 4 KiB of memory for descriptors, 2 for each endpoint */
58 #define ALLOC_DECS_NUM 128
60 #define TOTAL_DESCS_NUM (ALLOC_DECS_NUM * DESCS_AREAS)
61 #define QMGR_SCRATCH_SIZE (TOTAL_DESCS_NUM * 4)
63 #define QMGR_LRAM0_BASE 0x80
64 #define QMGR_LRAM_SIZE 0x84
65 #define QMGR_LRAM1_BASE 0x88
66 #define QMGR_MEMBASE(x) (0x1000 + (x) * 0x10)
67 #define QMGR_MEMCTRL(x) (0x1004 + (x) * 0x10)
68 #define QMGR_MEMCTRL_IDX_SH 16
69 #define QMGR_MEMCTRL_DESC_SH 8
71 #define QMGR_NUM_PEND 5
72 #define QMGR_PEND(x) (0x90 + (x) * 4)
74 #define QMGR_PENDING_SLOT_Q(x) (x / 32)
75 #define QMGR_PENDING_BIT_Q(x) (x % 32)
77 #define QMGR_QUEUE_A(n) (0x2000 + (n) * 0x10)
78 #define QMGR_QUEUE_B(n) (0x2004 + (n) * 0x10)
79 #define QMGR_QUEUE_C(n) (0x2008 + (n) * 0x10)
80 #define QMGR_QUEUE_D(n) (0x200c + (n) * 0x10)
82 /* Glue layer specific */
83 /* USBSS / USB AM335x */
84 #define USBSS_IRQ_STATUS 0x28
85 #define USBSS_IRQ_ENABLER 0x2c
86 #define USBSS_IRQ_CLEARR 0x30
88 #define USBSS_IRQ_PD_COMP (1 << 2)
90 /* Packet Descriptor */
91 #define PD2_ZERO_LENGTH (1 << 19)
93 struct cppi41_channel {
95 struct dma_async_tx_descriptor txd;
96 struct cppi41_dd *cdd;
97 struct cppi41_desc *desc;
99 void __iomem *gcr_reg;
104 unsigned int q_comp_num;
105 unsigned int port_num;
108 unsigned td_queued:1;
110 unsigned td_desc_seen:1;
112 struct list_head node; /* Node for pending list */
132 struct dma_device ddev;
135 dma_addr_t scratch_phys;
137 struct cppi41_desc *cd;
138 dma_addr_t descs_phys;
140 struct cppi41_channel *chan_busy[ALLOC_DECS_NUM];
142 void __iomem *usbss_mem;
143 void __iomem *ctrl_mem;
144 void __iomem *sched_mem;
145 void __iomem *qmgr_mem;
147 const struct chan_queues *queues_rx;
148 const struct chan_queues *queues_tx;
149 struct chan_queues td_queue;
151 struct list_head pending; /* Pending queued transfers */
152 spinlock_t lock; /* Lock for pending list */
154 /* context for suspend/resume */
155 unsigned int dma_tdfdq;
158 #define FIST_COMPLETION_QUEUE 93
159 static struct chan_queues usb_queues_tx[] = {
161 [ 0] = { .submit = 32, .complete = 93},
162 [ 1] = { .submit = 34, .complete = 94},
163 [ 2] = { .submit = 36, .complete = 95},
164 [ 3] = { .submit = 38, .complete = 96},
165 [ 4] = { .submit = 40, .complete = 97},
166 [ 5] = { .submit = 42, .complete = 98},
167 [ 6] = { .submit = 44, .complete = 99},
168 [ 7] = { .submit = 46, .complete = 100},
169 [ 8] = { .submit = 48, .complete = 101},
170 [ 9] = { .submit = 50, .complete = 102},
171 [10] = { .submit = 52, .complete = 103},
172 [11] = { .submit = 54, .complete = 104},
173 [12] = { .submit = 56, .complete = 105},
174 [13] = { .submit = 58, .complete = 106},
175 [14] = { .submit = 60, .complete = 107},
178 [15] = { .submit = 62, .complete = 125},
179 [16] = { .submit = 64, .complete = 126},
180 [17] = { .submit = 66, .complete = 127},
181 [18] = { .submit = 68, .complete = 128},
182 [19] = { .submit = 70, .complete = 129},
183 [20] = { .submit = 72, .complete = 130},
184 [21] = { .submit = 74, .complete = 131},
185 [22] = { .submit = 76, .complete = 132},
186 [23] = { .submit = 78, .complete = 133},
187 [24] = { .submit = 80, .complete = 134},
188 [25] = { .submit = 82, .complete = 135},
189 [26] = { .submit = 84, .complete = 136},
190 [27] = { .submit = 86, .complete = 137},
191 [28] = { .submit = 88, .complete = 138},
192 [29] = { .submit = 90, .complete = 139},
195 static const struct chan_queues usb_queues_rx[] = {
197 [ 0] = { .submit = 1, .complete = 109},
198 [ 1] = { .submit = 2, .complete = 110},
199 [ 2] = { .submit = 3, .complete = 111},
200 [ 3] = { .submit = 4, .complete = 112},
201 [ 4] = { .submit = 5, .complete = 113},
202 [ 5] = { .submit = 6, .complete = 114},
203 [ 6] = { .submit = 7, .complete = 115},
204 [ 7] = { .submit = 8, .complete = 116},
205 [ 8] = { .submit = 9, .complete = 117},
206 [ 9] = { .submit = 10, .complete = 118},
207 [10] = { .submit = 11, .complete = 119},
208 [11] = { .submit = 12, .complete = 120},
209 [12] = { .submit = 13, .complete = 121},
210 [13] = { .submit = 14, .complete = 122},
211 [14] = { .submit = 15, .complete = 123},
214 [15] = { .submit = 16, .complete = 141},
215 [16] = { .submit = 17, .complete = 142},
216 [17] = { .submit = 18, .complete = 143},
217 [18] = { .submit = 19, .complete = 144},
218 [19] = { .submit = 20, .complete = 145},
219 [20] = { .submit = 21, .complete = 146},
220 [21] = { .submit = 22, .complete = 147},
221 [22] = { .submit = 23, .complete = 148},
222 [23] = { .submit = 24, .complete = 149},
223 [24] = { .submit = 25, .complete = 150},
224 [25] = { .submit = 26, .complete = 151},
225 [26] = { .submit = 27, .complete = 152},
226 [27] = { .submit = 28, .complete = 153},
227 [28] = { .submit = 29, .complete = 154},
228 [29] = { .submit = 30, .complete = 155},
231 struct cppi_glue_infos {
232 irqreturn_t (*isr)(int irq, void *data);
233 const struct chan_queues *queues_rx;
234 const struct chan_queues *queues_tx;
235 struct chan_queues td_queue;
238 static struct cppi41_channel *to_cpp41_chan(struct dma_chan *c)
240 return container_of(c, struct cppi41_channel, chan);
243 static struct cppi41_channel *desc_to_chan(struct cppi41_dd *cdd, u32 desc)
245 struct cppi41_channel *c;
249 descs_size = sizeof(struct cppi41_desc) * ALLOC_DECS_NUM;
251 if (!((desc >= cdd->descs_phys) &&
252 (desc < (cdd->descs_phys + descs_size)))) {
256 desc_num = (desc - cdd->descs_phys) / sizeof(struct cppi41_desc);
257 BUG_ON(desc_num >= ALLOC_DECS_NUM);
258 c = cdd->chan_busy[desc_num];
259 cdd->chan_busy[desc_num] = NULL;
263 static void cppi_writel(u32 val, void *__iomem *mem)
265 __raw_writel(val, mem);
268 static u32 cppi_readl(void *__iomem *mem)
270 return __raw_readl(mem);
273 static u32 pd_trans_len(u32 val)
275 return val & ((1 << (DESC_LENGTH_BITS_NUM + 1)) - 1);
278 static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num)
282 desc = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(queue_num));
287 static irqreturn_t cppi41_irq(int irq, void *data)
289 struct cppi41_dd *cdd = data;
290 struct cppi41_channel *c;
294 status = cppi_readl(cdd->usbss_mem + USBSS_IRQ_STATUS);
295 if (!(status & USBSS_IRQ_PD_COMP))
297 cppi_writel(status, cdd->usbss_mem + USBSS_IRQ_STATUS);
299 for (i = QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE); i < QMGR_NUM_PEND;
304 val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i));
305 if (i == QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE) && val) {
307 /* set corresponding bit for completetion Q 93 */
308 mask = 1 << QMGR_PENDING_BIT_Q(FIST_COMPLETION_QUEUE);
309 /* not set all bits for queues less than Q 93 */
311 /* now invert and keep only Q 93+ set */
322 error = pm_runtime_get(cdd->ddev.dev);
324 dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n",
328 val &= ~(1 << q_num);
330 desc = cppi41_pop_desc(cdd, q_num);
331 c = desc_to_chan(cdd, desc);
333 pr_err("%s() q %d desc %08x\n", __func__,
338 if (c->desc->pd2 & PD2_ZERO_LENGTH)
341 len = pd_trans_len(c->desc->pd0);
343 c->residue = pd_trans_len(c->desc->pd6) - len;
344 dma_cookie_complete(&c->txd);
345 dmaengine_desc_get_callback_invoke(&c->txd, NULL);
347 pm_runtime_mark_last_busy(cdd->ddev.dev);
348 pm_runtime_put_autosuspend(cdd->ddev.dev);
354 static dma_cookie_t cppi41_tx_submit(struct dma_async_tx_descriptor *tx)
358 cookie = dma_cookie_assign(tx);
363 static int cppi41_dma_alloc_chan_resources(struct dma_chan *chan)
365 struct cppi41_channel *c = to_cpp41_chan(chan);
366 struct cppi41_dd *cdd = c->cdd;
369 error = pm_runtime_get_sync(cdd->ddev.dev);
371 dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n",
373 pm_runtime_put_noidle(cdd->ddev.dev);
378 dma_cookie_init(chan);
379 dma_async_tx_descriptor_init(&c->txd, chan);
380 c->txd.tx_submit = cppi41_tx_submit;
383 cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
385 pm_runtime_mark_last_busy(cdd->ddev.dev);
386 pm_runtime_put_autosuspend(cdd->ddev.dev);
391 static void cppi41_dma_free_chan_resources(struct dma_chan *chan)
393 struct cppi41_channel *c = to_cpp41_chan(chan);
394 struct cppi41_dd *cdd = c->cdd;
397 error = pm_runtime_get_sync(cdd->ddev.dev);
399 pm_runtime_put_noidle(cdd->ddev.dev);
404 WARN_ON(!list_empty(&cdd->pending));
406 pm_runtime_mark_last_busy(cdd->ddev.dev);
407 pm_runtime_put_autosuspend(cdd->ddev.dev);
410 static enum dma_status cppi41_dma_tx_status(struct dma_chan *chan,
411 dma_cookie_t cookie, struct dma_tx_state *txstate)
413 struct cppi41_channel *c = to_cpp41_chan(chan);
417 ret = dma_cookie_status(chan, cookie, txstate);
418 if (txstate && ret == DMA_COMPLETE)
419 txstate->residue = c->residue;
425 static void push_desc_queue(struct cppi41_channel *c)
427 struct cppi41_dd *cdd = c->cdd;
434 reg = GCR_CHAN_ENABLE;
436 reg |= GCR_STARV_RETRY;
437 reg |= GCR_DESC_TYPE_HOST;
438 reg |= c->q_comp_num;
441 cppi_writel(reg, c->gcr_reg);
444 * We don't use writel() but __raw_writel() so we have to make sure
445 * that the DMA descriptor in coherent memory made to the main memory
446 * before starting the dma engine.
450 desc_phys = lower_32_bits(c->desc_phys);
451 desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
452 WARN_ON(cdd->chan_busy[desc_num]);
453 cdd->chan_busy[desc_num] = c;
455 reg = (sizeof(struct cppi41_desc) - 24) / 4;
457 cppi_writel(reg, cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num));
460 static void pending_desc(struct cppi41_channel *c)
462 struct cppi41_dd *cdd = c->cdd;
465 spin_lock_irqsave(&cdd->lock, flags);
466 list_add_tail(&c->node, &cdd->pending);
467 spin_unlock_irqrestore(&cdd->lock, flags);
470 static void cppi41_dma_issue_pending(struct dma_chan *chan)
472 struct cppi41_channel *c = to_cpp41_chan(chan);
473 struct cppi41_dd *cdd = c->cdd;
476 error = pm_runtime_get(cdd->ddev.dev);
477 if ((error != -EINPROGRESS) && error < 0) {
478 pm_runtime_put_noidle(cdd->ddev.dev);
479 dev_err(cdd->ddev.dev, "Failed to pm_runtime_get: %i\n",
485 if (likely(pm_runtime_active(cdd->ddev.dev)))
490 pm_runtime_mark_last_busy(cdd->ddev.dev);
491 pm_runtime_put_autosuspend(cdd->ddev.dev);
494 static u32 get_host_pd0(u32 length)
498 reg = DESC_TYPE_HOST << DESC_TYPE;
504 static u32 get_host_pd1(struct cppi41_channel *c)
513 static u32 get_host_pd2(struct cppi41_channel *c)
518 reg |= c->q_comp_num;
523 static u32 get_host_pd3(u32 length)
527 /* PD3 = packet size */
533 static u32 get_host_pd6(u32 length)
537 /* PD6 buffer size */
538 reg = DESC_PD_COMPLETE;
544 static u32 get_host_pd4_or_7(u32 addr)
553 static u32 get_host_pd5(void)
562 static struct dma_async_tx_descriptor *cppi41_dma_prep_slave_sg(
563 struct dma_chan *chan, struct scatterlist *sgl, unsigned sg_len,
564 enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
566 struct cppi41_channel *c = to_cpp41_chan(chan);
567 struct cppi41_desc *d;
568 struct scatterlist *sg;
572 for_each_sg(sgl, sg, sg_len, i) {
576 /* We need to use more than one desc once musb supports sg */
577 addr = lower_32_bits(sg_dma_address(sg));
578 len = sg_dma_len(sg);
580 d->pd0 = get_host_pd0(len);
581 d->pd1 = get_host_pd1(c);
582 d->pd2 = get_host_pd2(c);
583 d->pd3 = get_host_pd3(len);
584 d->pd4 = get_host_pd4_or_7(addr);
585 d->pd5 = get_host_pd5();
586 d->pd6 = get_host_pd6(len);
587 d->pd7 = get_host_pd4_or_7(addr);
595 static void cppi41_compute_td_desc(struct cppi41_desc *d)
597 d->pd0 = DESC_TYPE_TEARD << DESC_TYPE;
600 static int cppi41_tear_down_chan(struct cppi41_channel *c)
602 struct cppi41_dd *cdd = c->cdd;
603 struct cppi41_desc *td;
609 td += cdd->first_td_desc;
611 td_desc_phys = cdd->descs_phys;
612 td_desc_phys += cdd->first_td_desc * sizeof(struct cppi41_desc);
615 cppi41_compute_td_desc(td);
618 reg = (sizeof(struct cppi41_desc) - 24) / 4;
620 cppi_writel(reg, cdd->qmgr_mem +
621 QMGR_QUEUE_D(cdd->td_queue.submit));
623 reg = GCR_CHAN_ENABLE;
625 reg |= GCR_STARV_RETRY;
626 reg |= GCR_DESC_TYPE_HOST;
627 reg |= c->q_comp_num;
630 cppi_writel(reg, c->gcr_reg);
635 if (!c->td_seen || !c->td_desc_seen) {
637 desc_phys = cppi41_pop_desc(cdd, cdd->td_queue.complete);
639 desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
641 if (desc_phys == c->desc_phys) {
644 } else if (desc_phys == td_desc_phys) {
649 WARN_ON((pd0 >> DESC_TYPE) != DESC_TYPE_TEARD);
650 WARN_ON(!c->is_tx && !(pd0 & TD_DESC_IS_RX));
651 WARN_ON((pd0 & 0x1f) != c->port_num);
653 } else if (desc_phys) {
659 * If the TX descriptor / channel is in use, the caller needs to poke
660 * his TD bit multiple times. After that he hardware releases the
661 * transfer descriptor followed by TD descriptor. Waiting seems not to
662 * cause any difference.
663 * RX seems to be thrown out right away. However once the TearDown
664 * descriptor gets through we are done. If we have seens the transfer
665 * descriptor before the TD we fetch it from enqueue, it has to be
666 * there waiting for us.
668 if (!c->td_seen && c->td_retry) {
672 WARN_ON(!c->td_retry);
674 if (!c->td_desc_seen) {
675 desc_phys = cppi41_pop_desc(cdd, c->q_num);
677 desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
684 cppi_writel(0, c->gcr_reg);
688 static int cppi41_stop_chan(struct dma_chan *chan)
690 struct cppi41_channel *c = to_cpp41_chan(chan);
691 struct cppi41_dd *cdd = c->cdd;
696 desc_phys = lower_32_bits(c->desc_phys);
697 desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
698 if (!cdd->chan_busy[desc_num])
701 ret = cppi41_tear_down_chan(c);
705 WARN_ON(!cdd->chan_busy[desc_num]);
706 cdd->chan_busy[desc_num] = NULL;
711 static void cleanup_chans(struct cppi41_dd *cdd)
713 while (!list_empty(&cdd->ddev.channels)) {
714 struct cppi41_channel *cchan;
716 cchan = list_first_entry(&cdd->ddev.channels,
717 struct cppi41_channel, chan.device_node);
718 list_del(&cchan->chan.device_node);
723 static int cppi41_add_chans(struct device *dev, struct cppi41_dd *cdd)
725 struct cppi41_channel *cchan;
730 ret = of_property_read_u32(dev->of_node, "#dma-channels",
735 * The channels can only be used as TX or as RX. So we add twice
736 * that much dma channels because USB can only do RX or TX.
740 for (i = 0; i < n_chans; i++) {
741 cchan = kzalloc(sizeof(*cchan), GFP_KERNEL);
747 cchan->gcr_reg = cdd->ctrl_mem + DMA_TXGCR(i >> 1);
750 cchan->gcr_reg = cdd->ctrl_mem + DMA_RXGCR(i >> 1);
753 cchan->port_num = i >> 1;
754 cchan->desc = &cdd->cd[i];
755 cchan->desc_phys = cdd->descs_phys;
756 cchan->desc_phys += i * sizeof(struct cppi41_desc);
757 cchan->chan.device = &cdd->ddev;
758 list_add_tail(&cchan->chan.device_node, &cdd->ddev.channels);
760 cdd->first_td_desc = n_chans;
768 static void purge_descs(struct device *dev, struct cppi41_dd *cdd)
770 unsigned int mem_decs;
773 mem_decs = ALLOC_DECS_NUM * sizeof(struct cppi41_desc);
775 for (i = 0; i < DESCS_AREAS; i++) {
777 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMBASE(i));
778 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMCTRL(i));
780 dma_free_coherent(dev, mem_decs, cdd->cd,
785 static void disable_sched(struct cppi41_dd *cdd)
787 cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
790 static void deinit_cppi41(struct device *dev, struct cppi41_dd *cdd)
794 purge_descs(dev, cdd);
796 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
797 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
798 dma_free_coherent(dev, QMGR_SCRATCH_SIZE, cdd->qmgr_scratch,
802 static int init_descs(struct device *dev, struct cppi41_dd *cdd)
804 unsigned int desc_size;
805 unsigned int mem_decs;
810 BUILD_BUG_ON(sizeof(struct cppi41_desc) &
811 (sizeof(struct cppi41_desc) - 1));
812 BUILD_BUG_ON(sizeof(struct cppi41_desc) < 32);
813 BUILD_BUG_ON(ALLOC_DECS_NUM < 32);
815 desc_size = sizeof(struct cppi41_desc);
816 mem_decs = ALLOC_DECS_NUM * desc_size;
819 for (i = 0; i < DESCS_AREAS; i++) {
821 reg = idx << QMGR_MEMCTRL_IDX_SH;
822 reg |= (ilog2(desc_size) - 5) << QMGR_MEMCTRL_DESC_SH;
823 reg |= ilog2(ALLOC_DECS_NUM) - 5;
825 BUILD_BUG_ON(DESCS_AREAS != 1);
826 cdd->cd = dma_alloc_coherent(dev, mem_decs,
827 &cdd->descs_phys, GFP_KERNEL);
831 cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
832 cppi_writel(reg, cdd->qmgr_mem + QMGR_MEMCTRL(i));
834 idx += ALLOC_DECS_NUM;
839 static void init_sched(struct cppi41_dd *cdd)
846 cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
847 for (ch = 0; ch < 15 * 2; ch += 2) {
849 reg = SCHED_ENTRY0_CHAN(ch);
850 reg |= SCHED_ENTRY1_CHAN(ch) | SCHED_ENTRY1_IS_RX;
852 reg |= SCHED_ENTRY2_CHAN(ch + 1);
853 reg |= SCHED_ENTRY3_CHAN(ch + 1) | SCHED_ENTRY3_IS_RX;
854 cppi_writel(reg, cdd->sched_mem + DMA_SCHED_WORD(word));
857 reg = 15 * 2 * 2 - 1;
858 reg |= DMA_SCHED_CTRL_EN;
859 cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL);
862 static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
866 BUILD_BUG_ON(QMGR_SCRATCH_SIZE > ((1 << 14) - 1));
867 cdd->qmgr_scratch = dma_alloc_coherent(dev, QMGR_SCRATCH_SIZE,
868 &cdd->scratch_phys, GFP_KERNEL);
869 if (!cdd->qmgr_scratch)
872 cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
873 cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
874 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
876 ret = init_descs(dev, cdd);
880 cppi_writel(cdd->td_queue.submit, cdd->ctrl_mem + DMA_TDFDQ);
884 deinit_cppi41(dev, cdd);
888 static struct platform_driver cpp41_dma_driver;
890 * The param format is:
898 static bool cpp41_dma_filter_fn(struct dma_chan *chan, void *param)
900 struct cppi41_channel *cchan;
901 struct cppi41_dd *cdd;
902 const struct chan_queues *queues;
905 if (chan->device->dev->driver != &cpp41_dma_driver.driver)
908 cchan = to_cpp41_chan(chan);
910 if (cchan->port_num != num[INFO_PORT])
913 if (cchan->is_tx && !num[INFO_IS_TX])
917 queues = cdd->queues_tx;
919 queues = cdd->queues_rx;
921 BUILD_BUG_ON(ARRAY_SIZE(usb_queues_rx) != ARRAY_SIZE(usb_queues_tx));
922 if (WARN_ON(cchan->port_num > ARRAY_SIZE(usb_queues_rx)))
925 cchan->q_num = queues[cchan->port_num].submit;
926 cchan->q_comp_num = queues[cchan->port_num].complete;
930 static struct of_dma_filter_info cpp41_dma_info = {
931 .filter_fn = cpp41_dma_filter_fn,
934 static struct dma_chan *cppi41_dma_xlate(struct of_phandle_args *dma_spec,
935 struct of_dma *ofdma)
937 int count = dma_spec->args_count;
938 struct of_dma_filter_info *info = ofdma->of_dma_data;
940 if (!info || !info->filter_fn)
946 return dma_request_channel(info->dma_cap, info->filter_fn,
950 static const struct cppi_glue_infos usb_infos = {
952 .queues_rx = usb_queues_rx,
953 .queues_tx = usb_queues_tx,
954 .td_queue = { .submit = 31, .complete = 0 },
957 static const struct of_device_id cppi41_dma_ids[] = {
958 { .compatible = "ti,am3359-cppi41", .data = &usb_infos},
961 MODULE_DEVICE_TABLE(of, cppi41_dma_ids);
963 static const struct cppi_glue_infos *get_glue_info(struct device *dev)
965 const struct of_device_id *of_id;
967 of_id = of_match_node(cppi41_dma_ids, dev->of_node);
973 #define CPPI41_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
974 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
975 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
976 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
978 static int cppi41_dma_probe(struct platform_device *pdev)
980 struct cppi41_dd *cdd;
981 struct device *dev = &pdev->dev;
982 const struct cppi_glue_infos *glue_info;
986 glue_info = get_glue_info(dev);
990 cdd = devm_kzalloc(&pdev->dev, sizeof(*cdd), GFP_KERNEL);
994 dma_cap_set(DMA_SLAVE, cdd->ddev.cap_mask);
995 cdd->ddev.device_alloc_chan_resources = cppi41_dma_alloc_chan_resources;
996 cdd->ddev.device_free_chan_resources = cppi41_dma_free_chan_resources;
997 cdd->ddev.device_tx_status = cppi41_dma_tx_status;
998 cdd->ddev.device_issue_pending = cppi41_dma_issue_pending;
999 cdd->ddev.device_prep_slave_sg = cppi41_dma_prep_slave_sg;
1000 cdd->ddev.device_terminate_all = cppi41_stop_chan;
1001 cdd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1002 cdd->ddev.src_addr_widths = CPPI41_DMA_BUSWIDTHS;
1003 cdd->ddev.dst_addr_widths = CPPI41_DMA_BUSWIDTHS;
1004 cdd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1005 cdd->ddev.dev = dev;
1006 INIT_LIST_HEAD(&cdd->ddev.channels);
1007 cpp41_dma_info.dma_cap = cdd->ddev.cap_mask;
1009 cdd->usbss_mem = of_iomap(dev->of_node, 0);
1010 cdd->ctrl_mem = of_iomap(dev->of_node, 1);
1011 cdd->sched_mem = of_iomap(dev->of_node, 2);
1012 cdd->qmgr_mem = of_iomap(dev->of_node, 3);
1013 spin_lock_init(&cdd->lock);
1014 INIT_LIST_HEAD(&cdd->pending);
1016 platform_set_drvdata(pdev, cdd);
1018 if (!cdd->usbss_mem || !cdd->ctrl_mem || !cdd->sched_mem ||
1022 pm_runtime_enable(dev);
1023 pm_runtime_set_autosuspend_delay(dev, 100);
1024 pm_runtime_use_autosuspend(dev);
1025 ret = pm_runtime_get_sync(dev);
1029 cdd->queues_rx = glue_info->queues_rx;
1030 cdd->queues_tx = glue_info->queues_tx;
1031 cdd->td_queue = glue_info->td_queue;
1033 ret = init_cppi41(dev, cdd);
1037 ret = cppi41_add_chans(dev, cdd);
1041 irq = irq_of_parse_and_map(dev->of_node, 0);
1047 cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
1049 ret = devm_request_irq(&pdev->dev, irq, glue_info->isr, IRQF_SHARED,
1050 dev_name(dev), cdd);
1055 ret = dma_async_device_register(&cdd->ddev);
1059 ret = of_dma_controller_register(dev->of_node,
1060 cppi41_dma_xlate, &cpp41_dma_info);
1064 pm_runtime_mark_last_busy(dev);
1065 pm_runtime_put_autosuspend(dev);
1069 dma_async_device_unregister(&cdd->ddev);
1072 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1075 deinit_cppi41(dev, cdd);
1077 pm_runtime_dont_use_autosuspend(dev);
1079 pm_runtime_put_sync(dev);
1080 pm_runtime_disable(dev);
1081 iounmap(cdd->usbss_mem);
1082 iounmap(cdd->ctrl_mem);
1083 iounmap(cdd->sched_mem);
1084 iounmap(cdd->qmgr_mem);
1088 static int cppi41_dma_remove(struct platform_device *pdev)
1090 struct cppi41_dd *cdd = platform_get_drvdata(pdev);
1093 error = pm_runtime_get_sync(&pdev->dev);
1095 dev_err(&pdev->dev, "%s could not pm_runtime_get: %i\n",
1097 of_dma_controller_free(pdev->dev.of_node);
1098 dma_async_device_unregister(&cdd->ddev);
1100 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1101 devm_free_irq(&pdev->dev, cdd->irq, cdd);
1103 deinit_cppi41(&pdev->dev, cdd);
1104 iounmap(cdd->usbss_mem);
1105 iounmap(cdd->ctrl_mem);
1106 iounmap(cdd->sched_mem);
1107 iounmap(cdd->qmgr_mem);
1108 pm_runtime_dont_use_autosuspend(&pdev->dev);
1109 pm_runtime_put_sync(&pdev->dev);
1110 pm_runtime_disable(&pdev->dev);
1114 static int __maybe_unused cppi41_suspend(struct device *dev)
1116 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1118 cdd->dma_tdfdq = cppi_readl(cdd->ctrl_mem + DMA_TDFDQ);
1119 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1125 static int __maybe_unused cppi41_resume(struct device *dev)
1127 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1128 struct cppi41_channel *c;
1131 for (i = 0; i < DESCS_AREAS; i++)
1132 cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
1134 list_for_each_entry(c, &cdd->ddev.channels, chan.device_node)
1136 cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
1140 cppi_writel(cdd->dma_tdfdq, cdd->ctrl_mem + DMA_TDFDQ);
1141 cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
1142 cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
1143 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
1145 cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
1150 static int __maybe_unused cppi41_runtime_suspend(struct device *dev)
1152 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1154 WARN_ON(!list_empty(&cdd->pending));
1159 static int __maybe_unused cppi41_runtime_resume(struct device *dev)
1161 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1162 struct cppi41_channel *c, *_c;
1163 unsigned long flags;
1165 spin_lock_irqsave(&cdd->lock, flags);
1166 list_for_each_entry_safe(c, _c, &cdd->pending, node) {
1170 spin_unlock_irqrestore(&cdd->lock, flags);
1175 static const struct dev_pm_ops cppi41_pm_ops = {
1176 SET_LATE_SYSTEM_SLEEP_PM_OPS(cppi41_suspend, cppi41_resume)
1177 SET_RUNTIME_PM_OPS(cppi41_runtime_suspend,
1178 cppi41_runtime_resume,
1182 static struct platform_driver cpp41_dma_driver = {
1183 .probe = cppi41_dma_probe,
1184 .remove = cppi41_dma_remove,
1186 .name = "cppi41-dma-engine",
1187 .pm = &cppi41_pm_ops,
1188 .of_match_table = of_match_ptr(cppi41_dma_ids),
1192 module_platform_driver(cpp41_dma_driver);
1193 MODULE_LICENSE("GPL");
1194 MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");