2 * Core driver for the Synopsys DesignWare DMA Controller
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
6 * Copyright (C) 2013 Intel Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/bitops.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/pm_runtime.h>
27 #include "../dmaengine.h"
31 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
33 * of which use ARM any more). See the "Databook" from Synopsys for
34 * information beyond what licensees probably provide.
36 * The driver has been tested with the Atmel AT32AP7000, which does not
37 * support descriptor writeback.
40 #define DWC_DEFAULT_CTLLO(_chan) ({ \
41 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
42 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
43 bool _is_slave = is_slave_direction(_dwc->direction); \
44 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
46 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
49 (DWC_CTLL_DST_MSIZE(_dmsize) \
50 | DWC_CTLL_SRC_MSIZE(_smsize) \
53 | DWC_CTLL_DMS(_dwc->dst_master) \
54 | DWC_CTLL_SMS(_dwc->src_master)); \
58 * Number of descriptors to allocate for each channel. This should be
59 * made configurable somehow; preferably, the clients (at least the
60 * ones using slave transfers) should be able to give us a hint.
62 #define NR_DESCS_PER_CHANNEL 64
64 /*----------------------------------------------------------------------*/
66 static struct device *chan2dev(struct dma_chan *chan)
68 return &chan->dev->device;
71 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
73 return to_dw_desc(dwc->active_list.next);
76 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
78 struct dw_desc *desc, *_desc;
79 struct dw_desc *ret = NULL;
83 spin_lock_irqsave(&dwc->lock, flags);
84 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
86 if (async_tx_test_ack(&desc->txd)) {
87 list_del(&desc->desc_node);
91 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
93 spin_unlock_irqrestore(&dwc->lock, flags);
95 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
101 * Move a descriptor, including any children, to the free list.
102 * `desc' must not be on any lists.
104 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
109 struct dw_desc *child;
111 spin_lock_irqsave(&dwc->lock, flags);
112 list_for_each_entry(child, &desc->tx_list, desc_node)
113 dev_vdbg(chan2dev(&dwc->chan),
114 "moving child desc %p to freelist\n",
116 list_splice_init(&desc->tx_list, &dwc->free_list);
117 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
118 list_add(&desc->desc_node, &dwc->free_list);
119 spin_unlock_irqrestore(&dwc->lock, flags);
123 static void dwc_initialize(struct dw_dma_chan *dwc)
125 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
126 struct dw_dma_slave *dws = dwc->chan.private;
127 u32 cfghi = DWC_CFGH_FIFO_MODE;
128 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
130 if (dwc->initialized == true)
135 * We need controller-specific data to set up slave
138 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
140 cfghi |= DWC_CFGH_DST_PER(dws->dst_id);
141 cfghi |= DWC_CFGH_SRC_PER(dws->src_id);
143 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
144 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
147 channel_writel(dwc, CFG_LO, cfglo);
148 channel_writel(dwc, CFG_HI, cfghi);
150 /* Enable interrupts */
151 channel_set_bit(dw, MASK.XFER, dwc->mask);
152 channel_set_bit(dw, MASK.ERROR, dwc->mask);
154 dwc->initialized = true;
157 /*----------------------------------------------------------------------*/
159 static inline unsigned int dwc_fast_fls(unsigned long long v)
162 * We can be a lot more clever here, but this should take care
163 * of the most common optimization.
174 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
176 dev_err(chan2dev(&dwc->chan),
177 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
178 channel_readl(dwc, SAR),
179 channel_readl(dwc, DAR),
180 channel_readl(dwc, LLP),
181 channel_readl(dwc, CTL_HI),
182 channel_readl(dwc, CTL_LO));
185 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
187 channel_clear_bit(dw, CH_EN, dwc->mask);
188 while (dma_readl(dw, CH_EN) & dwc->mask)
192 /*----------------------------------------------------------------------*/
194 /* Perform single block transfer */
195 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
196 struct dw_desc *desc)
198 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
202 * Software emulation of LLP mode relies on interrupts to continue
203 * multi block transfer.
205 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
207 channel_writel(dwc, SAR, desc->lli.sar);
208 channel_writel(dwc, DAR, desc->lli.dar);
209 channel_writel(dwc, CTL_LO, ctllo);
210 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
211 channel_set_bit(dw, CH_EN, dwc->mask);
213 /* Move pointer to next descriptor */
214 dwc->tx_node_active = dwc->tx_node_active->next;
217 /* Called with dwc->lock held and bh disabled */
218 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
220 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
221 unsigned long was_soft_llp;
223 /* ASSERT: channel is idle */
224 if (dma_readl(dw, CH_EN) & dwc->mask) {
225 dev_err(chan2dev(&dwc->chan),
226 "BUG: Attempted to start non-idle channel\n");
227 dwc_dump_chan_regs(dwc);
229 /* The tasklet will hopefully advance the queue... */
234 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
237 dev_err(chan2dev(&dwc->chan),
238 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
244 dwc->residue = first->total_len;
245 dwc->tx_node_active = &first->tx_list;
247 /* Submit first block */
248 dwc_do_single_block(dwc, first);
255 channel_writel(dwc, LLP, first->txd.phys);
256 channel_writel(dwc, CTL_LO,
257 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
258 channel_writel(dwc, CTL_HI, 0);
259 channel_set_bit(dw, CH_EN, dwc->mask);
262 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
264 struct dw_desc *desc;
266 if (list_empty(&dwc->queue))
269 list_move(dwc->queue.next, &dwc->active_list);
270 desc = dwc_first_active(dwc);
271 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
272 dwc_dostart(dwc, desc);
275 /*----------------------------------------------------------------------*/
278 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
279 bool callback_required)
281 dma_async_tx_callback callback = NULL;
283 struct dma_async_tx_descriptor *txd = &desc->txd;
284 struct dw_desc *child;
287 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
289 spin_lock_irqsave(&dwc->lock, flags);
290 dma_cookie_complete(txd);
291 if (callback_required) {
292 callback = txd->callback;
293 param = txd->callback_param;
297 list_for_each_entry(child, &desc->tx_list, desc_node)
298 async_tx_ack(&child->txd);
299 async_tx_ack(&desc->txd);
301 list_splice_init(&desc->tx_list, &dwc->free_list);
302 list_move(&desc->desc_node, &dwc->free_list);
304 dma_descriptor_unmap(txd);
305 spin_unlock_irqrestore(&dwc->lock, flags);
311 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
313 struct dw_desc *desc, *_desc;
317 spin_lock_irqsave(&dwc->lock, flags);
318 if (dma_readl(dw, CH_EN) & dwc->mask) {
319 dev_err(chan2dev(&dwc->chan),
320 "BUG: XFER bit set, but channel not idle!\n");
322 /* Try to continue after resetting the channel... */
323 dwc_chan_disable(dw, dwc);
327 * Submit queued descriptors ASAP, i.e. before we go through
328 * the completed ones.
330 list_splice_init(&dwc->active_list, &list);
331 dwc_dostart_first_queued(dwc);
333 spin_unlock_irqrestore(&dwc->lock, flags);
335 list_for_each_entry_safe(desc, _desc, &list, desc_node)
336 dwc_descriptor_complete(dwc, desc, true);
339 /* Returns how many bytes were already received from source */
340 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
342 u32 ctlhi = channel_readl(dwc, CTL_HI);
343 u32 ctllo = channel_readl(dwc, CTL_LO);
345 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
348 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
351 struct dw_desc *desc, *_desc;
352 struct dw_desc *child;
356 spin_lock_irqsave(&dwc->lock, flags);
357 llp = channel_readl(dwc, LLP);
358 status_xfer = dma_readl(dw, RAW.XFER);
360 if (status_xfer & dwc->mask) {
361 /* Everything we've submitted is done */
362 dma_writel(dw, CLEAR.XFER, dwc->mask);
364 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
365 struct list_head *head, *active = dwc->tx_node_active;
368 * We are inside first active descriptor.
369 * Otherwise something is really wrong.
371 desc = dwc_first_active(dwc);
373 head = &desc->tx_list;
374 if (active != head) {
375 /* Update desc to reflect last sent one */
376 if (active != head->next)
377 desc = to_dw_desc(active->prev);
379 dwc->residue -= desc->len;
381 child = to_dw_desc(active);
383 /* Submit next block */
384 dwc_do_single_block(dwc, child);
386 spin_unlock_irqrestore(&dwc->lock, flags);
390 /* We are done here */
391 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
396 spin_unlock_irqrestore(&dwc->lock, flags);
398 dwc_complete_all(dw, dwc);
402 if (list_empty(&dwc->active_list)) {
404 spin_unlock_irqrestore(&dwc->lock, flags);
408 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
409 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
410 spin_unlock_irqrestore(&dwc->lock, flags);
414 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
416 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
417 /* Initial residue value */
418 dwc->residue = desc->total_len;
420 /* Check first descriptors addr */
421 if (desc->txd.phys == llp) {
422 spin_unlock_irqrestore(&dwc->lock, flags);
426 /* Check first descriptors llp */
427 if (desc->lli.llp == llp) {
428 /* This one is currently in progress */
429 dwc->residue -= dwc_get_sent(dwc);
430 spin_unlock_irqrestore(&dwc->lock, flags);
434 dwc->residue -= desc->len;
435 list_for_each_entry(child, &desc->tx_list, desc_node) {
436 if (child->lli.llp == llp) {
437 /* Currently in progress */
438 dwc->residue -= dwc_get_sent(dwc);
439 spin_unlock_irqrestore(&dwc->lock, flags);
442 dwc->residue -= child->len;
446 * No descriptors so far seem to be in progress, i.e.
447 * this one must be done.
449 spin_unlock_irqrestore(&dwc->lock, flags);
450 dwc_descriptor_complete(dwc, desc, true);
451 spin_lock_irqsave(&dwc->lock, flags);
454 dev_err(chan2dev(&dwc->chan),
455 "BUG: All descriptors done, but channel not idle!\n");
457 /* Try to continue after resetting the channel... */
458 dwc_chan_disable(dw, dwc);
460 dwc_dostart_first_queued(dwc);
461 spin_unlock_irqrestore(&dwc->lock, flags);
464 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
466 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
467 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
470 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
472 struct dw_desc *bad_desc;
473 struct dw_desc *child;
476 dwc_scan_descriptors(dw, dwc);
478 spin_lock_irqsave(&dwc->lock, flags);
481 * The descriptor currently at the head of the active list is
482 * borked. Since we don't have any way to report errors, we'll
483 * just have to scream loudly and try to carry on.
485 bad_desc = dwc_first_active(dwc);
486 list_del_init(&bad_desc->desc_node);
487 list_move(dwc->queue.next, dwc->active_list.prev);
489 /* Clear the error flag and try to restart the controller */
490 dma_writel(dw, CLEAR.ERROR, dwc->mask);
491 if (!list_empty(&dwc->active_list))
492 dwc_dostart(dwc, dwc_first_active(dwc));
495 * WARN may seem harsh, but since this only happens
496 * when someone submits a bad physical address in a
497 * descriptor, we should consider ourselves lucky that the
498 * controller flagged an error instead of scribbling over
499 * random memory locations.
501 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
502 " cookie: %d\n", bad_desc->txd.cookie);
503 dwc_dump_lli(dwc, &bad_desc->lli);
504 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
505 dwc_dump_lli(dwc, &child->lli);
507 spin_unlock_irqrestore(&dwc->lock, flags);
509 /* Pretend the descriptor completed successfully */
510 dwc_descriptor_complete(dwc, bad_desc, true);
513 /* --------------------- Cyclic DMA API extensions -------------------- */
515 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
517 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
518 return channel_readl(dwc, SAR);
520 EXPORT_SYMBOL(dw_dma_get_src_addr);
522 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
524 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
525 return channel_readl(dwc, DAR);
527 EXPORT_SYMBOL(dw_dma_get_dst_addr);
529 /* Called with dwc->lock held and all DMAC interrupts disabled */
530 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
531 u32 status_err, u32 status_xfer)
536 void (*callback)(void *param);
537 void *callback_param;
539 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
540 channel_readl(dwc, LLP));
542 callback = dwc->cdesc->period_callback;
543 callback_param = dwc->cdesc->period_callback_param;
546 callback(callback_param);
550 * Error and transfer complete are highly unlikely, and will most
551 * likely be due to a configuration error by the user.
553 if (unlikely(status_err & dwc->mask) ||
554 unlikely(status_xfer & dwc->mask)) {
557 dev_err(chan2dev(&dwc->chan),
558 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
559 status_xfer ? "xfer" : "error");
561 spin_lock_irqsave(&dwc->lock, flags);
563 dwc_dump_chan_regs(dwc);
565 dwc_chan_disable(dw, dwc);
567 /* Make sure DMA does not restart by loading a new list */
568 channel_writel(dwc, LLP, 0);
569 channel_writel(dwc, CTL_LO, 0);
570 channel_writel(dwc, CTL_HI, 0);
572 dma_writel(dw, CLEAR.ERROR, dwc->mask);
573 dma_writel(dw, CLEAR.XFER, dwc->mask);
575 for (i = 0; i < dwc->cdesc->periods; i++)
576 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
578 spin_unlock_irqrestore(&dwc->lock, flags);
582 /* ------------------------------------------------------------------------- */
584 static void dw_dma_tasklet(unsigned long data)
586 struct dw_dma *dw = (struct dw_dma *)data;
587 struct dw_dma_chan *dwc;
592 status_xfer = dma_readl(dw, RAW.XFER);
593 status_err = dma_readl(dw, RAW.ERROR);
595 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
597 for (i = 0; i < dw->dma.chancnt; i++) {
599 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
600 dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
601 else if (status_err & (1 << i))
602 dwc_handle_error(dw, dwc);
603 else if (status_xfer & (1 << i))
604 dwc_scan_descriptors(dw, dwc);
608 * Re-enable interrupts.
610 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
611 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
614 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
616 struct dw_dma *dw = dev_id;
617 u32 status = dma_readl(dw, STATUS_INT);
619 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
621 /* Check if we have any interrupt from the DMAC */
626 * Just disable the interrupts. We'll turn them back on in the
629 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
630 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
632 status = dma_readl(dw, STATUS_INT);
635 "BUG: Unexpected interrupts pending: 0x%x\n",
639 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
640 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
641 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
642 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
645 tasklet_schedule(&dw->tasklet);
650 /*----------------------------------------------------------------------*/
652 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
654 struct dw_desc *desc = txd_to_dw_desc(tx);
655 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
659 spin_lock_irqsave(&dwc->lock, flags);
660 cookie = dma_cookie_assign(tx);
663 * REVISIT: We should attempt to chain as many descriptors as
664 * possible, perhaps even appending to those already submitted
665 * for DMA. But this is hard to do in a race-free manner.
668 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
669 list_add_tail(&desc->desc_node, &dwc->queue);
671 spin_unlock_irqrestore(&dwc->lock, flags);
676 static struct dma_async_tx_descriptor *
677 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
678 size_t len, unsigned long flags)
680 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
681 struct dw_dma *dw = to_dw_dma(chan->device);
682 struct dw_desc *desc;
683 struct dw_desc *first;
684 struct dw_desc *prev;
687 unsigned int src_width;
688 unsigned int dst_width;
689 unsigned int data_width;
692 dev_vdbg(chan2dev(chan),
693 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
694 &dest, &src, len, flags);
696 if (unlikely(!len)) {
697 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
701 dwc->direction = DMA_MEM_TO_MEM;
703 data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
704 dw->data_width[dwc->dst_master]);
706 src_width = dst_width = min_t(unsigned int, data_width,
707 dwc_fast_fls(src | dest | len));
709 ctllo = DWC_DEFAULT_CTLLO(chan)
710 | DWC_CTLL_DST_WIDTH(dst_width)
711 | DWC_CTLL_SRC_WIDTH(src_width)
717 for (offset = 0; offset < len; offset += xfer_count << src_width) {
718 xfer_count = min_t(size_t, (len - offset) >> src_width,
721 desc = dwc_desc_get(dwc);
725 desc->lli.sar = src + offset;
726 desc->lli.dar = dest + offset;
727 desc->lli.ctllo = ctllo;
728 desc->lli.ctlhi = xfer_count;
729 desc->len = xfer_count << src_width;
734 prev->lli.llp = desc->txd.phys;
735 list_add_tail(&desc->desc_node,
741 if (flags & DMA_PREP_INTERRUPT)
742 /* Trigger interrupt after last block */
743 prev->lli.ctllo |= DWC_CTLL_INT_EN;
746 first->txd.flags = flags;
747 first->total_len = len;
752 dwc_desc_put(dwc, first);
756 static struct dma_async_tx_descriptor *
757 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
758 unsigned int sg_len, enum dma_transfer_direction direction,
759 unsigned long flags, void *context)
761 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
762 struct dw_dma *dw = to_dw_dma(chan->device);
763 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
764 struct dw_desc *prev;
765 struct dw_desc *first;
768 unsigned int reg_width;
769 unsigned int mem_width;
770 unsigned int data_width;
772 struct scatterlist *sg;
773 size_t total_len = 0;
775 dev_vdbg(chan2dev(chan), "%s\n", __func__);
777 if (unlikely(!is_slave_direction(direction) || !sg_len))
780 dwc->direction = direction;
786 reg_width = __fls(sconfig->dst_addr_width);
787 reg = sconfig->dst_addr;
788 ctllo = (DWC_DEFAULT_CTLLO(chan)
789 | DWC_CTLL_DST_WIDTH(reg_width)
793 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
794 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
796 data_width = dw->data_width[dwc->src_master];
798 for_each_sg(sgl, sg, sg_len, i) {
799 struct dw_desc *desc;
802 mem = sg_dma_address(sg);
803 len = sg_dma_len(sg);
805 mem_width = min_t(unsigned int,
806 data_width, dwc_fast_fls(mem | len));
808 slave_sg_todev_fill_desc:
809 desc = dwc_desc_get(dwc);
811 dev_err(chan2dev(chan),
812 "not enough descriptors available\n");
818 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
819 if ((len >> mem_width) > dwc->block_size) {
820 dlen = dwc->block_size << mem_width;
828 desc->lli.ctlhi = dlen >> mem_width;
834 prev->lli.llp = desc->txd.phys;
835 list_add_tail(&desc->desc_node,
842 goto slave_sg_todev_fill_desc;
846 reg_width = __fls(sconfig->src_addr_width);
847 reg = sconfig->src_addr;
848 ctllo = (DWC_DEFAULT_CTLLO(chan)
849 | DWC_CTLL_SRC_WIDTH(reg_width)
853 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
854 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
856 data_width = dw->data_width[dwc->dst_master];
858 for_each_sg(sgl, sg, sg_len, i) {
859 struct dw_desc *desc;
862 mem = sg_dma_address(sg);
863 len = sg_dma_len(sg);
865 mem_width = min_t(unsigned int,
866 data_width, dwc_fast_fls(mem | len));
868 slave_sg_fromdev_fill_desc:
869 desc = dwc_desc_get(dwc);
871 dev_err(chan2dev(chan),
872 "not enough descriptors available\n");
878 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
879 if ((len >> reg_width) > dwc->block_size) {
880 dlen = dwc->block_size << reg_width;
887 desc->lli.ctlhi = dlen >> reg_width;
893 prev->lli.llp = desc->txd.phys;
894 list_add_tail(&desc->desc_node,
901 goto slave_sg_fromdev_fill_desc;
908 if (flags & DMA_PREP_INTERRUPT)
909 /* Trigger interrupt after last block */
910 prev->lli.ctllo |= DWC_CTLL_INT_EN;
913 first->total_len = total_len;
918 dwc_desc_put(dwc, first);
922 bool dw_dma_filter(struct dma_chan *chan, void *param)
924 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
925 struct dw_dma_slave *dws = param;
927 if (!dws || dws->dma_dev != chan->device->dev)
930 /* We have to copy data since dws can be temporary storage */
932 dwc->src_id = dws->src_id;
933 dwc->dst_id = dws->dst_id;
935 dwc->src_master = dws->src_master;
936 dwc->dst_master = dws->dst_master;
940 EXPORT_SYMBOL_GPL(dw_dma_filter);
943 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
944 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
946 * NOTE: burst size 2 is not supported by controller.
948 * This can be done by finding least significant bit set: n & (n - 1)
950 static inline void convert_burst(u32 *maxburst)
953 *maxburst = fls(*maxburst) - 2;
959 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
961 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
963 /* Check if chan will be configured for slave transfers */
964 if (!is_slave_direction(sconfig->direction))
967 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
968 dwc->direction = sconfig->direction;
970 convert_burst(&dwc->dma_sconfig.src_maxburst);
971 convert_burst(&dwc->dma_sconfig.dst_maxburst);
976 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
978 u32 cfglo = channel_readl(dwc, CFG_LO);
979 unsigned int count = 20; /* timeout iterations */
981 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
982 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
988 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
990 u32 cfglo = channel_readl(dwc, CFG_LO);
992 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
997 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1000 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1001 struct dw_dma *dw = to_dw_dma(chan->device);
1002 struct dw_desc *desc, *_desc;
1003 unsigned long flags;
1006 if (cmd == DMA_PAUSE) {
1007 spin_lock_irqsave(&dwc->lock, flags);
1009 dwc_chan_pause(dwc);
1011 spin_unlock_irqrestore(&dwc->lock, flags);
1012 } else if (cmd == DMA_RESUME) {
1016 spin_lock_irqsave(&dwc->lock, flags);
1018 dwc_chan_resume(dwc);
1020 spin_unlock_irqrestore(&dwc->lock, flags);
1021 } else if (cmd == DMA_TERMINATE_ALL) {
1022 spin_lock_irqsave(&dwc->lock, flags);
1024 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1026 dwc_chan_disable(dw, dwc);
1028 dwc_chan_resume(dwc);
1030 /* active_list entries will end up before queued entries */
1031 list_splice_init(&dwc->queue, &list);
1032 list_splice_init(&dwc->active_list, &list);
1034 spin_unlock_irqrestore(&dwc->lock, flags);
1036 /* Flush all pending and queued descriptors */
1037 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1038 dwc_descriptor_complete(dwc, desc, false);
1039 } else if (cmd == DMA_SLAVE_CONFIG) {
1040 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1048 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1050 unsigned long flags;
1053 spin_lock_irqsave(&dwc->lock, flags);
1055 residue = dwc->residue;
1056 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1057 residue -= dwc_get_sent(dwc);
1059 spin_unlock_irqrestore(&dwc->lock, flags);
1063 static enum dma_status
1064 dwc_tx_status(struct dma_chan *chan,
1065 dma_cookie_t cookie,
1066 struct dma_tx_state *txstate)
1068 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1069 enum dma_status ret;
1071 ret = dma_cookie_status(chan, cookie, txstate);
1072 if (ret == DMA_COMPLETE)
1075 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1077 ret = dma_cookie_status(chan, cookie, txstate);
1078 if (ret != DMA_COMPLETE)
1079 dma_set_residue(txstate, dwc_get_residue(dwc));
1081 if (dwc->paused && ret == DMA_IN_PROGRESS)
1087 static void dwc_issue_pending(struct dma_chan *chan)
1089 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1090 unsigned long flags;
1092 spin_lock_irqsave(&dwc->lock, flags);
1093 if (list_empty(&dwc->active_list))
1094 dwc_dostart_first_queued(dwc);
1095 spin_unlock_irqrestore(&dwc->lock, flags);
1098 /*----------------------------------------------------------------------*/
1100 static void dw_dma_off(struct dw_dma *dw)
1104 dma_writel(dw, CFG, 0);
1106 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1107 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1108 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1109 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1111 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1114 for (i = 0; i < dw->dma.chancnt; i++)
1115 dw->chan[i].initialized = false;
1118 static void dw_dma_on(struct dw_dma *dw)
1120 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1123 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1125 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1126 struct dw_dma *dw = to_dw_dma(chan->device);
1127 struct dw_desc *desc;
1129 unsigned long flags;
1131 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1133 /* ASSERT: channel is idle */
1134 if (dma_readl(dw, CH_EN) & dwc->mask) {
1135 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1139 dma_cookie_init(chan);
1142 * NOTE: some controllers may have additional features that we
1143 * need to initialize here, like "scatter-gather" (which
1144 * doesn't mean what you think it means), and status writeback.
1147 /* Enable controller here if needed */
1150 dw->in_use |= dwc->mask;
1152 spin_lock_irqsave(&dwc->lock, flags);
1153 i = dwc->descs_allocated;
1154 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1157 spin_unlock_irqrestore(&dwc->lock, flags);
1159 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1161 goto err_desc_alloc;
1163 memset(desc, 0, sizeof(struct dw_desc));
1165 INIT_LIST_HEAD(&desc->tx_list);
1166 dma_async_tx_descriptor_init(&desc->txd, chan);
1167 desc->txd.tx_submit = dwc_tx_submit;
1168 desc->txd.flags = DMA_CTRL_ACK;
1169 desc->txd.phys = phys;
1171 dwc_desc_put(dwc, desc);
1173 spin_lock_irqsave(&dwc->lock, flags);
1174 i = ++dwc->descs_allocated;
1177 spin_unlock_irqrestore(&dwc->lock, flags);
1179 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1184 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1189 static void dwc_free_chan_resources(struct dma_chan *chan)
1191 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1192 struct dw_dma *dw = to_dw_dma(chan->device);
1193 struct dw_desc *desc, *_desc;
1194 unsigned long flags;
1197 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1198 dwc->descs_allocated);
1200 /* ASSERT: channel is idle */
1201 BUG_ON(!list_empty(&dwc->active_list));
1202 BUG_ON(!list_empty(&dwc->queue));
1203 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1205 spin_lock_irqsave(&dwc->lock, flags);
1206 list_splice_init(&dwc->free_list, &list);
1207 dwc->descs_allocated = 0;
1208 dwc->initialized = false;
1210 /* Disable interrupts */
1211 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1212 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1214 spin_unlock_irqrestore(&dwc->lock, flags);
1216 /* Disable controller in case it was a last user */
1217 dw->in_use &= ~dwc->mask;
1221 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1222 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1223 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1226 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1229 /* --------------------- Cyclic DMA API extensions -------------------- */
1232 * dw_dma_cyclic_start - start the cyclic DMA transfer
1233 * @chan: the DMA channel to start
1235 * Must be called with soft interrupts disabled. Returns zero on success or
1236 * -errno on failure.
1238 int dw_dma_cyclic_start(struct dma_chan *chan)
1240 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1241 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1242 unsigned long flags;
1244 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1245 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1249 spin_lock_irqsave(&dwc->lock, flags);
1251 /* Assert channel is idle */
1252 if (dma_readl(dw, CH_EN) & dwc->mask) {
1253 dev_err(chan2dev(&dwc->chan),
1254 "BUG: Attempted to start non-idle channel\n");
1255 dwc_dump_chan_regs(dwc);
1256 spin_unlock_irqrestore(&dwc->lock, flags);
1260 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1261 dma_writel(dw, CLEAR.XFER, dwc->mask);
1263 /* Setup DMAC channel registers */
1264 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1265 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1266 channel_writel(dwc, CTL_HI, 0);
1268 channel_set_bit(dw, CH_EN, dwc->mask);
1270 spin_unlock_irqrestore(&dwc->lock, flags);
1274 EXPORT_SYMBOL(dw_dma_cyclic_start);
1277 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1278 * @chan: the DMA channel to stop
1280 * Must be called with soft interrupts disabled.
1282 void dw_dma_cyclic_stop(struct dma_chan *chan)
1284 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1285 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1286 unsigned long flags;
1288 spin_lock_irqsave(&dwc->lock, flags);
1290 dwc_chan_disable(dw, dwc);
1292 spin_unlock_irqrestore(&dwc->lock, flags);
1294 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1297 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1298 * @chan: the DMA channel to prepare
1299 * @buf_addr: physical DMA address where the buffer starts
1300 * @buf_len: total number of bytes for the entire buffer
1301 * @period_len: number of bytes for each period
1302 * @direction: transfer direction, to or from device
1304 * Must be called before trying to start the transfer. Returns a valid struct
1305 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1307 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1308 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1309 enum dma_transfer_direction direction)
1311 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1312 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1313 struct dw_cyclic_desc *cdesc;
1314 struct dw_cyclic_desc *retval = NULL;
1315 struct dw_desc *desc;
1316 struct dw_desc *last = NULL;
1317 unsigned long was_cyclic;
1318 unsigned int reg_width;
1319 unsigned int periods;
1321 unsigned long flags;
1323 spin_lock_irqsave(&dwc->lock, flags);
1325 spin_unlock_irqrestore(&dwc->lock, flags);
1326 dev_dbg(chan2dev(&dwc->chan),
1327 "channel doesn't support LLP transfers\n");
1328 return ERR_PTR(-EINVAL);
1331 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1332 spin_unlock_irqrestore(&dwc->lock, flags);
1333 dev_dbg(chan2dev(&dwc->chan),
1334 "queue and/or active list are not empty\n");
1335 return ERR_PTR(-EBUSY);
1338 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1339 spin_unlock_irqrestore(&dwc->lock, flags);
1341 dev_dbg(chan2dev(&dwc->chan),
1342 "channel already prepared for cyclic DMA\n");
1343 return ERR_PTR(-EBUSY);
1346 retval = ERR_PTR(-EINVAL);
1348 if (unlikely(!is_slave_direction(direction)))
1351 dwc->direction = direction;
1353 if (direction == DMA_MEM_TO_DEV)
1354 reg_width = __ffs(sconfig->dst_addr_width);
1356 reg_width = __ffs(sconfig->src_addr_width);
1358 periods = buf_len / period_len;
1360 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1361 if (period_len > (dwc->block_size << reg_width))
1363 if (unlikely(period_len & ((1 << reg_width) - 1)))
1365 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1368 retval = ERR_PTR(-ENOMEM);
1370 if (periods > NR_DESCS_PER_CHANNEL)
1373 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1377 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1381 for (i = 0; i < periods; i++) {
1382 desc = dwc_desc_get(dwc);
1384 goto out_err_desc_get;
1386 switch (direction) {
1387 case DMA_MEM_TO_DEV:
1388 desc->lli.dar = sconfig->dst_addr;
1389 desc->lli.sar = buf_addr + (period_len * i);
1390 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1391 | DWC_CTLL_DST_WIDTH(reg_width)
1392 | DWC_CTLL_SRC_WIDTH(reg_width)
1397 desc->lli.ctllo |= sconfig->device_fc ?
1398 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1399 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1402 case DMA_DEV_TO_MEM:
1403 desc->lli.dar = buf_addr + (period_len * i);
1404 desc->lli.sar = sconfig->src_addr;
1405 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1406 | DWC_CTLL_SRC_WIDTH(reg_width)
1407 | DWC_CTLL_DST_WIDTH(reg_width)
1412 desc->lli.ctllo |= sconfig->device_fc ?
1413 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1414 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1421 desc->lli.ctlhi = (period_len >> reg_width);
1422 cdesc->desc[i] = desc;
1425 last->lli.llp = desc->txd.phys;
1430 /* Let's make a cyclic list */
1431 last->lli.llp = cdesc->desc[0]->txd.phys;
1433 dev_dbg(chan2dev(&dwc->chan),
1434 "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1435 &buf_addr, buf_len, period_len, periods);
1437 cdesc->periods = periods;
1444 dwc_desc_put(dwc, cdesc->desc[i]);
1448 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1449 return (struct dw_cyclic_desc *)retval;
1451 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1454 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1455 * @chan: the DMA channel to free
1457 void dw_dma_cyclic_free(struct dma_chan *chan)
1459 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1460 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1461 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1463 unsigned long flags;
1465 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1470 spin_lock_irqsave(&dwc->lock, flags);
1472 dwc_chan_disable(dw, dwc);
1474 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1475 dma_writel(dw, CLEAR.XFER, dwc->mask);
1477 spin_unlock_irqrestore(&dwc->lock, flags);
1479 for (i = 0; i < cdesc->periods; i++)
1480 dwc_desc_put(dwc, cdesc->desc[i]);
1485 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1487 EXPORT_SYMBOL(dw_dma_cyclic_free);
1489 /*----------------------------------------------------------------------*/
1491 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1495 unsigned int dw_params;
1496 unsigned int nr_channels;
1497 unsigned int max_blk_size = 0;
1501 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1505 dw->regs = chip->regs;
1508 pm_runtime_get_sync(chip->dev);
1510 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1511 autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1513 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1515 if (!pdata && autocfg) {
1516 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1522 /* Fill platform data with the default values */
1523 pdata->is_private = true;
1524 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1525 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1526 } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1532 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1534 nr_channels = pdata->nr_channels;
1536 dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan),
1543 /* Get hardware configuration parameters */
1545 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1547 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1548 for (i = 0; i < dw->nr_masters; i++) {
1550 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1553 dw->nr_masters = pdata->nr_masters;
1554 memcpy(dw->data_width, pdata->data_width, 4);
1557 /* Calculate all channel mask before DMA setup */
1558 dw->all_chan_mask = (1 << nr_channels) - 1;
1560 /* Force dma off, just in case */
1563 /* Disable BLOCK interrupts as well */
1564 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1566 /* Create a pool of consistent memory blocks for hardware descriptors */
1567 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1568 sizeof(struct dw_desc), 4, 0);
1569 if (!dw->desc_pool) {
1570 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1575 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1577 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1582 INIT_LIST_HEAD(&dw->dma.channels);
1583 for (i = 0; i < nr_channels; i++) {
1584 struct dw_dma_chan *dwc = &dw->chan[i];
1585 int r = nr_channels - i - 1;
1587 dwc->chan.device = &dw->dma;
1588 dma_cookie_init(&dwc->chan);
1589 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1590 list_add_tail(&dwc->chan.device_node,
1593 list_add(&dwc->chan.device_node, &dw->dma.channels);
1595 /* 7 is highest priority & 0 is lowest. */
1596 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1601 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1602 spin_lock_init(&dwc->lock);
1605 INIT_LIST_HEAD(&dwc->active_list);
1606 INIT_LIST_HEAD(&dwc->queue);
1607 INIT_LIST_HEAD(&dwc->free_list);
1609 channel_clear_bit(dw, CH_EN, dwc->mask);
1611 dwc->direction = DMA_TRANS_NONE;
1613 /* Hardware configuration */
1615 unsigned int dwc_params;
1616 void __iomem *addr = chip->regs + r * sizeof(u32);
1618 dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1620 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1624 * Decode maximum block size for given channel. The
1625 * stored 4 bit value represents blocks from 0x00 for 3
1626 * up to 0x0a for 4095.
1629 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1631 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1633 dwc->block_size = pdata->block_size;
1635 /* Check if channel supports multi block transfer */
1636 channel_writel(dwc, LLP, 0xfffffffc);
1638 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1639 channel_writel(dwc, LLP, 0);
1643 /* Clear all interrupts on all channels. */
1644 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1645 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1646 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1647 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1648 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1650 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1651 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1652 if (pdata->is_private)
1653 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1654 dw->dma.dev = chip->dev;
1655 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1656 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1658 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1660 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1661 dw->dma.device_control = dwc_control;
1663 dw->dma.device_tx_status = dwc_tx_status;
1664 dw->dma.device_issue_pending = dwc_issue_pending;
1666 err = dma_async_device_register(&dw->dma);
1668 goto err_dma_register;
1670 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1673 pm_runtime_put_sync_suspend(chip->dev);
1678 free_irq(chip->irq, dw);
1680 pm_runtime_put_sync_suspend(chip->dev);
1683 EXPORT_SYMBOL_GPL(dw_dma_probe);
1685 int dw_dma_remove(struct dw_dma_chip *chip)
1687 struct dw_dma *dw = chip->dw;
1688 struct dw_dma_chan *dwc, *_dwc;
1690 pm_runtime_get_sync(chip->dev);
1693 dma_async_device_unregister(&dw->dma);
1695 free_irq(chip->irq, dw);
1696 tasklet_kill(&dw->tasklet);
1698 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1700 list_del(&dwc->chan.device_node);
1701 channel_clear_bit(dw, CH_EN, dwc->mask);
1704 pm_runtime_put_sync_suspend(chip->dev);
1707 EXPORT_SYMBOL_GPL(dw_dma_remove);
1709 int dw_dma_disable(struct dw_dma_chip *chip)
1711 struct dw_dma *dw = chip->dw;
1716 EXPORT_SYMBOL_GPL(dw_dma_disable);
1718 int dw_dma_enable(struct dw_dma_chip *chip)
1720 struct dw_dma *dw = chip->dw;
1725 EXPORT_SYMBOL_GPL(dw_dma_enable);
1727 MODULE_LICENSE("GPL v2");
1728 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1729 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1730 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");