drivers/dma/dw/core.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  * Copyright (C) 2013 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/mm.h>
  24 #include <linux/module.h>
  25 #include <linux/slab.h>
  26
  27 #include "../dmaengine.h"
  28 #include "internal.h"
  29
  30 /*
  31  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  32  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  33  * of which use ARM any more).  See the "Databook" from Synopsys for
  34  * information beyond what licensees probably provide.
  35  *
  36  * The driver has currently been tested only with the Atmel AT32AP7000,
  37  * which does not support descriptor writeback.
  38  */
  39
  40 static inline bool is_request_line_unset(struct dw_dma_chan *dwc)
  41 {
  42         return dwc->request_line == (typeof(dwc->request_line))~0;
  43 }
  44
  45 static inline void dwc_set_masters(struct dw_dma_chan *dwc)
  46 {
  47         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
  48         struct dw_dma_slave *dws = dwc->chan.private;
  49         unsigned char mmax = dw->nr_masters - 1;
  50
  51         if (!is_request_line_unset(dwc))
  52                 return;
  53
  54         dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws));
  55         dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws));
  56 }
  57
  58 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  59                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  60                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  61                 bool _is_slave = is_slave_direction(_dwc->direction);   \
  62                 u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
  63                         DW_DMA_MSIZE_16;                        \
  64                 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
  65                         DW_DMA_MSIZE_16;                        \
  66                                                                 \
  67                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  68                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  69                  | DWC_CTLL_LLP_D_EN                            \
  70                  | DWC_CTLL_LLP_S_EN                            \
  71                  | DWC_CTLL_DMS(_dwc->dst_master)               \
  72                  | DWC_CTLL_SMS(_dwc->src_master));             \
  73         })
  74
  75 /*
  76  * Number of descriptors to allocate for each channel. This should be
  77  * made configurable somehow; preferably, the clients (at least the
  78  * ones using slave transfers) should be able to give us a hint.
  79  */
  80 #define NR_DESCS_PER_CHANNEL    64
  81
  82 /*----------------------------------------------------------------------*/
  83
  84 static struct device *chan2dev(struct dma_chan *chan)
  85 {
  86         return &chan->dev->device;
  87 }
  88
  89 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  90 {
  91         return to_dw_desc(dwc->active_list.next);
  92 }
  93
  94 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
  95 {
  96         struct dw_desc *desc, *_desc;
  97         struct dw_desc *ret = NULL;
  98         unsigned int i = 0;
  99         unsigned long flags;
 100
 101         spin_lock_irqsave(&dwc->lock, flags);
 102         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
 103                 i++;
 104                 if (async_tx_test_ack(&desc->txd)) {
 105                         list_del(&desc->desc_node);
 106                         ret = desc;
 107                         break;
 108                 }
 109                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
 110         }
 111         spin_unlock_irqrestore(&dwc->lock, flags);
 112
 113         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 114
 115         return ret;
 116 }
 117
 118 /*
 119  * Move a descriptor, including any children, to the free list.
 120  * `desc' must not be on any lists.
 121  */
 122 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 123 {
 124         unsigned long flags;
 125
 126         if (desc) {
 127                 struct dw_desc *child;
 128
 129                 spin_lock_irqsave(&dwc->lock, flags);
 130                 list_for_each_entry(child, &desc->tx_list, desc_node)
 131                         dev_vdbg(chan2dev(&dwc->chan),
 132                                         "moving child desc %p to freelist\n",
 133                                         child);
 134                 list_splice_init(&desc->tx_list, &dwc->free_list);
 135                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 136                 list_add(&desc->desc_node, &dwc->free_list);
 137                 spin_unlock_irqrestore(&dwc->lock, flags);
 138         }
 139 }
 140
 141 static void dwc_initialize(struct dw_dma_chan *dwc)
 142 {
 143         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 144         struct dw_dma_slave *dws = dwc->chan.private;
 145         u32 cfghi = DWC_CFGH_FIFO_MODE;
 146         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 147
 148         if (dwc->initialized == true)
 149                 return;
 150
 151         if (dws) {
 152                 /*
 153                  * We need controller-specific data to set up slave
 154                  * transfers.
 155                  */
 156                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 157
 158                 cfghi = dws->cfg_hi;
 159                 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
 160         } else {
 161                 if (dwc->direction == DMA_MEM_TO_DEV)
 162                         cfghi = DWC_CFGH_DST_PER(dwc->request_line);
 163                 else if (dwc->direction == DMA_DEV_TO_MEM)
 164                         cfghi = DWC_CFGH_SRC_PER(dwc->request_line);
 165         }
 166
 167         channel_writel(dwc, CFG_LO, cfglo);
 168         channel_writel(dwc, CFG_HI, cfghi);
 169
 170         /* Enable interrupts */
 171         channel_set_bit(dw, MASK.XFER, dwc->mask);
 172         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 173
 174         dwc->initialized = true;
 175 }
 176
 177 /*----------------------------------------------------------------------*/
 178
 179 static inline unsigned int dwc_fast_fls(unsigned long long v)
 180 {
 181         /*
 182          * We can be a lot more clever here, but this should take care
 183          * of the most common optimization.
 184          */
 185         if (!(v & 7))
 186                 return 3;
 187         else if (!(v & 3))
 188                 return 2;
 189         else if (!(v & 1))
 190                 return 1;
 191         return 0;
 192 }
 193
 194 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 195 {
 196         dev_err(chan2dev(&dwc->chan),
 197                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 198                 channel_readl(dwc, SAR),
 199                 channel_readl(dwc, DAR),
 200                 channel_readl(dwc, LLP),
 201                 channel_readl(dwc, CTL_HI),
 202                 channel_readl(dwc, CTL_LO));
 203 }
 204
 205 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 206 {
 207         channel_clear_bit(dw, CH_EN, dwc->mask);
 208         while (dma_readl(dw, CH_EN) & dwc->mask)
 209                 cpu_relax();
 210 }
 211
 212 /*----------------------------------------------------------------------*/
 213
 214 /* Perform single block transfer */
 215 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 216                                        struct dw_desc *desc)
 217 {
 218         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 219         u32             ctllo;
 220
 221         /*
 222          * Software emulation of LLP mode relies on interrupts to continue
 223          * multi block transfer.
 224          */
 225         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 226
 227         channel_writel(dwc, SAR, desc->lli.sar);
 228         channel_writel(dwc, DAR, desc->lli.dar);
 229         channel_writel(dwc, CTL_LO, ctllo);
 230         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 231         channel_set_bit(dw, CH_EN, dwc->mask);
 232
 233         /* Move pointer to next descriptor */
 234         dwc->tx_node_active = dwc->tx_node_active->next;
 235 }
 236
 237 /* Called with dwc->lock held and bh disabled */
 238 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 239 {
 240         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 241         unsigned long   was_soft_llp;
 242
 243         /* ASSERT:  channel is idle */
 244         if (dma_readl(dw, CH_EN) & dwc->mask) {
 245                 dev_err(chan2dev(&dwc->chan),
 246                         "BUG: Attempted to start non-idle channel\n");
 247                 dwc_dump_chan_regs(dwc);
 248
 249                 /* The tasklet will hopefully advance the queue... */
 250                 return;
 251         }
 252
 253         if (dwc->nollp) {
 254                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 255                                                 &dwc->flags);
 256                 if (was_soft_llp) {
 257                         dev_err(chan2dev(&dwc->chan),
 258                                 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
 259                         return;
 260                 }
 261
 262                 dwc_initialize(dwc);
 263
 264                 dwc->residue = first->total_len;
 265                 dwc->tx_node_active = &first->tx_list;
 266
 267                 /* Submit first block */
 268                 dwc_do_single_block(dwc, first);
 269
 270                 return;
 271         }
 272
 273         dwc_initialize(dwc);
 274
 275         channel_writel(dwc, LLP, first->txd.phys);
 276         channel_writel(dwc, CTL_LO,
 277                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 278         channel_writel(dwc, CTL_HI, 0);
 279         channel_set_bit(dw, CH_EN, dwc->mask);
 280 }
 281
 282 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
 283 {
 284         if (list_empty(&dwc->queue))
 285                 return;
 286
 287         list_move(dwc->queue.next, &dwc->active_list);
 288         dwc_dostart(dwc, dwc_first_active(dwc));
 289 }
 290
 291 /*----------------------------------------------------------------------*/
 292
 293 static void
 294 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 295                 bool callback_required)
 296 {
 297         dma_async_tx_callback           callback = NULL;
 298         void                            *param = NULL;
 299         struct dma_async_tx_descriptor  *txd = &desc->txd;
 300         struct dw_desc                  *child;
 301         unsigned long                   flags;
 302
 303         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 304
 305         spin_lock_irqsave(&dwc->lock, flags);
 306         dma_cookie_complete(txd);
 307         if (callback_required) {
 308                 callback = txd->callback;
 309                 param = txd->callback_param;
 310         }
 311
 312         /* async_tx_ack */
 313         list_for_each_entry(child, &desc->tx_list, desc_node)
 314                 async_tx_ack(&child->txd);
 315         async_tx_ack(&desc->txd);
 316
 317         list_splice_init(&desc->tx_list, &dwc->free_list);
 318         list_move(&desc->desc_node, &dwc->free_list);
 319
 320         dma_descriptor_unmap(txd);
 321         spin_unlock_irqrestore(&dwc->lock, flags);
 322
 323         if (callback)
 324                 callback(param);
 325 }
 326
 327 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 328 {
 329         struct dw_desc *desc, *_desc;
 330         LIST_HEAD(list);
 331         unsigned long flags;
 332
 333         spin_lock_irqsave(&dwc->lock, flags);
 334         if (dma_readl(dw, CH_EN) & dwc->mask) {
 335                 dev_err(chan2dev(&dwc->chan),
 336                         "BUG: XFER bit set, but channel not idle!\n");
 337
 338                 /* Try to continue after resetting the channel... */
 339                 dwc_chan_disable(dw, dwc);
 340         }
 341
 342         /*
 343          * Submit queued descriptors ASAP, i.e. before we go through
 344          * the completed ones.
 345          */
 346         list_splice_init(&dwc->active_list, &list);
 347         dwc_dostart_first_queued(dwc);
 348
 349         spin_unlock_irqrestore(&dwc->lock, flags);
 350
 351         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 352                 dwc_descriptor_complete(dwc, desc, true);
 353 }
 354
 355 /* Returns how many bytes were already received from source */
 356 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
 357 {
 358         u32 ctlhi = channel_readl(dwc, CTL_HI);
 359         u32 ctllo = channel_readl(dwc, CTL_LO);
 360
 361         return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
 362 }
 363
 364 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 365 {
 366         dma_addr_t llp;
 367         struct dw_desc *desc, *_desc;
 368         struct dw_desc *child;
 369         u32 status_xfer;
 370         unsigned long flags;
 371
 372         spin_lock_irqsave(&dwc->lock, flags);
 373         llp = channel_readl(dwc, LLP);
 374         status_xfer = dma_readl(dw, RAW.XFER);
 375
 376         if (status_xfer & dwc->mask) {
 377                 /* Everything we've submitted is done */
 378                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 379
 380                 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 381                         struct list_head *head, *active = dwc->tx_node_active;
 382
 383                         /*
 384                          * We are inside first active descriptor.
 385                          * Otherwise something is really wrong.
 386                          */
 387                         desc = dwc_first_active(dwc);
 388
 389                         head = &desc->tx_list;
 390                         if (active != head) {
 391                                 /* Update desc to reflect last sent one */
 392                                 if (active != head->next)
 393                                         desc = to_dw_desc(active->prev);
 394
 395                                 dwc->residue -= desc->len;
 396
 397                                 child = to_dw_desc(active);
 398
 399                                 /* Submit next block */
 400                                 dwc_do_single_block(dwc, child);
 401
 402                                 spin_unlock_irqrestore(&dwc->lock, flags);
 403                                 return;
 404                         }
 405
 406                         /* We are done here */
 407                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 408                 }
 409
 410                 dwc->residue = 0;
 411
 412                 spin_unlock_irqrestore(&dwc->lock, flags);
 413
 414                 dwc_complete_all(dw, dwc);
 415                 return;
 416         }
 417
 418         if (list_empty(&dwc->active_list)) {
 419                 dwc->residue = 0;
 420                 spin_unlock_irqrestore(&dwc->lock, flags);
 421                 return;
 422         }
 423
 424         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 425                 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
 426                 spin_unlock_irqrestore(&dwc->lock, flags);
 427                 return;
 428         }
 429
 430         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
 431
 432         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 433                 /* Initial residue value */
 434                 dwc->residue = desc->total_len;
 435
 436                 /* Check first descriptors addr */
 437                 if (desc->txd.phys == llp) {
 438                         spin_unlock_irqrestore(&dwc->lock, flags);
 439                         return;
 440                 }
 441
 442                 /* Check first descriptors llp */
 443                 if (desc->lli.llp == llp) {
 444                         /* This one is currently in progress */
 445                         dwc->residue -= dwc_get_sent(dwc);
 446                         spin_unlock_irqrestore(&dwc->lock, flags);
 447                         return;
 448                 }
 449
 450                 dwc->residue -= desc->len;
 451                 list_for_each_entry(child, &desc->tx_list, desc_node) {
 452                         if (child->lli.llp == llp) {
 453                                 /* Currently in progress */
 454                                 dwc->residue -= dwc_get_sent(dwc);
 455                                 spin_unlock_irqrestore(&dwc->lock, flags);
 456                                 return;
 457                         }
 458                         dwc->residue -= child->len;
 459                 }
 460
 461                 /*
 462                  * No descriptors so far seem to be in progress, i.e.
 463                  * this one must be done.
 464                  */
 465                 spin_unlock_irqrestore(&dwc->lock, flags);
 466                 dwc_descriptor_complete(dwc, desc, true);
 467                 spin_lock_irqsave(&dwc->lock, flags);
 468         }
 469
 470         dev_err(chan2dev(&dwc->chan),
 471                 "BUG: All descriptors done, but channel not idle!\n");
 472
 473         /* Try to continue after resetting the channel... */
 474         dwc_chan_disable(dw, dwc);
 475
 476         dwc_dostart_first_queued(dwc);
 477         spin_unlock_irqrestore(&dwc->lock, flags);
 478 }
 479
 480 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 481 {
 482         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 483                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 484 }
 485
 486 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 487 {
 488         struct dw_desc *bad_desc;
 489         struct dw_desc *child;
 490         unsigned long flags;
 491
 492         dwc_scan_descriptors(dw, dwc);
 493
 494         spin_lock_irqsave(&dwc->lock, flags);
 495
 496         /*
 497          * The descriptor currently at the head of the active list is
 498          * borked. Since we don't have any way to report errors, we'll
 499          * just have to scream loudly and try to carry on.
 500          */
 501         bad_desc = dwc_first_active(dwc);
 502         list_del_init(&bad_desc->desc_node);
 503         list_move(dwc->queue.next, dwc->active_list.prev);
 504
 505         /* Clear the error flag and try to restart the controller */
 506         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 507         if (!list_empty(&dwc->active_list))
 508                 dwc_dostart(dwc, dwc_first_active(dwc));
 509
 510         /*
 511          * WARN may seem harsh, but since this only happens
 512          * when someone submits a bad physical address in a
 513          * descriptor, we should consider ourselves lucky that the
 514          * controller flagged an error instead of scribbling over
 515          * random memory locations.
 516          */
 517         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 518                                        "  cookie: %d\n", bad_desc->txd.cookie);
 519         dwc_dump_lli(dwc, &bad_desc->lli);
 520         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 521                 dwc_dump_lli(dwc, &child->lli);
 522
 523         spin_unlock_irqrestore(&dwc->lock, flags);
 524
 525         /* Pretend the descriptor completed successfully */
 526         dwc_descriptor_complete(dwc, bad_desc, true);
 527 }
 528
 529 /* --------------------- Cyclic DMA API extensions -------------------- */
 530
 531 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 532 {
 533         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 534         return channel_readl(dwc, SAR);
 535 }
 536 EXPORT_SYMBOL(dw_dma_get_src_addr);
 537
 538 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 539 {
 540         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 541         return channel_readl(dwc, DAR);
 542 }
 543 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 544
 545 /* Called with dwc->lock held and all DMAC interrupts disabled */
 546 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 547                 u32 status_err, u32 status_xfer)
 548 {
 549         unsigned long flags;
 550
 551         if (dwc->mask) {
 552                 void (*callback)(void *param);
 553                 void *callback_param;
 554
 555                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 556                                 channel_readl(dwc, LLP));
 557
 558                 callback = dwc->cdesc->period_callback;
 559                 callback_param = dwc->cdesc->period_callback_param;
 560
 561                 if (callback)
 562                         callback(callback_param);
 563         }
 564
 565         /*
 566          * Error and transfer complete are highly unlikely, and will most
 567          * likely be due to a configuration error by the user.
 568          */
 569         if (unlikely(status_err & dwc->mask) ||
 570                         unlikely(status_xfer & dwc->mask)) {
 571                 int i;
 572
 573                 dev_err(chan2dev(&dwc->chan),
 574                         "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
 575                         status_xfer ? "xfer" : "error");
 576
 577                 spin_lock_irqsave(&dwc->lock, flags);
 578
 579                 dwc_dump_chan_regs(dwc);
 580
 581                 dwc_chan_disable(dw, dwc);
 582
 583                 /* Make sure DMA does not restart by loading a new list */
 584                 channel_writel(dwc, LLP, 0);
 585                 channel_writel(dwc, CTL_LO, 0);
 586                 channel_writel(dwc, CTL_HI, 0);
 587
 588                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 589                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 590
 591                 for (i = 0; i < dwc->cdesc->periods; i++)
 592                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 593
 594                 spin_unlock_irqrestore(&dwc->lock, flags);
 595         }
 596 }
 597
 598 /* ------------------------------------------------------------------------- */
 599
 600 static void dw_dma_tasklet(unsigned long data)
 601 {
 602         struct dw_dma *dw = (struct dw_dma *)data;
 603         struct dw_dma_chan *dwc;
 604         u32 status_xfer;
 605         u32 status_err;
 606         int i;
 607
 608         status_xfer = dma_readl(dw, RAW.XFER);
 609         status_err = dma_readl(dw, RAW.ERROR);
 610
 611         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 612
 613         for (i = 0; i < dw->dma.chancnt; i++) {
 614                 dwc = &dw->chan[i];
 615                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 616                         dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
 617                 else if (status_err & (1 << i))
 618                         dwc_handle_error(dw, dwc);
 619                 else if (status_xfer & (1 << i))
 620                         dwc_scan_descriptors(dw, dwc);
 621         }
 622
 623         /*
 624          * Re-enable interrupts.
 625          */
 626         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 627         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 628 }
 629
 630 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 631 {
 632         struct dw_dma *dw = dev_id;
 633         u32 status = dma_readl(dw, STATUS_INT);
 634
 635         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
 636
 637         /* Check if we have any interrupt from the DMAC */
 638         if (!status)
 639                 return IRQ_NONE;
 640
 641         /*
 642          * Just disable the interrupts. We'll turn them back on in the
 643          * softirq handler.
 644          */
 645         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 646         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 647
 648         status = dma_readl(dw, STATUS_INT);
 649         if (status) {
 650                 dev_err(dw->dma.dev,
 651                         "BUG: Unexpected interrupts pending: 0x%x\n",
 652                         status);
 653
 654                 /* Try to recover */
 655                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 656                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 657                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 658                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 659         }
 660
 661         tasklet_schedule(&dw->tasklet);
 662
 663         return IRQ_HANDLED;
 664 }
 665
 666 /*----------------------------------------------------------------------*/
 667
 668 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 669 {
 670         struct dw_desc          *desc = txd_to_dw_desc(tx);
 671         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 672         dma_cookie_t            cookie;
 673         unsigned long           flags;
 674
 675         spin_lock_irqsave(&dwc->lock, flags);
 676         cookie = dma_cookie_assign(tx);
 677
 678         /*
 679          * REVISIT: We should attempt to chain as many descriptors as
 680          * possible, perhaps even appending to those already submitted
 681          * for DMA. But this is hard to do in a race-free manner.
 682          */
 683
 684         dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
 685         list_add_tail(&desc->desc_node, &dwc->queue);
 686
 687         spin_unlock_irqrestore(&dwc->lock, flags);
 688
 689         return cookie;
 690 }
 691
 692 static struct dma_async_tx_descriptor *
 693 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 694                 size_t len, unsigned long flags)
 695 {
 696         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 697         struct dw_dma           *dw = to_dw_dma(chan->device);
 698         struct dw_desc          *desc;
 699         struct dw_desc          *first;
 700         struct dw_desc          *prev;
 701         size_t                  xfer_count;
 702         size_t                  offset;
 703         unsigned int            src_width;
 704         unsigned int            dst_width;
 705         unsigned int            data_width;
 706         u32                     ctllo;
 707
 708         dev_vdbg(chan2dev(chan),
 709                         "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
 710                         &dest, &src, len, flags);
 711
 712         if (unlikely(!len)) {
 713                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 714                 return NULL;
 715         }
 716
 717         dwc->direction = DMA_MEM_TO_MEM;
 718
 719         data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
 720                            dw->data_width[dwc->dst_master]);
 721
 722         src_width = dst_width = min_t(unsigned int, data_width,
 723                                       dwc_fast_fls(src | dest | len));
 724
 725         ctllo = DWC_DEFAULT_CTLLO(chan)
 726                         | DWC_CTLL_DST_WIDTH(dst_width)
 727                         | DWC_CTLL_SRC_WIDTH(src_width)
 728                         | DWC_CTLL_DST_INC
 729                         | DWC_CTLL_SRC_INC
 730                         | DWC_CTLL_FC_M2M;
 731         prev = first = NULL;
 732
 733         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 734                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 735                                            dwc->block_size);
 736
 737                 desc = dwc_desc_get(dwc);
 738                 if (!desc)
 739                         goto err_desc_get;
 740
 741                 desc->lli.sar = src + offset;
 742                 desc->lli.dar = dest + offset;
 743                 desc->lli.ctllo = ctllo;
 744                 desc->lli.ctlhi = xfer_count;
 745                 desc->len = xfer_count << src_width;
 746
 747                 if (!first) {
 748                         first = desc;
 749                 } else {
 750                         prev->lli.llp = desc->txd.phys;
 751                         list_add_tail(&desc->desc_node,
 752                                         &first->tx_list);
 753                 }
 754                 prev = desc;
 755         }
 756
 757         if (flags & DMA_PREP_INTERRUPT)
 758                 /* Trigger interrupt after last block */
 759                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 760
 761         prev->lli.llp = 0;
 762         first->txd.flags = flags;
 763         first->total_len = len;
 764
 765         return &first->txd;
 766
 767 err_desc_get:
 768         dwc_desc_put(dwc, first);
 769         return NULL;
 770 }
 771
 772 static struct dma_async_tx_descriptor *
 773 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 774                 unsigned int sg_len, enum dma_transfer_direction direction,
 775                 unsigned long flags, void *context)
 776 {
 777         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 778         struct dw_dma           *dw = to_dw_dma(chan->device);
 779         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 780         struct dw_desc          *prev;
 781         struct dw_desc          *first;
 782         u32                     ctllo;
 783         dma_addr_t              reg;
 784         unsigned int            reg_width;
 785         unsigned int            mem_width;
 786         unsigned int            data_width;
 787         unsigned int            i;
 788         struct scatterlist      *sg;
 789         size_t                  total_len = 0;
 790
 791         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 792
 793         if (unlikely(!is_slave_direction(direction) || !sg_len))
 794                 return NULL;
 795
 796         dwc->direction = direction;
 797
 798         prev = first = NULL;
 799
 800         switch (direction) {
 801         case DMA_MEM_TO_DEV:
 802                 reg_width = __fls(sconfig->dst_addr_width);
 803                 reg = sconfig->dst_addr;
 804                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 805                                 | DWC_CTLL_DST_WIDTH(reg_width)
 806                                 | DWC_CTLL_DST_FIX
 807                                 | DWC_CTLL_SRC_INC);
 808
 809                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 810                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 811
 812                 data_width = dw->data_width[dwc->src_master];
 813
 814                 for_each_sg(sgl, sg, sg_len, i) {
 815                         struct dw_desc  *desc;
 816                         u32             len, dlen, mem;
 817
 818                         mem = sg_dma_address(sg);
 819                         len = sg_dma_len(sg);
 820
 821                         mem_width = min_t(unsigned int,
 822                                           data_width, dwc_fast_fls(mem | len));
 823
 824 slave_sg_todev_fill_desc:
 825                         desc = dwc_desc_get(dwc);
 826                         if (!desc) {
 827                                 dev_err(chan2dev(chan),
 828                                         "not enough descriptors available\n");
 829                                 goto err_desc_get;
 830                         }
 831
 832                         desc->lli.sar = mem;
 833                         desc->lli.dar = reg;
 834                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 835                         if ((len >> mem_width) > dwc->block_size) {
 836                                 dlen = dwc->block_size << mem_width;
 837                                 mem += dlen;
 838                                 len -= dlen;
 839                         } else {
 840                                 dlen = len;
 841                                 len = 0;
 842                         }
 843
 844                         desc->lli.ctlhi = dlen >> mem_width;
 845                         desc->len = dlen;
 846
 847                         if (!first) {
 848                                 first = desc;
 849                         } else {
 850                                 prev->lli.llp = desc->txd.phys;
 851                                 list_add_tail(&desc->desc_node,
 852                                                 &first->tx_list);
 853                         }
 854                         prev = desc;
 855                         total_len += dlen;
 856
 857                         if (len)
 858                                 goto slave_sg_todev_fill_desc;
 859                 }
 860                 break;
 861         case DMA_DEV_TO_MEM:
 862                 reg_width = __fls(sconfig->src_addr_width);
 863                 reg = sconfig->src_addr;
 864                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 865                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 866                                 | DWC_CTLL_DST_INC
 867                                 | DWC_CTLL_SRC_FIX);
 868
 869                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 870                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 871
 872                 data_width = dw->data_width[dwc->dst_master];
 873
 874                 for_each_sg(sgl, sg, sg_len, i) {
 875                         struct dw_desc  *desc;
 876                         u32             len, dlen, mem;
 877
 878                         mem = sg_dma_address(sg);
 879                         len = sg_dma_len(sg);
 880
 881                         mem_width = min_t(unsigned int,
 882                                           data_width, dwc_fast_fls(mem | len));
 883
 884 slave_sg_fromdev_fill_desc:
 885                         desc = dwc_desc_get(dwc);
 886                         if (!desc) {
 887                                 dev_err(chan2dev(chan),
 888                                                 "not enough descriptors available\n");
 889                                 goto err_desc_get;
 890                         }
 891
 892                         desc->lli.sar = reg;
 893                         desc->lli.dar = mem;
 894                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 895                         if ((len >> reg_width) > dwc->block_size) {
 896                                 dlen = dwc->block_size << reg_width;
 897                                 mem += dlen;
 898                                 len -= dlen;
 899                         } else {
 900                                 dlen = len;
 901                                 len = 0;
 902                         }
 903                         desc->lli.ctlhi = dlen >> reg_width;
 904                         desc->len = dlen;
 905
 906                         if (!first) {
 907                                 first = desc;
 908                         } else {
 909                                 prev->lli.llp = desc->txd.phys;
 910                                 list_add_tail(&desc->desc_node,
 911                                                 &first->tx_list);
 912                         }
 913                         prev = desc;
 914                         total_len += dlen;
 915
 916                         if (len)
 917                                 goto slave_sg_fromdev_fill_desc;
 918                 }
 919                 break;
 920         default:
 921                 return NULL;
 922         }
 923
 924         if (flags & DMA_PREP_INTERRUPT)
 925                 /* Trigger interrupt after last block */
 926                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 927
 928         prev->lli.llp = 0;
 929         first->total_len = total_len;
 930
 931         return &first->txd;
 932
 933 err_desc_get:
 934         dwc_desc_put(dwc, first);
 935         return NULL;
 936 }
 937
 938 /*
 939  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 940  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 941  *
 942  * NOTE: burst size 2 is not supported by controller.
 943  *
 944  * This can be done by finding least significant bit set: n & (n - 1)
 945  */
 946 static inline void convert_burst(u32 *maxburst)
 947 {
 948         if (*maxburst > 1)
 949                 *maxburst = fls(*maxburst) - 2;
 950         else
 951                 *maxburst = 0;
 952 }
 953
 954 static int
 955 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 956 {
 957         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 958
 959         /* Check if chan will be configured for slave transfers */
 960         if (!is_slave_direction(sconfig->direction))
 961                 return -EINVAL;
 962
 963         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 964         dwc->direction = sconfig->direction;
 965
 966         /* Take the request line from slave_id member */
 967         if (is_request_line_unset(dwc))
 968                 dwc->request_line = sconfig->slave_id;
 969
 970         convert_burst(&dwc->dma_sconfig.src_maxburst);
 971         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 972
 973         return 0;
 974 }
 975
 976 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
 977 {
 978         u32 cfglo = channel_readl(dwc, CFG_LO);
 979         unsigned int count = 20;        /* timeout iterations */
 980
 981         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
 982         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
 983                 udelay(2);
 984
 985         dwc->paused = true;
 986 }
 987
 988 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
 989 {
 990         u32 cfglo = channel_readl(dwc, CFG_LO);
 991
 992         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
 993
 994         dwc->paused = false;
 995 }
 996
 997 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 998                        unsigned long arg)
 999 {
1000         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1001         struct dw_dma           *dw = to_dw_dma(chan->device);
1002         struct dw_desc          *desc, *_desc;
1003         unsigned long           flags;
1004         LIST_HEAD(list);
1005
1006         if (cmd == DMA_PAUSE) {
1007                 spin_lock_irqsave(&dwc->lock, flags);
1008
1009                 dwc_chan_pause(dwc);
1010
1011                 spin_unlock_irqrestore(&dwc->lock, flags);
1012         } else if (cmd == DMA_RESUME) {
1013                 if (!dwc->paused)
1014                         return 0;
1015
1016                 spin_lock_irqsave(&dwc->lock, flags);
1017
1018                 dwc_chan_resume(dwc);
1019
1020                 spin_unlock_irqrestore(&dwc->lock, flags);
1021         } else if (cmd == DMA_TERMINATE_ALL) {
1022                 spin_lock_irqsave(&dwc->lock, flags);
1023
1024                 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1025
1026                 dwc_chan_disable(dw, dwc);
1027
1028                 dwc_chan_resume(dwc);
1029
1030                 /* active_list entries will end up before queued entries */
1031                 list_splice_init(&dwc->queue, &list);
1032                 list_splice_init(&dwc->active_list, &list);
1033
1034                 spin_unlock_irqrestore(&dwc->lock, flags);
1035
1036                 /* Flush all pending and queued descriptors */
1037                 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1038                         dwc_descriptor_complete(dwc, desc, false);
1039         } else if (cmd == DMA_SLAVE_CONFIG) {
1040                 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1041         } else {
1042                 return -ENXIO;
1043         }
1044
1045         return 0;
1046 }
1047
1048 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1049 {
1050         unsigned long flags;
1051         u32 residue;
1052
1053         spin_lock_irqsave(&dwc->lock, flags);
1054
1055         residue = dwc->residue;
1056         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1057                 residue -= dwc_get_sent(dwc);
1058
1059         spin_unlock_irqrestore(&dwc->lock, flags);
1060         return residue;
1061 }
1062
1063 static enum dma_status
1064 dwc_tx_status(struct dma_chan *chan,
1065               dma_cookie_t cookie,
1066               struct dma_tx_state *txstate)
1067 {
1068         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1069         enum dma_status         ret;
1070
1071         ret = dma_cookie_status(chan, cookie, txstate);
1072         if (ret == DMA_COMPLETE)
1073                 return ret;
1074
1075         dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1076
1077         ret = dma_cookie_status(chan, cookie, txstate);
1078         if (ret != DMA_COMPLETE)
1079                 dma_set_residue(txstate, dwc_get_residue(dwc));
1080
1081         if (dwc->paused && ret == DMA_IN_PROGRESS)
1082                 return DMA_PAUSED;
1083
1084         return ret;
1085 }
1086
1087 static void dwc_issue_pending(struct dma_chan *chan)
1088 {
1089         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1090         unsigned long           flags;
1091
1092         spin_lock_irqsave(&dwc->lock, flags);
1093         if (list_empty(&dwc->active_list))
1094                 dwc_dostart_first_queued(dwc);
1095         spin_unlock_irqrestore(&dwc->lock, flags);
1096 }
1097
1098 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1099 {
1100         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1101         struct dw_dma           *dw = to_dw_dma(chan->device);
1102         struct dw_desc          *desc;
1103         int                     i;
1104         unsigned long           flags;
1105
1106         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1107
1108         /* ASSERT:  channel is idle */
1109         if (dma_readl(dw, CH_EN) & dwc->mask) {
1110                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1111                 return -EIO;
1112         }
1113
1114         dma_cookie_init(chan);
1115
1116         /*
1117          * NOTE: some controllers may have additional features that we
1118          * need to initialize here, like "scatter-gather" (which
1119          * doesn't mean what you think it means), and status writeback.
1120          */
1121
1122         dwc_set_masters(dwc);
1123
1124         spin_lock_irqsave(&dwc->lock, flags);
1125         i = dwc->descs_allocated;
1126         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1127                 dma_addr_t phys;
1128
1129                 spin_unlock_irqrestore(&dwc->lock, flags);
1130
1131                 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1132                 if (!desc)
1133                         goto err_desc_alloc;
1134
1135                 memset(desc, 0, sizeof(struct dw_desc));
1136
1137                 INIT_LIST_HEAD(&desc->tx_list);
1138                 dma_async_tx_descriptor_init(&desc->txd, chan);
1139                 desc->txd.tx_submit = dwc_tx_submit;
1140                 desc->txd.flags = DMA_CTRL_ACK;
1141                 desc->txd.phys = phys;
1142
1143                 dwc_desc_put(dwc, desc);
1144
1145                 spin_lock_irqsave(&dwc->lock, flags);
1146                 i = ++dwc->descs_allocated;
1147         }
1148
1149         spin_unlock_irqrestore(&dwc->lock, flags);
1150
1151         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1152
1153         return i;
1154
1155 err_desc_alloc:
1156         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1157
1158         return i;
1159 }
1160
1161 static void dwc_free_chan_resources(struct dma_chan *chan)
1162 {
1163         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1164         struct dw_dma           *dw = to_dw_dma(chan->device);
1165         struct dw_desc          *desc, *_desc;
1166         unsigned long           flags;
1167         LIST_HEAD(list);
1168
1169         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1170                         dwc->descs_allocated);
1171
1172         /* ASSERT:  channel is idle */
1173         BUG_ON(!list_empty(&dwc->active_list));
1174         BUG_ON(!list_empty(&dwc->queue));
1175         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1176
1177         spin_lock_irqsave(&dwc->lock, flags);
1178         list_splice_init(&dwc->free_list, &list);
1179         dwc->descs_allocated = 0;
1180         dwc->initialized = false;
1181         dwc->request_line = ~0;
1182
1183         /* Disable interrupts */
1184         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1185         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1186
1187         spin_unlock_irqrestore(&dwc->lock, flags);
1188
1189         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1190                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1191                 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1192         }
1193
1194         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1195 }
1196
1197 /* --------------------- Cyclic DMA API extensions -------------------- */
1198
1199 /**
1200  * dw_dma_cyclic_start - start the cyclic DMA transfer
1201  * @chan: the DMA channel to start
1202  *
1203  * Must be called with soft interrupts disabled. Returns zero on success or
1204  * -errno on failure.
1205  */
1206 int dw_dma_cyclic_start(struct dma_chan *chan)
1207 {
1208         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1209         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1210         unsigned long           flags;
1211
1212         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1213                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1214                 return -ENODEV;
1215         }
1216
1217         spin_lock_irqsave(&dwc->lock, flags);
1218
1219         /* Assert channel is idle */
1220         if (dma_readl(dw, CH_EN) & dwc->mask) {
1221                 dev_err(chan2dev(&dwc->chan),
1222                         "BUG: Attempted to start non-idle channel\n");
1223                 dwc_dump_chan_regs(dwc);
1224                 spin_unlock_irqrestore(&dwc->lock, flags);
1225                 return -EBUSY;
1226         }
1227
1228         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1229         dma_writel(dw, CLEAR.XFER, dwc->mask);
1230
1231         /* Setup DMAC channel registers */
1232         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1233         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1234         channel_writel(dwc, CTL_HI, 0);
1235
1236         channel_set_bit(dw, CH_EN, dwc->mask);
1237
1238         spin_unlock_irqrestore(&dwc->lock, flags);
1239
1240         return 0;
1241 }
1242 EXPORT_SYMBOL(dw_dma_cyclic_start);
1243
1244 /**
1245  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1246  * @chan: the DMA channel to stop
1247  *
1248  * Must be called with soft interrupts disabled.
1249  */
1250 void dw_dma_cyclic_stop(struct dma_chan *chan)
1251 {
1252         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1253         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1254         unsigned long           flags;
1255
1256         spin_lock_irqsave(&dwc->lock, flags);
1257
1258         dwc_chan_disable(dw, dwc);
1259
1260         spin_unlock_irqrestore(&dwc->lock, flags);
1261 }
1262 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1263
1264 /**
1265  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1266  * @chan: the DMA channel to prepare
1267  * @buf_addr: physical DMA address where the buffer starts
1268  * @buf_len: total number of bytes for the entire buffer
1269  * @period_len: number of bytes for each period
1270  * @direction: transfer direction, to or from device
1271  *
1272  * Must be called before trying to start the transfer. Returns a valid struct
1273  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1274  */
1275 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1276                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1277                 enum dma_transfer_direction direction)
1278 {
1279         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1280         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1281         struct dw_cyclic_desc           *cdesc;
1282         struct dw_cyclic_desc           *retval = NULL;
1283         struct dw_desc                  *desc;
1284         struct dw_desc                  *last = NULL;
1285         unsigned long                   was_cyclic;
1286         unsigned int                    reg_width;
1287         unsigned int                    periods;
1288         unsigned int                    i;
1289         unsigned long                   flags;
1290
1291         spin_lock_irqsave(&dwc->lock, flags);
1292         if (dwc->nollp) {
1293                 spin_unlock_irqrestore(&dwc->lock, flags);
1294                 dev_dbg(chan2dev(&dwc->chan),
1295                                 "channel doesn't support LLP transfers\n");
1296                 return ERR_PTR(-EINVAL);
1297         }
1298
1299         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1300                 spin_unlock_irqrestore(&dwc->lock, flags);
1301                 dev_dbg(chan2dev(&dwc->chan),
1302                                 "queue and/or active list are not empty\n");
1303                 return ERR_PTR(-EBUSY);
1304         }
1305
1306         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1307         spin_unlock_irqrestore(&dwc->lock, flags);
1308         if (was_cyclic) {
1309                 dev_dbg(chan2dev(&dwc->chan),
1310                                 "channel already prepared for cyclic DMA\n");
1311                 return ERR_PTR(-EBUSY);
1312         }
1313
1314         retval = ERR_PTR(-EINVAL);
1315
1316         if (unlikely(!is_slave_direction(direction)))
1317                 goto out_err;
1318
1319         dwc->direction = direction;
1320
1321         if (direction == DMA_MEM_TO_DEV)
1322                 reg_width = __ffs(sconfig->dst_addr_width);
1323         else
1324                 reg_width = __ffs(sconfig->src_addr_width);
1325
1326         periods = buf_len / period_len;
1327
1328         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1329         if (period_len > (dwc->block_size << reg_width))
1330                 goto out_err;
1331         if (unlikely(period_len & ((1 << reg_width) - 1)))
1332                 goto out_err;
1333         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1334                 goto out_err;
1335
1336         retval = ERR_PTR(-ENOMEM);
1337
1338         if (periods > NR_DESCS_PER_CHANNEL)
1339                 goto out_err;
1340
1341         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1342         if (!cdesc)
1343                 goto out_err;
1344
1345         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1346         if (!cdesc->desc)
1347                 goto out_err_alloc;
1348
1349         for (i = 0; i < periods; i++) {
1350                 desc = dwc_desc_get(dwc);
1351                 if (!desc)
1352                         goto out_err_desc_get;
1353
1354                 switch (direction) {
1355                 case DMA_MEM_TO_DEV:
1356                         desc->lli.dar = sconfig->dst_addr;
1357                         desc->lli.sar = buf_addr + (period_len * i);
1358                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1359                                         | DWC_CTLL_DST_WIDTH(reg_width)
1360                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1361                                         | DWC_CTLL_DST_FIX
1362                                         | DWC_CTLL_SRC_INC
1363                                         | DWC_CTLL_INT_EN);
1364
1365                         desc->lli.ctllo |= sconfig->device_fc ?
1366                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1367                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1368
1369                         break;
1370                 case DMA_DEV_TO_MEM:
1371                         desc->lli.dar = buf_addr + (period_len * i);
1372                         desc->lli.sar = sconfig->src_addr;
1373                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1374                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1375                                         | DWC_CTLL_DST_WIDTH(reg_width)
1376                                         | DWC_CTLL_DST_INC
1377                                         | DWC_CTLL_SRC_FIX
1378                                         | DWC_CTLL_INT_EN);
1379
1380                         desc->lli.ctllo |= sconfig->device_fc ?
1381                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1382                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1383
1384                         break;
1385                 default:
1386                         break;
1387                 }
1388
1389                 desc->lli.ctlhi = (period_len >> reg_width);
1390                 cdesc->desc[i] = desc;
1391
1392                 if (last)
1393                         last->lli.llp = desc->txd.phys;
1394
1395                 last = desc;
1396         }
1397
1398         /* Let's make a cyclic list */
1399         last->lli.llp = cdesc->desc[0]->txd.phys;
1400
1401         dev_dbg(chan2dev(&dwc->chan),
1402                         "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1403                         &buf_addr, buf_len, period_len, periods);
1404
1405         cdesc->periods = periods;
1406         dwc->cdesc = cdesc;
1407
1408         return cdesc;
1409
1410 out_err_desc_get:
1411         while (i--)
1412                 dwc_desc_put(dwc, cdesc->desc[i]);
1413 out_err_alloc:
1414         kfree(cdesc);
1415 out_err:
1416         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1417         return (struct dw_cyclic_desc *)retval;
1418 }
1419 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1420
1421 /**
1422  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1423  * @chan: the DMA channel to free
1424  */
1425 void dw_dma_cyclic_free(struct dma_chan *chan)
1426 {
1427         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1428         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1429         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1430         int                     i;
1431         unsigned long           flags;
1432
1433         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1434
1435         if (!cdesc)
1436                 return;
1437
1438         spin_lock_irqsave(&dwc->lock, flags);
1439
1440         dwc_chan_disable(dw, dwc);
1441
1442         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1443         dma_writel(dw, CLEAR.XFER, dwc->mask);
1444
1445         spin_unlock_irqrestore(&dwc->lock, flags);
1446
1447         for (i = 0; i < cdesc->periods; i++)
1448                 dwc_desc_put(dwc, cdesc->desc[i]);
1449
1450         kfree(cdesc->desc);
1451         kfree(cdesc);
1452
1453         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1454 }
1455 EXPORT_SYMBOL(dw_dma_cyclic_free);
1456
1457 /*----------------------------------------------------------------------*/
1458
1459 static void dw_dma_off(struct dw_dma *dw)
1460 {
1461         int i;
1462
1463         dma_writel(dw, CFG, 0);
1464
1465         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1466         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1467         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1468         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1469
1470         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1471                 cpu_relax();
1472
1473         for (i = 0; i < dw->dma.chancnt; i++)
1474                 dw->chan[i].initialized = false;
1475 }
1476
1477 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1478 {
1479         struct dw_dma           *dw;
1480         size_t                  size;
1481         bool                    autocfg;
1482         unsigned int            dw_params;
1483         unsigned int            nr_channels;
1484         unsigned int            max_blk_size = 0;
1485         int                     err;
1486         int                     i;
1487
1488         dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1489         autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1490
1491         dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1492
1493         if (!pdata && autocfg) {
1494                 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1495                 if (!pdata)
1496                         return -ENOMEM;
1497
1498                 /* Fill platform data with the default values */
1499                 pdata->is_private = true;
1500                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1501                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1502         } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1503                 return -EINVAL;
1504
1505         if (autocfg)
1506                 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1507         else
1508                 nr_channels = pdata->nr_channels;
1509
1510         size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1511         dw = devm_kzalloc(chip->dev, size, GFP_KERNEL);
1512         if (!dw)
1513                 return -ENOMEM;
1514
1515         dw->clk = devm_clk_get(chip->dev, "hclk");
1516         if (IS_ERR(dw->clk))
1517                 return PTR_ERR(dw->clk);
1518         clk_prepare_enable(dw->clk);
1519
1520         dw->regs = chip->regs;
1521         chip->dw = dw;
1522
1523         /* Get hardware configuration parameters */
1524         if (autocfg) {
1525                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1526
1527                 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1528                 for (i = 0; i < dw->nr_masters; i++) {
1529                         dw->data_width[i] =
1530                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1531                 }
1532         } else {
1533                 dw->nr_masters = pdata->nr_masters;
1534                 memcpy(dw->data_width, pdata->data_width, 4);
1535         }
1536
1537         /* Calculate all channel mask before DMA setup */
1538         dw->all_chan_mask = (1 << nr_channels) - 1;
1539
1540         /* Force dma off, just in case */
1541         dw_dma_off(dw);
1542
1543         /* Disable BLOCK interrupts as well */
1544         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1545
1546         /* Create a pool of consistent memory blocks for hardware descriptors */
1547         dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1548                                          sizeof(struct dw_desc), 4, 0);
1549         if (!dw->desc_pool) {
1550                 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1551                 return -ENOMEM;
1552         }
1553
1554         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1555
1556         err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1557                           "dw_dmac", dw);
1558         if (err)
1559                 return err;
1560
1561         INIT_LIST_HEAD(&dw->dma.channels);
1562         for (i = 0; i < nr_channels; i++) {
1563                 struct dw_dma_chan      *dwc = &dw->chan[i];
1564                 int                     r = nr_channels - i - 1;
1565
1566                 dwc->chan.device = &dw->dma;
1567                 dma_cookie_init(&dwc->chan);
1568                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1569                         list_add_tail(&dwc->chan.device_node,
1570                                         &dw->dma.channels);
1571                 else
1572                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1573
1574                 /* 7 is highest priority & 0 is lowest. */
1575                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1576                         dwc->priority = r;
1577                 else
1578                         dwc->priority = i;
1579
1580                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1581                 spin_lock_init(&dwc->lock);
1582                 dwc->mask = 1 << i;
1583
1584                 INIT_LIST_HEAD(&dwc->active_list);
1585                 INIT_LIST_HEAD(&dwc->queue);
1586                 INIT_LIST_HEAD(&dwc->free_list);
1587
1588                 channel_clear_bit(dw, CH_EN, dwc->mask);
1589
1590                 dwc->direction = DMA_TRANS_NONE;
1591                 dwc->request_line = ~0;
1592
1593                 /* Hardware configuration */
1594                 if (autocfg) {
1595                         unsigned int dwc_params;
1596                         void __iomem *addr = chip->regs + r * sizeof(u32);
1597
1598                         dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1599
1600                         dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1601                                            dwc_params);
1602
1603                         /*
1604                          * Decode maximum block size for given channel. The
1605                          * stored 4 bit value represents blocks from 0x00 for 3
1606                          * up to 0x0a for 4095.
1607                          */
1608                         dwc->block_size =
1609                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1610                         dwc->nollp =
1611                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1612                 } else {
1613                         dwc->block_size = pdata->block_size;
1614
1615                         /* Check if channel supports multi block transfer */
1616                         channel_writel(dwc, LLP, 0xfffffffc);
1617                         dwc->nollp =
1618                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1619                         channel_writel(dwc, LLP, 0);
1620                 }
1621         }
1622
1623         /* Clear all interrupts on all channels. */
1624         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1625         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1626         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1627         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1628         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1629
1630         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1631         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1632         if (pdata->is_private)
1633                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1634         dw->dma.dev = chip->dev;
1635         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1636         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1637
1638         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1639
1640         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1641         dw->dma.device_control = dwc_control;
1642
1643         dw->dma.device_tx_status = dwc_tx_status;
1644         dw->dma.device_issue_pending = dwc_issue_pending;
1645
1646         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1647
1648         dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1649                  nr_channels);
1650
1651         dma_async_device_register(&dw->dma);
1652
1653         return 0;
1654 }
1655 EXPORT_SYMBOL_GPL(dw_dma_probe);
1656
1657 int dw_dma_remove(struct dw_dma_chip *chip)
1658 {
1659         struct dw_dma           *dw = chip->dw;
1660         struct dw_dma_chan      *dwc, *_dwc;
1661
1662         dw_dma_off(dw);
1663         dma_async_device_unregister(&dw->dma);
1664
1665         free_irq(chip->irq, dw);
1666         tasklet_kill(&dw->tasklet);
1667
1668         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1669                         chan.device_node) {
1670                 list_del(&dwc->chan.device_node);
1671                 channel_clear_bit(dw, CH_EN, dwc->mask);
1672         }
1673
1674         return 0;
1675 }
1676 EXPORT_SYMBOL_GPL(dw_dma_remove);
1677
1678 void dw_dma_shutdown(struct dw_dma_chip *chip)
1679 {
1680         struct dw_dma *dw = chip->dw;
1681
1682         dw_dma_off(dw);
1683         clk_disable_unprepare(dw->clk);
1684 }
1685 EXPORT_SYMBOL_GPL(dw_dma_shutdown);
1686
1687 #ifdef CONFIG_PM_SLEEP
1688
1689 int dw_dma_suspend(struct dw_dma_chip *chip)
1690 {
1691         struct dw_dma *dw = chip->dw;
1692
1693         dw_dma_off(dw);
1694         clk_disable_unprepare(dw->clk);
1695
1696         return 0;
1697 }
1698 EXPORT_SYMBOL_GPL(dw_dma_suspend);
1699
1700 int dw_dma_resume(struct dw_dma_chip *chip)
1701 {
1702         struct dw_dma *dw = chip->dw;
1703
1704         clk_prepare_enable(dw->clk);
1705         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1706
1707         return 0;
1708 }
1709 EXPORT_SYMBOL_GPL(dw_dma_resume);
1710
1711 #endif /* CONFIG_PM_SLEEP */
1712
1713 MODULE_LICENSE("GPL v2");
1714 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1715 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1716 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");