2 * Core driver for the Synopsys DesignWare DMA Controller
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
6 * Copyright (C) 2013 Intel Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/bitops.h>
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/dmaengine.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/dmapool.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
27 #include "../dmaengine.h"
31 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
33 * of which use ARM any more). See the "Databook" from Synopsys for
34 * information beyond what licensees probably provide.
36 * The driver has currently been tested only with the Atmel AT32AP7000,
37 * which does not support descriptor writeback.
40 static inline bool is_request_line_unset(struct dw_dma_chan *dwc)
42 return dwc->request_line == (typeof(dwc->request_line))~0;
45 static inline void dwc_set_masters(struct dw_dma_chan *dwc)
47 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
48 struct dw_dma_slave *dws = dwc->chan.private;
49 unsigned char mmax = dw->nr_masters - 1;
51 if (!is_request_line_unset(dwc))
54 dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws));
55 dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws));
58 #define DWC_DEFAULT_CTLLO(_chan) ({ \
59 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
60 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
61 bool _is_slave = is_slave_direction(_dwc->direction); \
62 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
64 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
67 (DWC_CTLL_DST_MSIZE(_dmsize) \
68 | DWC_CTLL_SRC_MSIZE(_smsize) \
71 | DWC_CTLL_DMS(_dwc->dst_master) \
72 | DWC_CTLL_SMS(_dwc->src_master)); \
76 * Number of descriptors to allocate for each channel. This should be
77 * made configurable somehow; preferably, the clients (at least the
78 * ones using slave transfers) should be able to give us a hint.
80 #define NR_DESCS_PER_CHANNEL 64
82 /*----------------------------------------------------------------------*/
84 static struct device *chan2dev(struct dma_chan *chan)
86 return &chan->dev->device;
89 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
91 return to_dw_desc(dwc->active_list.next);
94 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
96 struct dw_desc *desc, *_desc;
97 struct dw_desc *ret = NULL;
101 spin_lock_irqsave(&dwc->lock, flags);
102 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
104 if (async_tx_test_ack(&desc->txd)) {
105 list_del(&desc->desc_node);
109 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
111 spin_unlock_irqrestore(&dwc->lock, flags);
113 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
119 * Move a descriptor, including any children, to the free list.
120 * `desc' must not be on any lists.
122 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
127 struct dw_desc *child;
129 spin_lock_irqsave(&dwc->lock, flags);
130 list_for_each_entry(child, &desc->tx_list, desc_node)
131 dev_vdbg(chan2dev(&dwc->chan),
132 "moving child desc %p to freelist\n",
134 list_splice_init(&desc->tx_list, &dwc->free_list);
135 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
136 list_add(&desc->desc_node, &dwc->free_list);
137 spin_unlock_irqrestore(&dwc->lock, flags);
141 static void dwc_initialize(struct dw_dma_chan *dwc)
143 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
144 struct dw_dma_slave *dws = dwc->chan.private;
145 u32 cfghi = DWC_CFGH_FIFO_MODE;
146 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
148 if (dwc->initialized == true)
153 * We need controller-specific data to set up slave
156 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
159 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
161 if (dwc->direction == DMA_MEM_TO_DEV)
162 cfghi = DWC_CFGH_DST_PER(dwc->request_line);
163 else if (dwc->direction == DMA_DEV_TO_MEM)
164 cfghi = DWC_CFGH_SRC_PER(dwc->request_line);
167 channel_writel(dwc, CFG_LO, cfglo);
168 channel_writel(dwc, CFG_HI, cfghi);
170 /* Enable interrupts */
171 channel_set_bit(dw, MASK.XFER, dwc->mask);
172 channel_set_bit(dw, MASK.ERROR, dwc->mask);
174 dwc->initialized = true;
177 /*----------------------------------------------------------------------*/
179 static inline unsigned int dwc_fast_fls(unsigned long long v)
182 * We can be a lot more clever here, but this should take care
183 * of the most common optimization.
194 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
196 dev_err(chan2dev(&dwc->chan),
197 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
198 channel_readl(dwc, SAR),
199 channel_readl(dwc, DAR),
200 channel_readl(dwc, LLP),
201 channel_readl(dwc, CTL_HI),
202 channel_readl(dwc, CTL_LO));
205 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
207 channel_clear_bit(dw, CH_EN, dwc->mask);
208 while (dma_readl(dw, CH_EN) & dwc->mask)
212 /*----------------------------------------------------------------------*/
214 /* Perform single block transfer */
215 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
216 struct dw_desc *desc)
218 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
222 * Software emulation of LLP mode relies on interrupts to continue
223 * multi block transfer.
225 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
227 channel_writel(dwc, SAR, desc->lli.sar);
228 channel_writel(dwc, DAR, desc->lli.dar);
229 channel_writel(dwc, CTL_LO, ctllo);
230 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
231 channel_set_bit(dw, CH_EN, dwc->mask);
233 /* Move pointer to next descriptor */
234 dwc->tx_node_active = dwc->tx_node_active->next;
237 /* Called with dwc->lock held and bh disabled */
238 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
240 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
241 unsigned long was_soft_llp;
243 /* ASSERT: channel is idle */
244 if (dma_readl(dw, CH_EN) & dwc->mask) {
245 dev_err(chan2dev(&dwc->chan),
246 "BUG: Attempted to start non-idle channel\n");
247 dwc_dump_chan_regs(dwc);
249 /* The tasklet will hopefully advance the queue... */
254 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
257 dev_err(chan2dev(&dwc->chan),
258 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
264 dwc->residue = first->total_len;
265 dwc->tx_node_active = &first->tx_list;
267 /* Submit first block */
268 dwc_do_single_block(dwc, first);
275 channel_writel(dwc, LLP, first->txd.phys);
276 channel_writel(dwc, CTL_LO,
277 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
278 channel_writel(dwc, CTL_HI, 0);
279 channel_set_bit(dw, CH_EN, dwc->mask);
282 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
284 if (list_empty(&dwc->queue))
287 list_move(dwc->queue.next, &dwc->active_list);
288 dwc_dostart(dwc, dwc_first_active(dwc));
291 /*----------------------------------------------------------------------*/
294 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
295 bool callback_required)
297 dma_async_tx_callback callback = NULL;
299 struct dma_async_tx_descriptor *txd = &desc->txd;
300 struct dw_desc *child;
303 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
305 spin_lock_irqsave(&dwc->lock, flags);
306 dma_cookie_complete(txd);
307 if (callback_required) {
308 callback = txd->callback;
309 param = txd->callback_param;
313 list_for_each_entry(child, &desc->tx_list, desc_node)
314 async_tx_ack(&child->txd);
315 async_tx_ack(&desc->txd);
317 list_splice_init(&desc->tx_list, &dwc->free_list);
318 list_move(&desc->desc_node, &dwc->free_list);
320 dma_descriptor_unmap(txd);
321 spin_unlock_irqrestore(&dwc->lock, flags);
327 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
329 struct dw_desc *desc, *_desc;
333 spin_lock_irqsave(&dwc->lock, flags);
334 if (dma_readl(dw, CH_EN) & dwc->mask) {
335 dev_err(chan2dev(&dwc->chan),
336 "BUG: XFER bit set, but channel not idle!\n");
338 /* Try to continue after resetting the channel... */
339 dwc_chan_disable(dw, dwc);
343 * Submit queued descriptors ASAP, i.e. before we go through
344 * the completed ones.
346 list_splice_init(&dwc->active_list, &list);
347 dwc_dostart_first_queued(dwc);
349 spin_unlock_irqrestore(&dwc->lock, flags);
351 list_for_each_entry_safe(desc, _desc, &list, desc_node)
352 dwc_descriptor_complete(dwc, desc, true);
355 /* Returns how many bytes were already received from source */
356 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
358 u32 ctlhi = channel_readl(dwc, CTL_HI);
359 u32 ctllo = channel_readl(dwc, CTL_LO);
361 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
364 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
367 struct dw_desc *desc, *_desc;
368 struct dw_desc *child;
372 spin_lock_irqsave(&dwc->lock, flags);
373 llp = channel_readl(dwc, LLP);
374 status_xfer = dma_readl(dw, RAW.XFER);
376 if (status_xfer & dwc->mask) {
377 /* Everything we've submitted is done */
378 dma_writel(dw, CLEAR.XFER, dwc->mask);
380 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
381 struct list_head *head, *active = dwc->tx_node_active;
384 * We are inside first active descriptor.
385 * Otherwise something is really wrong.
387 desc = dwc_first_active(dwc);
389 head = &desc->tx_list;
390 if (active != head) {
391 /* Update desc to reflect last sent one */
392 if (active != head->next)
393 desc = to_dw_desc(active->prev);
395 dwc->residue -= desc->len;
397 child = to_dw_desc(active);
399 /* Submit next block */
400 dwc_do_single_block(dwc, child);
402 spin_unlock_irqrestore(&dwc->lock, flags);
406 /* We are done here */
407 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
412 spin_unlock_irqrestore(&dwc->lock, flags);
414 dwc_complete_all(dw, dwc);
418 if (list_empty(&dwc->active_list)) {
420 spin_unlock_irqrestore(&dwc->lock, flags);
424 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
425 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
426 spin_unlock_irqrestore(&dwc->lock, flags);
430 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
432 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
433 /* Initial residue value */
434 dwc->residue = desc->total_len;
436 /* Check first descriptors addr */
437 if (desc->txd.phys == llp) {
438 spin_unlock_irqrestore(&dwc->lock, flags);
442 /* Check first descriptors llp */
443 if (desc->lli.llp == llp) {
444 /* This one is currently in progress */
445 dwc->residue -= dwc_get_sent(dwc);
446 spin_unlock_irqrestore(&dwc->lock, flags);
450 dwc->residue -= desc->len;
451 list_for_each_entry(child, &desc->tx_list, desc_node) {
452 if (child->lli.llp == llp) {
453 /* Currently in progress */
454 dwc->residue -= dwc_get_sent(dwc);
455 spin_unlock_irqrestore(&dwc->lock, flags);
458 dwc->residue -= child->len;
462 * No descriptors so far seem to be in progress, i.e.
463 * this one must be done.
465 spin_unlock_irqrestore(&dwc->lock, flags);
466 dwc_descriptor_complete(dwc, desc, true);
467 spin_lock_irqsave(&dwc->lock, flags);
470 dev_err(chan2dev(&dwc->chan),
471 "BUG: All descriptors done, but channel not idle!\n");
473 /* Try to continue after resetting the channel... */
474 dwc_chan_disable(dw, dwc);
476 dwc_dostart_first_queued(dwc);
477 spin_unlock_irqrestore(&dwc->lock, flags);
480 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
482 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
483 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
486 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
488 struct dw_desc *bad_desc;
489 struct dw_desc *child;
492 dwc_scan_descriptors(dw, dwc);
494 spin_lock_irqsave(&dwc->lock, flags);
497 * The descriptor currently at the head of the active list is
498 * borked. Since we don't have any way to report errors, we'll
499 * just have to scream loudly and try to carry on.
501 bad_desc = dwc_first_active(dwc);
502 list_del_init(&bad_desc->desc_node);
503 list_move(dwc->queue.next, dwc->active_list.prev);
505 /* Clear the error flag and try to restart the controller */
506 dma_writel(dw, CLEAR.ERROR, dwc->mask);
507 if (!list_empty(&dwc->active_list))
508 dwc_dostart(dwc, dwc_first_active(dwc));
511 * WARN may seem harsh, but since this only happens
512 * when someone submits a bad physical address in a
513 * descriptor, we should consider ourselves lucky that the
514 * controller flagged an error instead of scribbling over
515 * random memory locations.
517 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
518 " cookie: %d\n", bad_desc->txd.cookie);
519 dwc_dump_lli(dwc, &bad_desc->lli);
520 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
521 dwc_dump_lli(dwc, &child->lli);
523 spin_unlock_irqrestore(&dwc->lock, flags);
525 /* Pretend the descriptor completed successfully */
526 dwc_descriptor_complete(dwc, bad_desc, true);
529 /* --------------------- Cyclic DMA API extensions -------------------- */
531 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
533 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
534 return channel_readl(dwc, SAR);
536 EXPORT_SYMBOL(dw_dma_get_src_addr);
538 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
540 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
541 return channel_readl(dwc, DAR);
543 EXPORT_SYMBOL(dw_dma_get_dst_addr);
545 /* Called with dwc->lock held and all DMAC interrupts disabled */
546 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
547 u32 status_err, u32 status_xfer)
552 void (*callback)(void *param);
553 void *callback_param;
555 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
556 channel_readl(dwc, LLP));
558 callback = dwc->cdesc->period_callback;
559 callback_param = dwc->cdesc->period_callback_param;
562 callback(callback_param);
566 * Error and transfer complete are highly unlikely, and will most
567 * likely be due to a configuration error by the user.
569 if (unlikely(status_err & dwc->mask) ||
570 unlikely(status_xfer & dwc->mask)) {
573 dev_err(chan2dev(&dwc->chan),
574 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
575 status_xfer ? "xfer" : "error");
577 spin_lock_irqsave(&dwc->lock, flags);
579 dwc_dump_chan_regs(dwc);
581 dwc_chan_disable(dw, dwc);
583 /* Make sure DMA does not restart by loading a new list */
584 channel_writel(dwc, LLP, 0);
585 channel_writel(dwc, CTL_LO, 0);
586 channel_writel(dwc, CTL_HI, 0);
588 dma_writel(dw, CLEAR.ERROR, dwc->mask);
589 dma_writel(dw, CLEAR.XFER, dwc->mask);
591 for (i = 0; i < dwc->cdesc->periods; i++)
592 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
594 spin_unlock_irqrestore(&dwc->lock, flags);
598 /* ------------------------------------------------------------------------- */
600 static void dw_dma_tasklet(unsigned long data)
602 struct dw_dma *dw = (struct dw_dma *)data;
603 struct dw_dma_chan *dwc;
608 status_xfer = dma_readl(dw, RAW.XFER);
609 status_err = dma_readl(dw, RAW.ERROR);
611 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
613 for (i = 0; i < dw->dma.chancnt; i++) {
615 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
616 dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
617 else if (status_err & (1 << i))
618 dwc_handle_error(dw, dwc);
619 else if (status_xfer & (1 << i))
620 dwc_scan_descriptors(dw, dwc);
624 * Re-enable interrupts.
626 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
627 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
630 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
632 struct dw_dma *dw = dev_id;
633 u32 status = dma_readl(dw, STATUS_INT);
635 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
637 /* Check if we have any interrupt from the DMAC */
642 * Just disable the interrupts. We'll turn them back on in the
645 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
646 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
648 status = dma_readl(dw, STATUS_INT);
651 "BUG: Unexpected interrupts pending: 0x%x\n",
655 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
656 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
657 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
658 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
661 tasklet_schedule(&dw->tasklet);
666 /*----------------------------------------------------------------------*/
668 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
670 struct dw_desc *desc = txd_to_dw_desc(tx);
671 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
675 spin_lock_irqsave(&dwc->lock, flags);
676 cookie = dma_cookie_assign(tx);
679 * REVISIT: We should attempt to chain as many descriptors as
680 * possible, perhaps even appending to those already submitted
681 * for DMA. But this is hard to do in a race-free manner.
684 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
685 list_add_tail(&desc->desc_node, &dwc->queue);
687 spin_unlock_irqrestore(&dwc->lock, flags);
692 static struct dma_async_tx_descriptor *
693 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
694 size_t len, unsigned long flags)
696 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
697 struct dw_dma *dw = to_dw_dma(chan->device);
698 struct dw_desc *desc;
699 struct dw_desc *first;
700 struct dw_desc *prev;
703 unsigned int src_width;
704 unsigned int dst_width;
705 unsigned int data_width;
708 dev_vdbg(chan2dev(chan),
709 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
710 &dest, &src, len, flags);
712 if (unlikely(!len)) {
713 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
717 dwc->direction = DMA_MEM_TO_MEM;
719 data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
720 dw->data_width[dwc->dst_master]);
722 src_width = dst_width = min_t(unsigned int, data_width,
723 dwc_fast_fls(src | dest | len));
725 ctllo = DWC_DEFAULT_CTLLO(chan)
726 | DWC_CTLL_DST_WIDTH(dst_width)
727 | DWC_CTLL_SRC_WIDTH(src_width)
733 for (offset = 0; offset < len; offset += xfer_count << src_width) {
734 xfer_count = min_t(size_t, (len - offset) >> src_width,
737 desc = dwc_desc_get(dwc);
741 desc->lli.sar = src + offset;
742 desc->lli.dar = dest + offset;
743 desc->lli.ctllo = ctllo;
744 desc->lli.ctlhi = xfer_count;
745 desc->len = xfer_count << src_width;
750 prev->lli.llp = desc->txd.phys;
751 list_add_tail(&desc->desc_node,
757 if (flags & DMA_PREP_INTERRUPT)
758 /* Trigger interrupt after last block */
759 prev->lli.ctllo |= DWC_CTLL_INT_EN;
762 first->txd.flags = flags;
763 first->total_len = len;
768 dwc_desc_put(dwc, first);
772 static struct dma_async_tx_descriptor *
773 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
774 unsigned int sg_len, enum dma_transfer_direction direction,
775 unsigned long flags, void *context)
777 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
778 struct dw_dma *dw = to_dw_dma(chan->device);
779 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
780 struct dw_desc *prev;
781 struct dw_desc *first;
784 unsigned int reg_width;
785 unsigned int mem_width;
786 unsigned int data_width;
788 struct scatterlist *sg;
789 size_t total_len = 0;
791 dev_vdbg(chan2dev(chan), "%s\n", __func__);
793 if (unlikely(!is_slave_direction(direction) || !sg_len))
796 dwc->direction = direction;
802 reg_width = __fls(sconfig->dst_addr_width);
803 reg = sconfig->dst_addr;
804 ctllo = (DWC_DEFAULT_CTLLO(chan)
805 | DWC_CTLL_DST_WIDTH(reg_width)
809 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
810 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
812 data_width = dw->data_width[dwc->src_master];
814 for_each_sg(sgl, sg, sg_len, i) {
815 struct dw_desc *desc;
818 mem = sg_dma_address(sg);
819 len = sg_dma_len(sg);
821 mem_width = min_t(unsigned int,
822 data_width, dwc_fast_fls(mem | len));
824 slave_sg_todev_fill_desc:
825 desc = dwc_desc_get(dwc);
827 dev_err(chan2dev(chan),
828 "not enough descriptors available\n");
834 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
835 if ((len >> mem_width) > dwc->block_size) {
836 dlen = dwc->block_size << mem_width;
844 desc->lli.ctlhi = dlen >> mem_width;
850 prev->lli.llp = desc->txd.phys;
851 list_add_tail(&desc->desc_node,
858 goto slave_sg_todev_fill_desc;
862 reg_width = __fls(sconfig->src_addr_width);
863 reg = sconfig->src_addr;
864 ctllo = (DWC_DEFAULT_CTLLO(chan)
865 | DWC_CTLL_SRC_WIDTH(reg_width)
869 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
870 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
872 data_width = dw->data_width[dwc->dst_master];
874 for_each_sg(sgl, sg, sg_len, i) {
875 struct dw_desc *desc;
878 mem = sg_dma_address(sg);
879 len = sg_dma_len(sg);
881 mem_width = min_t(unsigned int,
882 data_width, dwc_fast_fls(mem | len));
884 slave_sg_fromdev_fill_desc:
885 desc = dwc_desc_get(dwc);
887 dev_err(chan2dev(chan),
888 "not enough descriptors available\n");
894 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
895 if ((len >> reg_width) > dwc->block_size) {
896 dlen = dwc->block_size << reg_width;
903 desc->lli.ctlhi = dlen >> reg_width;
909 prev->lli.llp = desc->txd.phys;
910 list_add_tail(&desc->desc_node,
917 goto slave_sg_fromdev_fill_desc;
924 if (flags & DMA_PREP_INTERRUPT)
925 /* Trigger interrupt after last block */
926 prev->lli.ctllo |= DWC_CTLL_INT_EN;
929 first->total_len = total_len;
934 dwc_desc_put(dwc, first);
939 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
940 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
942 * NOTE: burst size 2 is not supported by controller.
944 * This can be done by finding least significant bit set: n & (n - 1)
946 static inline void convert_burst(u32 *maxburst)
949 *maxburst = fls(*maxburst) - 2;
955 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
957 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
959 /* Check if chan will be configured for slave transfers */
960 if (!is_slave_direction(sconfig->direction))
963 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
964 dwc->direction = sconfig->direction;
966 /* Take the request line from slave_id member */
967 if (is_request_line_unset(dwc))
968 dwc->request_line = sconfig->slave_id;
970 convert_burst(&dwc->dma_sconfig.src_maxburst);
971 convert_burst(&dwc->dma_sconfig.dst_maxburst);
976 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
978 u32 cfglo = channel_readl(dwc, CFG_LO);
979 unsigned int count = 20; /* timeout iterations */
981 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
982 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
988 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
990 u32 cfglo = channel_readl(dwc, CFG_LO);
992 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
997 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1000 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1001 struct dw_dma *dw = to_dw_dma(chan->device);
1002 struct dw_desc *desc, *_desc;
1003 unsigned long flags;
1006 if (cmd == DMA_PAUSE) {
1007 spin_lock_irqsave(&dwc->lock, flags);
1009 dwc_chan_pause(dwc);
1011 spin_unlock_irqrestore(&dwc->lock, flags);
1012 } else if (cmd == DMA_RESUME) {
1016 spin_lock_irqsave(&dwc->lock, flags);
1018 dwc_chan_resume(dwc);
1020 spin_unlock_irqrestore(&dwc->lock, flags);
1021 } else if (cmd == DMA_TERMINATE_ALL) {
1022 spin_lock_irqsave(&dwc->lock, flags);
1024 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1026 dwc_chan_disable(dw, dwc);
1028 dwc_chan_resume(dwc);
1030 /* active_list entries will end up before queued entries */
1031 list_splice_init(&dwc->queue, &list);
1032 list_splice_init(&dwc->active_list, &list);
1034 spin_unlock_irqrestore(&dwc->lock, flags);
1036 /* Flush all pending and queued descriptors */
1037 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1038 dwc_descriptor_complete(dwc, desc, false);
1039 } else if (cmd == DMA_SLAVE_CONFIG) {
1040 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1048 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1050 unsigned long flags;
1053 spin_lock_irqsave(&dwc->lock, flags);
1055 residue = dwc->residue;
1056 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1057 residue -= dwc_get_sent(dwc);
1059 spin_unlock_irqrestore(&dwc->lock, flags);
1063 static enum dma_status
1064 dwc_tx_status(struct dma_chan *chan,
1065 dma_cookie_t cookie,
1066 struct dma_tx_state *txstate)
1068 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1069 enum dma_status ret;
1071 ret = dma_cookie_status(chan, cookie, txstate);
1072 if (ret == DMA_COMPLETE)
1075 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1077 ret = dma_cookie_status(chan, cookie, txstate);
1078 if (ret != DMA_COMPLETE)
1079 dma_set_residue(txstate, dwc_get_residue(dwc));
1081 if (dwc->paused && ret == DMA_IN_PROGRESS)
1087 static void dwc_issue_pending(struct dma_chan *chan)
1089 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1090 unsigned long flags;
1092 spin_lock_irqsave(&dwc->lock, flags);
1093 if (list_empty(&dwc->active_list))
1094 dwc_dostart_first_queued(dwc);
1095 spin_unlock_irqrestore(&dwc->lock, flags);
1098 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1100 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1101 struct dw_dma *dw = to_dw_dma(chan->device);
1102 struct dw_desc *desc;
1104 unsigned long flags;
1106 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1108 /* ASSERT: channel is idle */
1109 if (dma_readl(dw, CH_EN) & dwc->mask) {
1110 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1114 dma_cookie_init(chan);
1117 * NOTE: some controllers may have additional features that we
1118 * need to initialize here, like "scatter-gather" (which
1119 * doesn't mean what you think it means), and status writeback.
1122 dwc_set_masters(dwc);
1124 spin_lock_irqsave(&dwc->lock, flags);
1125 i = dwc->descs_allocated;
1126 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1129 spin_unlock_irqrestore(&dwc->lock, flags);
1131 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1133 goto err_desc_alloc;
1135 memset(desc, 0, sizeof(struct dw_desc));
1137 INIT_LIST_HEAD(&desc->tx_list);
1138 dma_async_tx_descriptor_init(&desc->txd, chan);
1139 desc->txd.tx_submit = dwc_tx_submit;
1140 desc->txd.flags = DMA_CTRL_ACK;
1141 desc->txd.phys = phys;
1143 dwc_desc_put(dwc, desc);
1145 spin_lock_irqsave(&dwc->lock, flags);
1146 i = ++dwc->descs_allocated;
1149 spin_unlock_irqrestore(&dwc->lock, flags);
1151 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1156 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1161 static void dwc_free_chan_resources(struct dma_chan *chan)
1163 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1164 struct dw_dma *dw = to_dw_dma(chan->device);
1165 struct dw_desc *desc, *_desc;
1166 unsigned long flags;
1169 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1170 dwc->descs_allocated);
1172 /* ASSERT: channel is idle */
1173 BUG_ON(!list_empty(&dwc->active_list));
1174 BUG_ON(!list_empty(&dwc->queue));
1175 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1177 spin_lock_irqsave(&dwc->lock, flags);
1178 list_splice_init(&dwc->free_list, &list);
1179 dwc->descs_allocated = 0;
1180 dwc->initialized = false;
1181 dwc->request_line = ~0;
1183 /* Disable interrupts */
1184 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1185 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1187 spin_unlock_irqrestore(&dwc->lock, flags);
1189 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1190 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1191 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1194 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1197 /* --------------------- Cyclic DMA API extensions -------------------- */
1200 * dw_dma_cyclic_start - start the cyclic DMA transfer
1201 * @chan: the DMA channel to start
1203 * Must be called with soft interrupts disabled. Returns zero on success or
1204 * -errno on failure.
1206 int dw_dma_cyclic_start(struct dma_chan *chan)
1208 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1209 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1210 unsigned long flags;
1212 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1213 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1217 spin_lock_irqsave(&dwc->lock, flags);
1219 /* Assert channel is idle */
1220 if (dma_readl(dw, CH_EN) & dwc->mask) {
1221 dev_err(chan2dev(&dwc->chan),
1222 "BUG: Attempted to start non-idle channel\n");
1223 dwc_dump_chan_regs(dwc);
1224 spin_unlock_irqrestore(&dwc->lock, flags);
1228 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1229 dma_writel(dw, CLEAR.XFER, dwc->mask);
1231 /* Setup DMAC channel registers */
1232 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1233 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1234 channel_writel(dwc, CTL_HI, 0);
1236 channel_set_bit(dw, CH_EN, dwc->mask);
1238 spin_unlock_irqrestore(&dwc->lock, flags);
1242 EXPORT_SYMBOL(dw_dma_cyclic_start);
1245 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1246 * @chan: the DMA channel to stop
1248 * Must be called with soft interrupts disabled.
1250 void dw_dma_cyclic_stop(struct dma_chan *chan)
1252 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1253 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1254 unsigned long flags;
1256 spin_lock_irqsave(&dwc->lock, flags);
1258 dwc_chan_disable(dw, dwc);
1260 spin_unlock_irqrestore(&dwc->lock, flags);
1262 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1265 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1266 * @chan: the DMA channel to prepare
1267 * @buf_addr: physical DMA address where the buffer starts
1268 * @buf_len: total number of bytes for the entire buffer
1269 * @period_len: number of bytes for each period
1270 * @direction: transfer direction, to or from device
1272 * Must be called before trying to start the transfer. Returns a valid struct
1273 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1275 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1276 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1277 enum dma_transfer_direction direction)
1279 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1280 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1281 struct dw_cyclic_desc *cdesc;
1282 struct dw_cyclic_desc *retval = NULL;
1283 struct dw_desc *desc;
1284 struct dw_desc *last = NULL;
1285 unsigned long was_cyclic;
1286 unsigned int reg_width;
1287 unsigned int periods;
1289 unsigned long flags;
1291 spin_lock_irqsave(&dwc->lock, flags);
1293 spin_unlock_irqrestore(&dwc->lock, flags);
1294 dev_dbg(chan2dev(&dwc->chan),
1295 "channel doesn't support LLP transfers\n");
1296 return ERR_PTR(-EINVAL);
1299 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1300 spin_unlock_irqrestore(&dwc->lock, flags);
1301 dev_dbg(chan2dev(&dwc->chan),
1302 "queue and/or active list are not empty\n");
1303 return ERR_PTR(-EBUSY);
1306 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1307 spin_unlock_irqrestore(&dwc->lock, flags);
1309 dev_dbg(chan2dev(&dwc->chan),
1310 "channel already prepared for cyclic DMA\n");
1311 return ERR_PTR(-EBUSY);
1314 retval = ERR_PTR(-EINVAL);
1316 if (unlikely(!is_slave_direction(direction)))
1319 dwc->direction = direction;
1321 if (direction == DMA_MEM_TO_DEV)
1322 reg_width = __ffs(sconfig->dst_addr_width);
1324 reg_width = __ffs(sconfig->src_addr_width);
1326 periods = buf_len / period_len;
1328 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1329 if (period_len > (dwc->block_size << reg_width))
1331 if (unlikely(period_len & ((1 << reg_width) - 1)))
1333 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1336 retval = ERR_PTR(-ENOMEM);
1338 if (periods > NR_DESCS_PER_CHANNEL)
1341 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1345 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1349 for (i = 0; i < periods; i++) {
1350 desc = dwc_desc_get(dwc);
1352 goto out_err_desc_get;
1354 switch (direction) {
1355 case DMA_MEM_TO_DEV:
1356 desc->lli.dar = sconfig->dst_addr;
1357 desc->lli.sar = buf_addr + (period_len * i);
1358 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1359 | DWC_CTLL_DST_WIDTH(reg_width)
1360 | DWC_CTLL_SRC_WIDTH(reg_width)
1365 desc->lli.ctllo |= sconfig->device_fc ?
1366 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1367 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1370 case DMA_DEV_TO_MEM:
1371 desc->lli.dar = buf_addr + (period_len * i);
1372 desc->lli.sar = sconfig->src_addr;
1373 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1374 | DWC_CTLL_SRC_WIDTH(reg_width)
1375 | DWC_CTLL_DST_WIDTH(reg_width)
1380 desc->lli.ctllo |= sconfig->device_fc ?
1381 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1382 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1389 desc->lli.ctlhi = (period_len >> reg_width);
1390 cdesc->desc[i] = desc;
1393 last->lli.llp = desc->txd.phys;
1398 /* Let's make a cyclic list */
1399 last->lli.llp = cdesc->desc[0]->txd.phys;
1401 dev_dbg(chan2dev(&dwc->chan),
1402 "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1403 &buf_addr, buf_len, period_len, periods);
1405 cdesc->periods = periods;
1412 dwc_desc_put(dwc, cdesc->desc[i]);
1416 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1417 return (struct dw_cyclic_desc *)retval;
1419 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1422 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1423 * @chan: the DMA channel to free
1425 void dw_dma_cyclic_free(struct dma_chan *chan)
1427 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1428 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1429 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1431 unsigned long flags;
1433 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1438 spin_lock_irqsave(&dwc->lock, flags);
1440 dwc_chan_disable(dw, dwc);
1442 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1443 dma_writel(dw, CLEAR.XFER, dwc->mask);
1445 spin_unlock_irqrestore(&dwc->lock, flags);
1447 for (i = 0; i < cdesc->periods; i++)
1448 dwc_desc_put(dwc, cdesc->desc[i]);
1453 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1455 EXPORT_SYMBOL(dw_dma_cyclic_free);
1457 /*----------------------------------------------------------------------*/
1459 static void dw_dma_off(struct dw_dma *dw)
1463 dma_writel(dw, CFG, 0);
1465 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1466 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1467 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1468 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1470 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1473 for (i = 0; i < dw->dma.chancnt; i++)
1474 dw->chan[i].initialized = false;
1477 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1482 unsigned int dw_params;
1483 unsigned int nr_channels;
1484 unsigned int max_blk_size = 0;
1488 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1489 autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1491 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1493 if (!pdata && autocfg) {
1494 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1498 /* Fill platform data with the default values */
1499 pdata->is_private = true;
1500 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1501 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1502 } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1506 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1508 nr_channels = pdata->nr_channels;
1510 size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1511 dw = devm_kzalloc(chip->dev, size, GFP_KERNEL);
1515 dw->clk = devm_clk_get(chip->dev, "hclk");
1516 if (IS_ERR(dw->clk))
1517 return PTR_ERR(dw->clk);
1518 clk_prepare_enable(dw->clk);
1520 dw->regs = chip->regs;
1523 /* Get hardware configuration parameters */
1525 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1527 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1528 for (i = 0; i < dw->nr_masters; i++) {
1530 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1533 dw->nr_masters = pdata->nr_masters;
1534 memcpy(dw->data_width, pdata->data_width, 4);
1537 /* Calculate all channel mask before DMA setup */
1538 dw->all_chan_mask = (1 << nr_channels) - 1;
1540 /* Force dma off, just in case */
1543 /* Disable BLOCK interrupts as well */
1544 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1546 /* Create a pool of consistent memory blocks for hardware descriptors */
1547 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1548 sizeof(struct dw_desc), 4, 0);
1549 if (!dw->desc_pool) {
1550 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1554 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1556 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1561 INIT_LIST_HEAD(&dw->dma.channels);
1562 for (i = 0; i < nr_channels; i++) {
1563 struct dw_dma_chan *dwc = &dw->chan[i];
1564 int r = nr_channels - i - 1;
1566 dwc->chan.device = &dw->dma;
1567 dma_cookie_init(&dwc->chan);
1568 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1569 list_add_tail(&dwc->chan.device_node,
1572 list_add(&dwc->chan.device_node, &dw->dma.channels);
1574 /* 7 is highest priority & 0 is lowest. */
1575 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1580 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1581 spin_lock_init(&dwc->lock);
1584 INIT_LIST_HEAD(&dwc->active_list);
1585 INIT_LIST_HEAD(&dwc->queue);
1586 INIT_LIST_HEAD(&dwc->free_list);
1588 channel_clear_bit(dw, CH_EN, dwc->mask);
1590 dwc->direction = DMA_TRANS_NONE;
1591 dwc->request_line = ~0;
1593 /* Hardware configuration */
1595 unsigned int dwc_params;
1596 void __iomem *addr = chip->regs + r * sizeof(u32);
1598 dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1600 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1604 * Decode maximum block size for given channel. The
1605 * stored 4 bit value represents blocks from 0x00 for 3
1606 * up to 0x0a for 4095.
1609 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1611 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1613 dwc->block_size = pdata->block_size;
1615 /* Check if channel supports multi block transfer */
1616 channel_writel(dwc, LLP, 0xfffffffc);
1618 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1619 channel_writel(dwc, LLP, 0);
1623 /* Clear all interrupts on all channels. */
1624 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1625 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1626 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1627 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1628 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1630 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1631 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1632 if (pdata->is_private)
1633 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1634 dw->dma.dev = chip->dev;
1635 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1636 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1638 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1640 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1641 dw->dma.device_control = dwc_control;
1643 dw->dma.device_tx_status = dwc_tx_status;
1644 dw->dma.device_issue_pending = dwc_issue_pending;
1646 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1648 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1651 dma_async_device_register(&dw->dma);
1655 EXPORT_SYMBOL_GPL(dw_dma_probe);
1657 int dw_dma_remove(struct dw_dma_chip *chip)
1659 struct dw_dma *dw = chip->dw;
1660 struct dw_dma_chan *dwc, *_dwc;
1663 dma_async_device_unregister(&dw->dma);
1665 free_irq(chip->irq, dw);
1666 tasklet_kill(&dw->tasklet);
1668 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1670 list_del(&dwc->chan.device_node);
1671 channel_clear_bit(dw, CH_EN, dwc->mask);
1676 EXPORT_SYMBOL_GPL(dw_dma_remove);
1678 void dw_dma_shutdown(struct dw_dma_chip *chip)
1680 struct dw_dma *dw = chip->dw;
1683 clk_disable_unprepare(dw->clk);
1685 EXPORT_SYMBOL_GPL(dw_dma_shutdown);
1687 #ifdef CONFIG_PM_SLEEP
1689 int dw_dma_suspend(struct dw_dma_chip *chip)
1691 struct dw_dma *dw = chip->dw;
1694 clk_disable_unprepare(dw->clk);
1698 EXPORT_SYMBOL_GPL(dw_dma_suspend);
1700 int dw_dma_resume(struct dw_dma_chip *chip)
1702 struct dw_dma *dw = chip->dw;
1704 clk_prepare_enable(dw->clk);
1705 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1709 EXPORT_SYMBOL_GPL(dw_dma_resume);
1711 #endif /* CONFIG_PM_SLEEP */
1713 MODULE_LICENSE("GPL v2");
1714 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1715 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1716 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");