drivers/dma/dw_dmac.c

   1 /*
   2  * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
   3  * AVR32 systems.)
   4  *
   5  * Copyright (C) 2007-2008 Atmel Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/clk.h>
  12 #include <linux/delay.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/mm.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22
  23 #include "dw_dmac_regs.h"
  24
  25 /*
  26  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  27  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  28  * of which use ARM any more).  See the "Databook" from Synopsys for
  29  * information beyond what licensees probably provide.
  30  *
  31  * The driver has currently been tested only with the Atmel AT32AP7000,
  32  * which does not support descriptor writeback.
  33  */
  34
  35 #define DWC_DEFAULT_CTLLO(private) ({                           \
  36                 struct dw_dma_slave *__slave = (private);       \
  37                 int dms = __slave ? __slave->dst_master : 0;    \
  38                 int sms = __slave ? __slave->src_master : 1;    \
  39                                                                 \
  40                 (DWC_CTLL_DST_MSIZE(0)                          \
  41                  | DWC_CTLL_SRC_MSIZE(0)                        \
  42                  | DWC_CTLL_LLP_D_EN                            \
  43                  | DWC_CTLL_LLP_S_EN                            \
  44                  | DWC_CTLL_DMS(dms)                            \
  45                  | DWC_CTLL_SMS(sms));                          \
  46         })
  47
  48 /*
  49  * This is configuration-dependent and usually a funny size like 4095.
  50  *
  51  * Note that this is a transfer count, i.e. if we transfer 32-bit
  52  * words, we can do 16380 bytes per descriptor.
  53  *
  54  * This parameter is also system-specific.
  55  */
  56 #define DWC_MAX_COUNT   4095U
  57
  58 /*
  59  * Number of descriptors to allocate for each channel. This should be
  60  * made configurable somehow; preferably, the clients (at least the
  61  * ones using slave transfers) should be able to give us a hint.
  62  */
  63 #define NR_DESCS_PER_CHANNEL    64
  64
  65 /*----------------------------------------------------------------------*/
  66
  67 /*
  68  * Because we're not relying on writeback from the controller (it may not
  69  * even be configured into the core!) we don't need to use dma_pool.  These
  70  * descriptors -- and associated data -- are cacheable.  We do need to make
  71  * sure their dcache entries are written back before handing them off to
  72  * the controller, though.
  73  */
  74
  75 static struct device *chan2dev(struct dma_chan *chan)
  76 {
  77         return &chan->dev->device;
  78 }
  79 static struct device *chan2parent(struct dma_chan *chan)
  80 {
  81         return chan->dev->device.parent;
  82 }
  83
  84 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  85 {
  86         return list_entry(dwc->active_list.next, struct dw_desc, desc_node);
  87 }
  88
  89 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
  90 {
  91         struct dw_desc *desc, *_desc;
  92         struct dw_desc *ret = NULL;
  93         unsigned int i = 0;
  94
  95         spin_lock_bh(&dwc->lock);
  96         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
  97                 if (async_tx_test_ack(&desc->txd)) {
  98                         list_del(&desc->desc_node);
  99                         ret = desc;
 100                         break;
 101                 }
 102                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
 103                 i++;
 104         }
 105         spin_unlock_bh(&dwc->lock);
 106
 107         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 108
 109         return ret;
 110 }
 111
 112 static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc)
 113 {
 114         struct dw_desc  *child;
 115
 116         list_for_each_entry(child, &desc->tx_list, desc_node)
 117                 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
 118                                 child->txd.phys, sizeof(child->lli),
 119                                 DMA_TO_DEVICE);
 120         dma_sync_single_for_cpu(chan2parent(&dwc->chan),
 121                         desc->txd.phys, sizeof(desc->lli),
 122                         DMA_TO_DEVICE);
 123 }
 124
 125 /*
 126  * Move a descriptor, including any children, to the free list.
 127  * `desc' must not be on any lists.
 128  */
 129 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 130 {
 131         if (desc) {
 132                 struct dw_desc *child;
 133
 134                 dwc_sync_desc_for_cpu(dwc, desc);
 135
 136                 spin_lock_bh(&dwc->lock);
 137                 list_for_each_entry(child, &desc->tx_list, desc_node)
 138                         dev_vdbg(chan2dev(&dwc->chan),
 139                                         "moving child desc %p to freelist\n",
 140                                         child);
 141                 list_splice_init(&desc->tx_list, &dwc->free_list);
 142                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 143                 list_add(&desc->desc_node, &dwc->free_list);
 144                 spin_unlock_bh(&dwc->lock);
 145         }
 146 }
 147
 148 /* Called with dwc->lock held and bh disabled */
 149 static dma_cookie_t
 150 dwc_assign_cookie(struct dw_dma_chan *dwc, struct dw_desc *desc)
 151 {
 152         dma_cookie_t cookie = dwc->chan.cookie;
 153
 154         if (++cookie < 0)
 155                 cookie = 1;
 156
 157         dwc->chan.cookie = cookie;
 158         desc->txd.cookie = cookie;
 159
 160         return cookie;
 161 }
 162
 163 /*----------------------------------------------------------------------*/
 164
 165 /* Called with dwc->lock held and bh disabled */
 166 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 167 {
 168         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 169
 170         /* ASSERT:  channel is idle */
 171         if (dma_readl(dw, CH_EN) & dwc->mask) {
 172                 dev_err(chan2dev(&dwc->chan),
 173                         "BUG: Attempted to start non-idle channel\n");
 174                 dev_err(chan2dev(&dwc->chan),
 175                         "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 176                         channel_readl(dwc, SAR),
 177                         channel_readl(dwc, DAR),
 178                         channel_readl(dwc, LLP),
 179                         channel_readl(dwc, CTL_HI),
 180                         channel_readl(dwc, CTL_LO));
 181
 182                 /* The tasklet will hopefully advance the queue... */
 183                 return;
 184         }
 185
 186         channel_writel(dwc, LLP, first->txd.phys);
 187         channel_writel(dwc, CTL_LO,
 188                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 189         channel_writel(dwc, CTL_HI, 0);
 190         channel_set_bit(dw, CH_EN, dwc->mask);
 191 }
 192
 193 /*----------------------------------------------------------------------*/
 194
 195 static void
 196 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc)
 197 {
 198         dma_async_tx_callback           callback;
 199         void                            *param;
 200         struct dma_async_tx_descriptor  *txd = &desc->txd;
 201
 202         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 203
 204         dwc->completed = txd->cookie;
 205         callback = txd->callback;
 206         param = txd->callback_param;
 207
 208         dwc_sync_desc_for_cpu(dwc, desc);
 209         list_splice_init(&desc->tx_list, &dwc->free_list);
 210         list_move(&desc->desc_node, &dwc->free_list);
 211
 212         if (!dwc->chan.private) {
 213                 struct device *parent = chan2parent(&dwc->chan);
 214                 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
 215                         if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
 216                                 dma_unmap_single(parent, desc->lli.dar,
 217                                                 desc->len, DMA_FROM_DEVICE);
 218                         else
 219                                 dma_unmap_page(parent, desc->lli.dar,
 220                                                 desc->len, DMA_FROM_DEVICE);
 221                 }
 222                 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
 223                         if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
 224                                 dma_unmap_single(parent, desc->lli.sar,
 225                                                 desc->len, DMA_TO_DEVICE);
 226                         else
 227                                 dma_unmap_page(parent, desc->lli.sar,
 228                                                 desc->len, DMA_TO_DEVICE);
 229                 }
 230         }
 231
 232         /*
 233          * The API requires that no submissions are done from a
 234          * callback, so we don't need to drop the lock here
 235          */
 236         if (callback)
 237                 callback(param);
 238 }
 239
 240 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 241 {
 242         struct dw_desc *desc, *_desc;
 243         LIST_HEAD(list);
 244
 245         if (dma_readl(dw, CH_EN) & dwc->mask) {
 246                 dev_err(chan2dev(&dwc->chan),
 247                         "BUG: XFER bit set, but channel not idle!\n");
 248
 249                 /* Try to continue after resetting the channel... */
 250                 channel_clear_bit(dw, CH_EN, dwc->mask);
 251                 while (dma_readl(dw, CH_EN) & dwc->mask)
 252                         cpu_relax();
 253         }
 254
 255         /*
 256          * Submit queued descriptors ASAP, i.e. before we go through
 257          * the completed ones.
 258          */
 259         list_splice_init(&dwc->active_list, &list);
 260         if (!list_empty(&dwc->queue)) {
 261                 list_move(dwc->queue.next, &dwc->active_list);
 262                 dwc_dostart(dwc, dwc_first_active(dwc));
 263         }
 264
 265         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 266                 dwc_descriptor_complete(dwc, desc);
 267 }
 268
 269 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 270 {
 271         dma_addr_t llp;
 272         struct dw_desc *desc, *_desc;
 273         struct dw_desc *child;
 274         u32 status_xfer;
 275
 276         /*
 277          * Clear block interrupt flag before scanning so that we don't
 278          * miss any, and read LLP before RAW_XFER to ensure it is
 279          * valid if we decide to scan the list.
 280          */
 281         dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 282         llp = channel_readl(dwc, LLP);
 283         status_xfer = dma_readl(dw, RAW.XFER);
 284
 285         if (status_xfer & dwc->mask) {
 286                 /* Everything we've submitted is done */
 287                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 288                 dwc_complete_all(dw, dwc);
 289                 return;
 290         }
 291
 292         if (list_empty(&dwc->active_list))
 293                 return;
 294
 295         dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%x\n", llp);
 296
 297         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 298                 if (desc->lli.llp == llp)
 299                         /* This one is currently in progress */
 300                         return;
 301
 302                 list_for_each_entry(child, &desc->tx_list, desc_node)
 303                         if (child->lli.llp == llp)
 304                                 /* Currently in progress */
 305                                 return;
 306
 307                 /*
 308                  * No descriptors so far seem to be in progress, i.e.
 309                  * this one must be done.
 310                  */
 311                 dwc_descriptor_complete(dwc, desc);
 312         }
 313
 314         dev_err(chan2dev(&dwc->chan),
 315                 "BUG: All descriptors done, but channel not idle!\n");
 316
 317         /* Try to continue after resetting the channel... */
 318         channel_clear_bit(dw, CH_EN, dwc->mask);
 319         while (dma_readl(dw, CH_EN) & dwc->mask)
 320                 cpu_relax();
 321
 322         if (!list_empty(&dwc->queue)) {
 323                 list_move(dwc->queue.next, &dwc->active_list);
 324                 dwc_dostart(dwc, dwc_first_active(dwc));
 325         }
 326 }
 327
 328 static void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 329 {
 330         dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
 331                         "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 332                         lli->sar, lli->dar, lli->llp,
 333                         lli->ctlhi, lli->ctllo);
 334 }
 335
 336 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 337 {
 338         struct dw_desc *bad_desc;
 339         struct dw_desc *child;
 340
 341         dwc_scan_descriptors(dw, dwc);
 342
 343         /*
 344          * The descriptor currently at the head of the active list is
 345          * borked. Since we don't have any way to report errors, we'll
 346          * just have to scream loudly and try to carry on.
 347          */
 348         bad_desc = dwc_first_active(dwc);
 349         list_del_init(&bad_desc->desc_node);
 350         list_move(dwc->queue.next, dwc->active_list.prev);
 351
 352         /* Clear the error flag and try to restart the controller */
 353         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 354         if (!list_empty(&dwc->active_list))
 355                 dwc_dostart(dwc, dwc_first_active(dwc));
 356
 357         /*
 358          * KERN_CRITICAL may seem harsh, but since this only happens
 359          * when someone submits a bad physical address in a
 360          * descriptor, we should consider ourselves lucky that the
 361          * controller flagged an error instead of scribbling over
 362          * random memory locations.
 363          */
 364         dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
 365                         "Bad descriptor submitted for DMA!\n");
 366         dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
 367                         "  cookie: %d\n", bad_desc->txd.cookie);
 368         dwc_dump_lli(dwc, &bad_desc->lli);
 369         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 370                 dwc_dump_lli(dwc, &child->lli);
 371
 372         /* Pretend the descriptor completed successfully */
 373         dwc_descriptor_complete(dwc, bad_desc);
 374 }
 375
 376 /* --------------------- Cyclic DMA API extensions -------------------- */
 377
 378 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 379 {
 380         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 381         return channel_readl(dwc, SAR);
 382 }
 383 EXPORT_SYMBOL(dw_dma_get_src_addr);
 384
 385 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 386 {
 387         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 388         return channel_readl(dwc, DAR);
 389 }
 390 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 391
 392 /* called with dwc->lock held and all DMAC interrupts disabled */
 393 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 394                 u32 status_block, u32 status_err, u32 status_xfer)
 395 {
 396         if (status_block & dwc->mask) {
 397                 void (*callback)(void *param);
 398                 void *callback_param;
 399
 400                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 401                                 channel_readl(dwc, LLP));
 402                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 403
 404                 callback = dwc->cdesc->period_callback;
 405                 callback_param = dwc->cdesc->period_callback_param;
 406                 if (callback) {
 407                         spin_unlock(&dwc->lock);
 408                         callback(callback_param);
 409                         spin_lock(&dwc->lock);
 410                 }
 411         }
 412
 413         /*
 414          * Error and transfer complete are highly unlikely, and will most
 415          * likely be due to a configuration error by the user.
 416          */
 417         if (unlikely(status_err & dwc->mask) ||
 418                         unlikely(status_xfer & dwc->mask)) {
 419                 int i;
 420
 421                 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
 422                                 "interrupt, stopping DMA transfer\n",
 423                                 status_xfer ? "xfer" : "error");
 424                 dev_err(chan2dev(&dwc->chan),
 425                         "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 426                         channel_readl(dwc, SAR),
 427                         channel_readl(dwc, DAR),
 428                         channel_readl(dwc, LLP),
 429                         channel_readl(dwc, CTL_HI),
 430                         channel_readl(dwc, CTL_LO));
 431
 432                 channel_clear_bit(dw, CH_EN, dwc->mask);
 433                 while (dma_readl(dw, CH_EN) & dwc->mask)
 434                         cpu_relax();
 435
 436                 /* make sure DMA does not restart by loading a new list */
 437                 channel_writel(dwc, LLP, 0);
 438                 channel_writel(dwc, CTL_LO, 0);
 439                 channel_writel(dwc, CTL_HI, 0);
 440
 441                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 442                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 443                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 444
 445                 for (i = 0; i < dwc->cdesc->periods; i++)
 446                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 447         }
 448 }
 449
 450 /* ------------------------------------------------------------------------- */
 451
 452 static void dw_dma_tasklet(unsigned long data)
 453 {
 454         struct dw_dma *dw = (struct dw_dma *)data;
 455         struct dw_dma_chan *dwc;
 456         u32 status_block;
 457         u32 status_xfer;
 458         u32 status_err;
 459         int i;
 460
 461         status_block = dma_readl(dw, RAW.BLOCK);
 462         status_xfer = dma_readl(dw, RAW.XFER);
 463         status_err = dma_readl(dw, RAW.ERROR);
 464
 465         dev_vdbg(dw->dma.dev, "tasklet: status_block=%x status_err=%x\n",
 466                         status_block, status_err);
 467
 468         for (i = 0; i < dw->dma.chancnt; i++) {
 469                 dwc = &dw->chan[i];
 470                 spin_lock(&dwc->lock);
 471                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 472                         dwc_handle_cyclic(dw, dwc, status_block, status_err,
 473                                         status_xfer);
 474                 else if (status_err & (1 << i))
 475                         dwc_handle_error(dw, dwc);
 476                 else if ((status_block | status_xfer) & (1 << i))
 477                         dwc_scan_descriptors(dw, dwc);
 478                 spin_unlock(&dwc->lock);
 479         }
 480
 481         /*
 482          * Re-enable interrupts. Block Complete interrupts are only
 483          * enabled if the INT_EN bit in the descriptor is set. This
 484          * will trigger a scan before the whole list is done.
 485          */
 486         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 487         channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask);
 488         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 489 }
 490
 491 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 492 {
 493         struct dw_dma *dw = dev_id;
 494         u32 status;
 495
 496         dev_vdbg(dw->dma.dev, "interrupt: status=0x%x\n",
 497                         dma_readl(dw, STATUS_INT));
 498
 499         /*
 500          * Just disable the interrupts. We'll turn them back on in the
 501          * softirq handler.
 502          */
 503         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 504         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
 505         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 506
 507         status = dma_readl(dw, STATUS_INT);
 508         if (status) {
 509                 dev_err(dw->dma.dev,
 510                         "BUG: Unexpected interrupts pending: 0x%x\n",
 511                         status);
 512
 513                 /* Try to recover */
 514                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 515                 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
 516                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 517                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 518                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 519         }
 520
 521         tasklet_schedule(&dw->tasklet);
 522
 523         return IRQ_HANDLED;
 524 }
 525
 526 /*----------------------------------------------------------------------*/
 527
 528 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 529 {
 530         struct dw_desc          *desc = txd_to_dw_desc(tx);
 531         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 532         dma_cookie_t            cookie;
 533
 534         spin_lock_bh(&dwc->lock);
 535         cookie = dwc_assign_cookie(dwc, desc);
 536
 537         /*
 538          * REVISIT: We should attempt to chain as many descriptors as
 539          * possible, perhaps even appending to those already submitted
 540          * for DMA. But this is hard to do in a race-free manner.
 541          */
 542         if (list_empty(&dwc->active_list)) {
 543                 dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
 544                                 desc->txd.cookie);
 545                 list_add_tail(&desc->desc_node, &dwc->active_list);
 546                 dwc_dostart(dwc, dwc_first_active(dwc));
 547         } else {
 548                 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
 549                                 desc->txd.cookie);
 550
 551                 list_add_tail(&desc->desc_node, &dwc->queue);
 552         }
 553
 554         spin_unlock_bh(&dwc->lock);
 555
 556         return cookie;
 557 }
 558
 559 static struct dma_async_tx_descriptor *
 560 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 561                 size_t len, unsigned long flags)
 562 {
 563         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 564         struct dw_desc          *desc;
 565         struct dw_desc          *first;
 566         struct dw_desc          *prev;
 567         size_t                  xfer_count;
 568         size_t                  offset;
 569         unsigned int            src_width;
 570         unsigned int            dst_width;
 571         u32                     ctllo;
 572
 573         dev_vdbg(chan2dev(chan), "prep_dma_memcpy d0x%x s0x%x l0x%zx f0x%lx\n",
 574                         dest, src, len, flags);
 575
 576         if (unlikely(!len)) {
 577                 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
 578                 return NULL;
 579         }
 580
 581         /*
 582          * We can be a lot more clever here, but this should take care
 583          * of the most common optimization.
 584          */
 585         if (!((src | dest  | len) & 7))
 586                 src_width = dst_width = 3;
 587         else if (!((src | dest  | len) & 3))
 588                 src_width = dst_width = 2;
 589         else if (!((src | dest | len) & 1))
 590                 src_width = dst_width = 1;
 591         else
 592                 src_width = dst_width = 0;
 593
 594         ctllo = DWC_DEFAULT_CTLLO(chan->private)
 595                         | DWC_CTLL_DST_WIDTH(dst_width)
 596                         | DWC_CTLL_SRC_WIDTH(src_width)
 597                         | DWC_CTLL_DST_INC
 598                         | DWC_CTLL_SRC_INC
 599                         | DWC_CTLL_FC_M2M;
 600         prev = first = NULL;
 601
 602         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 603                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 604                                 DWC_MAX_COUNT);
 605
 606                 desc = dwc_desc_get(dwc);
 607                 if (!desc)
 608                         goto err_desc_get;
 609
 610                 desc->lli.sar = src + offset;
 611                 desc->lli.dar = dest + offset;
 612                 desc->lli.ctllo = ctllo;
 613                 desc->lli.ctlhi = xfer_count;
 614
 615                 if (!first) {
 616                         first = desc;
 617                 } else {
 618                         prev->lli.llp = desc->txd.phys;
 619                         dma_sync_single_for_device(chan2parent(chan),
 620                                         prev->txd.phys, sizeof(prev->lli),
 621                                         DMA_TO_DEVICE);
 622                         list_add_tail(&desc->desc_node,
 623                                         &first->tx_list);
 624                 }
 625                 prev = desc;
 626         }
 627
 628
 629         if (flags & DMA_PREP_INTERRUPT)
 630                 /* Trigger interrupt after last block */
 631                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 632
 633         prev->lli.llp = 0;
 634         dma_sync_single_for_device(chan2parent(chan),
 635                         prev->txd.phys, sizeof(prev->lli),
 636                         DMA_TO_DEVICE);
 637
 638         first->txd.flags = flags;
 639         first->len = len;
 640
 641         return &first->txd;
 642
 643 err_desc_get:
 644         dwc_desc_put(dwc, first);
 645         return NULL;
 646 }
 647
 648 static struct dma_async_tx_descriptor *
 649 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 650                 unsigned int sg_len, enum dma_data_direction direction,
 651                 unsigned long flags)
 652 {
 653         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 654         struct dw_dma_slave     *dws = chan->private;
 655         struct dw_desc          *prev;
 656         struct dw_desc          *first;
 657         u32                     ctllo;
 658         dma_addr_t              reg;
 659         unsigned int            reg_width;
 660         unsigned int            mem_width;
 661         unsigned int            i;
 662         struct scatterlist      *sg;
 663         size_t                  total_len = 0;
 664
 665         dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
 666
 667         if (unlikely(!dws || !sg_len))
 668                 return NULL;
 669
 670         reg_width = dws->reg_width;
 671         prev = first = NULL;
 672
 673         switch (direction) {
 674         case DMA_TO_DEVICE:
 675                 ctllo = (DWC_DEFAULT_CTLLO(chan->private)
 676                                 | DWC_CTLL_DST_WIDTH(reg_width)
 677                                 | DWC_CTLL_DST_FIX
 678                                 | DWC_CTLL_SRC_INC
 679                                 | DWC_CTLL_FC_M2P);
 680                 reg = dws->tx_reg;
 681                 for_each_sg(sgl, sg, sg_len, i) {
 682                         struct dw_desc  *desc;
 683                         u32             len;
 684                         u32             mem;
 685
 686                         desc = dwc_desc_get(dwc);
 687                         if (!desc) {
 688                                 dev_err(chan2dev(chan),
 689                                         "not enough descriptors available\n");
 690                                 goto err_desc_get;
 691                         }
 692
 693                         mem = sg_phys(sg);
 694                         len = sg_dma_len(sg);
 695                         mem_width = 2;
 696                         if (unlikely(mem & 3 || len & 3))
 697                                 mem_width = 0;
 698
 699                         desc->lli.sar = mem;
 700                         desc->lli.dar = reg;
 701                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 702                         desc->lli.ctlhi = len >> mem_width;
 703
 704                         if (!first) {
 705                                 first = desc;
 706                         } else {
 707                                 prev->lli.llp = desc->txd.phys;
 708                                 dma_sync_single_for_device(chan2parent(chan),
 709                                                 prev->txd.phys,
 710                                                 sizeof(prev->lli),
 711                                                 DMA_TO_DEVICE);
 712                                 list_add_tail(&desc->desc_node,
 713                                                 &first->tx_list);
 714                         }
 715                         prev = desc;
 716                         total_len += len;
 717                 }
 718                 break;
 719         case DMA_FROM_DEVICE:
 720                 ctllo = (DWC_DEFAULT_CTLLO(chan->private)
 721                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 722                                 | DWC_CTLL_DST_INC
 723                                 | DWC_CTLL_SRC_FIX
 724                                 | DWC_CTLL_FC_P2M);
 725
 726                 reg = dws->rx_reg;
 727                 for_each_sg(sgl, sg, sg_len, i) {
 728                         struct dw_desc  *desc;
 729                         u32             len;
 730                         u32             mem;
 731
 732                         desc = dwc_desc_get(dwc);
 733                         if (!desc) {
 734                                 dev_err(chan2dev(chan),
 735                                         "not enough descriptors available\n");
 736                                 goto err_desc_get;
 737                         }
 738
 739                         mem = sg_phys(sg);
 740                         len = sg_dma_len(sg);
 741                         mem_width = 2;
 742                         if (unlikely(mem & 3 || len & 3))
 743                                 mem_width = 0;
 744
 745                         desc->lli.sar = reg;
 746                         desc->lli.dar = mem;
 747                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 748                         desc->lli.ctlhi = len >> reg_width;
 749
 750                         if (!first) {
 751                                 first = desc;
 752                         } else {
 753                                 prev->lli.llp = desc->txd.phys;
 754                                 dma_sync_single_for_device(chan2parent(chan),
 755                                                 prev->txd.phys,
 756                                                 sizeof(prev->lli),
 757                                                 DMA_TO_DEVICE);
 758                                 list_add_tail(&desc->desc_node,
 759                                                 &first->tx_list);
 760                         }
 761                         prev = desc;
 762                         total_len += len;
 763                 }
 764                 break;
 765         default:
 766                 return NULL;
 767         }
 768
 769         if (flags & DMA_PREP_INTERRUPT)
 770                 /* Trigger interrupt after last block */
 771                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 772
 773         prev->lli.llp = 0;
 774         dma_sync_single_for_device(chan2parent(chan),
 775                         prev->txd.phys, sizeof(prev->lli),
 776                         DMA_TO_DEVICE);
 777
 778         first->len = total_len;
 779
 780         return &first->txd;
 781
 782 err_desc_get:
 783         dwc_desc_put(dwc, first);
 784         return NULL;
 785 }
 786
 787 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 788                        unsigned long arg)
 789 {
 790         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 791         struct dw_dma           *dw = to_dw_dma(chan->device);
 792         struct dw_desc          *desc, *_desc;
 793         LIST_HEAD(list);
 794
 795         /* Only supports DMA_TERMINATE_ALL */
 796         if (cmd != DMA_TERMINATE_ALL)
 797                 return -ENXIO;
 798
 799         /*
 800          * This is only called when something went wrong elsewhere, so
 801          * we don't really care about the data. Just disable the
 802          * channel. We still have to poll the channel enable bit due
 803          * to AHB/HSB limitations.
 804          */
 805         spin_lock_bh(&dwc->lock);
 806
 807         channel_clear_bit(dw, CH_EN, dwc->mask);
 808
 809         while (dma_readl(dw, CH_EN) & dwc->mask)
 810                 cpu_relax();
 811
 812         /* active_list entries will end up before queued entries */
 813         list_splice_init(&dwc->queue, &list);
 814         list_splice_init(&dwc->active_list, &list);
 815
 816         spin_unlock_bh(&dwc->lock);
 817
 818         /* Flush all pending and queued descriptors */
 819         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 820                 dwc_descriptor_complete(dwc, desc);
 821
 822         return 0;
 823 }
 824
 825 static enum dma_status
 826 dwc_tx_status(struct dma_chan *chan,
 827               dma_cookie_t cookie,
 828               struct dma_tx_state *txstate)
 829 {
 830         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 831         dma_cookie_t            last_used;
 832         dma_cookie_t            last_complete;
 833         int                     ret;
 834
 835         last_complete = dwc->completed;
 836         last_used = chan->cookie;
 837
 838         ret = dma_async_is_complete(cookie, last_complete, last_used);
 839         if (ret != DMA_SUCCESS) {
 840                 spin_lock_bh(&dwc->lock);
 841                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
 842                 spin_unlock_bh(&dwc->lock);
 843
 844                 last_complete = dwc->completed;
 845                 last_used = chan->cookie;
 846
 847                 ret = dma_async_is_complete(cookie, last_complete, last_used);
 848         }
 849
 850         dma_set_tx_state(txstate, last_complete, last_used, 0);
 851
 852         return ret;
 853 }
 854
 855 static void dwc_issue_pending(struct dma_chan *chan)
 856 {
 857         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 858
 859         spin_lock_bh(&dwc->lock);
 860         if (!list_empty(&dwc->queue))
 861                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
 862         spin_unlock_bh(&dwc->lock);
 863 }
 864
 865 static int dwc_alloc_chan_resources(struct dma_chan *chan)
 866 {
 867         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 868         struct dw_dma           *dw = to_dw_dma(chan->device);
 869         struct dw_desc          *desc;
 870         struct dw_dma_slave     *dws;
 871         int                     i;
 872         u32                     cfghi;
 873         u32                     cfglo;
 874
 875         dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
 876
 877         /* ASSERT:  channel is idle */
 878         if (dma_readl(dw, CH_EN) & dwc->mask) {
 879                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
 880                 return -EIO;
 881         }
 882
 883         dwc->completed = chan->cookie = 1;
 884
 885         cfghi = DWC_CFGH_FIFO_MODE;
 886         cfglo = 0;
 887
 888         dws = chan->private;
 889         if (dws) {
 890                 /*
 891                  * We need controller-specific data to set up slave
 892                  * transfers.
 893                  */
 894                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 895
 896                 cfghi = dws->cfg_hi;
 897                 cfglo = dws->cfg_lo;
 898         }
 899         channel_writel(dwc, CFG_LO, cfglo);
 900         channel_writel(dwc, CFG_HI, cfghi);
 901
 902         /*
 903          * NOTE: some controllers may have additional features that we
 904          * need to initialize here, like "scatter-gather" (which
 905          * doesn't mean what you think it means), and status writeback.
 906          */
 907
 908         spin_lock_bh(&dwc->lock);
 909         i = dwc->descs_allocated;
 910         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
 911                 spin_unlock_bh(&dwc->lock);
 912
 913                 desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL);
 914                 if (!desc) {
 915                         dev_info(chan2dev(chan),
 916                                 "only allocated %d descriptors\n", i);
 917                         spin_lock_bh(&dwc->lock);
 918                         break;
 919                 }
 920
 921                 INIT_LIST_HEAD(&desc->tx_list);
 922                 dma_async_tx_descriptor_init(&desc->txd, chan);
 923                 desc->txd.tx_submit = dwc_tx_submit;
 924                 desc->txd.flags = DMA_CTRL_ACK;
 925                 desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
 926                                 sizeof(desc->lli), DMA_TO_DEVICE);
 927                 dwc_desc_put(dwc, desc);
 928
 929                 spin_lock_bh(&dwc->lock);
 930                 i = ++dwc->descs_allocated;
 931         }
 932
 933         /* Enable interrupts */
 934         channel_set_bit(dw, MASK.XFER, dwc->mask);
 935         channel_set_bit(dw, MASK.BLOCK, dwc->mask);
 936         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 937
 938         spin_unlock_bh(&dwc->lock);
 939
 940         dev_dbg(chan2dev(chan),
 941                 "alloc_chan_resources allocated %d descriptors\n", i);
 942
 943         return i;
 944 }
 945
 946 static void dwc_free_chan_resources(struct dma_chan *chan)
 947 {
 948         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 949         struct dw_dma           *dw = to_dw_dma(chan->device);
 950         struct dw_desc          *desc, *_desc;
 951         LIST_HEAD(list);
 952
 953         dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
 954                         dwc->descs_allocated);
 955
 956         /* ASSERT:  channel is idle */
 957         BUG_ON(!list_empty(&dwc->active_list));
 958         BUG_ON(!list_empty(&dwc->queue));
 959         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
 960
 961         spin_lock_bh(&dwc->lock);
 962         list_splice_init(&dwc->free_list, &list);
 963         dwc->descs_allocated = 0;
 964
 965         /* Disable interrupts */
 966         channel_clear_bit(dw, MASK.XFER, dwc->mask);
 967         channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
 968         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
 969
 970         spin_unlock_bh(&dwc->lock);
 971
 972         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
 973                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
 974                 dma_unmap_single(chan2parent(chan), desc->txd.phys,
 975                                 sizeof(desc->lli), DMA_TO_DEVICE);
 976                 kfree(desc);
 977         }
 978
 979         dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
 980 }
 981
 982 /* --------------------- Cyclic DMA API extensions -------------------- */
 983
 984 /**
 985  * dw_dma_cyclic_start - start the cyclic DMA transfer
 986  * @chan: the DMA channel to start
 987  *
 988  * Must be called with soft interrupts disabled. Returns zero on success or
 989  * -errno on failure.
 990  */
 991 int dw_dma_cyclic_start(struct dma_chan *chan)
 992 {
 993         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 994         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
 995
 996         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
 997                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
 998                 return -ENODEV;
 999         }
1000
1001         spin_lock(&dwc->lock);
1002
1003         /* assert channel is idle */
1004         if (dma_readl(dw, CH_EN) & dwc->mask) {
1005                 dev_err(chan2dev(&dwc->chan),
1006                         "BUG: Attempted to start non-idle channel\n");
1007                 dev_err(chan2dev(&dwc->chan),
1008                         "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
1009                         channel_readl(dwc, SAR),
1010                         channel_readl(dwc, DAR),
1011                         channel_readl(dwc, LLP),
1012                         channel_readl(dwc, CTL_HI),
1013                         channel_readl(dwc, CTL_LO));
1014                 spin_unlock(&dwc->lock);
1015                 return -EBUSY;
1016         }
1017
1018         dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1019         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1020         dma_writel(dw, CLEAR.XFER, dwc->mask);
1021
1022         /* setup DMAC channel registers */
1023         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1024         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1025         channel_writel(dwc, CTL_HI, 0);
1026
1027         channel_set_bit(dw, CH_EN, dwc->mask);
1028
1029         spin_unlock(&dwc->lock);
1030
1031         return 0;
1032 }
1033 EXPORT_SYMBOL(dw_dma_cyclic_start);
1034
1035 /**
1036  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1037  * @chan: the DMA channel to stop
1038  *
1039  * Must be called with soft interrupts disabled.
1040  */
1041 void dw_dma_cyclic_stop(struct dma_chan *chan)
1042 {
1043         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1044         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1045
1046         spin_lock(&dwc->lock);
1047
1048         channel_clear_bit(dw, CH_EN, dwc->mask);
1049         while (dma_readl(dw, CH_EN) & dwc->mask)
1050                 cpu_relax();
1051
1052         spin_unlock(&dwc->lock);
1053 }
1054 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1055
1056 /**
1057  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1058  * @chan: the DMA channel to prepare
1059  * @buf_addr: physical DMA address where the buffer starts
1060  * @buf_len: total number of bytes for the entire buffer
1061  * @period_len: number of bytes for each period
1062  * @direction: transfer direction, to or from device
1063  *
1064  * Must be called before trying to start the transfer. Returns a valid struct
1065  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1066  */
1067 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1068                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1069                 enum dma_data_direction direction)
1070 {
1071         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1072         struct dw_cyclic_desc           *cdesc;
1073         struct dw_cyclic_desc           *retval = NULL;
1074         struct dw_desc                  *desc;
1075         struct dw_desc                  *last = NULL;
1076         struct dw_dma_slave             *dws = chan->private;
1077         unsigned long                   was_cyclic;
1078         unsigned int                    reg_width;
1079         unsigned int                    periods;
1080         unsigned int                    i;
1081
1082         spin_lock_bh(&dwc->lock);
1083         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1084                 spin_unlock_bh(&dwc->lock);
1085                 dev_dbg(chan2dev(&dwc->chan),
1086                                 "queue and/or active list are not empty\n");
1087                 return ERR_PTR(-EBUSY);
1088         }
1089
1090         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1091         spin_unlock_bh(&dwc->lock);
1092         if (was_cyclic) {
1093                 dev_dbg(chan2dev(&dwc->chan),
1094                                 "channel already prepared for cyclic DMA\n");
1095                 return ERR_PTR(-EBUSY);
1096         }
1097
1098         retval = ERR_PTR(-EINVAL);
1099         reg_width = dws->reg_width;
1100         periods = buf_len / period_len;
1101
1102         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1103         if (period_len > (DWC_MAX_COUNT << reg_width))
1104                 goto out_err;
1105         if (unlikely(period_len & ((1 << reg_width) - 1)))
1106                 goto out_err;
1107         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1108                 goto out_err;
1109         if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
1110                 goto out_err;
1111
1112         retval = ERR_PTR(-ENOMEM);
1113
1114         if (periods > NR_DESCS_PER_CHANNEL)
1115                 goto out_err;
1116
1117         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1118         if (!cdesc)
1119                 goto out_err;
1120
1121         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1122         if (!cdesc->desc)
1123                 goto out_err_alloc;
1124
1125         for (i = 0; i < periods; i++) {
1126                 desc = dwc_desc_get(dwc);
1127                 if (!desc)
1128                         goto out_err_desc_get;
1129
1130                 switch (direction) {
1131                 case DMA_TO_DEVICE:
1132                         desc->lli.dar = dws->tx_reg;
1133                         desc->lli.sar = buf_addr + (period_len * i);
1134                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)
1135                                         | DWC_CTLL_DST_WIDTH(reg_width)
1136                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1137                                         | DWC_CTLL_DST_FIX
1138                                         | DWC_CTLL_SRC_INC
1139                                         | DWC_CTLL_FC_M2P
1140                                         | DWC_CTLL_INT_EN);
1141                         break;
1142                 case DMA_FROM_DEVICE:
1143                         desc->lli.dar = buf_addr + (period_len * i);
1144                         desc->lli.sar = dws->rx_reg;
1145                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)
1146                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1147                                         | DWC_CTLL_DST_WIDTH(reg_width)
1148                                         | DWC_CTLL_DST_INC
1149                                         | DWC_CTLL_SRC_FIX
1150                                         | DWC_CTLL_FC_P2M
1151                                         | DWC_CTLL_INT_EN);
1152                         break;
1153                 default:
1154                         break;
1155                 }
1156
1157                 desc->lli.ctlhi = (period_len >> reg_width);
1158                 cdesc->desc[i] = desc;
1159
1160                 if (last) {
1161                         last->lli.llp = desc->txd.phys;
1162                         dma_sync_single_for_device(chan2parent(chan),
1163                                         last->txd.phys, sizeof(last->lli),
1164                                         DMA_TO_DEVICE);
1165                 }
1166
1167                 last = desc;
1168         }
1169
1170         /* lets make a cyclic list */
1171         last->lli.llp = cdesc->desc[0]->txd.phys;
1172         dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
1173                         sizeof(last->lli), DMA_TO_DEVICE);
1174
1175         dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%08x len %zu "
1176                         "period %zu periods %d\n", buf_addr, buf_len,
1177                         period_len, periods);
1178
1179         cdesc->periods = periods;
1180         dwc->cdesc = cdesc;
1181
1182         return cdesc;
1183
1184 out_err_desc_get:
1185         while (i--)
1186                 dwc_desc_put(dwc, cdesc->desc[i]);
1187 out_err_alloc:
1188         kfree(cdesc);
1189 out_err:
1190         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1191         return (struct dw_cyclic_desc *)retval;
1192 }
1193 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1194
1195 /**
1196  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1197  * @chan: the DMA channel to free
1198  */
1199 void dw_dma_cyclic_free(struct dma_chan *chan)
1200 {
1201         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1202         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1203         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1204         int                     i;
1205
1206         dev_dbg(chan2dev(&dwc->chan), "cyclic free\n");
1207
1208         if (!cdesc)
1209                 return;
1210
1211         spin_lock_bh(&dwc->lock);
1212
1213         channel_clear_bit(dw, CH_EN, dwc->mask);
1214         while (dma_readl(dw, CH_EN) & dwc->mask)
1215                 cpu_relax();
1216
1217         dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1218         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1219         dma_writel(dw, CLEAR.XFER, dwc->mask);
1220
1221         spin_unlock_bh(&dwc->lock);
1222
1223         for (i = 0; i < cdesc->periods; i++)
1224                 dwc_desc_put(dwc, cdesc->desc[i]);
1225
1226         kfree(cdesc->desc);
1227         kfree(cdesc);
1228
1229         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1230 }
1231 EXPORT_SYMBOL(dw_dma_cyclic_free);
1232
1233 /*----------------------------------------------------------------------*/
1234
1235 static void dw_dma_off(struct dw_dma *dw)
1236 {
1237         dma_writel(dw, CFG, 0);
1238
1239         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1240         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1241         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1242         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1243         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1244
1245         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1246                 cpu_relax();
1247 }
1248
1249 static int __init dw_probe(struct platform_device *pdev)
1250 {
1251         struct dw_dma_platform_data *pdata;
1252         struct resource         *io;
1253         struct dw_dma           *dw;
1254         size_t                  size;
1255         int                     irq;
1256         int                     err;
1257         int                     i;
1258
1259         pdata = pdev->dev.platform_data;
1260         if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1261                 return -EINVAL;
1262
1263         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1264         if (!io)
1265                 return -EINVAL;
1266
1267         irq = platform_get_irq(pdev, 0);
1268         if (irq < 0)
1269                 return irq;
1270
1271         size = sizeof(struct dw_dma);
1272         size += pdata->nr_channels * sizeof(struct dw_dma_chan);
1273         dw = kzalloc(size, GFP_KERNEL);
1274         if (!dw)
1275                 return -ENOMEM;
1276
1277         if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) {
1278                 err = -EBUSY;
1279                 goto err_kfree;
1280         }
1281
1282         dw->regs = ioremap(io->start, DW_REGLEN);
1283         if (!dw->regs) {
1284                 err = -ENOMEM;
1285                 goto err_release_r;
1286         }
1287
1288         dw->clk = clk_get(&pdev->dev, "hclk");
1289         if (IS_ERR(dw->clk)) {
1290                 err = PTR_ERR(dw->clk);
1291                 goto err_clk;
1292         }
1293         clk_enable(dw->clk);
1294
1295         /* force dma off, just in case */
1296         dw_dma_off(dw);
1297
1298         err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw);
1299         if (err)
1300                 goto err_irq;
1301
1302         platform_set_drvdata(pdev, dw);
1303
1304         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1305
1306         dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1307
1308         INIT_LIST_HEAD(&dw->dma.channels);
1309         for (i = 0; i < pdata->nr_channels; i++, dw->dma.chancnt++) {
1310                 struct dw_dma_chan      *dwc = &dw->chan[i];
1311
1312                 dwc->chan.device = &dw->dma;
1313                 dwc->chan.cookie = dwc->completed = 1;
1314                 dwc->chan.chan_id = i;
1315                 list_add_tail(&dwc->chan.device_node, &dw->dma.channels);
1316
1317                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1318                 spin_lock_init(&dwc->lock);
1319                 dwc->mask = 1 << i;
1320
1321                 INIT_LIST_HEAD(&dwc->active_list);
1322                 INIT_LIST_HEAD(&dwc->queue);
1323                 INIT_LIST_HEAD(&dwc->free_list);
1324
1325                 channel_clear_bit(dw, CH_EN, dwc->mask);
1326         }
1327
1328         /* Clear/disable all interrupts on all channels. */
1329         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1330         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1331         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1332         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1333         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1334
1335         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1336         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1337         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1338         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1339         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1340
1341         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1342         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1343         if (pdata->is_private)
1344                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1345         dw->dma.dev = &pdev->dev;
1346         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1347         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1348
1349         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1350
1351         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1352         dw->dma.device_control = dwc_control;
1353
1354         dw->dma.device_tx_status = dwc_tx_status;
1355         dw->dma.device_issue_pending = dwc_issue_pending;
1356
1357         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1358
1359         printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n",
1360                         dev_name(&pdev->dev), dw->dma.chancnt);
1361
1362         dma_async_device_register(&dw->dma);
1363
1364         return 0;
1365
1366 err_irq:
1367         clk_disable(dw->clk);
1368         clk_put(dw->clk);
1369 err_clk:
1370         iounmap(dw->regs);
1371         dw->regs = NULL;
1372 err_release_r:
1373         release_resource(io);
1374 err_kfree:
1375         kfree(dw);
1376         return err;
1377 }
1378
1379 static int __exit dw_remove(struct platform_device *pdev)
1380 {
1381         struct dw_dma           *dw = platform_get_drvdata(pdev);
1382         struct dw_dma_chan      *dwc, *_dwc;
1383         struct resource         *io;
1384
1385         dw_dma_off(dw);
1386         dma_async_device_unregister(&dw->dma);
1387
1388         free_irq(platform_get_irq(pdev, 0), dw);
1389         tasklet_kill(&dw->tasklet);
1390
1391         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1392                         chan.device_node) {
1393                 list_del(&dwc->chan.device_node);
1394                 channel_clear_bit(dw, CH_EN, dwc->mask);
1395         }
1396
1397         clk_disable(dw->clk);
1398         clk_put(dw->clk);
1399
1400         iounmap(dw->regs);
1401         dw->regs = NULL;
1402
1403         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1404         release_mem_region(io->start, DW_REGLEN);
1405
1406         kfree(dw);
1407
1408         return 0;
1409 }
1410
1411 static void dw_shutdown(struct platform_device *pdev)
1412 {
1413         struct dw_dma   *dw = platform_get_drvdata(pdev);
1414
1415         dw_dma_off(platform_get_drvdata(pdev));
1416         clk_disable(dw->clk);
1417 }
1418
1419 static int dw_suspend_noirq(struct device *dev)
1420 {
1421         struct platform_device *pdev = to_platform_device(dev);
1422         struct dw_dma   *dw = platform_get_drvdata(pdev);
1423
1424         dw_dma_off(platform_get_drvdata(pdev));
1425         clk_disable(dw->clk);
1426         return 0;
1427 }
1428
1429 static int dw_resume_noirq(struct device *dev)
1430 {
1431         struct platform_device *pdev = to_platform_device(dev);
1432         struct dw_dma   *dw = platform_get_drvdata(pdev);
1433
1434         clk_enable(dw->clk);
1435         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1436         return 0;
1437 }
1438
1439 static const struct dev_pm_ops dw_dev_pm_ops = {
1440         .suspend_noirq = dw_suspend_noirq,
1441         .resume_noirq = dw_resume_noirq,
1442 };
1443
1444 static struct platform_driver dw_driver = {
1445         .remove         = __exit_p(dw_remove),
1446         .shutdown       = dw_shutdown,
1447         .driver = {
1448                 .name   = "dw_dmac",
1449                 .pm     = &dw_dev_pm_ops,
1450         },
1451 };
1452
1453 static int __init dw_init(void)
1454 {
1455         return platform_driver_probe(&dw_driver, dw_probe);
1456 }
1457 subsys_initcall(dw_init);
1458
1459 static void __exit dw_exit(void)
1460 {
1461         platform_driver_unregister(&dw_driver);
1462 }
1463 module_exit(dw_exit);
1464
1465 MODULE_LICENSE("GPL v2");
1466 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1467 MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");