2 * TI EDMA DMA engine driver
4 * Copyright 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/dmaengine.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/list.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
27 #include <linux/platform_data/edma.h>
29 #include "dmaengine.h"
33 * This will go away when the private EDMA API is folded
34 * into this driver and the platform device(s) are
35 * instantiated in the arch code. We can only get away
36 * with this simplification because DA8XX may not be built
37 * in the same kernel image with other DaVinci parts. This
38 * avoids having to sprinkle dmaengine driver platform devices
39 * and data throughout all the existing board files.
41 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
47 #endif /* CONFIG_ARCH_DAVINCI_DA8XX */
50 * Max of 20 segments per channel to conserve PaRAM slots
51 * Also note that MAX_NR_SG should be atleast the no.of periods
52 * that are required for ASoC, otherwise DMA prep calls will
53 * fail. Today davinci-pcm is the only user of this driver and
54 * requires atleast 17 slots, so we setup the default to 20.
57 #define EDMA_MAX_SLOTS MAX_NR_SG
58 #define EDMA_DESCRIPTORS 16
61 struct virt_dma_desc vdesc;
62 struct list_head node;
66 struct edmacc_param pset[0];
72 struct virt_dma_chan vchan;
73 struct list_head node;
74 struct edma_desc *edesc;
78 int slot[EDMA_MAX_SLOTS];
80 struct dma_slave_config cfg;
85 struct dma_device dma_slave;
86 struct edma_chan slave_chans[EDMA_CHANS];
91 static inline struct edma_cc *to_edma_cc(struct dma_device *d)
93 return container_of(d, struct edma_cc, dma_slave);
96 static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
98 return container_of(c, struct edma_chan, vchan.chan);
101 static inline struct edma_desc
102 *to_edma_desc(struct dma_async_tx_descriptor *tx)
104 return container_of(tx, struct edma_desc, vdesc.tx);
107 static void edma_desc_free(struct virt_dma_desc *vdesc)
109 kfree(container_of(vdesc, struct edma_desc, vdesc));
112 /* Dispatch a queued descriptor to the controller (caller holds lock) */
113 static void edma_execute(struct edma_chan *echan)
115 struct virt_dma_desc *vdesc;
116 struct edma_desc *edesc;
117 struct device *dev = echan->vchan.chan.device->dev;
118 int i, j, left, nslots;
120 /* If either we processed all psets or we're still not started */
122 echan->edesc->pset_nr == echan->edesc->processed) {
124 vdesc = vchan_next_desc(&echan->vchan);
129 list_del(&vdesc->node);
130 echan->edesc = to_edma_desc(&vdesc->tx);
133 edesc = echan->edesc;
135 /* Find out how many left */
136 left = edesc->pset_nr - edesc->processed;
137 nslots = min(MAX_NR_SG, left);
139 /* Write descriptor PaRAM set(s) */
140 for (i = 0; i < nslots; i++) {
141 j = i + edesc->processed;
142 edma_write_slot(echan->slot[i], &edesc->pset[j]);
143 dev_dbg(echan->vchan.chan.device->dev,
155 j, echan->ch_num, echan->slot[i],
159 edesc->pset[j].a_b_cnt,
161 edesc->pset[j].src_dst_bidx,
162 edesc->pset[j].src_dst_cidx,
163 edesc->pset[j].link_bcntrld);
164 /* Link to the previous slot if not the last set */
165 if (i != (nslots - 1))
166 edma_link(echan->slot[i], echan->slot[i+1]);
169 edesc->processed += nslots;
172 * If this is either the last set in a set of SG-list transactions
173 * then setup a link to the dummy slot, this results in all future
174 * events being absorbed and that's OK because we're done
176 if (edesc->processed == edesc->pset_nr)
177 edma_link(echan->slot[nslots-1], echan->ecc->dummy_slot);
179 edma_resume(echan->ch_num);
181 if (edesc->processed <= MAX_NR_SG) {
182 dev_dbg(dev, "first transfer starting %d\n", echan->ch_num);
183 edma_start(echan->ch_num);
187 * This happens due to setup times between intermediate transfers
188 * in long SG lists which have to be broken up into transfers of
192 dev_dbg(dev, "missed event in execute detected\n");
193 edma_clean_channel(echan->ch_num);
194 edma_stop(echan->ch_num);
195 edma_start(echan->ch_num);
196 edma_trigger_channel(echan->ch_num);
201 static int edma_terminate_all(struct edma_chan *echan)
206 spin_lock_irqsave(&echan->vchan.lock, flags);
209 * Stop DMA activity: we assume the callback will not be called
210 * after edma_dma() returns (even if it does, it will see
211 * echan->edesc is NULL and exit.)
215 edma_stop(echan->ch_num);
218 vchan_get_all_descriptors(&echan->vchan, &head);
219 spin_unlock_irqrestore(&echan->vchan.lock, flags);
220 vchan_dma_desc_free_list(&echan->vchan, &head);
225 static int edma_slave_config(struct edma_chan *echan,
226 struct dma_slave_config *cfg)
228 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
229 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
232 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
237 static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
241 struct dma_slave_config *config;
242 struct edma_chan *echan = to_edma_chan(chan);
245 case DMA_TERMINATE_ALL:
246 edma_terminate_all(echan);
248 case DMA_SLAVE_CONFIG:
249 config = (struct dma_slave_config *)arg;
250 ret = edma_slave_config(echan, config);
260 * A PaRAM set configuration abstraction used by other modes
261 * @chan: Channel who's PaRAM set we're configuring
262 * @pset: PaRAM set to initialize and setup.
263 * @src_addr: Source address of the DMA
264 * @dst_addr: Destination address of the DMA
265 * @burst: In units of dev_width, how much to send
266 * @dev_width: How much is the dev_width
267 * @dma_length: Total length of the DMA transfer
268 * @direction: Direction of the transfer
270 static int edma_config_pset(struct dma_chan *chan, struct edmacc_param *pset,
271 dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
272 enum dma_slave_buswidth dev_width, unsigned int dma_length,
273 enum dma_transfer_direction direction)
275 struct edma_chan *echan = to_edma_chan(chan);
276 struct device *dev = chan->device->dev;
277 int acnt, bcnt, ccnt, cidx;
278 int src_bidx, dst_bidx, src_cidx, dst_cidx;
283 * If the maxburst is equal to the fifo width, use
284 * A-synced transfers. This allows for large contiguous
285 * buffer transfers using only one PaRAM set.
289 * For the A-sync case, bcnt and ccnt are the remainder
290 * and quotient respectively of the division of:
291 * (dma_length / acnt) by (SZ_64K -1). This is so
292 * that in case bcnt over flows, we have ccnt to use.
293 * Note: In A-sync tranfer only, bcntrld is used, but it
294 * only applies for sg_dma_len(sg) >= SZ_64K.
295 * In this case, the best way adopted is- bccnt for the
296 * first frame will be the remainder below. Then for
297 * every successive frame, bcnt will be SZ_64K-1. This
298 * is assured as bcntrld = 0xffff in end of function.
301 ccnt = dma_length / acnt / (SZ_64K - 1);
302 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
304 * If bcnt is non-zero, we have a remainder and hence an
305 * extra frame to transfer, so increment ccnt.
314 * If maxburst is greater than the fifo address_width,
315 * use AB-synced transfers where A count is the fifo
316 * address_width and B count is the maxburst. In this
317 * case, we are limited to transfers of C count frames
318 * of (address_width * maxburst) where C count is limited
319 * to SZ_64K-1. This places an upper bound on the length
320 * of an SG segment that can be handled.
324 ccnt = dma_length / (acnt * bcnt);
325 if (ccnt > (SZ_64K - 1)) {
326 dev_err(dev, "Exceeded max SG segment size\n");
332 if (direction == DMA_MEM_TO_DEV) {
337 } else if (direction == DMA_DEV_TO_MEM) {
343 dev_err(dev, "%s: direction not implemented yet\n", __func__);
347 pset->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
348 /* Configure A or AB synchronized transfers */
350 pset->opt |= SYNCDIM;
352 pset->src = src_addr;
353 pset->dst = dst_addr;
355 pset->src_dst_bidx = (dst_bidx << 16) | src_bidx;
356 pset->src_dst_cidx = (dst_cidx << 16) | src_cidx;
358 pset->a_b_cnt = bcnt << 16 | acnt;
361 * Only time when (bcntrld) auto reload is required is for
362 * A-sync case, and in this case, a requirement of reload value
363 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
364 * and then later will be populated by edma_execute.
366 pset->link_bcntrld = 0xffffffff;
370 static struct dma_async_tx_descriptor *edma_prep_slave_sg(
371 struct dma_chan *chan, struct scatterlist *sgl,
372 unsigned int sg_len, enum dma_transfer_direction direction,
373 unsigned long tx_flags, void *context)
375 struct edma_chan *echan = to_edma_chan(chan);
376 struct device *dev = chan->device->dev;
377 struct edma_desc *edesc;
378 dma_addr_t src_addr = 0, dst_addr = 0;
379 enum dma_slave_buswidth dev_width;
381 struct scatterlist *sg;
384 if (unlikely(!echan || !sgl || !sg_len))
387 if (direction == DMA_DEV_TO_MEM) {
388 src_addr = echan->cfg.src_addr;
389 dev_width = echan->cfg.src_addr_width;
390 burst = echan->cfg.src_maxburst;
391 } else if (direction == DMA_MEM_TO_DEV) {
392 dst_addr = echan->cfg.dst_addr;
393 dev_width = echan->cfg.dst_addr_width;
394 burst = echan->cfg.dst_maxburst;
396 dev_err(dev, "%s: bad direction?\n", __func__);
400 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
401 dev_err(dev, "Undefined slave buswidth\n");
405 edesc = kzalloc(sizeof(*edesc) + sg_len *
406 sizeof(edesc->pset[0]), GFP_ATOMIC);
408 dev_dbg(dev, "Failed to allocate a descriptor\n");
412 edesc->pset_nr = sg_len;
414 /* Allocate a PaRAM slot, if needed */
415 nslots = min_t(unsigned, MAX_NR_SG, sg_len);
417 for (i = 0; i < nslots; i++) {
418 if (echan->slot[i] < 0) {
420 edma_alloc_slot(EDMA_CTLR(echan->ch_num),
422 if (echan->slot[i] < 0) {
423 dev_err(dev, "Failed to allocate slot\n");
430 /* Configure PaRAM sets for each SG */
431 for_each_sg(sgl, sg, sg_len, i) {
432 /* Get address for each SG */
433 if (direction == DMA_DEV_TO_MEM)
434 dst_addr = sg_dma_address(sg);
436 src_addr = sg_dma_address(sg);
438 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
439 dst_addr, burst, dev_width,
440 sg_dma_len(sg), direction);
446 /* If this is the last in a current SG set of transactions,
447 enable interrupts so that next set is processed */
448 if (!((i+1) % MAX_NR_SG))
449 edesc->pset[i].opt |= TCINTEN;
451 /* If this is the last set, enable completion interrupt flag */
453 edesc->pset[i].opt |= TCINTEN;
456 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
459 static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
461 struct edma_chan *echan = data;
462 struct device *dev = echan->vchan.chan.device->dev;
463 struct edma_desc *edesc;
465 struct edmacc_param p;
467 /* Pause the channel */
468 edma_pause(echan->ch_num);
472 spin_lock_irqsave(&echan->vchan.lock, flags);
474 edesc = echan->edesc;
476 if (edesc->processed == edesc->pset_nr) {
477 dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
478 edma_stop(echan->ch_num);
479 vchan_cookie_complete(&edesc->vdesc);
481 dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
487 spin_unlock_irqrestore(&echan->vchan.lock, flags);
491 spin_lock_irqsave(&echan->vchan.lock, flags);
493 edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
496 * Issue later based on missed flag which will be sure
498 * (1) we finished transmitting an intermediate slot and
499 * edma_execute is coming up.
500 * (2) or we finished current transfer and issue will
503 * Important note: issuing can be dangerous here and
504 * lead to some nasty recursion when we are in a NULL
505 * slot. So we avoid doing so and set the missed flag.
507 if (p.a_b_cnt == 0 && p.ccnt == 0) {
508 dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n");
512 * The slot is already programmed but the event got
513 * missed, so its safe to issue it here.
515 dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
516 edma_clean_channel(echan->ch_num);
517 edma_stop(echan->ch_num);
518 edma_start(echan->ch_num);
519 edma_trigger_channel(echan->ch_num);
522 spin_unlock_irqrestore(&echan->vchan.lock, flags);
530 /* Alloc channel resources */
531 static int edma_alloc_chan_resources(struct dma_chan *chan)
533 struct edma_chan *echan = to_edma_chan(chan);
534 struct device *dev = chan->device->dev;
539 a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
540 chan, EVENTQ_DEFAULT);
547 if (a_ch_num != echan->ch_num) {
548 dev_err(dev, "failed to allocate requested channel %u:%u\n",
549 EDMA_CTLR(echan->ch_num),
550 EDMA_CHAN_SLOT(echan->ch_num));
555 echan->alloced = true;
556 echan->slot[0] = echan->ch_num;
558 dev_info(dev, "allocated channel for %u:%u\n",
559 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
564 edma_free_channel(a_ch_num);
569 /* Free channel resources */
570 static void edma_free_chan_resources(struct dma_chan *chan)
572 struct edma_chan *echan = to_edma_chan(chan);
573 struct device *dev = chan->device->dev;
576 /* Terminate transfers */
577 edma_stop(echan->ch_num);
579 vchan_free_chan_resources(&echan->vchan);
581 /* Free EDMA PaRAM slots */
582 for (i = 1; i < EDMA_MAX_SLOTS; i++) {
583 if (echan->slot[i] >= 0) {
584 edma_free_slot(echan->slot[i]);
589 /* Free EDMA channel */
590 if (echan->alloced) {
591 edma_free_channel(echan->ch_num);
592 echan->alloced = false;
595 dev_info(dev, "freeing channel for %u\n", echan->ch_num);
598 /* Send pending descriptor to hardware */
599 static void edma_issue_pending(struct dma_chan *chan)
601 struct edma_chan *echan = to_edma_chan(chan);
604 spin_lock_irqsave(&echan->vchan.lock, flags);
605 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
607 spin_unlock_irqrestore(&echan->vchan.lock, flags);
610 static size_t edma_desc_size(struct edma_desc *edesc)
616 for (size = i = 0; i < edesc->pset_nr; i++)
617 size += (edesc->pset[i].a_b_cnt & 0xffff) *
618 (edesc->pset[i].a_b_cnt >> 16) *
621 size = (edesc->pset[0].a_b_cnt & 0xffff) *
622 (edesc->pset[0].a_b_cnt >> 16) +
623 (edesc->pset[0].a_b_cnt & 0xffff) *
624 (SZ_64K - 1) * edesc->pset[0].ccnt;
629 /* Check request completion status */
630 static enum dma_status edma_tx_status(struct dma_chan *chan,
632 struct dma_tx_state *txstate)
634 struct edma_chan *echan = to_edma_chan(chan);
635 struct virt_dma_desc *vdesc;
639 ret = dma_cookie_status(chan, cookie, txstate);
640 if (ret == DMA_COMPLETE || !txstate)
643 spin_lock_irqsave(&echan->vchan.lock, flags);
644 vdesc = vchan_find_desc(&echan->vchan, cookie);
646 txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx));
647 } else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
648 struct edma_desc *edesc = echan->edesc;
649 txstate->residue = edma_desc_size(edesc);
651 spin_unlock_irqrestore(&echan->vchan.lock, flags);
656 static void __init edma_chan_init(struct edma_cc *ecc,
657 struct dma_device *dma,
658 struct edma_chan *echans)
662 for (i = 0; i < EDMA_CHANS; i++) {
663 struct edma_chan *echan = &echans[i];
664 echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
666 echan->vchan.desc_free = edma_desc_free;
668 vchan_init(&echan->vchan, dma);
670 INIT_LIST_HEAD(&echan->node);
671 for (j = 0; j < EDMA_MAX_SLOTS; j++)
676 static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
679 dma->device_prep_slave_sg = edma_prep_slave_sg;
680 dma->device_alloc_chan_resources = edma_alloc_chan_resources;
681 dma->device_free_chan_resources = edma_free_chan_resources;
682 dma->device_issue_pending = edma_issue_pending;
683 dma->device_tx_status = edma_tx_status;
684 dma->device_control = edma_control;
687 INIT_LIST_HEAD(&dma->channels);
690 static int edma_probe(struct platform_device *pdev)
695 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
699 ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
701 dev_err(&pdev->dev, "Can't allocate controller\n");
705 ecc->ctlr = pdev->id;
706 ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
707 if (ecc->dummy_slot < 0) {
708 dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
712 dma_cap_zero(ecc->dma_slave.cap_mask);
713 dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
715 edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
717 edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
719 ret = dma_async_device_register(&ecc->dma_slave);
723 platform_set_drvdata(pdev, ecc);
725 dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
730 edma_free_slot(ecc->dummy_slot);
734 static int edma_remove(struct platform_device *pdev)
736 struct device *dev = &pdev->dev;
737 struct edma_cc *ecc = dev_get_drvdata(dev);
739 dma_async_device_unregister(&ecc->dma_slave);
740 edma_free_slot(ecc->dummy_slot);
745 static struct platform_driver edma_driver = {
747 .remove = edma_remove,
749 .name = "edma-dma-engine",
750 .owner = THIS_MODULE,
754 bool edma_filter_fn(struct dma_chan *chan, void *param)
756 if (chan->device->dev->driver == &edma_driver.driver) {
757 struct edma_chan *echan = to_edma_chan(chan);
758 unsigned ch_req = *(unsigned *)param;
759 return ch_req == echan->ch_num;
763 EXPORT_SYMBOL(edma_filter_fn);
765 static struct platform_device *pdev0, *pdev1;
767 static const struct platform_device_info edma_dev_info0 = {
768 .name = "edma-dma-engine",
770 .dma_mask = DMA_BIT_MASK(32),
773 static const struct platform_device_info edma_dev_info1 = {
774 .name = "edma-dma-engine",
776 .dma_mask = DMA_BIT_MASK(32),
779 static int edma_init(void)
781 int ret = platform_driver_register(&edma_driver);
784 pdev0 = platform_device_register_full(&edma_dev_info0);
786 platform_driver_unregister(&edma_driver);
787 ret = PTR_ERR(pdev0);
792 if (EDMA_CTLRS == 2) {
793 pdev1 = platform_device_register_full(&edma_dev_info1);
795 platform_driver_unregister(&edma_driver);
796 platform_device_unregister(pdev0);
797 ret = PTR_ERR(pdev1);
804 subsys_initcall(edma_init);
806 static void __exit edma_exit(void)
808 platform_device_unregister(pdev0);
810 platform_device_unregister(pdev1);
811 platform_driver_unregister(&edma_driver);
813 module_exit(edma_exit);
815 MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
816 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
817 MODULE_LICENSE("GPL v2");