drivers/dma/imx-sdma.c

   1 /*
   2  * drivers/dma/imx-sdma.c
   3  *
   4  * This file contains a driver for the Freescale Smart DMA engine
   5  *
   6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  *
   8  * Based on code from Freescale:
   9  *
  10  * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  * The code contained herein is licensed under the GNU General Public
  13  * License. You may obtain a copy of the GNU General Public License
  14  * Version 2 or later at the following locations:
  15  *
  16  * http://www.opensource.org/licenses/gpl-license.html
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/types.h>
  23 #include <linux/bitops.h>
  24 #include <linux/mm.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/clk.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/semaphore.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/device.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/firmware.h>
  34 #include <linux/slab.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/dmaengine.h>
  37 #include <linux/of.h>
  38 #include <linux/of_device.h>
  39 #include <linux/of_dma.h>
  40
  41 #include <asm/irq.h>
  42 #include <linux/platform_data/dma-imx-sdma.h>
  43 #include <linux/platform_data/dma-imx.h>
  44
  45 #include "dmaengine.h"
  46
  47 /* SDMA registers */
  48 #define SDMA_H_C0PTR            0x000
  49 #define SDMA_H_INTR             0x004
  50 #define SDMA_H_STATSTOP         0x008
  51 #define SDMA_H_START            0x00c
  52 #define SDMA_H_EVTOVR           0x010
  53 #define SDMA_H_DSPOVR           0x014
  54 #define SDMA_H_HOSTOVR          0x018
  55 #define SDMA_H_EVTPEND          0x01c
  56 #define SDMA_H_DSPENBL          0x020
  57 #define SDMA_H_RESET            0x024
  58 #define SDMA_H_EVTERR           0x028
  59 #define SDMA_H_INTRMSK          0x02c
  60 #define SDMA_H_PSW              0x030
  61 #define SDMA_H_EVTERRDBG        0x034
  62 #define SDMA_H_CONFIG           0x038
  63 #define SDMA_ONCE_ENB           0x040
  64 #define SDMA_ONCE_DATA          0x044
  65 #define SDMA_ONCE_INSTR         0x048
  66 #define SDMA_ONCE_STAT          0x04c
  67 #define SDMA_ONCE_CMD           0x050
  68 #define SDMA_EVT_MIRROR         0x054
  69 #define SDMA_ILLINSTADDR        0x058
  70 #define SDMA_CHN0ADDR           0x05c
  71 #define SDMA_ONCE_RTB           0x060
  72 #define SDMA_XTRIG_CONF1        0x070
  73 #define SDMA_XTRIG_CONF2        0x074
  74 #define SDMA_CHNENBL0_IMX35     0x200
  75 #define SDMA_CHNENBL0_IMX31     0x080
  76 #define SDMA_CHNPRI_0           0x100
  77
  78 /*
  79  * Buffer descriptor status values.
  80  */
  81 #define BD_DONE  0x01
  82 #define BD_WRAP  0x02
  83 #define BD_CONT  0x04
  84 #define BD_INTR  0x08
  85 #define BD_RROR  0x10
  86 #define BD_LAST  0x20
  87 #define BD_EXTD  0x80
  88
  89 /*
  90  * Data Node descriptor status values.
  91  */
  92 #define DND_END_OF_FRAME  0x80
  93 #define DND_END_OF_XFER   0x40
  94 #define DND_DONE          0x20
  95 #define DND_UNUSED        0x01
  96
  97 /*
  98  * IPCV2 descriptor status values.
  99  */
 100 #define BD_IPCV2_END_OF_FRAME  0x40
 101
 102 #define IPCV2_MAX_NODES        50
 103 /*
 104  * Error bit set in the CCB status field by the SDMA,
 105  * in setbd routine, in case of a transfer error
 106  */
 107 #define DATA_ERROR  0x10000000
 108
 109 /*
 110  * Buffer descriptor commands.
 111  */
 112 #define C0_ADDR             0x01
 113 #define C0_LOAD             0x02
 114 #define C0_DUMP             0x03
 115 #define C0_SETCTX           0x07
 116 #define C0_GETCTX           0x03
 117 #define C0_SETDM            0x01
 118 #define C0_SETPM            0x04
 119 #define C0_GETDM            0x02
 120 #define C0_GETPM            0x08
 121 /*
 122  * Change endianness indicator in the BD command field
 123  */
 124 #define CHANGE_ENDIANNESS   0x80
 125
 126 /*
 127  * Mode/Count of data node descriptors - IPCv2
 128  */
 129 struct sdma_mode_count {
 130         u32 count   : 16; /* size of the buffer pointed by this BD */
 131         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 132         u32 command :  8; /* command mostlky used for channel 0 */
 133 };
 134
 135 /*
 136  * Buffer descriptor
 137  */
 138 struct sdma_buffer_descriptor {
 139         struct sdma_mode_count  mode;
 140         u32 buffer_addr;        /* address of the buffer described */
 141         u32 ext_buffer_addr;    /* extended buffer address */
 142 } __attribute__ ((packed));
 143
 144 /**
 145  * struct sdma_channel_control - Channel control Block
 146  *
 147  * @current_bd_ptr      current buffer descriptor processed
 148  * @base_bd_ptr         first element of buffer descriptor array
 149  * @unused              padding. The SDMA engine expects an array of 128 byte
 150  *                      control blocks
 151  */
 152 struct sdma_channel_control {
 153         u32 current_bd_ptr;
 154         u32 base_bd_ptr;
 155         u32 unused[2];
 156 } __attribute__ ((packed));
 157
 158 /**
 159  * struct sdma_state_registers - SDMA context for a channel
 160  *
 161  * @pc:         program counter
 162  * @t:          test bit: status of arithmetic & test instruction
 163  * @rpc:        return program counter
 164  * @sf:         source fault while loading data
 165  * @spc:        loop start program counter
 166  * @df:         destination fault while storing data
 167  * @epc:        loop end program counter
 168  * @lm:         loop mode
 169  */
 170 struct sdma_state_registers {
 171         u32 pc     :14;
 172         u32 unused1: 1;
 173         u32 t      : 1;
 174         u32 rpc    :14;
 175         u32 unused0: 1;
 176         u32 sf     : 1;
 177         u32 spc    :14;
 178         u32 unused2: 1;
 179         u32 df     : 1;
 180         u32 epc    :14;
 181         u32 lm     : 2;
 182 } __attribute__ ((packed));
 183
 184 /**
 185  * struct sdma_context_data - sdma context specific to a channel
 186  *
 187  * @channel_state:      channel state bits
 188  * @gReg:               general registers
 189  * @mda:                burst dma destination address register
 190  * @msa:                burst dma source address register
 191  * @ms:                 burst dma status register
 192  * @md:                 burst dma data register
 193  * @pda:                peripheral dma destination address register
 194  * @psa:                peripheral dma source address register
 195  * @ps:                 peripheral dma status register
 196  * @pd:                 peripheral dma data register
 197  * @ca:                 CRC polynomial register
 198  * @cs:                 CRC accumulator register
 199  * @dda:                dedicated core destination address register
 200  * @dsa:                dedicated core source address register
 201  * @ds:                 dedicated core status register
 202  * @dd:                 dedicated core data register
 203  */
 204 struct sdma_context_data {
 205         struct sdma_state_registers  channel_state;
 206         u32  gReg[8];
 207         u32  mda;
 208         u32  msa;
 209         u32  ms;
 210         u32  md;
 211         u32  pda;
 212         u32  psa;
 213         u32  ps;
 214         u32  pd;
 215         u32  ca;
 216         u32  cs;
 217         u32  dda;
 218         u32  dsa;
 219         u32  ds;
 220         u32  dd;
 221         u32  scratch0;
 222         u32  scratch1;
 223         u32  scratch2;
 224         u32  scratch3;
 225         u32  scratch4;
 226         u32  scratch5;
 227         u32  scratch6;
 228         u32  scratch7;
 229 } __attribute__ ((packed));
 230
 231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 232
 233 struct sdma_engine;
 234
 235 /**
 236  * struct sdma_channel - housekeeping for a SDMA channel
 237  *
 238  * @sdma                pointer to the SDMA engine for this channel
 239  * @channel             the channel number, matches dmaengine chan_id + 1
 240  * @direction           transfer type. Needed for setting SDMA script
 241  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 242  * @event_id0           aka dma request line
 243  * @event_id1           for channels that use 2 events
 244  * @word_size           peripheral access size
 245  * @buf_tail            ID of the buffer that was processed
 246  * @num_bd              max NUM_BD. number of descriptors currently handling
 247  */
 248 struct sdma_channel {
 249         struct sdma_engine              *sdma;
 250         unsigned int                    channel;
 251         enum dma_transfer_direction             direction;
 252         enum sdma_peripheral_type       peripheral_type;
 253         unsigned int                    event_id0;
 254         unsigned int                    event_id1;
 255         enum dma_slave_buswidth         word_size;
 256         unsigned int                    buf_tail;
 257         unsigned int                    num_bd;
 258         unsigned int                    period_len;
 259         struct sdma_buffer_descriptor   *bd;
 260         dma_addr_t                      bd_phys;
 261         unsigned int                    pc_from_device, pc_to_device;
 262         unsigned int                    device_to_device;
 263         unsigned long                   flags;
 264         dma_addr_t                      per_address, per_address2;
 265         unsigned long                   event_mask[2];
 266         unsigned long                   watermark_level;
 267         u32                             shp_addr, per_addr;
 268         struct dma_chan                 chan;
 269         spinlock_t                      lock;
 270         struct dma_async_tx_descriptor  desc;
 271         enum dma_status                 status;
 272         unsigned int                    chn_count;
 273         unsigned int                    chn_real_count;
 274         struct tasklet_struct           tasklet;
 275         struct imx_dma_data             data;
 276 };
 277
 278 #define IMX_DMA_SG_LOOP         BIT(0)
 279
 280 #define MAX_DMA_CHANNELS 32
 281 #define MXC_SDMA_DEFAULT_PRIORITY 1
 282 #define MXC_SDMA_MIN_PRIORITY 1
 283 #define MXC_SDMA_MAX_PRIORITY 7
 284
 285 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 286
 287 /**
 288  * struct sdma_firmware_header - Layout of the firmware image
 289  *
 290  * @magic               "SDMA"
 291  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 292  *                      changes.
 293  * @version_minor       firmware minor version (for binary compatible changes)
 294  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 295  * @num_script_addrs    Number of script addresses in this image
 296  * @ram_code_start      offset of SDMA ram image in this firmware image
 297  * @ram_code_size       size of SDMA ram image
 298  * @script_addrs        Stores the start address of the SDMA scripts
 299  *                      (in SDMA memory space)
 300  */
 301 struct sdma_firmware_header {
 302         u32     magic;
 303         u32     version_major;
 304         u32     version_minor;
 305         u32     script_addrs_start;
 306         u32     num_script_addrs;
 307         u32     ram_code_start;
 308         u32     ram_code_size;
 309 };
 310
 311 struct sdma_driver_data {
 312         int chnenbl0;
 313         int num_events;
 314         struct sdma_script_start_addrs  *script_addrs;
 315 };
 316
 317 struct sdma_engine {
 318         struct device                   *dev;
 319         struct device_dma_parameters    dma_parms;
 320         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 321         struct sdma_channel_control     *channel_control;
 322         void __iomem                    *regs;
 323         struct sdma_context_data        *context;
 324         dma_addr_t                      context_phys;
 325         struct dma_device               dma_device;
 326         struct clk                      *clk_ipg;
 327         struct clk                      *clk_ahb;
 328         spinlock_t                      channel_0_lock;
 329         u32                             script_number;
 330         struct sdma_script_start_addrs  *script_addrs;
 331         const struct sdma_driver_data   *drvdata;
 332 };
 333
 334 static struct sdma_driver_data sdma_imx31 = {
 335         .chnenbl0 = SDMA_CHNENBL0_IMX31,
 336         .num_events = 32,
 337 };
 338
 339 static struct sdma_script_start_addrs sdma_script_imx25 = {
 340         .ap_2_ap_addr = 729,
 341         .uart_2_mcu_addr = 904,
 342         .per_2_app_addr = 1255,
 343         .mcu_2_app_addr = 834,
 344         .uartsh_2_mcu_addr = 1120,
 345         .per_2_shp_addr = 1329,
 346         .mcu_2_shp_addr = 1048,
 347         .ata_2_mcu_addr = 1560,
 348         .mcu_2_ata_addr = 1479,
 349         .app_2_per_addr = 1189,
 350         .app_2_mcu_addr = 770,
 351         .shp_2_per_addr = 1407,
 352         .shp_2_mcu_addr = 979,
 353 };
 354
 355 static struct sdma_driver_data sdma_imx25 = {
 356         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 357         .num_events = 48,
 358         .script_addrs = &sdma_script_imx25,
 359 };
 360
 361 static struct sdma_driver_data sdma_imx35 = {
 362         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 363         .num_events = 48,
 364 };
 365
 366 static struct sdma_script_start_addrs sdma_script_imx51 = {
 367         .ap_2_ap_addr = 642,
 368         .uart_2_mcu_addr = 817,
 369         .mcu_2_app_addr = 747,
 370         .mcu_2_shp_addr = 961,
 371         .ata_2_mcu_addr = 1473,
 372         .mcu_2_ata_addr = 1392,
 373         .app_2_per_addr = 1033,
 374         .app_2_mcu_addr = 683,
 375         .shp_2_per_addr = 1251,
 376         .shp_2_mcu_addr = 892,
 377 };
 378
 379 static struct sdma_driver_data sdma_imx51 = {
 380         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 381         .num_events = 48,
 382         .script_addrs = &sdma_script_imx51,
 383 };
 384
 385 static struct sdma_script_start_addrs sdma_script_imx53 = {
 386         .ap_2_ap_addr = 642,
 387         .app_2_mcu_addr = 683,
 388         .mcu_2_app_addr = 747,
 389         .uart_2_mcu_addr = 817,
 390         .shp_2_mcu_addr = 891,
 391         .mcu_2_shp_addr = 960,
 392         .uartsh_2_mcu_addr = 1032,
 393         .spdif_2_mcu_addr = 1100,
 394         .mcu_2_spdif_addr = 1134,
 395         .firi_2_mcu_addr = 1193,
 396         .mcu_2_firi_addr = 1290,
 397 };
 398
 399 static struct sdma_driver_data sdma_imx53 = {
 400         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 401         .num_events = 48,
 402         .script_addrs = &sdma_script_imx53,
 403 };
 404
 405 static struct sdma_script_start_addrs sdma_script_imx6q = {
 406         .ap_2_ap_addr = 642,
 407         .uart_2_mcu_addr = 817,
 408         .mcu_2_app_addr = 747,
 409         .per_2_per_addr = 6331,
 410         .uartsh_2_mcu_addr = 1032,
 411         .mcu_2_shp_addr = 960,
 412         .app_2_mcu_addr = 683,
 413         .shp_2_mcu_addr = 891,
 414         .spdif_2_mcu_addr = 1100,
 415         .mcu_2_spdif_addr = 1134,
 416 };
 417
 418 static struct sdma_driver_data sdma_imx6q = {
 419         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 420         .num_events = 48,
 421         .script_addrs = &sdma_script_imx6q,
 422 };
 423
 424 static struct platform_device_id sdma_devtypes[] = {
 425         {
 426                 .name = "imx25-sdma",
 427                 .driver_data = (unsigned long)&sdma_imx25,
 428         }, {
 429                 .name = "imx31-sdma",
 430                 .driver_data = (unsigned long)&sdma_imx31,
 431         }, {
 432                 .name = "imx35-sdma",
 433                 .driver_data = (unsigned long)&sdma_imx35,
 434         }, {
 435                 .name = "imx51-sdma",
 436                 .driver_data = (unsigned long)&sdma_imx51,
 437         }, {
 438                 .name = "imx53-sdma",
 439                 .driver_data = (unsigned long)&sdma_imx53,
 440         }, {
 441                 .name = "imx6q-sdma",
 442                 .driver_data = (unsigned long)&sdma_imx6q,
 443         }, {
 444                 /* sentinel */
 445         }
 446 };
 447 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 448
 449 static const struct of_device_id sdma_dt_ids[] = {
 450         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
 451         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
 452         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
 453         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
 454         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
 455         { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
 456         { /* sentinel */ }
 457 };
 458 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 459
 460 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
 461 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
 462 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
 463 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 464
 465 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 466 {
 467         u32 chnenbl0 = sdma->drvdata->chnenbl0;
 468         return chnenbl0 + event * 4;
 469 }
 470
 471 static int sdma_config_ownership(struct sdma_channel *sdmac,
 472                 bool event_override, bool mcu_override, bool dsp_override)
 473 {
 474         struct sdma_engine *sdma = sdmac->sdma;
 475         int channel = sdmac->channel;
 476         unsigned long evt, mcu, dsp;
 477
 478         if (event_override && mcu_override && dsp_override)
 479                 return -EINVAL;
 480
 481         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 482         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 483         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 484
 485         if (dsp_override)
 486                 __clear_bit(channel, &dsp);
 487         else
 488                 __set_bit(channel, &dsp);
 489
 490         if (event_override)
 491                 __clear_bit(channel, &evt);
 492         else
 493                 __set_bit(channel, &evt);
 494
 495         if (mcu_override)
 496                 __clear_bit(channel, &mcu);
 497         else
 498                 __set_bit(channel, &mcu);
 499
 500         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 501         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 502         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 503
 504         return 0;
 505 }
 506
 507 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 508 {
 509         writel(BIT(channel), sdma->regs + SDMA_H_START);
 510 }
 511
 512 /*
 513  * sdma_run_channel0 - run a channel and wait till it's done
 514  */
 515 static int sdma_run_channel0(struct sdma_engine *sdma)
 516 {
 517         int ret;
 518         unsigned long timeout = 500;
 519
 520         sdma_enable_channel(sdma, 0);
 521
 522         while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) {
 523                 if (timeout-- <= 0)
 524                         break;
 525                 udelay(1);
 526         }
 527
 528         if (ret) {
 529                 /* Clear the interrupt status */
 530                 writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
 531         } else {
 532                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 533         }
 534
 535         return ret ? 0 : -ETIMEDOUT;
 536 }
 537
 538 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 539                 u32 address)
 540 {
 541         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 542         void *buf_virt;
 543         dma_addr_t buf_phys;
 544         int ret;
 545         unsigned long flags;
 546
 547         buf_virt = dma_alloc_coherent(NULL,
 548                         size,
 549                         &buf_phys, GFP_KERNEL);
 550         if (!buf_virt) {
 551                 return -ENOMEM;
 552         }
 553
 554         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 555
 556         bd0->mode.command = C0_SETPM;
 557         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 558         bd0->mode.count = size / 2;
 559         bd0->buffer_addr = buf_phys;
 560         bd0->ext_buffer_addr = address;
 561
 562         memcpy(buf_virt, buf, size);
 563
 564         ret = sdma_run_channel0(sdma);
 565
 566         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 567
 568         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 569
 570         return ret;
 571 }
 572
 573 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 574 {
 575         struct sdma_engine *sdma = sdmac->sdma;
 576         int channel = sdmac->channel;
 577         unsigned long val;
 578         u32 chnenbl = chnenbl_ofs(sdma, event);
 579
 580         val = readl_relaxed(sdma->regs + chnenbl);
 581         __set_bit(channel, &val);
 582         writel_relaxed(val, sdma->regs + chnenbl);
 583 }
 584
 585 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 586 {
 587         struct sdma_engine *sdma = sdmac->sdma;
 588         int channel = sdmac->channel;
 589         u32 chnenbl = chnenbl_ofs(sdma, event);
 590         unsigned long val;
 591
 592         val = readl_relaxed(sdma->regs + chnenbl);
 593         __clear_bit(channel, &val);
 594         writel_relaxed(val, sdma->regs + chnenbl);
 595 }
 596
 597 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 598 {
 599         if (sdmac->desc.callback)
 600                 sdmac->desc.callback(sdmac->desc.callback_param);
 601 }
 602
 603 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
 604 {
 605         struct sdma_buffer_descriptor *bd;
 606
 607         /*
 608          * loop mode. Iterate over descriptors, re-setup them and
 609          * call callback function.
 610          */
 611         while (1) {
 612                 bd = &sdmac->bd[sdmac->buf_tail];
 613
 614                 if (bd->mode.status & BD_DONE)
 615                         break;
 616
 617                 if (bd->mode.status & BD_RROR)
 618                         sdmac->status = DMA_ERROR;
 619                 else
 620                         sdmac->status = DMA_IN_PROGRESS;
 621
 622                 bd->mode.status |= BD_DONE;
 623                 sdmac->buf_tail++;
 624                 sdmac->buf_tail %= sdmac->num_bd;
 625         }
 626 }
 627
 628 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 629 {
 630         struct sdma_buffer_descriptor *bd;
 631         int i, error = 0;
 632
 633         sdmac->chn_real_count = 0;
 634         /*
 635          * non loop mode. Iterate over all descriptors, collect
 636          * errors and call callback function
 637          */
 638         for (i = 0; i < sdmac->num_bd; i++) {
 639                 bd = &sdmac->bd[i];
 640
 641                  if (bd->mode.status & (BD_DONE | BD_RROR))
 642                         error = -EIO;
 643                  sdmac->chn_real_count += bd->mode.count;
 644         }
 645
 646         if (error)
 647                 sdmac->status = DMA_ERROR;
 648         else
 649                 sdmac->status = DMA_COMPLETE;
 650
 651         dma_cookie_complete(&sdmac->desc);
 652         if (sdmac->desc.callback)
 653                 sdmac->desc.callback(sdmac->desc.callback_param);
 654 }
 655
 656 static void sdma_tasklet(unsigned long data)
 657 {
 658         struct sdma_channel *sdmac = (struct sdma_channel *) data;
 659
 660         if (sdmac->flags & IMX_DMA_SG_LOOP)
 661                 sdma_handle_channel_loop(sdmac);
 662         else
 663                 mxc_sdma_handle_channel_normal(sdmac);
 664 }
 665
 666 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 667 {
 668         struct sdma_engine *sdma = dev_id;
 669         unsigned long stat;
 670
 671         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 672         /* not interested in channel 0 interrupts */
 673         stat &= ~1;
 674         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 675
 676         while (stat) {
 677                 int channel = fls(stat) - 1;
 678                 struct sdma_channel *sdmac = &sdma->channel[channel];
 679
 680                 if (sdmac->flags & IMX_DMA_SG_LOOP)
 681                         sdma_update_channel_loop(sdmac);
 682
 683                 tasklet_schedule(&sdmac->tasklet);
 684
 685                 __clear_bit(channel, &stat);
 686         }
 687
 688         return IRQ_HANDLED;
 689 }
 690
 691 /*
 692  * sets the pc of SDMA script according to the peripheral type
 693  */
 694 static void sdma_get_pc(struct sdma_channel *sdmac,
 695                 enum sdma_peripheral_type peripheral_type)
 696 {
 697         struct sdma_engine *sdma = sdmac->sdma;
 698         int per_2_emi = 0, emi_2_per = 0;
 699         /*
 700          * These are needed once we start to support transfers between
 701          * two peripherals or memory-to-memory transfers
 702          */
 703         int per_2_per = 0, emi_2_emi = 0;
 704
 705         sdmac->pc_from_device = 0;
 706         sdmac->pc_to_device = 0;
 707         sdmac->device_to_device = 0;
 708
 709         switch (peripheral_type) {
 710         case IMX_DMATYPE_MEMORY:
 711                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 712                 break;
 713         case IMX_DMATYPE_DSP:
 714                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 715                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 716                 break;
 717         case IMX_DMATYPE_FIRI:
 718                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 719                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 720                 break;
 721         case IMX_DMATYPE_UART:
 722                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 723                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 724                 break;
 725         case IMX_DMATYPE_UART_SP:
 726                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 727                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 728                 break;
 729         case IMX_DMATYPE_ATA:
 730                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 731                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 732                 break;
 733         case IMX_DMATYPE_CSPI:
 734         case IMX_DMATYPE_EXT:
 735         case IMX_DMATYPE_SSI:
 736                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 737                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 738                 break;
 739         case IMX_DMATYPE_SSI_DUAL:
 740                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
 741                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
 742                 break;
 743         case IMX_DMATYPE_SSI_SP:
 744         case IMX_DMATYPE_MMC:
 745         case IMX_DMATYPE_SDHC:
 746         case IMX_DMATYPE_CSPI_SP:
 747         case IMX_DMATYPE_ESAI:
 748         case IMX_DMATYPE_MSHC_SP:
 749                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 750                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 751                 break;
 752         case IMX_DMATYPE_ASRC:
 753                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 754                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 755                 per_2_per = sdma->script_addrs->per_2_per_addr;
 756                 break;
 757         case IMX_DMATYPE_ASRC_SP:
 758                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 759                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 760                 per_2_per = sdma->script_addrs->per_2_per_addr;
 761                 break;
 762         case IMX_DMATYPE_MSHC:
 763                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 764                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 765                 break;
 766         case IMX_DMATYPE_CCM:
 767                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 768                 break;
 769         case IMX_DMATYPE_SPDIF:
 770                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 771                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 772                 break;
 773         case IMX_DMATYPE_IPU_MEMORY:
 774                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 775                 break;
 776         default:
 777                 break;
 778         }
 779
 780         sdmac->pc_from_device = per_2_emi;
 781         sdmac->pc_to_device = emi_2_per;
 782         sdmac->device_to_device = per_2_per;
 783 }
 784
 785 static int sdma_load_context(struct sdma_channel *sdmac)
 786 {
 787         struct sdma_engine *sdma = sdmac->sdma;
 788         int channel = sdmac->channel;
 789         int load_address;
 790         struct sdma_context_data *context = sdma->context;
 791         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 792         int ret;
 793         unsigned long flags;
 794
 795         if (sdmac->direction == DMA_DEV_TO_MEM)
 796                 load_address = sdmac->pc_from_device;
 797         else if (sdmac->direction == DMA_DEV_TO_DEV)
 798                 load_address = sdmac->device_to_device;
 799         else
 800                 load_address = sdmac->pc_to_device;
 801
 802         if (load_address < 0)
 803                 return load_address;
 804
 805         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 806         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
 807         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 808         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 809         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
 810         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
 811
 812         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 813
 814         memset(context, 0, sizeof(*context));
 815         context->channel_state.pc = load_address;
 816
 817         /* Send by context the event mask,base address for peripheral
 818          * and watermark level
 819          */
 820         context->gReg[0] = sdmac->event_mask[1];
 821         context->gReg[1] = sdmac->event_mask[0];
 822         context->gReg[2] = sdmac->per_addr;
 823         context->gReg[6] = sdmac->shp_addr;
 824         context->gReg[7] = sdmac->watermark_level;
 825
 826         bd0->mode.command = C0_SETDM;
 827         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 828         bd0->mode.count = sizeof(*context) / 4;
 829         bd0->buffer_addr = sdma->context_phys;
 830         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 831         ret = sdma_run_channel0(sdma);
 832
 833         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 834
 835         return ret;
 836 }
 837
 838 static void sdma_disable_channel(struct sdma_channel *sdmac)
 839 {
 840         struct sdma_engine *sdma = sdmac->sdma;
 841         int channel = sdmac->channel;
 842
 843         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
 844         sdmac->status = DMA_ERROR;
 845 }
 846
 847 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
 848 {
 849         int lwml = sdmac->watermark_level & 0xff;
 850         int hwml = (sdmac->watermark_level >> 16) & 0xff;
 851
 852         if (sdmac->event_id0 > 31) {
 853                 sdmac->event_mask[0] |= 0;
 854                 __set_bit(28, &sdmac->watermark_level);
 855                 sdmac->event_mask[1] |=
 856                                 BIT(sdmac->event_id0 % 32);
 857         } else {
 858                 sdmac->event_mask[0] |= 0;
 859                 sdmac->event_mask[1] |=
 860                                 BIT(sdmac->event_id0 % 32);
 861         }
 862         if (sdmac->event_id1 > 31) {
 863                 sdmac->event_mask[1] |= 0;
 864                 __set_bit(29, &sdmac->watermark_level);
 865                 sdmac->event_mask[0] |=
 866                         BIT(sdmac->event_id1 % 32);
 867         } else {
 868                 sdmac->event_mask[1] |= 0;
 869                 sdmac->event_mask[0] |=
 870                         BIT(sdmac->event_id1 % 32);
 871         }
 872
 873         /*
 874          * If LWML(src_maxburst) > HWML(dst_maxburst), we need
 875          * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
 876          * r0(event_mask[1]) and r1(event_mask[0]).
 877          */
 878         if (lwml > hwml) {
 879                 sdmac->watermark_level &= ~0xff00ff;
 880                 sdmac->watermark_level |= hwml;
 881                 sdmac->watermark_level |= lwml << 16;
 882                 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
 883         }
 884         /* BIT 11:
 885          * 1 : Source on SPBA
 886          * 0 : Source on AIPS
 887          */
 888         __set_bit(11, &sdmac->watermark_level);
 889         /* BIT 12:
 890          * 1 : Destination on SPBA
 891          * 0 : Destination on AIPS
 892          */
 893         __set_bit(12, &sdmac->watermark_level);
 894         __set_bit(31, &sdmac->watermark_level);
 895         /* BIT 31:
 896          * 1 : Amount of samples to be transferred is
 897          * unknown and script will keep on transferring
 898          * samples as long as both events are detected
 899          * and script must be manually stopped by the
 900          * application.
 901          * 0 : The amount of samples to be is equal to
 902          * the count field of mode word
 903          *
 904          */
 905         __set_bit(25, &sdmac->watermark_level);
 906         __clear_bit(24, &sdmac->watermark_level);
 907 }
 908
 909 static int sdma_config_channel(struct sdma_channel *sdmac)
 910 {
 911         int ret;
 912
 913         sdma_disable_channel(sdmac);
 914
 915         sdmac->event_mask[0] = 0;
 916         sdmac->event_mask[1] = 0;
 917         sdmac->shp_addr = 0;
 918         sdmac->per_addr = 0;
 919
 920         if (sdmac->event_id0) {
 921                 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
 922                         return -EINVAL;
 923                 sdma_event_enable(sdmac, sdmac->event_id0);
 924         }
 925
 926         if (sdmac->event_id1) {
 927                 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
 928                         return -EINVAL;
 929                 sdma_event_enable(sdmac, sdmac->event_id1);
 930         }
 931
 932         switch (sdmac->peripheral_type) {
 933         case IMX_DMATYPE_DSP:
 934                 sdma_config_ownership(sdmac, false, true, true);
 935                 break;
 936         case IMX_DMATYPE_MEMORY:
 937                 sdma_config_ownership(sdmac, false, true, false);
 938                 break;
 939         default:
 940                 sdma_config_ownership(sdmac, true, true, false);
 941                 break;
 942         }
 943
 944         sdma_get_pc(sdmac, sdmac->peripheral_type);
 945
 946         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
 947                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
 948                 /* Handle multiple event channels differently */
 949                 if (sdmac->event_id1) {
 950                         if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
 951                             sdmac->peripheral_type == IMX_DMATYPE_ASRC)
 952                                 sdma_set_watermarklevel_for_p2p(sdmac);
 953                 } else
 954                         __set_bit(sdmac->event_id0, sdmac->event_mask);
 955
 956                 /* Watermark Level */
 957                 sdmac->watermark_level |= sdmac->watermark_level;
 958                 /* Address */
 959                 if (sdmac->direction == DMA_DEV_TO_DEV) {
 960                         sdmac->shp_addr = sdmac->per_address2;
 961                         sdmac->per_addr = sdmac->per_address;
 962                 } else {
 963                         sdmac->shp_addr = sdmac->per_address;
 964                 }
 965         } else {
 966                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
 967         }
 968
 969         ret = sdma_load_context(sdmac);
 970
 971         return ret;
 972 }
 973
 974 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
 975                 unsigned int priority)
 976 {
 977         struct sdma_engine *sdma = sdmac->sdma;
 978         int channel = sdmac->channel;
 979
 980         if (priority < MXC_SDMA_MIN_PRIORITY
 981             || priority > MXC_SDMA_MAX_PRIORITY) {
 982                 return -EINVAL;
 983         }
 984
 985         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
 986
 987         return 0;
 988 }
 989
 990 static int sdma_request_channel(struct sdma_channel *sdmac)
 991 {
 992         struct sdma_engine *sdma = sdmac->sdma;
 993         int channel = sdmac->channel;
 994         int ret = -EBUSY;
 995
 996         sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
 997         if (!sdmac->bd) {
 998                 ret = -ENOMEM;
 999                 goto out;
1000         }
1001
1002         memset(sdmac->bd, 0, PAGE_SIZE);
1003
1004         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
1005         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1006
1007         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
1008         return 0;
1009 out:
1010
1011         return ret;
1012 }
1013
1014 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
1015 {
1016         return container_of(chan, struct sdma_channel, chan);
1017 }
1018
1019 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
1020 {
1021         unsigned long flags;
1022         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
1023         dma_cookie_t cookie;
1024
1025         spin_lock_irqsave(&sdmac->lock, flags);
1026
1027         cookie = dma_cookie_assign(tx);
1028
1029         spin_unlock_irqrestore(&sdmac->lock, flags);
1030
1031         return cookie;
1032 }
1033
1034 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1035 {
1036         struct sdma_channel *sdmac = to_sdma_chan(chan);
1037         struct imx_dma_data *data = chan->private;
1038         int prio, ret;
1039
1040         if (!data)
1041                 return -EINVAL;
1042
1043         switch (data->priority) {
1044         case DMA_PRIO_HIGH:
1045                 prio = 3;
1046                 break;
1047         case DMA_PRIO_MEDIUM:
1048                 prio = 2;
1049                 break;
1050         case DMA_PRIO_LOW:
1051         default:
1052                 prio = 1;
1053                 break;
1054         }
1055
1056         sdmac->peripheral_type = data->peripheral_type;
1057         sdmac->event_id0 = data->dma_request;
1058         sdmac->event_id1 = data->dma_request2;
1059
1060         clk_enable(sdmac->sdma->clk_ipg);
1061         clk_enable(sdmac->sdma->clk_ahb);
1062
1063         ret = sdma_request_channel(sdmac);
1064         if (ret)
1065                 return ret;
1066
1067         ret = sdma_set_channel_priority(sdmac, prio);
1068         if (ret)
1069                 return ret;
1070
1071         dma_async_tx_descriptor_init(&sdmac->desc, chan);
1072         sdmac->desc.tx_submit = sdma_tx_submit;
1073         /* txd.flags will be overwritten in prep funcs */
1074         sdmac->desc.flags = DMA_CTRL_ACK;
1075
1076         return 0;
1077 }
1078
1079 static void sdma_free_chan_resources(struct dma_chan *chan)
1080 {
1081         struct sdma_channel *sdmac = to_sdma_chan(chan);
1082         struct sdma_engine *sdma = sdmac->sdma;
1083
1084         sdma_disable_channel(sdmac);
1085
1086         if (sdmac->event_id0)
1087                 sdma_event_disable(sdmac, sdmac->event_id0);
1088         if (sdmac->event_id1)
1089                 sdma_event_disable(sdmac, sdmac->event_id1);
1090
1091         sdmac->event_id0 = 0;
1092         sdmac->event_id1 = 0;
1093
1094         sdma_set_channel_priority(sdmac, 0);
1095
1096         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1097
1098         clk_disable(sdma->clk_ipg);
1099         clk_disable(sdma->clk_ahb);
1100 }
1101
1102 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1103                 struct dma_chan *chan, struct scatterlist *sgl,
1104                 unsigned int sg_len, enum dma_transfer_direction direction,
1105                 unsigned long flags, void *context)
1106 {
1107         struct sdma_channel *sdmac = to_sdma_chan(chan);
1108         struct sdma_engine *sdma = sdmac->sdma;
1109         int ret, i, count;
1110         int channel = sdmac->channel;
1111         struct scatterlist *sg;
1112
1113         if (sdmac->status == DMA_IN_PROGRESS)
1114                 return NULL;
1115         sdmac->status = DMA_IN_PROGRESS;
1116
1117         sdmac->flags = 0;
1118
1119         sdmac->buf_tail = 0;
1120
1121         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1122                         sg_len, channel);
1123
1124         sdmac->direction = direction;
1125         ret = sdma_load_context(sdmac);
1126         if (ret)
1127                 goto err_out;
1128
1129         if (sg_len > NUM_BD) {
1130                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1131                                 channel, sg_len, NUM_BD);
1132                 ret = -EINVAL;
1133                 goto err_out;
1134         }
1135
1136         sdmac->chn_count = 0;
1137         for_each_sg(sgl, sg, sg_len, i) {
1138                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1139                 int param;
1140
1141                 bd->buffer_addr = sg->dma_address;
1142
1143                 count = sg_dma_len(sg);
1144
1145                 if (count > 0xffff) {
1146                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1147                                         channel, count, 0xffff);
1148                         ret = -EINVAL;
1149                         goto err_out;
1150                 }
1151
1152                 bd->mode.count = count;
1153                 sdmac->chn_count += count;
1154
1155                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1156                         ret =  -EINVAL;
1157                         goto err_out;
1158                 }
1159
1160                 switch (sdmac->word_size) {
1161                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1162                         bd->mode.command = 0;
1163                         if (count & 3 || sg->dma_address & 3)
1164                                 return NULL;
1165                         break;
1166                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1167                         bd->mode.command = 2;
1168                         if (count & 1 || sg->dma_address & 1)
1169                                 return NULL;
1170                         break;
1171                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1172                         bd->mode.command = 1;
1173                         break;
1174                 default:
1175                         return NULL;
1176                 }
1177
1178                 param = BD_DONE | BD_EXTD | BD_CONT;
1179
1180                 if (i + 1 == sg_len) {
1181                         param |= BD_INTR;
1182                         param |= BD_LAST;
1183                         param &= ~BD_CONT;
1184                 }
1185
1186                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1187                                 i, count, (u64)sg->dma_address,
1188                                 param & BD_WRAP ? "wrap" : "",
1189                                 param & BD_INTR ? " intr" : "");
1190
1191                 bd->mode.status = param;
1192         }
1193
1194         sdmac->num_bd = sg_len;
1195         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1196
1197         return &sdmac->desc;
1198 err_out:
1199         sdmac->status = DMA_ERROR;
1200         return NULL;
1201 }
1202
1203 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1204                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1205                 size_t period_len, enum dma_transfer_direction direction,
1206                 unsigned long flags, void *context)
1207 {
1208         struct sdma_channel *sdmac = to_sdma_chan(chan);
1209         struct sdma_engine *sdma = sdmac->sdma;
1210         int num_periods = buf_len / period_len;
1211         int channel = sdmac->channel;
1212         int ret, i = 0, buf = 0;
1213
1214         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1215
1216         if (sdmac->status == DMA_IN_PROGRESS)
1217                 return NULL;
1218
1219         sdmac->status = DMA_IN_PROGRESS;
1220
1221         sdmac->buf_tail = 0;
1222         sdmac->period_len = period_len;
1223
1224         sdmac->flags |= IMX_DMA_SG_LOOP;
1225         sdmac->direction = direction;
1226         ret = sdma_load_context(sdmac);
1227         if (ret)
1228                 goto err_out;
1229
1230         if (num_periods > NUM_BD) {
1231                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1232                                 channel, num_periods, NUM_BD);
1233                 goto err_out;
1234         }
1235
1236         if (period_len > 0xffff) {
1237                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1238                                 channel, period_len, 0xffff);
1239                 goto err_out;
1240         }
1241
1242         while (buf < buf_len) {
1243                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1244                 int param;
1245
1246                 bd->buffer_addr = dma_addr;
1247
1248                 bd->mode.count = period_len;
1249
1250                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1251                         goto err_out;
1252                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1253                         bd->mode.command = 0;
1254                 else
1255                         bd->mode.command = sdmac->word_size;
1256
1257                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1258                 if (i + 1 == num_periods)
1259                         param |= BD_WRAP;
1260
1261                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1262                                 i, period_len, (u64)dma_addr,
1263                                 param & BD_WRAP ? "wrap" : "",
1264                                 param & BD_INTR ? " intr" : "");
1265
1266                 bd->mode.status = param;
1267
1268                 dma_addr += period_len;
1269                 buf += period_len;
1270
1271                 i++;
1272         }
1273
1274         sdmac->num_bd = num_periods;
1275         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1276
1277         return &sdmac->desc;
1278 err_out:
1279         sdmac->status = DMA_ERROR;
1280         return NULL;
1281 }
1282
1283 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1284                 unsigned long arg)
1285 {
1286         struct sdma_channel *sdmac = to_sdma_chan(chan);
1287         struct dma_slave_config *dmaengine_cfg = (void *)arg;
1288
1289         switch (cmd) {
1290         case DMA_TERMINATE_ALL:
1291                 sdma_disable_channel(sdmac);
1292                 return 0;
1293         case DMA_SLAVE_CONFIG:
1294                 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1295                         sdmac->per_address = dmaengine_cfg->src_addr;
1296                         sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1297                                                 dmaengine_cfg->src_addr_width;
1298                         sdmac->word_size = dmaengine_cfg->src_addr_width;
1299                 } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
1300                         sdmac->per_address = dmaengine_cfg->src_addr;
1301                         sdmac->per_address2 = dmaengine_cfg->dst_addr;
1302                         sdmac->watermark_level =
1303                                 dmaengine_cfg->src_maxburst & 0xff;
1304                         sdmac->watermark_level |=
1305                                 (dmaengine_cfg->dst_maxburst & 0xff) << 16;
1306                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1307                 } else {
1308                         sdmac->per_address = dmaengine_cfg->dst_addr;
1309                         sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1310                                                 dmaengine_cfg->dst_addr_width;
1311                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1312                 }
1313                 sdmac->direction = dmaengine_cfg->direction;
1314                 return sdma_config_channel(sdmac);
1315         default:
1316                 return -ENOSYS;
1317         }
1318
1319         return -EINVAL;
1320 }
1321
1322 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1323                                       dma_cookie_t cookie,
1324                                       struct dma_tx_state *txstate)
1325 {
1326         struct sdma_channel *sdmac = to_sdma_chan(chan);
1327         u32 residue;
1328
1329         if (sdmac->flags & IMX_DMA_SG_LOOP)
1330                 residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len;
1331         else
1332                 residue = sdmac->chn_count - sdmac->chn_real_count;
1333
1334         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1335                          residue);
1336
1337         return sdmac->status;
1338 }
1339
1340 static void sdma_issue_pending(struct dma_chan *chan)
1341 {
1342         struct sdma_channel *sdmac = to_sdma_chan(chan);
1343         struct sdma_engine *sdma = sdmac->sdma;
1344
1345         if (sdmac->status == DMA_IN_PROGRESS)
1346                 sdma_enable_channel(sdma, sdmac->channel);
1347 }
1348
1349 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1350 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1351 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 40
1352
1353 static void sdma_add_scripts(struct sdma_engine *sdma,
1354                 const struct sdma_script_start_addrs *addr)
1355 {
1356         s32 *addr_arr = (u32 *)addr;
1357         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1358         int i;
1359
1360         /* use the default firmware in ROM if missing external firmware */
1361         if (!sdma->script_number)
1362                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1363
1364         for (i = 0; i < sdma->script_number; i++)
1365                 if (addr_arr[i] > 0)
1366                         saddr_arr[i] = addr_arr[i];
1367 }
1368
1369 static void sdma_load_firmware(const struct firmware *fw, void *context)
1370 {
1371         struct sdma_engine *sdma = context;
1372         const struct sdma_firmware_header *header;
1373         const struct sdma_script_start_addrs *addr;
1374         unsigned short *ram_code;
1375
1376         if (!fw) {
1377                 dev_err(sdma->dev, "firmware not found\n");
1378                 return;
1379         }
1380
1381         if (fw->size < sizeof(*header))
1382                 goto err_firmware;
1383
1384         header = (struct sdma_firmware_header *)fw->data;
1385
1386         if (header->magic != SDMA_FIRMWARE_MAGIC)
1387                 goto err_firmware;
1388         if (header->ram_code_start + header->ram_code_size > fw->size)
1389                 goto err_firmware;
1390         switch (header->version_major) {
1391                 case 1:
1392                         sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1393                         break;
1394                 case 2:
1395                         sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1396                         break;
1397                 case 3:
1398                         sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1399                         break;
1400                 default:
1401                         dev_err(sdma->dev, "unknown firmware version\n");
1402                         goto err_firmware;
1403         }
1404
1405         addr = (void *)header + header->script_addrs_start;
1406         ram_code = (void *)header + header->ram_code_start;
1407
1408         clk_enable(sdma->clk_ipg);
1409         clk_enable(sdma->clk_ahb);
1410         /* download the RAM image for SDMA */
1411         sdma_load_script(sdma, ram_code,
1412                         header->ram_code_size,
1413                         addr->ram_code_start_addr);
1414         clk_disable(sdma->clk_ipg);
1415         clk_disable(sdma->clk_ahb);
1416
1417         sdma_add_scripts(sdma, addr);
1418
1419         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1420                         header->version_major,
1421                         header->version_minor);
1422
1423 err_firmware:
1424         release_firmware(fw);
1425 }
1426
1427 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1428                 const char *fw_name)
1429 {
1430         int ret;
1431
1432         ret = request_firmware_nowait(THIS_MODULE,
1433                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1434                         GFP_KERNEL, sdma, sdma_load_firmware);
1435
1436         return ret;
1437 }
1438
1439 static int __init sdma_init(struct sdma_engine *sdma)
1440 {
1441         int i, ret;
1442         dma_addr_t ccb_phys;
1443
1444         clk_enable(sdma->clk_ipg);
1445         clk_enable(sdma->clk_ahb);
1446
1447         /* Be sure SDMA has not started yet */
1448         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1449
1450         sdma->channel_control = dma_alloc_coherent(NULL,
1451                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1452                         sizeof(struct sdma_context_data),
1453                         &ccb_phys, GFP_KERNEL);
1454
1455         if (!sdma->channel_control) {
1456                 ret = -ENOMEM;
1457                 goto err_dma_alloc;
1458         }
1459
1460         sdma->context = (void *)sdma->channel_control +
1461                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1462         sdma->context_phys = ccb_phys +
1463                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1464
1465         /* Zero-out the CCB structures array just allocated */
1466         memset(sdma->channel_control, 0,
1467                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1468
1469         /* disable all channels */
1470         for (i = 0; i < sdma->drvdata->num_events; i++)
1471                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1472
1473         /* All channels have priority 0 */
1474         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1475                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1476
1477         ret = sdma_request_channel(&sdma->channel[0]);
1478         if (ret)
1479                 goto err_dma_alloc;
1480
1481         sdma_config_ownership(&sdma->channel[0], false, true, false);
1482
1483         /* Set Command Channel (Channel Zero) */
1484         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1485
1486         /* Set bits of CONFIG register but with static context switching */
1487         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1488         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1489
1490         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1491
1492         /* Set bits of CONFIG register with given context switching mode */
1493         writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1494
1495         /* Initializes channel's priorities */
1496         sdma_set_channel_priority(&sdma->channel[0], 7);
1497
1498         clk_disable(sdma->clk_ipg);
1499         clk_disable(sdma->clk_ahb);
1500
1501         return 0;
1502
1503 err_dma_alloc:
1504         clk_disable(sdma->clk_ipg);
1505         clk_disable(sdma->clk_ahb);
1506         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1507         return ret;
1508 }
1509
1510 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1511 {
1512         struct sdma_channel *sdmac = to_sdma_chan(chan);
1513         struct imx_dma_data *data = fn_param;
1514
1515         if (!imx_dma_is_general_purpose(chan))
1516                 return false;
1517
1518         sdmac->data = *data;
1519         chan->private = &sdmac->data;
1520
1521         return true;
1522 }
1523
1524 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1525                                    struct of_dma *ofdma)
1526 {
1527         struct sdma_engine *sdma = ofdma->of_dma_data;
1528         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1529         struct imx_dma_data data;
1530
1531         if (dma_spec->args_count != 3)
1532                 return NULL;
1533
1534         data.dma_request = dma_spec->args[0];
1535         data.peripheral_type = dma_spec->args[1];
1536         data.priority = dma_spec->args[2];
1537
1538         /*
1539          * init dma_request2 to zero, which is not used by the dts.
1540          * For P2P, dma_request2 is init from dma_request_channel(),
1541          * chan->private will point to the imx_dma_data, and in
1542          * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1543          * be set to sdmac->event_id1.
1544          */
1545         data.dma_request2 = 0;
1546
1547         return dma_request_channel(mask, sdma_filter_fn, &data);
1548 }
1549
1550 static int __init sdma_probe(struct platform_device *pdev)
1551 {
1552         const struct of_device_id *of_id =
1553                         of_match_device(sdma_dt_ids, &pdev->dev);
1554         struct device_node *np = pdev->dev.of_node;
1555         const char *fw_name;
1556         int ret;
1557         int irq;
1558         struct resource *iores;
1559         struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1560         int i;
1561         struct sdma_engine *sdma;
1562         s32 *saddr_arr;
1563         const struct sdma_driver_data *drvdata = NULL;
1564
1565         if (of_id)
1566                 drvdata = of_id->data;
1567         else if (pdev->id_entry)
1568                 drvdata = (void *)pdev->id_entry->driver_data;
1569
1570         if (!drvdata) {
1571                 dev_err(&pdev->dev, "unable to find driver data\n");
1572                 return -EINVAL;
1573         }
1574
1575         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1576         if (ret)
1577                 return ret;
1578
1579         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1580         if (!sdma)
1581                 return -ENOMEM;
1582
1583         spin_lock_init(&sdma->channel_0_lock);
1584
1585         sdma->dev = &pdev->dev;
1586         sdma->drvdata = drvdata;
1587
1588         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1589         irq = platform_get_irq(pdev, 0);
1590         if (!iores || irq < 0) {
1591                 ret = -EINVAL;
1592                 goto err_irq;
1593         }
1594
1595         if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1596                 ret = -EBUSY;
1597                 goto err_request_region;
1598         }
1599
1600         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1601         if (IS_ERR(sdma->clk_ipg)) {
1602                 ret = PTR_ERR(sdma->clk_ipg);
1603                 goto err_clk;
1604         }
1605
1606         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1607         if (IS_ERR(sdma->clk_ahb)) {
1608                 ret = PTR_ERR(sdma->clk_ahb);
1609                 goto err_clk;
1610         }
1611
1612         clk_prepare(sdma->clk_ipg);
1613         clk_prepare(sdma->clk_ahb);
1614
1615         sdma->regs = ioremap(iores->start, resource_size(iores));
1616         if (!sdma->regs) {
1617                 ret = -ENOMEM;
1618                 goto err_ioremap;
1619         }
1620
1621         ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1622         if (ret)
1623                 goto err_request_irq;
1624
1625         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1626         if (!sdma->script_addrs) {
1627                 ret = -ENOMEM;
1628                 goto err_alloc;
1629         }
1630
1631         /* initially no scripts available */
1632         saddr_arr = (s32 *)sdma->script_addrs;
1633         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1634                 saddr_arr[i] = -EINVAL;
1635
1636         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1637         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1638
1639         INIT_LIST_HEAD(&sdma->dma_device.channels);
1640         /* Initialize channel parameters */
1641         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1642                 struct sdma_channel *sdmac = &sdma->channel[i];
1643
1644                 sdmac->sdma = sdma;
1645                 spin_lock_init(&sdmac->lock);
1646
1647                 sdmac->chan.device = &sdma->dma_device;
1648                 dma_cookie_init(&sdmac->chan);
1649                 sdmac->channel = i;
1650
1651                 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1652                              (unsigned long) sdmac);
1653                 /*
1654                  * Add the channel to the DMAC list. Do not add channel 0 though
1655                  * because we need it internally in the SDMA driver. This also means
1656                  * that channel 0 in dmaengine counting matches sdma channel 1.
1657                  */
1658                 if (i)
1659                         list_add_tail(&sdmac->chan.device_node,
1660                                         &sdma->dma_device.channels);
1661         }
1662
1663         ret = sdma_init(sdma);
1664         if (ret)
1665                 goto err_init;
1666
1667         if (sdma->drvdata->script_addrs)
1668                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1669         if (pdata && pdata->script_addrs)
1670                 sdma_add_scripts(sdma, pdata->script_addrs);
1671
1672         if (pdata) {
1673                 ret = sdma_get_firmware(sdma, pdata->fw_name);
1674                 if (ret)
1675                         dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1676         } else {
1677                 /*
1678                  * Because that device tree does not encode ROM script address,
1679                  * the RAM script in firmware is mandatory for device tree
1680                  * probe, otherwise it fails.
1681                  */
1682                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1683                                               &fw_name);
1684                 if (ret)
1685                         dev_warn(&pdev->dev, "failed to get firmware name\n");
1686                 else {
1687                         ret = sdma_get_firmware(sdma, fw_name);
1688                         if (ret)
1689                                 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1690                 }
1691         }
1692
1693         sdma->dma_device.dev = &pdev->dev;
1694
1695         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1696         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1697         sdma->dma_device.device_tx_status = sdma_tx_status;
1698         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1699         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1700         sdma->dma_device.device_control = sdma_control;
1701         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1702         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1703         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1704
1705         ret = dma_async_device_register(&sdma->dma_device);
1706         if (ret) {
1707                 dev_err(&pdev->dev, "unable to register\n");
1708                 goto err_init;
1709         }
1710
1711         if (np) {
1712                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1713                 if (ret) {
1714                         dev_err(&pdev->dev, "failed to register controller\n");
1715                         goto err_register;
1716                 }
1717         }
1718
1719         dev_info(sdma->dev, "initialized\n");
1720
1721         return 0;
1722
1723 err_register:
1724         dma_async_device_unregister(&sdma->dma_device);
1725 err_init:
1726         kfree(sdma->script_addrs);
1727 err_alloc:
1728         free_irq(irq, sdma);
1729 err_request_irq:
1730         iounmap(sdma->regs);
1731 err_ioremap:
1732 err_clk:
1733         release_mem_region(iores->start, resource_size(iores));
1734 err_request_region:
1735 err_irq:
1736         kfree(sdma);
1737         return ret;
1738 }
1739
1740 static int sdma_remove(struct platform_device *pdev)
1741 {
1742         return -EBUSY;
1743 }
1744
1745 static struct platform_driver sdma_driver = {
1746         .driver         = {
1747                 .name   = "imx-sdma",
1748                 .of_match_table = sdma_dt_ids,
1749         },
1750         .id_table       = sdma_devtypes,
1751         .remove         = sdma_remove,
1752 };
1753
1754 static int __init sdma_module_init(void)
1755 {
1756         return platform_driver_probe(&sdma_driver, sdma_probe);
1757 }
1758 module_init(sdma_module_init);
1759
1760 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1761 MODULE_DESCRIPTION("i.MX SDMA driver");
1762 MODULE_LICENSE("GPL");