drivers/dma/imx-sdma.c

   1 /*
   2  * drivers/dma/imx-sdma.c
   3  *
   4  * This file contains a driver for the Freescale Smart DMA engine
   5  *
   6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  *
   8  * Based on code from Freescale:
   9  *
  10  * Copyright 2004-2013 Freescale Semiconductor, Inc.
  11  *
  12  * The code contained herein is licensed under the GNU General Public
  13  * License. You may obtain a copy of the GNU General Public License
  14  * Version 2 or later at the following locations:
  15  *
  16  * http://www.opensource.org/licenses/gpl-license.html
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/types.h>
  22 #include <linux/mm.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/clk.h>
  25 #include <linux/wait.h>
  26 #include <linux/sched.h>
  27 #include <linux/semaphore.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/device.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/firmware.h>
  32 #include <linux/slab.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/dmaengine.h>
  35 #include <linux/delay.h>
  36 #include <linux/genalloc.h>
  37
  38 #include <asm/irq.h>
  39 #include <mach/sdma.h>
  40 #include <mach/dma.h>
  41 #include <mach/hardware.h>
  42 #include <mach/iram.h>
  43
  44
  45 /* SDMA registers */
  46 #define SDMA_H_C0PTR            0x000
  47 #define SDMA_H_INTR             0x004
  48 #define SDMA_H_STATSTOP         0x008
  49 #define SDMA_H_START            0x00c
  50 #define SDMA_H_EVTOVR           0x010
  51 #define SDMA_H_DSPOVR           0x014
  52 #define SDMA_H_HOSTOVR          0x018
  53 #define SDMA_H_EVTPEND          0x01c
  54 #define SDMA_H_DSPENBL          0x020
  55 #define SDMA_H_RESET            0x024
  56 #define SDMA_H_EVTERR           0x028
  57 #define SDMA_H_INTRMSK          0x02c
  58 #define SDMA_H_PSW              0x030
  59 #define SDMA_H_EVTERRDBG        0x034
  60 #define SDMA_H_CONFIG           0x038
  61 #define SDMA_ONCE_ENB           0x040
  62 #define SDMA_ONCE_DATA          0x044
  63 #define SDMA_ONCE_INSTR         0x048
  64 #define SDMA_ONCE_STAT          0x04c
  65 #define SDMA_ONCE_CMD           0x050
  66 #define SDMA_EVT_MIRROR         0x054
  67 #define SDMA_ILLINSTADDR        0x058
  68 #define SDMA_CHN0ADDR           0x05c
  69 #define SDMA_ONCE_RTB           0x060
  70 #define SDMA_XTRIG_CONF1        0x070
  71 #define SDMA_XTRIG_CONF2        0x074
  72 #define SDMA_CHNENBL0_V2        0x200
  73 #define SDMA_CHNENBL0_V1        0x080
  74 #define SDMA_CHNPRI_0           0x100
  75
  76 /*
  77  * Buffer descriptor status values.
  78  */
  79 #define BD_DONE  0x01
  80 #define BD_WRAP  0x02
  81 #define BD_CONT  0x04
  82 #define BD_INTR  0x08
  83 #define BD_RROR  0x10
  84 #define BD_LAST  0x20
  85 #define BD_EXTD  0x80
  86
  87 /*
  88  * Data Node descriptor status values.
  89  */
  90 #define DND_END_OF_FRAME  0x80
  91 #define DND_END_OF_XFER   0x40
  92 #define DND_DONE          0x20
  93 #define DND_UNUSED        0x01
  94
  95 /*
  96  * IPCV2 descriptor status values.
  97  */
  98 #define BD_IPCV2_END_OF_FRAME  0x40
  99
 100 #define IPCV2_MAX_NODES        50
 101 /*
 102  * Error bit set in the CCB status field by the SDMA,
 103  * in setbd routine, in case of a transfer error
 104  */
 105 #define DATA_ERROR  0x10000000
 106
 107 /*
 108  * Buffer descriptor commands.
 109  */
 110 #define C0_ADDR             0x01
 111 #define C0_LOAD             0x02
 112 #define C0_DUMP             0x03
 113 #define C0_SETCTX           0x07
 114 #define C0_GETCTX           0x03
 115 #define C0_SETDM            0x01
 116 #define C0_SETPM            0x04
 117 #define C0_GETDM            0x02
 118 #define C0_GETPM            0x08
 119 /*
 120  * Change endianness indicator in the BD command field
 121  */
 122 #define CHANGE_ENDIANNESS   0x80
 123
 124 /*
 125  * Mode/Count of data node descriptors - IPCv2
 126  */
 127 struct sdma_mode_count {
 128         u32 count   : 16; /* size of the buffer pointed by this BD */
 129         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 130         u32 command :  8; /* command mostlky used for channel 0 */
 131 };
 132
 133 /*
 134  * Buffer descriptor
 135  */
 136 struct sdma_buffer_descriptor {
 137         struct sdma_mode_count  mode;
 138         u32 buffer_addr;        /* address of the buffer described */
 139         u32 ext_buffer_addr;    /* extended buffer address */
 140 } __attribute__ ((packed));
 141
 142 /**
 143  * struct sdma_channel_control - Channel control Block
 144  *
 145  * @current_bd_ptr      current buffer descriptor processed
 146  * @base_bd_ptr         first element of buffer descriptor array
 147  * @unused              padding. The SDMA engine expects an array of 128 byte
 148  *                      control blocks
 149  */
 150 struct sdma_channel_control {
 151         u32 current_bd_ptr;
 152         u32 base_bd_ptr;
 153         u32 unused[2];
 154 } __attribute__ ((packed));
 155
 156 /**
 157  * struct sdma_state_registers - SDMA context for a channel
 158  *
 159  * @pc:         program counter
 160  * @t:          test bit: status of arithmetic & test instruction
 161  * @rpc:        return program counter
 162  * @sf:         source fault while loading data
 163  * @spc:        loop start program counter
 164  * @df:         destination fault while storing data
 165  * @epc:        loop end program counter
 166  * @lm:         loop mode
 167  */
 168 struct sdma_state_registers {
 169         u32 pc     :14;
 170         u32 unused1: 1;
 171         u32 t      : 1;
 172         u32 rpc    :14;
 173         u32 unused0: 1;
 174         u32 sf     : 1;
 175         u32 spc    :14;
 176         u32 unused2: 1;
 177         u32 df     : 1;
 178         u32 epc    :14;
 179         u32 lm     : 2;
 180 } __attribute__ ((packed));
 181
 182 /**
 183  * struct sdma_context_data - sdma context specific to a channel
 184  *
 185  * @channel_state:      channel state bits
 186  * @gReg:               general registers
 187  * @mda:                burst dma destination address register
 188  * @msa:                burst dma source address register
 189  * @ms:                 burst dma status register
 190  * @md:                 burst dma data register
 191  * @pda:                peripheral dma destination address register
 192  * @psa:                peripheral dma source address register
 193  * @ps:                 peripheral dma status register
 194  * @pd:                 peripheral dma data register
 195  * @ca:                 CRC polynomial register
 196  * @cs:                 CRC accumulator register
 197  * @dda:                dedicated core destination address register
 198  * @dsa:                dedicated core source address register
 199  * @ds:                 dedicated core status register
 200  * @dd:                 dedicated core data register
 201  */
 202 struct sdma_context_data {
 203         struct sdma_state_registers  channel_state;
 204         u32  gReg[8];
 205         u32  mda;
 206         u32  msa;
 207         u32  ms;
 208         u32  md;
 209         u32  pda;
 210         u32  psa;
 211         u32  ps;
 212         u32  pd;
 213         u32  ca;
 214         u32  cs;
 215         u32  dda;
 216         u32  dsa;
 217         u32  ds;
 218         u32  dd;
 219         u32  scratch0;
 220         u32  scratch1;
 221         u32  scratch2;
 222         u32  scratch3;
 223         u32  scratch4;
 224         u32  scratch5;
 225         u32  scratch6;
 226         u32  scratch7;
 227 } __attribute__ ((packed));
 228
 229 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 230
 231 struct sdma_engine;
 232
 233 enum sdma_mode {
 234         SDMA_MODE_INVALID = 0,
 235         SDMA_MODE_LOOP,
 236         SDMA_MODE_NORMAL,
 237         SDMA_MODE_P2P,
 238         SDMA_MODE_NO_BD,
 239 };
 240
 241 /**
 242  * struct sdma_channel - housekeeping for a SDMA channel
 243  *
 244  * @sdma                pointer to the SDMA engine for this channel
 245  * @channel             the channel number, matches dmaengine chan_id + 1
 246  * @direction           transfer type. Needed for setting SDMA script
 247  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 248  * @event_id0           aka dma request line
 249  * @event_id1           for channels that use 2 events
 250  * @word_size           peripheral access size
 251  * @buf_tail            ID of the buffer that was processed
 252  * @done                channel completion
 253  * @num_bd              max NUM_BD. number of descriptors currently handling
 254  */
 255 struct sdma_channel {
 256         struct sdma_engine              *sdma;
 257         unsigned int                    channel;
 258         enum dma_transfer_direction             direction;
 259         enum sdma_peripheral_type       peripheral_type;
 260         unsigned int                    event_id0;
 261         unsigned int                    event_id1;
 262         enum dma_slave_buswidth         word_size;
 263         unsigned int                    buf_tail;
 264         struct completion               done;
 265         unsigned int                    num_bd;
 266         struct sdma_buffer_descriptor   *bd;
 267         dma_addr_t                      bd_phys;
 268         unsigned int                    pc_from_device;
 269         unsigned int                    pc_to_device;
 270         unsigned int                    device_to_device;
 271         unsigned int                    other_script;
 272         unsigned int                    pc_to_pc;
 273         enum sdma_mode                  mode;
 274         dma_addr_t                      per_address, per_address2;
 275         u32                             event_mask0, event_mask1;
 276         u32                             watermark_level;
 277         u32                             shp_addr, per_addr;
 278         u32                             data_addr1, data_addr2;
 279         struct dma_chan                 chan;
 280         spinlock_t                      lock;
 281         struct dma_async_tx_descriptor  desc;
 282         dma_cookie_t                    last_completed;
 283         enum dma_status                 status;
 284         unsigned int                    chn_count;
 285         unsigned int                    chn_real_count;
 286         unsigned int                    irq_handling;
 287 };
 288
 289 #define MAX_DMA_CHANNELS 32
 290 #define MXC_SDMA_DEFAULT_PRIORITY 1
 291 #define MXC_SDMA_MIN_PRIORITY 1
 292 #define MXC_SDMA_MAX_PRIORITY 7
 293
 294 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 295
 296 /**
 297  * struct sdma_firmware_header - Layout of the firmware image
 298  *
 299  * @magic               "SDMA"
 300  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 301  *                      changes.
 302  * @version_minor       firmware minor version (for binary compatible changes)
 303  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 304  * @num_script_addrs    Number of script addresses in this image
 305  * @ram_code_start      offset of SDMA ram image in this firmware image
 306  * @ram_code_size       size of SDMA ram image
 307  * @script_addrs        Stores the start address of the SDMA scripts
 308  *                      (in SDMA memory space)
 309  */
 310 struct sdma_firmware_header {
 311         u32     magic;
 312         u32     version_major;
 313         u32     version_minor;
 314         u32     script_addrs_start;
 315         u32     num_script_addrs;
 316         u32     ram_code_start;
 317         u32     ram_code_size;
 318 };
 319
 320 struct sdma_engine {
 321         struct device                   *dev;
 322         struct device_dma_parameters    dma_parms;
 323         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 324         struct sdma_channel_control     *channel_control;
 325         void __iomem                    *regs;
 326         unsigned int                    version;
 327         unsigned int                    num_events;
 328         struct sdma_context_data        *context;
 329         dma_addr_t                      context_phys;
 330         struct dma_device               dma_device;
 331         struct clk                      *clk;
 332         struct sdma_script_start_addrs  *script_addrs;
 333         spinlock_t                      irq_reg_lock;
 334         spinlock_t                      channel_0_lock;
 335 };
 336
 337 #define SDMA_H_CONFIG_DSPDMA    (1 << 12) /* indicates if the DSPDMA is used */
 338 #define SDMA_H_CONFIG_RTD_PINS  (1 << 11) /* indicates if Real-Time Debug pins are enabled */
 339 #define SDMA_H_CONFIG_ACR       (1 << 4)  /* indicates if AHB freq /core freq = 2 or 1 */
 340 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 341
 342 #ifdef CONFIG_SDMA_IRAM
 343 static unsigned long sdma_iram_paddr;
 344 static void *sdma_iram_vaddr;
 345 #define sdma_iram_phys_to_virt(p) (sdma_iram_vaddr + ((p) - sdma_iram_paddr))
 346 #define sdma_iram_virt_to_phys(v) (sdma_iram_paddr + ((v) - sdma_iram_vaddr))
 347 static struct gen_pool *sdma_iram_pool;
 348
 349 /*!
 350  * Allocates uncacheable buffer from IRAM
 351  */
 352 void __iomem *sdma_iram_malloc(size_t size, unsigned long *buf)
 353 {
 354         *buf = gen_pool_alloc(sdma_iram_pool, size);
 355         if (!buf)
 356                 return NULL;
 357
 358         return sdma_iram_phys_to_virt(*buf);
 359 }
 360
 361 void sdma_iram_free(unsigned long buf, size_t size)
 362 {
 363         if (!sdma_iram_pool)
 364                 return;
 365
 366         gen_pool_free(sdma_iram_pool, buf, size);
 367 }
 368 #endif                          /*CONFIG_SDMA_IRAM */
 369
 370
 371 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 372 {
 373         u32 chnenbl0 = (sdma->version == 2 ? SDMA_CHNENBL0_V2 : SDMA_CHNENBL0_V1);
 374
 375         return chnenbl0 + event * 4;
 376 }
 377
 378 static int sdma_config_ownership(struct sdma_channel *sdmac,
 379                 bool event_override, bool mcu_override, bool dsp_override)
 380 {
 381         struct sdma_engine *sdma = sdmac->sdma;
 382         int channel = sdmac->channel;
 383         u32 evt, mcu, dsp;
 384
 385         if (event_override && mcu_override && dsp_override)
 386                 return -EINVAL;
 387
 388         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 389         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 390         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 391
 392         if (dsp_override)
 393                 dsp &= ~(1 << channel);
 394         else
 395                 dsp |= (1 << channel);
 396
 397         if (event_override)
 398                 evt &= ~(1 << channel);
 399         else
 400                 evt |= (1 << channel);
 401
 402         if (mcu_override)
 403                 mcu &= ~(1 << channel);
 404         else
 405                 mcu |= (1 << channel);
 406
 407         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 408         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 409         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 410
 411         return 0;
 412 }
 413
 414 /*
 415  * sdma_run_channel - run a channel and wait till it's done
 416  */
 417 static int sdma_run_channel(struct sdma_channel *sdmac)
 418 {
 419         struct sdma_engine *sdma = sdmac->sdma;
 420         int channel = sdmac->channel;
 421         unsigned long timeout = 1000;
 422         int ret;
 423
 424         writel(1 << channel, sdma->regs + SDMA_H_START);
 425
 426         while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) {
 427                 if (timeout-- <= 0)
 428                         break;
 429                 udelay(1);
 430         }
 431
 432         if (ret) {
 433                 /* Clear the interrupt status */
 434                 writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
 435         } else {
 436                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 437         }
 438
 439         return ret ? 0 : -ETIMEDOUT;
 440 }
 441
 442 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 443                 u32 address)
 444 {
 445         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 446         void *buf_virt;
 447         dma_addr_t buf_phys;
 448         unsigned long flags;
 449         int ret;
 450
 451 #ifdef CONFIG_SDMA_IRAM
 452         buf_virt = sdma_iram_malloc(size, (unsigned long *)&buf_phys);
 453 #else
 454         buf_virt = dma_alloc_coherent(NULL,
 455                         size,
 456                         &buf_phys, GFP_KERNEL);
 457 #endif
 458         if (!buf_virt)
 459                 return -ENOMEM;
 460
 461         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 462
 463         bd0->mode.command = C0_SETPM;
 464         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 465         bd0->mode.count = size / 2;
 466         bd0->buffer_addr = buf_phys;
 467         bd0->ext_buffer_addr = address;
 468
 469         memcpy(buf_virt, buf, size);
 470
 471         ret = sdma_run_channel(&sdma->channel[0]);
 472
 473         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 474 #ifdef CONFIG_SDMA_IRAM
 475         sdma_iram_free(buf_phys, size);
 476 #else
 477         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 478 #endif
 479
 480         return ret;
 481 }
 482
 483 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 484 {
 485         struct sdma_engine *sdma = sdmac->sdma;
 486         int channel = sdmac->channel;
 487         u32 val;
 488         u32 chnenbl = chnenbl_ofs(sdma, event);
 489
 490         val = readl_relaxed(sdma->regs + chnenbl);
 491         val |= (1 << channel);
 492         writel_relaxed(val, sdma->regs + chnenbl);
 493 }
 494
 495 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 496 {
 497         struct sdma_engine *sdma = sdmac->sdma;
 498         int channel = sdmac->channel;
 499         u32 chnenbl = chnenbl_ofs(sdma, event);
 500         u32 val;
 501
 502         val = readl_relaxed(sdma->regs + chnenbl);
 503         val &= ~(1 << channel);
 504         writel_relaxed(val, sdma->regs + chnenbl);
 505 }
 506
 507 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 508 {
 509         struct sdma_buffer_descriptor *bd;
 510         /*
 511          * loop mode. Iterate over descriptors, re-setup them and
 512          * call callback function.
 513          */
 514         while (1) {
 515                 bd = &sdmac->bd[sdmac->buf_tail];
 516
 517                 if (bd->mode.status & BD_DONE)
 518                         break;
 519
 520                 if (bd->mode.status & BD_RROR)
 521                         sdmac->status = DMA_ERROR;
 522                 else
 523                         sdmac->status = DMA_IN_PROGRESS;
 524
 525                 bd->mode.status |= BD_DONE;
 526                 sdmac->buf_tail++;
 527                 sdmac->buf_tail %= sdmac->num_bd;
 528
 529                 if (sdmac->desc.callback)
 530                         sdmac->desc.callback(sdmac->desc.callback_param);
 531         }
 532 }
 533
 534 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 535 {
 536         struct sdma_buffer_descriptor *bd;
 537         int i, error = 0;
 538
 539         sdmac->chn_real_count = 0;
 540         /*
 541          * non loop mode. Iterate over all descriptors, collect
 542          * errors and call callback function
 543          */
 544         for (i = 0; i < sdmac->num_bd; i++) {
 545                 bd = &sdmac->bd[i];
 546
 547                  if (bd->mode.status & (BD_DONE | BD_RROR))
 548                         error = -EIO;
 549                  sdmac->chn_real_count += bd->mode.count;
 550         }
 551
 552         if (error)
 553                 sdmac->status = DMA_ERROR;
 554         else
 555                 sdmac->status = DMA_SUCCESS;
 556
 557         sdmac->last_completed = sdmac->desc.cookie;
 558         if (sdmac->desc.callback)
 559                 sdmac->desc.callback(sdmac->desc.callback_param);
 560 }
 561
 562
 563 static void sdma_handle_other_intr(struct sdma_channel *sdmac)
 564 {
 565         sdmac->last_completed = sdmac->desc.cookie;
 566
 567         if (sdmac->desc.callback)
 568                 sdmac->desc.callback(sdmac->desc.callback_param);
 569 }
 570
 571 static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
 572 {
 573         complete(&sdmac->done);
 574
 575         switch (sdmac->mode) {
 576         case SDMA_MODE_LOOP:
 577                 sdma_handle_channel_loop(sdmac);
 578                 break;
 579         case SDMA_MODE_NORMAL:
 580                 mxc_sdma_handle_channel_normal(sdmac);
 581                 break;
 582         case SDMA_MODE_NO_BD:
 583                 sdma_handle_other_intr(sdmac);
 584                 break;
 585         default:
 586                 pr_err("Unvalid SDMA MODE!\n");
 587                 break;
 588         }
 589 }
 590
 591 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 592 {
 593         struct sdma_engine *sdma = dev_id;
 594         struct sdma_channel *sdmac;
 595         unsigned long flag;
 596         int channel;
 597         u32 stat, stat_bak;
 598
 599         spin_lock_irqsave(&sdma->irq_reg_lock, flag);
 600         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 601         /* not interested in channel 0 interrupts */
 602         stat &= ~1;
 603         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 604         spin_unlock_irqrestore(&sdma->irq_reg_lock, flag);
 605
 606         stat_bak = stat;
 607         while (stat_bak) {
 608                 channel = fls(stat_bak) - 1;
 609                 sdmac = &sdma->channel[channel];
 610                 sdmac->irq_handling = 1;
 611                 stat_bak &= ~(1 << channel);
 612         }
 613
 614         while (stat) {
 615                 channel = fls(stat) - 1;
 616                 sdmac = &sdma->channel[channel];
 617
 618                 if (sdmac->irq_handling)
 619                         mxc_sdma_handle_channel(sdmac);
 620
 621                 stat &= ~(1 << channel);
 622                 sdmac->irq_handling = 0;
 623         }
 624
 625         return IRQ_HANDLED;
 626 }
 627
 628 /*
 629  * sets the pc of SDMA script according to the peripheral type
 630  */
 631 static void sdma_get_pc(struct sdma_channel *sdmac,
 632                 enum sdma_peripheral_type peripheral_type)
 633 {
 634         struct sdma_engine *sdma = sdmac->sdma;
 635         int per_2_emi = 0, emi_2_per = 0;
 636         /*
 637          * These are needed once we start to support transfers between
 638          * two peripherals or memory-to-memory transfers
 639          */
 640         int per_2_per = 0, emi_2_emi = 0;
 641         int other = 0;
 642
 643         sdmac->pc_from_device = 0;
 644         sdmac->pc_to_device = 0;
 645         sdmac->device_to_device = 0;
 646         sdmac->other_script = 0;
 647         sdmac->pc_to_pc = 0;
 648
 649         switch (peripheral_type) {
 650         case IMX_DMATYPE_MEMORY:
 651                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 652                 break;
 653         case IMX_DMATYPE_DSP:
 654                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 655                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 656                 break;
 657         case IMX_DMATYPE_FIRI:
 658                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 659                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 660                 break;
 661         case IMX_DMATYPE_UART:
 662                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 663                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 664                 break;
 665         case IMX_DMATYPE_UART_SP:
 666                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 667                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 668                 break;
 669         case IMX_DMATYPE_ATA:
 670                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 671                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 672                 break;
 673         case IMX_DMATYPE_CSPI:
 674         case IMX_DMATYPE_EXT:
 675         case IMX_DMATYPE_SSI:
 676                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 677                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 678                 break;
 679         case IMX_DMATYPE_SSI_SP:
 680                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
 681                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
 682                 break;
 683         case IMX_DMATYPE_MMC:
 684         case IMX_DMATYPE_SDHC:
 685         case IMX_DMATYPE_CSPI_SP:
 686         case IMX_DMATYPE_ESAI:
 687         case IMX_DMATYPE_MSHC_SP:
 688                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 689                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 690                 break;
 691         case IMX_DMATYPE_ASRC:
 692                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 693                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 694                 per_2_per = sdma->script_addrs->per_2_per_addr;
 695                 break;
 696         case IMX_DMATYPE_MSHC:
 697                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 698                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 699                 break;
 700         case IMX_DMATYPE_CCM:
 701                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 702                 break;
 703         case IMX_DMATYPE_SPDIF:
 704                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 705                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 706                 break;
 707         case IMX_DMATYPE_IPU_MEMORY:
 708                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 709                 break;
 710         case IMX_DMATYPE_HDMI:
 711                 other = sdma->script_addrs->hdmi_dma_addr;
 712         default:
 713                 break;
 714         }
 715
 716         sdmac->pc_from_device = per_2_emi;
 717         sdmac->pc_to_device = emi_2_per;
 718         sdmac->device_to_device = per_2_per;
 719         sdmac->other_script = other;
 720         sdmac->pc_to_pc = emi_2_emi;
 721 }
 722
 723 static int sdma_set_context_reg(struct sdma_channel *sdmac,
 724                                 struct sdma_context_data *context)
 725 {
 726         switch (sdmac->peripheral_type) {
 727         case IMX_DMATYPE_HDMI:
 728                 context->gReg[4] = sdmac->data_addr1;
 729                 context->gReg[6] = sdmac->data_addr2;
 730                 break;
 731         default:
 732                 context->gReg[0] = sdmac->event_mask1;
 733                 context->gReg[1] = sdmac->event_mask0;
 734                 context->gReg[2] = sdmac->per_addr;
 735                 context->gReg[6] = sdmac->shp_addr;
 736                 context->gReg[7] = sdmac->watermark_level;
 737                 break;
 738         }
 739
 740         return 0;
 741 }
 742
 743 static int sdma_load_context(struct sdma_channel *sdmac)
 744 {
 745         struct sdma_engine *sdma = sdmac->sdma;
 746         int channel = sdmac->channel;
 747         int load_address;
 748         struct sdma_context_data *context = sdma->context;
 749         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 750         int ret;
 751         unsigned long flags;
 752
 753
 754         if (sdmac->direction == DMA_DEV_TO_MEM)
 755                 load_address = sdmac->pc_from_device;
 756         else if (sdmac->direction == DMA_DEV_TO_DEV)
 757                 load_address = sdmac->device_to_device;
 758         else if (sdmac->direction == DMA_MEM_TO_DEV)
 759                 load_address = sdmac->pc_to_device;
 760         else if (sdmac->direction == DMA_MEM_TO_MEM)
 761                 load_address = sdmac->pc_to_pc;
 762         else
 763                 load_address = sdmac->other_script;
 764
 765
 766         if (load_address < 0)
 767                 return load_address;
 768
 769         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 770         dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
 771         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 772         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 773         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
 774         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
 775
 776         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 777         memset(context, 0, sizeof(*context));
 778         context->channel_state.pc = load_address;
 779
 780         /* Send by context the event mask,base address for peripheral
 781          * and watermark level
 782          */
 783         sdma_set_context_reg(sdmac, context);
 784
 785         bd0->mode.command = C0_SETDM;
 786         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 787         bd0->mode.count = sizeof(*context) / 4;
 788         bd0->buffer_addr = sdma->context_phys;
 789         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 790
 791         ret = sdma_run_channel(&sdma->channel[0]);
 792
 793         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 794         return ret;
 795 }
 796
 797 static void sdma_disable_channel(struct sdma_channel *sdmac)
 798 {
 799         struct sdma_engine *sdma = sdmac->sdma;
 800         int channel = sdmac->channel;
 801
 802         writel_relaxed(1 << channel, sdma->regs + SDMA_H_STATSTOP);
 803         sdmac->status = DMA_ERROR;
 804 }
 805
 806 static int sdma_set_chan_private_data(struct sdma_channel *sdmac)
 807 {
 808         struct sdma_engine *sdma = sdmac->sdma;
 809         struct imx_dma_data *data = sdmac->chan.private;
 810
 811         sdmac->shp_addr = 0;
 812         sdmac->per_addr = 0;
 813         sdmac->data_addr1 = 0;
 814         sdmac->data_addr2 = 0;
 815
 816
 817         if (sdmac->direction == DMA_DEV_TO_DEV) {
 818                 sdmac->per_addr = sdmac->per_address;
 819                 sdmac->shp_addr = sdmac->per_address2;
 820         } else if (sdmac->direction == DMA_TRANS_NONE) {
 821                 switch (sdmac->peripheral_type) {
 822                 case IMX_DMATYPE_HDMI:
 823                         sdmac->data_addr1 = *(u32 *)data->private;;
 824                         sdmac->data_addr2 = *((u32 *)data->private + 1);
 825                         break;
 826                 default:
 827                         dev_dbg(sdma->dev,
 828                         "periphal type not support for DMA_TRANS_NONE!\n");
 829                         break;
 830                 }
 831         } else {
 832                 sdmac->shp_addr = sdmac->per_address;
 833         }
 834
 835         return 0;
 836 }
 837
 838 static int sdma_config_channel(struct sdma_channel *sdmac)
 839 {
 840         int ret;
 841
 842         sdma_disable_channel(sdmac);
 843
 844         sdmac->event_mask0 = 0;
 845         sdmac->event_mask1 = 0;
 846
 847         if (sdmac->event_id0)
 848                 sdma_event_enable(sdmac, sdmac->event_id0);
 849
 850         if (sdmac->event_id1)
 851                 sdma_event_enable(sdmac, sdmac->event_id1);
 852
 853         switch (sdmac->peripheral_type) {
 854         case IMX_DMATYPE_DSP:
 855                 sdma_config_ownership(sdmac, false, true, true);
 856                 break;
 857         case IMX_DMATYPE_MEMORY:
 858                 sdma_config_ownership(sdmac, false, true, false);
 859                 break;
 860         default:
 861                 sdma_config_ownership(sdmac, true, true, false);
 862                 break;
 863         }
 864
 865         sdma_get_pc(sdmac, sdmac->peripheral_type);
 866
 867         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
 868                         (sdmac->peripheral_type != IMX_DMATYPE_DSP) &&
 869                         (sdmac->peripheral_type != IMX_DMATYPE_HDMI)) {
 870                 /* Handle multiple event channels differently */
 871                 if (sdmac->event_id1) {
 872                         if (sdmac->event_id0 > 31) {
 873                                 sdmac->watermark_level |= 1 << 28;
 874                                 sdmac->event_mask0 |= 0;
 875                                 sdmac->event_mask1 |=
 876                                         1 << ((sdmac->event_id0)%32);
 877                         } else {
 878                                 sdmac->event_mask0 |=
 879                                         1 << ((sdmac->event_id0)%32);
 880                                 sdmac->event_mask1 |= 0;
 881                         }
 882                         if (sdmac->event_id1 > 31) {
 883                                 sdmac->watermark_level |= 1 << 29;
 884                                 sdmac->event_mask0 |= 0;
 885                                 sdmac->event_mask1 |=
 886                                         1 << ((sdmac->event_id1)%32);
 887                         } else {
 888                                 sdmac->event_mask0 |=
 889                                         1 << ((sdmac->event_id1)%32);
 890                                 sdmac->event_mask1 |= 0;
 891                         }
 892                         sdmac->watermark_level |= (unsigned int)(3<<11);
 893                         sdmac->watermark_level |= (unsigned int)(1<<31);
 894                         sdmac->watermark_level |= (unsigned int)(2<<24);
 895                 } else {
 896                         if (sdmac->event_id0 > 31) {
 897                                 sdmac->event_mask0 = 0;
 898                                 sdmac->event_mask1 =
 899                                         1 << ((sdmac->event_id0)%32);
 900                         } else {
 901                                 sdmac->event_mask0 =
 902                                         1 << ((sdmac->event_id0)%32);
 903                                 sdmac->event_mask1 = 0;
 904                         }
 905                 }
 906                 /* Watermark Level */
 907                 sdmac->watermark_level |= sdmac->watermark_level;
 908         } else {
 909                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
 910         }
 911         sdma_set_chan_private_data(sdmac);
 912
 913         ret = sdma_load_context(sdmac);
 914
 915         return ret;
 916 }
 917
 918 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
 919                 unsigned int priority)
 920 {
 921         struct sdma_engine *sdma = sdmac->sdma;
 922         int channel = sdmac->channel;
 923
 924         if (priority < MXC_SDMA_MIN_PRIORITY
 925             || priority > MXC_SDMA_MAX_PRIORITY) {
 926                 return -EINVAL;
 927         }
 928
 929         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
 930
 931         return 0;
 932 }
 933
 934 static int sdma_request_channel(struct sdma_channel *sdmac)
 935 {
 936         struct sdma_engine *sdma = sdmac->sdma;
 937         int channel = sdmac->channel;
 938         int ret = -EBUSY;
 939
 940 #ifdef CONFIG_SDMA_IRAM
 941         sdmac->bd = sdma_iram_malloc(sizeof(sdmac->bd),
 942                                         (unsigned long *)&sdmac->bd_phys);
 943 #else
 944         sdmac->bd = dma_alloc_noncached(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
 945 #endif
 946         if (!sdmac->bd) {
 947                 ret = -ENOMEM;
 948                 goto out;
 949         }
 950
 951         memset(sdmac->bd, 0, PAGE_SIZE);
 952
 953         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
 954         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
 955
 956         clk_enable(sdma->clk);
 957
 958         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
 959
 960         init_completion(&sdmac->done);
 961
 962         sdmac->buf_tail = 0;
 963
 964         sdmac->irq_handling = 0;
 965
 966         return 0;
 967 out:
 968
 969         return ret;
 970 }
 971
 972 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 973 {
 974         wmb();
 975         writel(1 << channel, sdma->regs + SDMA_H_START);
 976 }
 977
 978 static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac)
 979 {
 980         dma_cookie_t cookie = sdmac->chan.cookie;
 981
 982         if (++cookie < 0)
 983                 cookie = 1;
 984
 985         sdmac->chan.cookie = cookie;
 986         sdmac->desc.cookie = cookie;
 987
 988         return cookie;
 989 }
 990
 991 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 992 {
 993         return container_of(chan, struct sdma_channel, chan);
 994 }
 995
 996 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
 997 {
 998         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
 999         struct sdma_engine *sdma = sdmac->sdma;
1000         dma_cookie_t cookie;
1001         unsigned long flag;
1002
1003         spin_lock_irqsave(&sdmac->lock, flag);
1004
1005         cookie = sdma_assign_cookie(sdmac);
1006
1007         sdma_enable_channel(sdma, sdmac->channel);
1008
1009         spin_unlock_irqrestore(&sdmac->lock, flag);
1010
1011         return cookie;
1012 }
1013
1014 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1015 {
1016         struct sdma_channel *sdmac = to_sdma_chan(chan);
1017         struct imx_dma_data *data = chan->private;
1018         int prio, ret;
1019
1020         if (!data)
1021                 return -EINVAL;
1022
1023         switch (data->priority) {
1024         case DMA_PRIO_HIGH:
1025                 prio = 3;
1026                 break;
1027         case DMA_PRIO_MEDIUM:
1028                 prio = 2;
1029                 break;
1030         case DMA_PRIO_LOW:
1031         default:
1032                 prio = 1;
1033                 break;
1034         }
1035
1036         sdmac->peripheral_type = data->peripheral_type;
1037         sdmac->event_id0 = data->dma_request;
1038         if (data->dma_request_p2p > 0)
1039                 sdmac->event_id1 = data->dma_request_p2p;
1040         else
1041                 sdmac->event_id1 = 0;
1042         ret = sdma_request_channel(sdmac);
1043         if (ret)
1044                 return ret;
1045
1046         ret = sdma_set_channel_priority(sdmac, prio);
1047         if (ret)
1048                 return ret;
1049
1050         dma_async_tx_descriptor_init(&sdmac->desc, chan);
1051         sdmac->desc.tx_submit = sdma_tx_submit;
1052         /* txd.flags will be overwritten in prep funcs */
1053         sdmac->desc.flags = DMA_CTRL_ACK;
1054
1055         /* Set SDMA channel mode to unvalid to avoid misconfig */
1056         sdmac->mode = SDMA_MODE_INVALID;
1057
1058         return 0;
1059 }
1060
1061 static void sdma_irq_pending_check(struct sdma_channel *sdmac)
1062 {
1063         struct sdma_engine *sdma = sdmac->sdma;
1064         unsigned long flag;
1065         u32 stat;
1066
1067         spin_lock_irqsave(&sdma->irq_reg_lock, flag);
1068         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
1069
1070         /*Check if the current channel's IRQ hasn't been responded*/
1071         if (stat & (1 << sdmac->channel)) {
1072                 /*Handle the irq manually*/
1073                 writel_relaxed(1 << sdmac->channel, sdma->regs + SDMA_H_INTR);
1074                 spin_unlock_irqrestore(&sdma->irq_reg_lock, flag);
1075
1076                 /*Prevent irq_handler from doing handle_channel() again*/
1077                 sdmac->irq_handling = 0;
1078                 mxc_sdma_handle_channel(sdmac);
1079         } else {
1080                 spin_unlock_irqrestore(&sdma->irq_reg_lock, flag);
1081         }
1082
1083         /*Wait here until irq_handler's finished*/
1084         while (sdmac->irq_handling)
1085                 udelay(100);
1086 }
1087
1088 static void sdma_free_chan_resources(struct dma_chan *chan)
1089 {
1090         struct sdma_channel *sdmac = to_sdma_chan(chan);
1091         struct sdma_engine *sdma = sdmac->sdma;
1092
1093         /*Check if irq to the channel is still pending*/
1094         sdma_irq_pending_check(sdmac);
1095
1096         sdma_disable_channel(sdmac);
1097
1098         if (sdmac->event_id0)
1099                 sdma_event_disable(sdmac, sdmac->event_id0);
1100         if (sdmac->event_id1)
1101                 sdma_event_disable(sdmac, sdmac->event_id1);
1102
1103         sdmac->event_id0 = 0;
1104         sdmac->event_id1 = 0;
1105
1106         sdma_set_channel_priority(sdmac, 0);
1107
1108 #ifdef CONFIG_SDMA_IRAM
1109         sdma_iram_free(sdmac->bd_phys, sizeof(sdmac->bd));
1110 #else
1111         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1112 #endif
1113         clk_disable(sdma->clk);
1114 }
1115
1116 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1117                 struct dma_chan *chan, struct scatterlist *sgl,
1118                 unsigned int sg_len, enum dma_transfer_direction direction,
1119                 unsigned long flags)
1120 {
1121         struct sdma_channel *sdmac = to_sdma_chan(chan);
1122         struct sdma_engine *sdma = sdmac->sdma;
1123         int ret, i, count;
1124         int channel = sdmac->channel;
1125         struct scatterlist *sg;
1126
1127         /*
1128          * For SDMA M2M use, we need 2 scatterlists, the src addresses are
1129          * stored in the first sg, and the dst addresses are stored in the
1130          * second sg. In the former code, when the first sg entered 'sdma_
1131          * prep_slave_sg', 'sdmac->status' would be set to 'DMA_IN_PROGRESS',
1132          * and the second sg would return 'NULL' when entered 'sdma_prep_slave
1133          * _sg'. To avoid this error, in the code, we check if for M2M use,
1134          * the second sg will not return 'NULL' when enters 'sdma_prep_slave
1135          * _sg'.
1136          */
1137         if (!((direction == DMA_MEM_TO_MEM) && (flags == 0))) {
1138                 if (sdmac->status == DMA_IN_PROGRESS)
1139                         return NULL;
1140         }
1141         sdmac->status = DMA_IN_PROGRESS;
1142
1143         sdmac->mode = SDMA_MODE_NORMAL;
1144
1145         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1146                         sg_len, channel);
1147
1148         sdmac->direction = direction;
1149         ret = sdma_load_context(sdmac);
1150         if (ret)
1151                 goto err_out;
1152
1153         if (sg_len > NUM_BD) {
1154                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1155                                 channel, sg_len, NUM_BD);
1156                 ret = -EINVAL;
1157                 goto err_out;
1158         }
1159
1160         sdmac->chn_count = 0;
1161         for_each_sg(sgl, sg, sg_len, i) {
1162                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1163                 int param;
1164
1165                 if (sdmac->direction == DMA_MEM_TO_MEM) {
1166                         if (flags == 1)
1167                                 bd->buffer_addr = sg->dma_address;
1168                         if (flags == 0)
1169                                 bd->ext_buffer_addr = sg->dma_address;
1170                 } else
1171                 bd->buffer_addr = sg->dma_address;
1172
1173                 count = sg->length;
1174
1175                 if (count > 0xffff) {
1176                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1177                                         channel, count, 0xffff);
1178                         ret = -EINVAL;
1179                         goto err_out;
1180                 }
1181
1182                 bd->mode.count = count;
1183                 sdmac->chn_count += count;
1184
1185                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1186                         ret =  -EINVAL;
1187                         goto err_out;
1188                 }
1189
1190                 switch (sdmac->word_size) {
1191                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1192                         bd->mode.command = 0;
1193                         if (count & 3 || sg->dma_address & 3)
1194                                 return NULL;
1195                         break;
1196                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1197                         bd->mode.command = 2;
1198                         if (count & 1 || sg->dma_address & 1)
1199                                 return NULL;
1200                         break;
1201                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1202                         bd->mode.command = 1;
1203                         break;
1204                 default:
1205                         return NULL;
1206                 }
1207
1208                 param = BD_DONE | BD_EXTD | BD_CONT;
1209
1210                 if (i + 1 == sg_len) {
1211                         param |= BD_INTR;
1212                         param |= BD_LAST;
1213                         param &= ~BD_CONT;
1214                 }
1215
1216                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1217                                 i, count, sg->dma_address,
1218                                 param & BD_WRAP ? "wrap" : "",
1219                                 param & BD_INTR ? " intr" : "");
1220
1221                 bd->mode.status = param;
1222         }
1223
1224         sdmac->num_bd = sg_len;
1225         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1226
1227         return &sdmac->desc;
1228 err_out:
1229         sdmac->status = DMA_ERROR;
1230         return NULL;
1231 }
1232
1233 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1234                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1235                 size_t period_len, enum dma_transfer_direction direction)
1236 {
1237         struct sdma_channel *sdmac = to_sdma_chan(chan);
1238         struct sdma_engine *sdma = sdmac->sdma;
1239         int num_periods;
1240         int channel = sdmac->channel;
1241         int ret, i = 0, buf = 0;
1242
1243         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1244
1245         if (sdmac->status == DMA_IN_PROGRESS)
1246                 return NULL;
1247
1248         sdmac->status = DMA_IN_PROGRESS;
1249         sdmac->direction = direction;
1250
1251         switch (sdmac->direction) {
1252         case DMA_DEV_TO_DEV:
1253                 sdmac->mode = SDMA_MODE_P2P;
1254                 break;
1255         case DMA_TRANS_NONE:
1256                 sdmac->mode = SDMA_MODE_NO_BD;
1257                 break;
1258         case DMA_MEM_TO_DEV:
1259         case DMA_DEV_TO_MEM:
1260                 sdmac->mode = SDMA_MODE_LOOP;
1261                 break;
1262         default:
1263                 pr_err("SDMA direction is not support!");
1264                 return NULL;
1265         }
1266
1267         ret = sdma_load_context(sdmac);
1268         if (ret)
1269                 goto err_out;
1270
1271         if (period_len)
1272                 num_periods = buf_len / period_len;
1273         else
1274                 return &sdmac->desc;
1275
1276         if (num_periods > NUM_BD) {
1277                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1278                                 channel, num_periods, NUM_BD);
1279                 goto err_out;
1280         }
1281
1282         if (period_len > 0xffff) {
1283                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1284                                 channel, period_len, 0xffff);
1285                 goto err_out;
1286         }
1287
1288         while (buf < buf_len) {
1289                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1290                 int param;
1291
1292                 bd->buffer_addr = dma_addr;
1293
1294                 bd->mode.count = period_len;
1295
1296                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1297                         goto err_out;
1298                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1299                         bd->mode.command = 0;
1300                 else
1301                         bd->mode.command = sdmac->word_size;
1302
1303                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1304                 if (i + 1 == num_periods)
1305                         param |= BD_WRAP;
1306
1307                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1308                                 i, period_len, dma_addr,
1309                                 param & BD_WRAP ? "wrap" : "",
1310                                 param & BD_INTR ? " intr" : "");
1311
1312                 bd->mode.status = param;
1313
1314                 dma_addr += period_len;
1315                 buf += period_len;
1316
1317                 i++;
1318         }
1319
1320         sdmac->num_bd = num_periods;
1321         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1322
1323         return &sdmac->desc;
1324 err_out:
1325         sdmac->status = DMA_ERROR;
1326         return NULL;
1327 }
1328
1329 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1330                 unsigned long arg)
1331 {
1332         struct sdma_channel *sdmac = to_sdma_chan(chan);
1333         struct dma_slave_config *dmaengine_cfg = (void *)arg;
1334
1335         switch (cmd) {
1336         case DMA_TERMINATE_ALL:
1337                 sdma_disable_channel(sdmac);
1338                 return 0;
1339         case DMA_SLAVE_CONFIG:
1340                 if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
1341                         sdmac->per_address = dmaengine_cfg->src_addr;
1342                         sdmac->per_address2 = dmaengine_cfg->dst_addr;
1343                         sdmac->watermark_level = 0;
1344                         sdmac->watermark_level |=
1345                                 dmaengine_cfg->src_maxburst;
1346                         sdmac->watermark_level |=
1347                                 dmaengine_cfg->dst_maxburst << 16;
1348                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1349                 } else if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1350                         sdmac->per_address = dmaengine_cfg->src_addr;
1351                         sdmac->watermark_level = dmaengine_cfg->src_maxburst;
1352                         sdmac->word_size = dmaengine_cfg->src_addr_width;
1353                 } else if (dmaengine_cfg->direction == DMA_MEM_TO_DEV) {
1354                         sdmac->per_address = dmaengine_cfg->dst_addr;
1355                         sdmac->watermark_level = dmaengine_cfg->dst_maxburst;
1356                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1357                 } else if (dmaengine_cfg->direction == DMA_MEM_TO_MEM) {
1358                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1359                 }
1360                 sdmac->direction = dmaengine_cfg->direction;
1361                 return sdma_config_channel(sdmac);
1362         default:
1363                 return -ENOSYS;
1364         }
1365
1366         return -EINVAL;
1367 }
1368
1369 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1370                                             dma_cookie_t cookie,
1371                                             struct dma_tx_state *txstate)
1372 {
1373         struct sdma_channel *sdmac = to_sdma_chan(chan);
1374         dma_cookie_t last_used;
1375
1376         last_used = chan->cookie;
1377
1378         dma_set_tx_state(txstate, sdmac->last_completed, last_used,
1379                         sdmac->chn_count - sdmac->chn_real_count);
1380
1381         return sdmac->status;
1382 }
1383
1384 static void sdma_issue_pending(struct dma_chan *chan)
1385 {
1386         /*
1387          * Nothing to do. We only have a single descriptor
1388          */
1389 }
1390
1391 void sdma_set_event_pending(struct dma_chan *chan)
1392 {
1393         struct sdma_channel *sdmac = to_sdma_chan(chan);
1394         struct sdma_engine *sdma = sdmac->sdma;
1395         u32 reg;
1396         u32 channel;
1397
1398         channel = sdmac->channel;
1399         reg = readl_relaxed(sdma->regs + SDMA_H_EVTPEND);
1400         reg |= 1 << channel;
1401         writel_relaxed(reg, sdma->regs + SDMA_H_EVTPEND);
1402
1403         return;
1404 }
1405 EXPORT_SYMBOL(sdma_set_event_pending);
1406
1407 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 38
1408
1409 static void sdma_add_scripts(struct sdma_engine *sdma,
1410                 const struct sdma_script_start_addrs *addr)
1411 {
1412         s32 *addr_arr = (u32 *)addr;
1413         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1414         int i;
1415
1416         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1417                 if (addr_arr[i] > 0)
1418                         saddr_arr[i] = addr_arr[i];
1419 }
1420
1421 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1422                 const char *cpu_name, int to_version)
1423 {
1424         const struct firmware *fw;
1425         char *fwname;
1426         const struct sdma_firmware_header *header;
1427         int ret;
1428         const struct sdma_script_start_addrs *addr;
1429         unsigned short *ram_code;
1430
1431         fwname = kasprintf(GFP_KERNEL, "imx/sdma/sdma-%s-to%d.bin",
1432                                 cpu_name, to_version);
1433         if (!fwname)
1434                 return -ENOMEM;
1435
1436         ret = request_firmware(&fw, fwname, sdma->dev);
1437         if (ret) {
1438                 kfree(fwname);
1439                 return ret;
1440         }
1441         kfree(fwname);
1442
1443         if (fw->size < sizeof(*header))
1444                 goto err_firmware;
1445
1446         header = (struct sdma_firmware_header *)fw->data;
1447
1448         if (header->magic != SDMA_FIRMWARE_MAGIC)
1449                 goto err_firmware;
1450         if (header->ram_code_start + header->ram_code_size > fw->size)
1451                 goto err_firmware;
1452
1453         addr = (void *)header + header->script_addrs_start;
1454         ram_code = (void *)header + header->ram_code_start;
1455
1456         /* download the RAM image for SDMA */
1457         sdma_load_script(sdma, ram_code,
1458                         header->ram_code_size,
1459                         addr->ram_code_start_addr);
1460         clk_disable(sdma->clk);
1461
1462         sdma_add_scripts(sdma, addr);
1463
1464         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1465                         header->version_major,
1466                         header->version_minor);
1467
1468 err_firmware:
1469         release_firmware(fw);
1470
1471         return ret;
1472 }
1473
1474 static int __init sdma_init(struct sdma_engine *sdma)
1475 {
1476         int i, ret;
1477         dma_addr_t ccb_phys;
1478
1479         switch (sdma->version) {
1480         case 1:
1481                 sdma->num_events = 32;
1482                 break;
1483         case 2:
1484                 sdma->num_events = 48;
1485                 break;
1486         default:
1487                 dev_err(sdma->dev, "Unknown version %d. aborting\n", sdma->version);
1488                 return -ENODEV;
1489         }
1490
1491         clk_enable(sdma->clk);
1492
1493         /* Be sure SDMA has not started yet */
1494         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1495
1496 #ifdef CONFIG_SDMA_IRAM
1497         /* Allocate memory for SDMA channel and buffer descriptors */
1498         sdma_iram_vaddr = iram_alloc(SZ_4K, &sdma_iram_paddr);
1499         sdma_iram_pool = gen_pool_create(PAGE_SHIFT/2, -1);
1500         gen_pool_add(sdma_iram_pool, sdma_iram_paddr, SZ_4K, -1);
1501
1502         sdma->channel_control = sdma_iram_malloc(MAX_DMA_CHANNELS *
1503                         sizeof(struct sdma_channel_control)
1504                         + sizeof(struct sdma_context_data),
1505                         (unsigned long *)&ccb_phys);
1506 #else
1507         sdma->channel_control = dma_alloc_coherent(NULL,
1508                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1509                         sizeof(struct sdma_context_data),
1510                         &ccb_phys, GFP_KERNEL);
1511 #endif
1512
1513         if (!sdma->channel_control) {
1514                 ret = -ENOMEM;
1515                 goto err_dma_alloc;
1516         }
1517
1518         sdma->context = (void *)sdma->channel_control +
1519                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1520         sdma->context_phys = ccb_phys +
1521                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1522
1523         /* Zero-out the CCB structures array just allocated */
1524         memset(sdma->channel_control, 0,
1525                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1526
1527         /* disable all channels */
1528         for (i = 0; i < sdma->num_events; i++)
1529                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1530
1531         /* All channels have priority 0 */
1532         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1533                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1534
1535         ret = sdma_request_channel(&sdma->channel[0]);
1536         if (ret)
1537                 goto err_dma_alloc;
1538
1539         sdma_config_ownership(&sdma->channel[0], false, true, false);
1540
1541         /* Set Command Channel (Channel Zero) */
1542         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1543
1544         /* Set bits of CONFIG register but with static context switching */
1545         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1546         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1547
1548         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1549
1550         /* Set bits of CONFIG register with given context switching mode */
1551         writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1552
1553         /* Initializes channel's priorities */
1554         sdma_set_channel_priority(&sdma->channel[0], 7);
1555
1556         clk_disable(sdma->clk);
1557
1558         return 0;
1559
1560 err_dma_alloc:
1561         clk_disable(sdma->clk);
1562         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1563         return ret;
1564 }
1565
1566 static int __init sdma_probe(struct platform_device *pdev)
1567 {
1568         int ret;
1569         int irq;
1570         struct resource *iores;
1571         struct sdma_platform_data *pdata = pdev->dev.platform_data;
1572         int i;
1573         struct sdma_engine *sdma;
1574
1575         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1576         if (!sdma)
1577                 return -ENOMEM;
1578
1579         spin_lock_init(&sdma->channel_0_lock);
1580
1581         sdma->dev = &pdev->dev;
1582
1583         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1584         irq = platform_get_irq(pdev, 0);
1585         if (!iores || irq < 0 || !pdata) {
1586                 ret = -EINVAL;
1587                 goto err_irq;
1588         }
1589
1590         if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1591                 ret = -EBUSY;
1592                 goto err_request_region;
1593         }
1594
1595         sdma->clk = clk_get(&pdev->dev, NULL);
1596         if (IS_ERR(sdma->clk)) {
1597                 ret = PTR_ERR(sdma->clk);
1598                 goto err_clk;
1599         }
1600
1601         sdma->regs = ioremap(iores->start, resource_size(iores));
1602         if (!sdma->regs) {
1603                 ret = -ENOMEM;
1604                 goto err_ioremap;
1605         }
1606
1607         ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1608         if (ret)
1609                 goto err_request_irq;
1610
1611         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1612         if (!sdma->script_addrs)
1613                 goto err_alloc;
1614
1615         sdma->version = pdata->sdma_version;
1616
1617         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1618         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1619
1620         spin_lock_init(&sdma->irq_reg_lock);
1621
1622         INIT_LIST_HEAD(&sdma->dma_device.channels);
1623         /* Initialize channel parameters */
1624         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1625                 struct sdma_channel *sdmac = &sdma->channel[i];
1626
1627                 sdmac->sdma = sdma;
1628                 spin_lock_init(&sdmac->lock);
1629
1630                 sdmac->chan.device = &sdma->dma_device;
1631                 sdmac->channel = i;
1632
1633                 /*
1634                  * Add the channel to the DMAC list. Do not add channel 0 though
1635                  * because we need it internally in the SDMA driver. This also means
1636                  * that channel 0 in dmaengine counting matches sdma channel 1.
1637                  */
1638                 if (i)
1639                         list_add_tail(&sdmac->chan.device_node,
1640                                         &sdma->dma_device.channels);
1641         }
1642
1643         ret = sdma_init(sdma);
1644         if (ret)
1645                 goto err_init;
1646
1647         if (pdata->script_addrs)
1648                 sdma_add_scripts(sdma, pdata->script_addrs);
1649
1650         sdma_get_firmware(sdma, pdata->cpu_name, pdata->to_version);
1651
1652         sdma->dma_device.dev = &pdev->dev;
1653
1654         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1655         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1656         sdma->dma_device.device_tx_status = sdma_tx_status;
1657         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1658         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1659         sdma->dma_device.device_control = sdma_control;
1660         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1661         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1662         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1663
1664         ret = dma_async_device_register(&sdma->dma_device);
1665         if (ret) {
1666                 dev_err(&pdev->dev, "unable to register\n");
1667                 goto err_init;
1668         }
1669
1670         dev_info(sdma->dev, "initialized\n");
1671
1672         return 0;
1673
1674 err_init:
1675         kfree(sdma->script_addrs);
1676 err_alloc:
1677         free_irq(irq, sdma);
1678 err_request_irq:
1679         iounmap(sdma->regs);
1680 err_ioremap:
1681         clk_put(sdma->clk);
1682 err_clk:
1683         release_mem_region(iores->start, resource_size(iores));
1684 err_request_region:
1685 err_irq:
1686         kfree(sdma);
1687         return ret;
1688 }
1689
1690 static int __exit sdma_remove(struct platform_device *pdev)
1691 {
1692         return -EBUSY;
1693 }
1694
1695 static struct platform_driver sdma_driver = {
1696         .driver         = {
1697                 .name   = "imx-sdma",
1698         },
1699         .remove         = __exit_p(sdma_remove),
1700 };
1701
1702 static int __init sdma_module_init(void)
1703 {
1704         return platform_driver_probe(&sdma_driver, sdma_probe);
1705 }
1706 module_init(sdma_module_init);
1707
1708 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1709 MODULE_DESCRIPTION("i.MX SDMA driver");
1710 MODULE_LICENSE("GPL");