2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2009 Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
24 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/interrupt.h>
32 #include <linux/dmaengine.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/workqueue.h>
36 #include <linux/i7300_idle.h>
38 #include "registers.h"
41 int ioat_pending_level = 4;
42 module_param(ioat_pending_level, int, 0644);
43 MODULE_PARM_DESC(ioat_pending_level,
44 "high-water mark for pushing ioat descriptors (default: 4)");
46 /* internal functions */
47 static void ioat1_cleanup(struct ioat_dma_chan *ioat);
48 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat);
51 * ioat_dma_do_interrupt - handler used for single vector interrupt mode
53 * @data: interrupt data
55 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
57 struct ioatdma_device *instance = data;
58 struct ioat_chan_common *chan;
59 unsigned long attnstatus;
63 intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
65 if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
68 if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
69 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
73 attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
74 for_each_bit(bit, &attnstatus, BITS_PER_LONG) {
75 chan = ioat_chan_by_index(instance, bit);
76 tasklet_schedule(&chan->cleanup_task);
79 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
84 * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
86 * @data: interrupt data
88 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
90 struct ioat_chan_common *chan = data;
92 tasklet_schedule(&chan->cleanup_task);
97 static void ioat1_cleanup_tasklet(unsigned long data);
99 /* common channel initialization */
100 void ioat_init_channel(struct ioatdma_device *device,
101 struct ioat_chan_common *chan, int idx,
102 work_func_t work_fn, void (*tasklet)(unsigned long),
103 unsigned long tasklet_data)
105 struct dma_device *dma = &device->common;
107 chan->device = device;
108 chan->reg_base = device->reg_base + (0x80 * (idx + 1));
109 INIT_DELAYED_WORK(&chan->work, work_fn);
110 spin_lock_init(&chan->cleanup_lock);
111 chan->common.device = dma;
112 list_add_tail(&chan->common.device_node, &dma->channels);
113 device->idx[idx] = chan;
114 tasklet_init(&chan->cleanup_task, tasklet, tasklet_data);
115 tasklet_disable(&chan->cleanup_task);
118 static void ioat1_reset_part2(struct work_struct *work);
121 * ioat1_dma_enumerate_channels - find and initialize the device's channels
122 * @device: the device to be enumerated
124 static int ioat1_enumerate_channels(struct ioatdma_device *device)
129 struct ioat_dma_chan *ioat;
130 struct device *dev = &device->pdev->dev;
131 struct dma_device *dma = &device->common;
133 INIT_LIST_HEAD(&dma->channels);
134 dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
135 dma->chancnt &= 0x1f; /* bits [4:0] valid */
136 if (dma->chancnt > ARRAY_SIZE(device->idx)) {
137 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
138 dma->chancnt, ARRAY_SIZE(device->idx));
139 dma->chancnt = ARRAY_SIZE(device->idx);
141 xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
142 xfercap_scale &= 0x1f; /* bits [4:0] valid */
143 xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
144 dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap);
146 #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
147 if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
150 for (i = 0; i < dma->chancnt; i++) {
151 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
155 ioat_init_channel(device, &ioat->base, i,
157 ioat1_cleanup_tasklet,
158 (unsigned long) ioat);
159 ioat->xfercap = xfercap;
160 spin_lock_init(&ioat->desc_lock);
161 INIT_LIST_HEAD(&ioat->free_desc);
162 INIT_LIST_HEAD(&ioat->used_desc);
169 * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
171 * @chan: DMA channel handle
174 __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat)
176 void __iomem *reg_base = ioat->base.reg_base;
178 dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n",
179 __func__, ioat->pending);
181 writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET);
184 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
186 struct ioat_dma_chan *ioat = to_ioat_chan(chan);
188 if (ioat->pending > 0) {
189 spin_lock_bh(&ioat->desc_lock);
190 __ioat1_dma_memcpy_issue_pending(ioat);
191 spin_unlock_bh(&ioat->desc_lock);
196 * ioat1_reset_part2 - reinit the channel after a reset
198 static void ioat1_reset_part2(struct work_struct *work)
200 struct ioat_chan_common *chan;
201 struct ioat_dma_chan *ioat;
202 struct ioat_desc_sw *desc;
204 bool start_null = false;
206 chan = container_of(work, struct ioat_chan_common, work.work);
207 ioat = container_of(chan, struct ioat_dma_chan, base);
208 spin_lock_bh(&chan->cleanup_lock);
209 spin_lock_bh(&ioat->desc_lock);
211 *chan->completion = 0;
214 /* count the descriptors waiting */
216 if (ioat->used_desc.prev) {
217 desc = to_ioat_desc(ioat->used_desc.prev);
220 desc = to_ioat_desc(desc->node.next);
221 } while (&desc->node != ioat->used_desc.next);
226 * write the new starting descriptor address
227 * this puts channel engine into ARMED state
229 desc = to_ioat_desc(ioat->used_desc.prev);
230 writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
231 chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
232 writel(((u64) desc->txd.phys) >> 32,
233 chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
235 writeb(IOAT_CHANCMD_START, chan->reg_base
236 + IOAT_CHANCMD_OFFSET(chan->device->version));
239 spin_unlock_bh(&ioat->desc_lock);
240 spin_unlock_bh(&chan->cleanup_lock);
242 dev_err(to_dev(chan),
243 "chan%d reset - %d descs waiting, %d total desc\n",
244 chan_num(chan), dmacount, ioat->desccount);
247 ioat1_dma_start_null_desc(ioat);
251 * ioat1_reset_channel - restart a channel
252 * @ioat: IOAT DMA channel handle
254 static void ioat1_reset_channel(struct ioat_dma_chan *ioat)
256 struct ioat_chan_common *chan = &ioat->base;
257 void __iomem *reg_base = chan->reg_base;
258 u32 chansts, chanerr;
260 if (!ioat->used_desc.prev)
263 dev_dbg(to_dev(chan), "%s\n", __func__);
264 chanerr = readl(reg_base + IOAT_CHANERR_OFFSET);
265 chansts = *chan->completion & IOAT_CHANSTS_DMA_TRANSFER_STATUS;
267 dev_err(to_dev(chan),
268 "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
269 chan_num(chan), chansts, chanerr);
270 writel(chanerr, reg_base + IOAT_CHANERR_OFFSET);
274 * whack it upside the head with a reset
275 * and wait for things to settle out.
276 * force the pending count to a really big negative
277 * to make sure no one forces an issue_pending
278 * while we're waiting.
281 spin_lock_bh(&ioat->desc_lock);
282 ioat->pending = INT_MIN;
283 writeb(IOAT_CHANCMD_RESET,
284 reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
285 spin_unlock_bh(&ioat->desc_lock);
287 /* schedule the 2nd half instead of sleeping a long time */
288 schedule_delayed_work(&chan->work, RESET_DELAY);
292 * ioat1_chan_watchdog - watch for stuck channels
294 static void ioat1_chan_watchdog(struct work_struct *work)
296 struct ioatdma_device *device =
297 container_of(work, struct ioatdma_device, work.work);
298 struct ioat_dma_chan *ioat;
299 struct ioat_chan_common *chan;
303 unsigned long compl_desc_addr_hw;
305 for (i = 0; i < device->common.chancnt; i++) {
306 chan = ioat_chan_by_index(device, i);
307 ioat = container_of(chan, struct ioat_dma_chan, base);
309 if (/* have we started processing anything yet */
310 chan->last_completion
311 /* have we completed any since last watchdog cycle? */
312 && (chan->last_completion == chan->watchdog_completion)
313 /* has TCP stuck on one cookie since last watchdog? */
314 && (chan->watchdog_tcp_cookie == chan->watchdog_last_tcp_cookie)
315 && (chan->watchdog_tcp_cookie != chan->completed_cookie)
316 /* is there something in the chain to be processed? */
317 /* CB1 chain always has at least the last one processed */
318 && (ioat->used_desc.prev != ioat->used_desc.next)
319 && ioat->pending == 0) {
322 * check CHANSTS register for completed
323 * descriptor address.
324 * if it is different than completion writeback,
326 * and it has changed since the last watchdog
327 * we can assume that channel
328 * is still working correctly
329 * and the problem is in completion writeback.
330 * update completion writeback
331 * with actual CHANSTS value
333 * try resetting the channel
336 /* we need to read the low address first as this
337 * causes the chipset to latch the upper bits
338 * for the subsequent read
340 completion_low = readl(chan->reg_base +
341 IOAT_CHANSTS_OFFSET_LOW(chan->device->version));
342 completion = readl(chan->reg_base +
343 IOAT_CHANSTS_OFFSET_HIGH(chan->device->version));
345 completion |= completion_low;
346 compl_desc_addr_hw = completion &
347 IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
349 if ((compl_desc_addr_hw != 0)
350 && (compl_desc_addr_hw != chan->watchdog_completion)
351 && (compl_desc_addr_hw != chan->last_compl_desc_addr_hw)) {
352 chan->last_compl_desc_addr_hw = compl_desc_addr_hw;
353 *chan->completion = completion;
355 ioat1_reset_channel(ioat);
356 chan->watchdog_completion = 0;
357 chan->last_compl_desc_addr_hw = 0;
360 chan->last_compl_desc_addr_hw = 0;
361 chan->watchdog_completion = chan->last_completion;
364 chan->watchdog_last_tcp_cookie = chan->watchdog_tcp_cookie;
367 schedule_delayed_work(&device->work, WATCHDOG_DELAY);
370 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
372 struct dma_chan *c = tx->chan;
373 struct ioat_dma_chan *ioat = to_ioat_chan(c);
374 struct ioat_desc_sw *desc = tx_to_ioat_desc(tx);
375 struct ioat_desc_sw *first;
376 struct ioat_desc_sw *chain_tail;
379 spin_lock_bh(&ioat->desc_lock);
380 /* cookie incr and addition to used_list must be atomic */
387 dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
389 /* write address into NextDescriptor field of last desc in chain */
390 first = to_ioat_desc(tx->tx_list.next);
391 chain_tail = to_ioat_desc(ioat->used_desc.prev);
392 /* make descriptor updates globally visible before chaining */
394 chain_tail->hw->next = first->txd.phys;
395 list_splice_tail_init(&tx->tx_list, &ioat->used_desc);
396 dump_desc_dbg(ioat, chain_tail);
397 dump_desc_dbg(ioat, first);
399 ioat->pending += desc->tx_cnt;
400 if (ioat->pending >= ioat_pending_level)
401 __ioat1_dma_memcpy_issue_pending(ioat);
402 spin_unlock_bh(&ioat->desc_lock);
408 * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
409 * @ioat: the channel supplying the memory pool for the descriptors
410 * @flags: allocation flags
412 static struct ioat_desc_sw *
413 ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags)
415 struct ioat_dma_descriptor *desc;
416 struct ioat_desc_sw *desc_sw;
417 struct ioatdma_device *ioatdma_device;
420 ioatdma_device = ioat->base.device;
421 desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
425 desc_sw = kzalloc(sizeof(*desc_sw), flags);
426 if (unlikely(!desc_sw)) {
427 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
431 memset(desc, 0, sizeof(*desc));
433 dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common);
434 desc_sw->txd.tx_submit = ioat1_tx_submit;
436 desc_sw->txd.phys = phys;
437 set_desc_id(desc_sw, -1);
442 static int ioat_initial_desc_count = 256;
443 module_param(ioat_initial_desc_count, int, 0644);
444 MODULE_PARM_DESC(ioat_initial_desc_count,
445 "ioat1: initial descriptors per channel (default: 256)");
447 * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors
448 * @chan: the channel to be filled out
450 static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
452 struct ioat_dma_chan *ioat = to_ioat_chan(c);
453 struct ioat_chan_common *chan = &ioat->base;
454 struct ioat_desc_sw *desc;
460 /* have we already been set up? */
461 if (!list_empty(&ioat->free_desc))
462 return ioat->desccount;
464 /* Setup register to interrupt and write completion status on error */
465 chanctrl = IOAT_CHANCTRL_ERR_INT_EN |
466 IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
467 IOAT_CHANCTRL_ERR_COMPLETION_EN;
468 writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET);
470 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
472 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
473 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
476 /* Allocate descriptors */
477 for (i = 0; i < ioat_initial_desc_count; i++) {
478 desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL);
480 dev_err(to_dev(chan), "Only %d initial descriptors\n", i);
483 set_desc_id(desc, i);
484 list_add_tail(&desc->node, &tmp_list);
486 spin_lock_bh(&ioat->desc_lock);
488 list_splice(&tmp_list, &ioat->free_desc);
489 spin_unlock_bh(&ioat->desc_lock);
491 /* allocate a completion writeback area */
492 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
493 chan->completion = pci_pool_alloc(chan->device->completion_pool,
494 GFP_KERNEL, &chan->completion_dma);
495 memset(chan->completion, 0, sizeof(*chan->completion));
496 writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
497 chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
498 writel(((u64) chan->completion_dma) >> 32,
499 chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
501 tasklet_enable(&chan->cleanup_task);
502 ioat1_dma_start_null_desc(ioat); /* give chain to dma device */
503 dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
504 __func__, ioat->desccount);
505 return ioat->desccount;
509 * ioat1_dma_free_chan_resources - release all the descriptors
510 * @chan: the channel to be cleaned
512 static void ioat1_dma_free_chan_resources(struct dma_chan *c)
514 struct ioat_dma_chan *ioat = to_ioat_chan(c);
515 struct ioat_chan_common *chan = &ioat->base;
516 struct ioatdma_device *ioatdma_device = chan->device;
517 struct ioat_desc_sw *desc, *_desc;
518 int in_use_descs = 0;
520 /* Before freeing channel resources first check
521 * if they have been previously allocated for this channel.
523 if (ioat->desccount == 0)
526 tasklet_disable(&chan->cleanup_task);
529 /* Delay 100ms after reset to allow internal DMA logic to quiesce
530 * before removing DMA descriptor resources.
532 writeb(IOAT_CHANCMD_RESET,
533 chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
536 spin_lock_bh(&ioat->desc_lock);
537 list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
538 dev_dbg(to_dev(chan), "%s: freeing %d from used list\n",
539 __func__, desc_id(desc));
540 dump_desc_dbg(ioat, desc);
542 list_del(&desc->node);
543 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
547 list_for_each_entry_safe(desc, _desc,
548 &ioat->free_desc, node) {
549 list_del(&desc->node);
550 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
554 spin_unlock_bh(&ioat->desc_lock);
556 pci_pool_free(ioatdma_device->completion_pool,
558 chan->completion_dma);
560 /* one is ok since we left it on there on purpose */
561 if (in_use_descs > 1)
562 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
565 chan->last_completion = 0;
566 chan->completion_dma = 0;
567 chan->watchdog_completion = 0;
568 chan->last_compl_desc_addr_hw = 0;
569 chan->watchdog_tcp_cookie = chan->watchdog_last_tcp_cookie = 0;
575 * ioat1_dma_get_next_descriptor - return the next available descriptor
576 * @ioat: IOAT DMA channel handle
578 * Gets the next descriptor from the chain, and must be called with the
579 * channel's desc_lock held. Allocates more descriptors if the channel
582 static struct ioat_desc_sw *
583 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat)
585 struct ioat_desc_sw *new;
587 if (!list_empty(&ioat->free_desc)) {
588 new = to_ioat_desc(ioat->free_desc.next);
589 list_del(&new->node);
591 /* try to get another desc */
592 new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC);
594 dev_err(to_dev(&ioat->base), "alloc failed\n");
598 dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n",
599 __func__, desc_id(new));
604 static struct dma_async_tx_descriptor *
605 ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
606 dma_addr_t dma_src, size_t len, unsigned long flags)
608 struct ioat_dma_chan *ioat = to_ioat_chan(c);
609 struct ioat_desc_sw *desc;
612 dma_addr_t src = dma_src;
613 dma_addr_t dest = dma_dest;
614 size_t total_len = len;
615 struct ioat_dma_descriptor *hw = NULL;
618 spin_lock_bh(&ioat->desc_lock);
619 desc = ioat1_dma_get_next_descriptor(ioat);
625 copy = min_t(size_t, len, ioat->xfercap);
633 list_add_tail(&desc->node, &chain);
639 struct ioat_desc_sw *next;
641 async_tx_ack(&desc->txd);
642 next = ioat1_dma_get_next_descriptor(ioat);
643 hw->next = next ? next->txd.phys : 0;
644 dump_desc_dbg(ioat, desc);
651 struct ioat_chan_common *chan = &ioat->base;
653 dev_err(to_dev(chan),
654 "chan%d - get_next_desc failed\n", chan_num(chan));
655 list_splice(&chain, &ioat->free_desc);
656 spin_unlock_bh(&ioat->desc_lock);
659 spin_unlock_bh(&ioat->desc_lock);
661 desc->txd.flags = flags;
662 desc->tx_cnt = tx_cnt;
663 desc->len = total_len;
664 list_splice(&chain, &desc->txd.tx_list);
665 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
666 hw->ctl_f.compl_write = 1;
667 dump_desc_dbg(ioat, desc);
672 static void ioat1_cleanup_tasklet(unsigned long data)
674 struct ioat_dma_chan *chan = (void *)data;
676 writew(IOAT_CHANCTRL_INT_DISABLE,
677 chan->base.reg_base + IOAT_CHANCTRL_OFFSET);
680 static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,
681 int direction, enum dma_ctrl_flags flags, bool dst)
683 if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) ||
684 (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE)))
685 pci_unmap_single(pdev, addr, len, direction);
687 pci_unmap_page(pdev, addr, len, direction);
691 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
692 size_t len, struct ioat_dma_descriptor *hw)
694 struct pci_dev *pdev = chan->device->pdev;
695 size_t offset = len - hw->size;
697 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
698 ioat_unmap(pdev, hw->dst_addr - offset, len,
699 PCI_DMA_FROMDEVICE, flags, 1);
701 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP))
702 ioat_unmap(pdev, hw->src_addr - offset, len,
703 PCI_DMA_TODEVICE, flags, 0);
706 unsigned long ioat_get_current_completion(struct ioat_chan_common *chan)
708 unsigned long phys_complete;
711 completion = *chan->completion;
712 phys_complete = completion & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
714 dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__,
715 (unsigned long long) phys_complete);
717 if ((completion & IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
718 IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
719 dev_err(to_dev(chan), "Channel halted, chanerr = %x\n",
720 readl(chan->reg_base + IOAT_CHANERR_OFFSET));
722 /* TODO do something to salvage the situation */
725 return phys_complete;
729 * ioat1_cleanup - cleanup up finished descriptors
730 * @chan: ioat channel to be cleaned up
732 static void ioat1_cleanup(struct ioat_dma_chan *ioat)
734 struct ioat_chan_common *chan = &ioat->base;
735 unsigned long phys_complete;
736 struct ioat_desc_sw *desc, *_desc;
737 dma_cookie_t cookie = 0;
738 struct dma_async_tx_descriptor *tx;
740 prefetch(chan->completion);
742 if (!spin_trylock_bh(&chan->cleanup_lock))
745 phys_complete = ioat_get_current_completion(chan);
746 if (phys_complete == chan->last_completion) {
747 spin_unlock_bh(&chan->cleanup_lock);
749 * perhaps we're stuck so hard that the watchdog can't go off?
750 * try to catch it after 2 seconds
752 if (time_after(jiffies,
753 chan->last_completion_time + HZ*WATCHDOG_DELAY)) {
754 ioat1_chan_watchdog(&(chan->device->work.work));
755 chan->last_completion_time = jiffies;
759 chan->last_completion_time = jiffies;
762 if (!spin_trylock_bh(&ioat->desc_lock)) {
763 spin_unlock_bh(&chan->cleanup_lock);
767 dev_dbg(to_dev(chan), "%s: phys_complete: %lx\n",
768 __func__, phys_complete);
769 list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
772 * Incoming DMA requests may use multiple descriptors,
773 * due to exceeding xfercap, perhaps. If so, only the
774 * last one will have a cookie, and require unmapping.
776 dump_desc_dbg(ioat, desc);
779 ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
781 tx->callback(tx->callback_param);
786 if (tx->phys != phys_complete) {
788 * a completed entry, but not the last, so clean
789 * up if the client is done with the descriptor
791 if (async_tx_test_ack(tx))
792 list_move_tail(&desc->node, &ioat->free_desc);
797 * last used desc. Do not remove, so we can
798 * append from it, but don't look at it next
803 /* TODO check status bits? */
808 spin_unlock_bh(&ioat->desc_lock);
810 chan->last_completion = phys_complete;
812 chan->completed_cookie = cookie;
814 spin_unlock_bh(&chan->cleanup_lock);
817 static enum dma_status
818 ioat1_dma_is_complete(struct dma_chan *c, dma_cookie_t cookie,
819 dma_cookie_t *done, dma_cookie_t *used)
821 struct ioat_dma_chan *ioat = to_ioat_chan(c);
823 if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
828 return ioat_is_complete(c, cookie, done, used);
831 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
833 struct ioat_chan_common *chan = &ioat->base;
834 struct ioat_desc_sw *desc;
835 struct ioat_dma_descriptor *hw;
837 spin_lock_bh(&ioat->desc_lock);
839 desc = ioat1_dma_get_next_descriptor(ioat);
842 dev_err(to_dev(chan),
843 "Unable to start null desc - get next desc failed\n");
844 spin_unlock_bh(&ioat->desc_lock);
851 hw->ctl_f.int_en = 1;
852 hw->ctl_f.compl_write = 1;
853 /* set size to non-zero value (channel returns error when size is 0) */
854 hw->size = NULL_DESC_BUFFER_SIZE;
857 async_tx_ack(&desc->txd);
859 list_add_tail(&desc->node, &ioat->used_desc);
860 dump_desc_dbg(ioat, desc);
862 writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
863 chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
864 writel(((u64) desc->txd.phys) >> 32,
865 chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
867 writeb(IOAT_CHANCMD_START, chan->reg_base
868 + IOAT_CHANCMD_OFFSET(chan->device->version));
869 spin_unlock_bh(&ioat->desc_lock);
873 * Perform a IOAT transaction to verify the HW works.
875 #define IOAT_TEST_SIZE 2000
877 static void ioat_dma_test_callback(void *dma_async_param)
879 struct completion *cmp = dma_async_param;
885 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
886 * @device: device to be tested
888 static int ioat_dma_self_test(struct ioatdma_device *device)
893 struct dma_device *dma = &device->common;
894 struct device *dev = &device->pdev->dev;
895 struct dma_chan *dma_chan;
896 struct dma_async_tx_descriptor *tx;
897 dma_addr_t dma_dest, dma_src;
900 struct completion cmp;
904 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
907 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
913 /* Fill in src buffer */
914 for (i = 0; i < IOAT_TEST_SIZE; i++)
917 /* Start copy, using first DMA channel */
918 dma_chan = container_of(dma->channels.next, struct dma_chan,
920 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
921 dev_err(dev, "selftest cannot allocate chan resource\n");
926 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
927 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
928 flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE |
930 tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
931 IOAT_TEST_SIZE, flags);
933 dev_err(dev, "Self-test prep failed, disabling\n");
939 init_completion(&cmp);
940 tx->callback = ioat_dma_test_callback;
941 tx->callback_param = &cmp;
942 cookie = tx->tx_submit(tx);
944 dev_err(dev, "Self-test setup failed, disabling\n");
948 dma->device_issue_pending(dma_chan);
950 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
953 dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL)
955 dev_err(dev, "Self-test copy timed out, disabling\n");
959 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
960 dev_err(dev, "Self-test copy failed compare, disabling\n");
966 dma->device_free_chan_resources(dma_chan);
973 static char ioat_interrupt_style[32] = "msix";
974 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
975 sizeof(ioat_interrupt_style), 0644);
976 MODULE_PARM_DESC(ioat_interrupt_style,
977 "set ioat interrupt style: msix (default), "
978 "msix-single-vector, msi, intx)");
981 * ioat_dma_setup_interrupts - setup interrupt handler
982 * @device: ioat device
984 static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
986 struct ioat_chan_common *chan;
987 struct pci_dev *pdev = device->pdev;
988 struct device *dev = &pdev->dev;
989 struct msix_entry *msix;
994 if (!strcmp(ioat_interrupt_style, "msix"))
996 if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
997 goto msix_single_vector;
998 if (!strcmp(ioat_interrupt_style, "msi"))
1000 if (!strcmp(ioat_interrupt_style, "intx"))
1002 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
1006 /* The number of MSI-X vectors should equal the number of channels */
1007 msixcnt = device->common.chancnt;
1008 for (i = 0; i < msixcnt; i++)
1009 device->msix_entries[i].entry = i;
1011 err = pci_enable_msix(pdev, device->msix_entries, msixcnt);
1015 goto msix_single_vector;
1017 for (i = 0; i < msixcnt; i++) {
1018 msix = &device->msix_entries[i];
1019 chan = ioat_chan_by_index(device, i);
1020 err = devm_request_irq(dev, msix->vector,
1021 ioat_dma_do_interrupt_msix, 0,
1024 for (j = 0; j < i; j++) {
1025 msix = &device->msix_entries[j];
1026 chan = ioat_chan_by_index(device, j);
1027 devm_free_irq(dev, msix->vector, chan);
1029 goto msix_single_vector;
1032 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
1036 msix = &device->msix_entries[0];
1038 err = pci_enable_msix(pdev, device->msix_entries, 1);
1042 err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0,
1043 "ioat-msix", device);
1045 pci_disable_msix(pdev);
1051 err = pci_enable_msi(pdev);
1055 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
1056 "ioat-msi", device);
1058 pci_disable_msi(pdev);
1064 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
1065 IRQF_SHARED, "ioat-intx", device);
1070 if (device->intr_quirk)
1071 device->intr_quirk(device);
1072 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
1073 writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
1077 /* Disable all interrupt generation */
1078 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1079 dev_err(dev, "no usable interrupts\n");
1083 static void ioat_disable_interrupts(struct ioatdma_device *device)
1085 /* Disable all interrupt generation */
1086 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1089 int ioat_probe(struct ioatdma_device *device)
1092 struct dma_device *dma = &device->common;
1093 struct pci_dev *pdev = device->pdev;
1094 struct device *dev = &pdev->dev;
1096 /* DMA coherent memory pool for DMA descriptor allocations */
1097 device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1098 sizeof(struct ioat_dma_descriptor),
1100 if (!device->dma_pool) {
1105 device->completion_pool = pci_pool_create("completion_pool", pdev,
1106 sizeof(u64), SMP_CACHE_BYTES,
1109 if (!device->completion_pool) {
1111 goto err_completion_pool;
1114 device->enumerate_channels(device);
1116 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
1117 dma->dev = &pdev->dev;
1119 dev_err(dev, "Intel(R) I/OAT DMA Engine found,"
1120 " %d channels, device version 0x%02x, driver version %s\n",
1121 dma->chancnt, device->version, IOAT_DMA_VERSION);
1123 if (!dma->chancnt) {
1124 dev_err(dev, "Intel(R) I/OAT DMA Engine problem found: "
1125 "zero channels detected\n");
1126 goto err_setup_interrupts;
1129 err = ioat_dma_setup_interrupts(device);
1131 goto err_setup_interrupts;
1133 err = ioat_dma_self_test(device);
1140 ioat_disable_interrupts(device);
1141 err_setup_interrupts:
1142 pci_pool_destroy(device->completion_pool);
1143 err_completion_pool:
1144 pci_pool_destroy(device->dma_pool);
1149 int ioat_register(struct ioatdma_device *device)
1151 int err = dma_async_device_register(&device->common);
1154 ioat_disable_interrupts(device);
1155 pci_pool_destroy(device->completion_pool);
1156 pci_pool_destroy(device->dma_pool);
1162 /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */
1163 static void ioat1_intr_quirk(struct ioatdma_device *device)
1165 struct pci_dev *pdev = device->pdev;
1168 pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1169 if (pdev->msi_enabled)
1170 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1172 dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN;
1173 pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1176 int ioat1_dma_probe(struct ioatdma_device *device, int dca)
1178 struct pci_dev *pdev = device->pdev;
1179 struct dma_device *dma;
1182 device->intr_quirk = ioat1_intr_quirk;
1183 device->enumerate_channels = ioat1_enumerate_channels;
1184 dma = &device->common;
1185 dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1186 dma->device_issue_pending = ioat1_dma_memcpy_issue_pending;
1187 dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources;
1188 dma->device_free_chan_resources = ioat1_dma_free_chan_resources;
1189 dma->device_is_tx_complete = ioat1_dma_is_complete;
1191 err = ioat_probe(device);
1194 ioat_set_tcp_copy_break(4096);
1195 err = ioat_register(device);
1199 device->dca = ioat_dca_init(pdev, device->reg_base);
1201 INIT_DELAYED_WORK(&device->work, ioat1_chan_watchdog);
1202 schedule_delayed_work(&device->work, WATCHDOG_DELAY);
1207 void ioat_dma_remove(struct ioatdma_device *device)
1209 struct dma_device *dma = &device->common;
1211 if (device->version != IOAT_VER_3_0)
1212 cancel_delayed_work(&device->work);
1214 ioat_disable_interrupts(device);
1216 dma_async_device_unregister(dma);
1218 pci_pool_destroy(device->dma_pool);
1219 pci_pool_destroy(device->completion_pool);
1221 INIT_LIST_HEAD(&dma->channels);