2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
23 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/interrupt.h>
31 #include <linux/dmaengine.h>
32 #include <linux/delay.h>
33 #include <linux/dma-mapping.h>
35 #include "ioatdma_registers.h"
36 #include "ioatdma_hw.h"
38 #define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common)
39 #define to_ioat_device(dev) container_of(dev, struct ioat_device, common)
40 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
42 /* internal functions */
43 static int __devinit ioat_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
44 static void __devexit ioat_remove(struct pci_dev *pdev);
46 static int enumerate_dma_channels(struct ioat_device *device)
51 struct ioat_dma_chan *ioat_chan;
53 device->common.chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
54 xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
55 xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
57 for (i = 0; i < device->common.chancnt; i++) {
58 ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL);
60 device->common.chancnt = i;
64 ioat_chan->device = device;
65 ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1));
66 ioat_chan->xfercap = xfercap;
67 spin_lock_init(&ioat_chan->cleanup_lock);
68 spin_lock_init(&ioat_chan->desc_lock);
69 INIT_LIST_HEAD(&ioat_chan->free_desc);
70 INIT_LIST_HEAD(&ioat_chan->used_desc);
71 /* This should be made common somewhere in dmaengine.c */
72 ioat_chan->common.device = &device->common;
73 ioat_chan->common.client = NULL;
74 list_add_tail(&ioat_chan->common.device_node,
75 &device->common.channels);
77 return device->common.chancnt;
80 static struct ioat_desc_sw *ioat_dma_alloc_descriptor(
81 struct ioat_dma_chan *ioat_chan,
84 struct ioat_dma_descriptor *desc;
85 struct ioat_desc_sw *desc_sw;
86 struct ioat_device *ioat_device;
89 ioat_device = to_ioat_device(ioat_chan->common.device);
90 desc = pci_pool_alloc(ioat_device->dma_pool, flags, &phys);
94 desc_sw = kzalloc(sizeof(*desc_sw), flags);
95 if (unlikely(!desc_sw)) {
96 pci_pool_free(ioat_device->dma_pool, desc, phys);
100 memset(desc, 0, sizeof(*desc));
102 desc_sw->phys = phys;
107 #define INITIAL_IOAT_DESC_COUNT 128
109 static void ioat_start_null_desc(struct ioat_dma_chan *ioat_chan);
111 /* returns the actual number of allocated descriptors */
112 static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
114 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
115 struct ioat_desc_sw *desc = NULL;
122 * In-use bit automatically set by reading chanctrl
123 * If 0, we got it, if 1, someone else did
125 chanctrl = readw(ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
126 if (chanctrl & IOAT_CHANCTRL_CHANNEL_IN_USE)
129 /* Setup register to interrupt and write completion status on error */
130 chanctrl = IOAT_CHANCTRL_CHANNEL_IN_USE |
131 IOAT_CHANCTRL_ERR_INT_EN |
132 IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
133 IOAT_CHANCTRL_ERR_COMPLETION_EN;
134 writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
136 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
138 printk("IOAT: CHANERR = %x, clearing\n", chanerr);
139 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
142 /* Allocate descriptors */
143 for (i = 0; i < INITIAL_IOAT_DESC_COUNT; i++) {
144 desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL);
146 printk(KERN_ERR "IOAT: Only %d initial descriptors\n", i);
149 list_add_tail(&desc->node, &tmp_list);
151 spin_lock_bh(&ioat_chan->desc_lock);
152 list_splice(&tmp_list, &ioat_chan->free_desc);
153 spin_unlock_bh(&ioat_chan->desc_lock);
155 /* allocate a completion writeback area */
156 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
157 ioat_chan->completion_virt =
158 pci_pool_alloc(ioat_chan->device->completion_pool,
160 &ioat_chan->completion_addr);
161 memset(ioat_chan->completion_virt, 0,
162 sizeof(*ioat_chan->completion_virt));
163 writel(((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF,
164 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
165 writel(((u64) ioat_chan->completion_addr) >> 32,
166 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
168 ioat_start_null_desc(ioat_chan);
172 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan);
174 static void ioat_dma_free_chan_resources(struct dma_chan *chan)
176 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
177 struct ioat_device *ioat_device = to_ioat_device(chan->device);
178 struct ioat_desc_sw *desc, *_desc;
180 int in_use_descs = 0;
182 ioat_dma_memcpy_cleanup(ioat_chan);
184 writeb(IOAT_CHANCMD_RESET, ioat_chan->reg_base + IOAT_CHANCMD_OFFSET);
186 spin_lock_bh(&ioat_chan->desc_lock);
187 list_for_each_entry_safe(desc, _desc, &ioat_chan->used_desc, node) {
189 list_del(&desc->node);
190 pci_pool_free(ioat_device->dma_pool, desc->hw, desc->phys);
193 list_for_each_entry_safe(desc, _desc, &ioat_chan->free_desc, node) {
194 list_del(&desc->node);
195 pci_pool_free(ioat_device->dma_pool, desc->hw, desc->phys);
198 spin_unlock_bh(&ioat_chan->desc_lock);
200 pci_pool_free(ioat_device->completion_pool,
201 ioat_chan->completion_virt,
202 ioat_chan->completion_addr);
204 /* one is ok since we left it on there on purpose */
205 if (in_use_descs > 1)
206 printk(KERN_ERR "IOAT: Freeing %d in use descriptors!\n",
209 ioat_chan->last_completion = ioat_chan->completion_addr = 0;
211 /* Tell hw the chan is free */
212 chanctrl = readw(ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
213 chanctrl &= ~IOAT_CHANCTRL_CHANNEL_IN_USE;
214 writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
218 * do_ioat_dma_memcpy - actual function that initiates a IOAT DMA transaction
219 * @ioat_chan: IOAT DMA channel handle
220 * @dest: DMA destination address
221 * @src: DMA source address
222 * @len: transaction length in bytes
225 static dma_cookie_t do_ioat_dma_memcpy(struct ioat_dma_chan *ioat_chan,
230 struct ioat_desc_sw *first;
231 struct ioat_desc_sw *prev;
232 struct ioat_desc_sw *new;
234 LIST_HEAD(new_chain);
237 dma_addr_t orig_src, orig_dst;
238 unsigned int desc_count = 0;
239 unsigned int append = 0;
241 if (!ioat_chan || !dest || !src)
245 return ioat_chan->common.cookie;
254 spin_lock_bh(&ioat_chan->desc_lock);
257 if (!list_empty(&ioat_chan->free_desc)) {
258 new = to_ioat_desc(ioat_chan->free_desc.next);
259 list_del(&new->node);
261 /* try to get another desc */
262 new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
263 /* will this ever happen? */
264 /* TODO add upper limit on these */
268 copy = min((u32) len, ioat_chan->xfercap);
270 new->hw->size = copy;
272 new->hw->src_addr = src;
273 new->hw->dst_addr = dest;
276 /* chain together the physical address list for the HW */
280 prev->hw->next = (u64) new->phys;
288 list_add_tail(&new->node, &new_chain);
291 new->hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
294 /* cookie incr and addition to used_list must be atomic */
296 cookie = ioat_chan->common.cookie;
300 ioat_chan->common.cookie = new->cookie = cookie;
302 pci_unmap_addr_set(new, src, orig_src);
303 pci_unmap_addr_set(new, dst, orig_dst);
304 pci_unmap_len_set(new, src_len, orig_len);
305 pci_unmap_len_set(new, dst_len, orig_len);
307 /* write address into NextDescriptor field of last desc in chain */
308 to_ioat_desc(ioat_chan->used_desc.prev)->hw->next = first->phys;
309 list_splice_init(&new_chain, ioat_chan->used_desc.prev);
311 ioat_chan->pending += desc_count;
312 if (ioat_chan->pending >= 4) {
314 ioat_chan->pending = 0;
317 spin_unlock_bh(&ioat_chan->desc_lock);
320 writeb(IOAT_CHANCMD_APPEND,
321 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET);
326 * ioat_dma_memcpy_buf_to_buf - wrapper that takes src & dest bufs
327 * @chan: IOAT DMA channel handle
328 * @dest: DMA destination address
329 * @src: DMA source address
330 * @len: transaction length in bytes
333 static dma_cookie_t ioat_dma_memcpy_buf_to_buf(struct dma_chan *chan,
338 dma_addr_t dest_addr;
340 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
342 dest_addr = pci_map_single(ioat_chan->device->pdev,
343 dest, len, PCI_DMA_FROMDEVICE);
344 src_addr = pci_map_single(ioat_chan->device->pdev,
345 src, len, PCI_DMA_TODEVICE);
347 return do_ioat_dma_memcpy(ioat_chan, dest_addr, src_addr, len);
351 * ioat_dma_memcpy_buf_to_pg - wrapper, copying from a buf to a page
352 * @chan: IOAT DMA channel handle
353 * @page: pointer to the page to copy to
354 * @offset: offset into that page
355 * @src: DMA source address
356 * @len: transaction length in bytes
359 static dma_cookie_t ioat_dma_memcpy_buf_to_pg(struct dma_chan *chan,
365 dma_addr_t dest_addr;
367 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
369 dest_addr = pci_map_page(ioat_chan->device->pdev,
370 page, offset, len, PCI_DMA_FROMDEVICE);
371 src_addr = pci_map_single(ioat_chan->device->pdev,
372 src, len, PCI_DMA_TODEVICE);
374 return do_ioat_dma_memcpy(ioat_chan, dest_addr, src_addr, len);
378 * ioat_dma_memcpy_pg_to_pg - wrapper, copying between two pages
379 * @chan: IOAT DMA channel handle
380 * @dest_pg: pointer to the page to copy to
381 * @dest_off: offset into that page
382 * @src_pg: pointer to the page to copy from
383 * @src_off: offset into that page
384 * @len: transaction length in bytes. This is guaranteed not to make a copy
385 * across a page boundary.
388 static dma_cookie_t ioat_dma_memcpy_pg_to_pg(struct dma_chan *chan,
389 struct page *dest_pg,
390 unsigned int dest_off,
392 unsigned int src_off,
395 dma_addr_t dest_addr;
397 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
399 dest_addr = pci_map_page(ioat_chan->device->pdev,
400 dest_pg, dest_off, len, PCI_DMA_FROMDEVICE);
401 src_addr = pci_map_page(ioat_chan->device->pdev,
402 src_pg, src_off, len, PCI_DMA_TODEVICE);
404 return do_ioat_dma_memcpy(ioat_chan, dest_addr, src_addr, len);
408 * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended descriptors to hw
409 * @chan: DMA channel handle
412 static void ioat_dma_memcpy_issue_pending(struct dma_chan *chan)
414 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
416 if (ioat_chan->pending != 0) {
417 ioat_chan->pending = 0;
418 writeb(IOAT_CHANCMD_APPEND,
419 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET);
423 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *chan)
425 unsigned long phys_complete;
426 struct ioat_desc_sw *desc, *_desc;
427 dma_cookie_t cookie = 0;
429 prefetch(chan->completion_virt);
431 if (!spin_trylock(&chan->cleanup_lock))
434 /* The completion writeback can happen at any time,
435 so reads by the driver need to be atomic operations
436 The descriptor physical addresses are limited to 32-bits
437 when the CPU can only do a 32-bit mov */
439 #if (BITS_PER_LONG == 64)
441 chan->completion_virt->full & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
443 phys_complete = chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK;
446 if ((chan->completion_virt->full & IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
447 IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
448 printk("IOAT: Channel halted, chanerr = %x\n",
449 readl(chan->reg_base + IOAT_CHANERR_OFFSET));
451 /* TODO do something to salvage the situation */
454 if (phys_complete == chan->last_completion) {
455 spin_unlock(&chan->cleanup_lock);
459 spin_lock_bh(&chan->desc_lock);
460 list_for_each_entry_safe(desc, _desc, &chan->used_desc, node) {
463 * Incoming DMA requests may use multiple descriptors, due to
464 * exceeding xfercap, perhaps. If so, only the last one will
465 * have a cookie, and require unmapping.
468 cookie = desc->cookie;
470 /* yes we are unmapping both _page and _single alloc'd
471 regions with unmap_page. Is this *really* that bad?
473 pci_unmap_page(chan->device->pdev,
474 pci_unmap_addr(desc, dst),
475 pci_unmap_len(desc, dst_len),
477 pci_unmap_page(chan->device->pdev,
478 pci_unmap_addr(desc, src),
479 pci_unmap_len(desc, src_len),
483 if (desc->phys != phys_complete) {
484 /* a completed entry, but not the last, so cleanup */
485 list_del(&desc->node);
486 list_add_tail(&desc->node, &chan->free_desc);
488 /* last used desc. Do not remove, so we can append from
489 it, but don't look at it next time, either */
492 /* TODO check status bits? */
497 spin_unlock_bh(&chan->desc_lock);
499 chan->last_completion = phys_complete;
501 chan->completed_cookie = cookie;
503 spin_unlock(&chan->cleanup_lock);
507 * ioat_dma_is_complete - poll the status of a IOAT DMA transaction
508 * @chan: IOAT DMA channel handle
509 * @cookie: DMA transaction identifier
510 * @done: if not %NULL, updated with last completed transaction
511 * @used: if not %NULL, updated with last used transaction
514 static enum dma_status ioat_dma_is_complete(struct dma_chan *chan,
519 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
520 dma_cookie_t last_used;
521 dma_cookie_t last_complete;
524 last_used = chan->cookie;
525 last_complete = ioat_chan->completed_cookie;
528 *done= last_complete;
532 ret = dma_async_is_complete(cookie, last_complete, last_used);
533 if (ret == DMA_SUCCESS)
536 ioat_dma_memcpy_cleanup(ioat_chan);
538 last_used = chan->cookie;
539 last_complete = ioat_chan->completed_cookie;
542 *done= last_complete;
546 return dma_async_is_complete(cookie, last_complete, last_used);
551 static struct pci_device_id ioat_pci_tbl[] = {
552 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT) },
556 static struct pci_driver ioat_pci_driver = {
558 .id_table = ioat_pci_tbl,
560 .remove = __devexit_p(ioat_remove),
563 static irqreturn_t ioat_do_interrupt(int irq, void *data)
565 struct ioat_device *instance = data;
566 unsigned long attnstatus;
569 intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
571 if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
574 if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
575 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
579 attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
581 printk(KERN_ERR "ioatdma error: interrupt! status %lx\n", attnstatus);
583 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
587 static void ioat_start_null_desc(struct ioat_dma_chan *ioat_chan)
589 struct ioat_desc_sw *desc;
591 spin_lock_bh(&ioat_chan->desc_lock);
593 if (!list_empty(&ioat_chan->free_desc)) {
594 desc = to_ioat_desc(ioat_chan->free_desc.next);
595 list_del(&desc->node);
597 /* try to get another desc */
598 spin_unlock_bh(&ioat_chan->desc_lock);
599 desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL);
600 spin_lock_bh(&ioat_chan->desc_lock);
601 /* will this ever happen? */
605 desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL;
608 list_add_tail(&desc->node, &ioat_chan->used_desc);
609 spin_unlock_bh(&ioat_chan->desc_lock);
611 #if (BITS_PER_LONG == 64)
612 writeq(desc->phys, ioat_chan->reg_base + IOAT_CHAINADDR_OFFSET);
614 writel((u32) desc->phys,
615 ioat_chan->reg_base + IOAT_CHAINADDR_OFFSET_LOW);
616 writel(0, ioat_chan->reg_base + IOAT_CHAINADDR_OFFSET_HIGH);
618 writeb(IOAT_CHANCMD_START, ioat_chan->reg_base + IOAT_CHANCMD_OFFSET);
622 * Perform a IOAT transaction to verify the HW works.
624 #define IOAT_TEST_SIZE 2000
626 static int ioat_self_test(struct ioat_device *device)
631 struct dma_chan *dma_chan;
635 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
638 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
644 /* Fill in src buffer */
645 for (i = 0; i < IOAT_TEST_SIZE; i++)
648 /* Start copy, using first DMA channel */
649 dma_chan = container_of(device->common.channels.next,
652 if (ioat_dma_alloc_chan_resources(dma_chan) < 1) {
657 cookie = ioat_dma_memcpy_buf_to_buf(dma_chan, dest, src, IOAT_TEST_SIZE);
658 ioat_dma_memcpy_issue_pending(dma_chan);
661 if (ioat_dma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
662 printk(KERN_ERR "ioatdma: Self-test copy timed out, disabling\n");
666 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
667 printk(KERN_ERR "ioatdma: Self-test copy failed compare, disabling\n");
673 ioat_dma_free_chan_resources(dma_chan);
680 static int __devinit ioat_probe(struct pci_dev *pdev,
681 const struct pci_device_id *ent)
684 unsigned long mmio_start, mmio_len;
685 void __iomem *reg_base;
686 struct ioat_device *device;
688 err = pci_enable_device(pdev);
690 goto err_enable_device;
692 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
694 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
696 goto err_set_dma_mask;
698 err = pci_request_regions(pdev, ioat_pci_driver.name);
700 goto err_request_regions;
702 mmio_start = pci_resource_start(pdev, 0);
703 mmio_len = pci_resource_len(pdev, 0);
705 reg_base = ioremap(mmio_start, mmio_len);
711 device = kzalloc(sizeof(*device), GFP_KERNEL);
717 /* DMA coherent memory pool for DMA descriptor allocations */
718 device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
719 sizeof(struct ioat_dma_descriptor), 64, 0);
720 if (!device->dma_pool) {
725 device->completion_pool = pci_pool_create("completion_pool", pdev, sizeof(u64), SMP_CACHE_BYTES, SMP_CACHE_BYTES);
726 if (!device->completion_pool) {
728 goto err_completion_pool;
732 pci_set_drvdata(pdev, device);
733 #ifdef CONFIG_PCI_MSI
734 if (pci_enable_msi(pdev) == 0) {
740 err = request_irq(pdev->irq, &ioat_do_interrupt, IRQF_SHARED, "ioat",
745 device->reg_base = reg_base;
747 writeb(IOAT_INTRCTRL_MASTER_INT_EN, device->reg_base + IOAT_INTRCTRL_OFFSET);
748 pci_set_master(pdev);
750 INIT_LIST_HEAD(&device->common.channels);
751 enumerate_dma_channels(device);
753 device->common.device_alloc_chan_resources = ioat_dma_alloc_chan_resources;
754 device->common.device_free_chan_resources = ioat_dma_free_chan_resources;
755 device->common.device_memcpy_buf_to_buf = ioat_dma_memcpy_buf_to_buf;
756 device->common.device_memcpy_buf_to_pg = ioat_dma_memcpy_buf_to_pg;
757 device->common.device_memcpy_pg_to_pg = ioat_dma_memcpy_pg_to_pg;
758 device->common.device_memcpy_complete = ioat_dma_is_complete;
759 device->common.device_memcpy_issue_pending = ioat_dma_memcpy_issue_pending;
760 printk(KERN_INFO "Intel(R) I/OAT DMA Engine found, %d channels\n",
761 device->common.chancnt);
763 err = ioat_self_test(device);
767 dma_async_device_register(&device->common);
773 pci_pool_destroy(device->completion_pool);
775 pci_pool_destroy(device->dma_pool);
781 pci_release_regions(pdev);
784 pci_disable_device(pdev);
789 static void __devexit ioat_remove(struct pci_dev *pdev)
791 struct ioat_device *device;
792 struct dma_chan *chan, *_chan;
793 struct ioat_dma_chan *ioat_chan;
795 device = pci_get_drvdata(pdev);
796 dma_async_device_unregister(&device->common);
798 free_irq(device->pdev->irq, device);
799 #ifdef CONFIG_PCI_MSI
801 pci_disable_msi(device->pdev);
803 pci_pool_destroy(device->dma_pool);
804 pci_pool_destroy(device->completion_pool);
805 iounmap(device->reg_base);
806 pci_release_regions(pdev);
807 pci_disable_device(pdev);
808 list_for_each_entry_safe(chan, _chan, &device->common.channels, device_node) {
809 ioat_chan = to_ioat_chan(chan);
810 list_del(&chan->device_node);
817 MODULE_VERSION("1.9");
818 MODULE_LICENSE("GPL");
819 MODULE_AUTHOR("Intel Corporation");
821 static int __init ioat_init_module(void)
823 /* it's currently unsafe to unload this module */
824 /* if forced, worst case is that rmmod hangs */
825 __unsafe(THIS_MODULE);
827 return pci_register_driver(&ioat_pci_driver);
830 module_init(ioat_init_module);
832 static void __exit ioat_exit_module(void)
834 pci_unregister_driver(&ioat_pci_driver);
837 module_exit(ioat_exit_module);