2 * offload engine driver for the Intel Xscale series of i/o processors
3 * Copyright © 2006, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * This driver supports the asynchrounous DMA copy and RAID engines available
22 * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/spinlock.h>
30 #include <linux/interrupt.h>
31 #include <linux/platform_device.h>
32 #include <linux/memory.h>
33 #include <linux/ioport.h>
34 #include <linux/raid/pq.h>
36 #include <mach/adma.h>
38 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
39 #define to_iop_adma_device(dev) \
40 container_of(dev, struct iop_adma_device, common)
41 #define tx_to_iop_adma_slot(tx) \
42 container_of(tx, struct iop_adma_desc_slot, async_tx)
45 * iop_adma_free_slots - flags descriptor slots for reuse
47 * Caller must hold &iop_chan->lock while calling this function
49 static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
51 int stride = slot->slots_per_op;
54 slot->slots_per_op = 0;
55 slot = list_entry(slot->slot_node.next,
56 struct iop_adma_desc_slot,
62 iop_desc_unmap(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc)
64 struct dma_async_tx_descriptor *tx = &desc->async_tx;
65 struct iop_adma_desc_slot *unmap = desc->group_head;
66 struct device *dev = &iop_chan->device->pdev->dev;
67 u32 len = unmap->unmap_len;
68 enum dma_ctrl_flags flags = tx->flags;
73 src_cnt = unmap->unmap_src_cnt;
74 dest = iop_desc_get_dest_addr(unmap, iop_chan);
75 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
76 enum dma_data_direction dir;
78 if (src_cnt > 1) /* is xor? */
79 dir = DMA_BIDIRECTIONAL;
81 dir = DMA_FROM_DEVICE;
83 dma_unmap_page(dev, dest, len, dir);
86 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
88 addr = iop_desc_get_src_addr(unmap, iop_chan, src_cnt);
91 dma_unmap_page(dev, addr, len, DMA_TO_DEVICE);
94 desc->group_head = NULL;
98 iop_desc_unmap_pq(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc)
100 struct dma_async_tx_descriptor *tx = &desc->async_tx;
101 struct iop_adma_desc_slot *unmap = desc->group_head;
102 struct device *dev = &iop_chan->device->pdev->dev;
103 u32 len = unmap->unmap_len;
104 enum dma_ctrl_flags flags = tx->flags;
105 u32 src_cnt = unmap->unmap_src_cnt;
106 dma_addr_t pdest = iop_desc_get_dest_addr(unmap, iop_chan);
107 dma_addr_t qdest = iop_desc_get_qdest_addr(unmap, iop_chan);
110 if (tx->flags & DMA_PREP_CONTINUE)
113 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP) && !desc->pq_check_result) {
114 dma_unmap_page(dev, pdest, len, DMA_BIDIRECTIONAL);
115 dma_unmap_page(dev, qdest, len, DMA_BIDIRECTIONAL);
118 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
121 for (i = 0; i < src_cnt; i++) {
122 addr = iop_desc_get_src_addr(unmap, iop_chan, i);
123 dma_unmap_page(dev, addr, len, DMA_TO_DEVICE);
125 if (desc->pq_check_result) {
126 dma_unmap_page(dev, pdest, len, DMA_TO_DEVICE);
127 dma_unmap_page(dev, qdest, len, DMA_TO_DEVICE);
131 desc->group_head = NULL;
136 iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
137 struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
139 struct dma_async_tx_descriptor *tx = &desc->async_tx;
141 BUG_ON(tx->cookie < 0);
142 if (tx->cookie > 0) {
146 /* call the callback (must not sleep or submit new
147 * operations to this channel)
150 tx->callback(tx->callback_param);
152 /* unmap dma addresses
153 * (unmap_single vs unmap_page?)
155 if (desc->group_head && desc->unmap_len) {
156 if (iop_desc_is_pq(desc))
157 iop_desc_unmap_pq(iop_chan, desc);
159 iop_desc_unmap(iop_chan, desc);
163 /* run dependent operations */
164 dma_run_dependencies(tx);
170 iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
171 struct iop_adma_chan *iop_chan)
173 /* the client is allowed to attach dependent operations
176 if (!async_tx_test_ack(&desc->async_tx))
179 /* leave the last descriptor in the chain
180 * so we can append to it
182 if (desc->chain_node.next == &iop_chan->chain)
185 dev_dbg(iop_chan->device->common.dev,
186 "\tfree slot: %d slots_per_op: %d\n",
187 desc->idx, desc->slots_per_op);
189 list_del(&desc->chain_node);
190 iop_adma_free_slots(desc);
195 static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
197 struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
198 dma_cookie_t cookie = 0;
199 u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
200 int busy = iop_chan_is_busy(iop_chan);
201 int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
203 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
204 /* free completed slots from the chain starting with
205 * the oldest descriptor
207 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
209 pr_debug("\tcookie: %d slot: %d busy: %d "
210 "this_desc: %#x next_desc: %#x ack: %d\n",
211 iter->async_tx.cookie, iter->idx, busy,
212 iter->async_tx.phys, iop_desc_get_next_desc(iter),
213 async_tx_test_ack(&iter->async_tx));
215 prefetch(&_iter->async_tx);
217 /* do not advance past the current descriptor loaded into the
218 * hardware channel, subsequent descriptors are either in
219 * process or have not been submitted
224 /* stop the search if we reach the current descriptor and the
225 * channel is busy, or if it appears that the current descriptor
226 * needs to be re-read (i.e. has been appended to)
228 if (iter->async_tx.phys == current_desc) {
229 BUG_ON(seen_current++);
230 if (busy || iop_desc_get_next_desc(iter))
234 /* detect the start of a group transaction */
235 if (!slot_cnt && !slots_per_op) {
236 slot_cnt = iter->slot_cnt;
237 slots_per_op = iter->slots_per_op;
238 if (slot_cnt <= slots_per_op) {
245 pr_debug("\tgroup++\n");
248 slot_cnt -= slots_per_op;
251 /* all the members of a group are complete */
252 if (slots_per_op != 0 && slot_cnt == 0) {
253 struct iop_adma_desc_slot *grp_iter, *_grp_iter;
254 int end_of_chain = 0;
255 pr_debug("\tgroup end\n");
257 /* collect the total results */
258 if (grp_start->xor_check_result) {
259 u32 zero_sum_result = 0;
260 slot_cnt = grp_start->slot_cnt;
261 grp_iter = grp_start;
263 list_for_each_entry_from(grp_iter,
264 &iop_chan->chain, chain_node) {
266 iop_desc_get_zero_result(grp_iter);
267 pr_debug("\titer%d result: %d\n",
268 grp_iter->idx, zero_sum_result);
269 slot_cnt -= slots_per_op;
273 pr_debug("\tgrp_start->xor_check_result: %p\n",
274 grp_start->xor_check_result);
275 *grp_start->xor_check_result = zero_sum_result;
278 /* clean up the group */
279 slot_cnt = grp_start->slot_cnt;
280 grp_iter = grp_start;
281 list_for_each_entry_safe_from(grp_iter, _grp_iter,
282 &iop_chan->chain, chain_node) {
283 cookie = iop_adma_run_tx_complete_actions(
284 grp_iter, iop_chan, cookie);
286 slot_cnt -= slots_per_op;
287 end_of_chain = iop_adma_clean_slot(grp_iter,
290 if (slot_cnt == 0 || end_of_chain)
294 /* the group should be complete at this point */
303 } else if (slots_per_op) /* wait for group completion */
306 /* write back zero sum results (single descriptor case) */
307 if (iter->xor_check_result && iter->async_tx.cookie)
308 *iter->xor_check_result =
309 iop_desc_get_zero_result(iter);
311 cookie = iop_adma_run_tx_complete_actions(
312 iter, iop_chan, cookie);
314 if (iop_adma_clean_slot(iter, iop_chan))
319 iop_chan->completed_cookie = cookie;
320 pr_debug("\tcompleted cookie %d\n", cookie);
325 iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
327 spin_lock_bh(&iop_chan->lock);
328 __iop_adma_slot_cleanup(iop_chan);
329 spin_unlock_bh(&iop_chan->lock);
332 static void iop_adma_tasklet(unsigned long data)
334 struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
336 /* lockdep will flag depedency submissions as potentially
337 * recursive locking, this is not the case as a dependency
338 * submission will never recurse a channels submit routine.
339 * There are checks in async_tx.c to prevent this.
341 spin_lock_nested(&iop_chan->lock, SINGLE_DEPTH_NESTING);
342 __iop_adma_slot_cleanup(iop_chan);
343 spin_unlock(&iop_chan->lock);
346 static struct iop_adma_desc_slot *
347 iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
350 struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
352 int slots_found, retry = 0;
354 /* start search from the last allocated descrtiptor
355 * if a contiguous allocation can not be found start searching
356 * from the beginning of the list
361 iter = iop_chan->last_used;
363 iter = list_entry(&iop_chan->all_slots,
364 struct iop_adma_desc_slot,
367 list_for_each_entry_safe_continue(
368 iter, _iter, &iop_chan->all_slots, slot_node) {
370 prefetch(&_iter->async_tx);
371 if (iter->slots_per_op) {
372 /* give up after finding the first busy slot
373 * on the second pass through the list
382 /* start the allocation if the slot is correctly aligned */
383 if (!slots_found++) {
384 if (iop_desc_is_aligned(iter, slots_per_op))
392 if (slots_found == num_slots) {
393 struct iop_adma_desc_slot *alloc_tail = NULL;
394 struct iop_adma_desc_slot *last_used = NULL;
398 dev_dbg(iop_chan->device->common.dev,
399 "allocated slot: %d "
400 "(desc %p phys: %#x) slots_per_op %d\n",
401 iter->idx, iter->hw_desc,
402 iter->async_tx.phys, slots_per_op);
404 /* pre-ack all but the last descriptor */
405 if (num_slots != slots_per_op)
406 async_tx_ack(&iter->async_tx);
408 list_add_tail(&iter->chain_node, &chain);
410 iter->async_tx.cookie = 0;
411 iter->slot_cnt = num_slots;
412 iter->xor_check_result = NULL;
413 for (i = 0; i < slots_per_op; i++) {
414 iter->slots_per_op = slots_per_op - i;
416 iter = list_entry(iter->slot_node.next,
417 struct iop_adma_desc_slot,
420 num_slots -= slots_per_op;
422 alloc_tail->group_head = alloc_start;
423 alloc_tail->async_tx.cookie = -EBUSY;
424 list_splice(&chain, &alloc_tail->tx_list);
425 iop_chan->last_used = last_used;
426 iop_desc_clear_next_desc(alloc_start);
427 iop_desc_clear_next_desc(alloc_tail);
434 /* perform direct reclaim if the allocation fails */
435 __iop_adma_slot_cleanup(iop_chan);
441 iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
442 struct iop_adma_desc_slot *desc)
444 dma_cookie_t cookie = iop_chan->common.cookie;
448 iop_chan->common.cookie = desc->async_tx.cookie = cookie;
452 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
454 dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
457 if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
458 iop_chan->pending = 0;
459 iop_chan_append(iop_chan);
464 iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
466 struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
467 struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
468 struct iop_adma_desc_slot *grp_start, *old_chain_tail;
474 grp_start = sw_desc->group_head;
475 slot_cnt = grp_start->slot_cnt;
476 slots_per_op = grp_start->slots_per_op;
478 spin_lock_bh(&iop_chan->lock);
479 cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
481 old_chain_tail = list_entry(iop_chan->chain.prev,
482 struct iop_adma_desc_slot, chain_node);
483 list_splice_init(&sw_desc->tx_list,
484 &old_chain_tail->chain_node);
486 /* fix up the hardware chain */
487 next_dma = grp_start->async_tx.phys;
488 iop_desc_set_next_desc(old_chain_tail, next_dma);
489 BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */
491 /* check for pre-chained descriptors */
492 iop_paranoia(iop_desc_get_next_desc(sw_desc));
494 /* increment the pending count by the number of slots
495 * memcpy operations have a 1:1 (slot:operation) relation
496 * other operations are heavier and will pop the threshold
499 iop_chan->pending += slot_cnt;
500 iop_adma_check_threshold(iop_chan);
501 spin_unlock_bh(&iop_chan->lock);
503 dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
504 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
509 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
510 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
513 * iop_adma_alloc_chan_resources - returns the number of allocated descriptors
514 * @chan - allocate descriptor resources for this channel
515 * @client - current client requesting the channel be ready for requests
517 * Note: We keep the slots for 1 operation on iop_chan->chain at all times. To
518 * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be
519 * greater than 2x the number slots needed to satisfy a device->max_xor
522 static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
526 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
527 struct iop_adma_desc_slot *slot = NULL;
528 int init = iop_chan->slots_allocated ? 0 : 1;
529 struct iop_adma_platform_data *plat_data =
530 iop_chan->device->pdev->dev.platform_data;
531 int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
533 /* Allocate descriptor slots */
535 idx = iop_chan->slots_allocated;
536 if (idx == num_descs_in_pool)
539 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
541 printk(KERN_INFO "IOP ADMA Channel only initialized"
542 " %d descriptor slots", idx);
545 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
546 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
548 dma_async_tx_descriptor_init(&slot->async_tx, chan);
549 slot->async_tx.tx_submit = iop_adma_tx_submit;
550 INIT_LIST_HEAD(&slot->tx_list);
551 INIT_LIST_HEAD(&slot->chain_node);
552 INIT_LIST_HEAD(&slot->slot_node);
553 hw_desc = (char *) iop_chan->device->dma_desc_pool;
554 slot->async_tx.phys =
555 (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
558 spin_lock_bh(&iop_chan->lock);
559 iop_chan->slots_allocated++;
560 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
561 spin_unlock_bh(&iop_chan->lock);
562 } while (iop_chan->slots_allocated < num_descs_in_pool);
564 if (idx && !iop_chan->last_used)
565 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
566 struct iop_adma_desc_slot,
569 dev_dbg(iop_chan->device->common.dev,
570 "allocated %d descriptor slots last_used: %p\n",
571 iop_chan->slots_allocated, iop_chan->last_used);
573 /* initialize the channel and the chain with a null operation */
575 if (dma_has_cap(DMA_MEMCPY,
576 iop_chan->device->common.cap_mask))
577 iop_chan_start_null_memcpy(iop_chan);
578 else if (dma_has_cap(DMA_XOR,
579 iop_chan->device->common.cap_mask))
580 iop_chan_start_null_xor(iop_chan);
585 return (idx > 0) ? idx : -ENOMEM;
588 static struct dma_async_tx_descriptor *
589 iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
591 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
592 struct iop_adma_desc_slot *sw_desc, *grp_start;
593 int slot_cnt, slots_per_op;
595 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
597 spin_lock_bh(&iop_chan->lock);
598 slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
599 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
601 grp_start = sw_desc->group_head;
602 iop_desc_init_interrupt(grp_start, iop_chan);
603 grp_start->unmap_len = 0;
604 sw_desc->async_tx.flags = flags;
606 spin_unlock_bh(&iop_chan->lock);
608 return sw_desc ? &sw_desc->async_tx : NULL;
611 static struct dma_async_tx_descriptor *
612 iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
613 dma_addr_t dma_src, size_t len, unsigned long flags)
615 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
616 struct iop_adma_desc_slot *sw_desc, *grp_start;
617 int slot_cnt, slots_per_op;
621 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
623 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
626 spin_lock_bh(&iop_chan->lock);
627 slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
628 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
630 grp_start = sw_desc->group_head;
631 iop_desc_init_memcpy(grp_start, flags);
632 iop_desc_set_byte_count(grp_start, iop_chan, len);
633 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
634 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
635 sw_desc->unmap_src_cnt = 1;
636 sw_desc->unmap_len = len;
637 sw_desc->async_tx.flags = flags;
639 spin_unlock_bh(&iop_chan->lock);
641 return sw_desc ? &sw_desc->async_tx : NULL;
644 static struct dma_async_tx_descriptor *
645 iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
646 int value, size_t len, unsigned long flags)
648 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
649 struct iop_adma_desc_slot *sw_desc, *grp_start;
650 int slot_cnt, slots_per_op;
654 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
656 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
659 spin_lock_bh(&iop_chan->lock);
660 slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
661 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
663 grp_start = sw_desc->group_head;
664 iop_desc_init_memset(grp_start, flags);
665 iop_desc_set_byte_count(grp_start, iop_chan, len);
666 iop_desc_set_block_fill_val(grp_start, value);
667 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
668 sw_desc->unmap_src_cnt = 1;
669 sw_desc->unmap_len = len;
670 sw_desc->async_tx.flags = flags;
672 spin_unlock_bh(&iop_chan->lock);
674 return sw_desc ? &sw_desc->async_tx : NULL;
677 static struct dma_async_tx_descriptor *
678 iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
679 dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
682 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
683 struct iop_adma_desc_slot *sw_desc, *grp_start;
684 int slot_cnt, slots_per_op;
688 BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT));
690 dev_dbg(iop_chan->device->common.dev,
691 "%s src_cnt: %d len: %u flags: %lx\n",
692 __func__, src_cnt, len, flags);
694 spin_lock_bh(&iop_chan->lock);
695 slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
696 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
698 grp_start = sw_desc->group_head;
699 iop_desc_init_xor(grp_start, src_cnt, flags);
700 iop_desc_set_byte_count(grp_start, iop_chan, len);
701 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
702 sw_desc->unmap_src_cnt = src_cnt;
703 sw_desc->unmap_len = len;
704 sw_desc->async_tx.flags = flags;
706 iop_desc_set_xor_src_addr(grp_start, src_cnt,
709 spin_unlock_bh(&iop_chan->lock);
711 return sw_desc ? &sw_desc->async_tx : NULL;
714 static struct dma_async_tx_descriptor *
715 iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src,
716 unsigned int src_cnt, size_t len, u32 *result,
719 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
720 struct iop_adma_desc_slot *sw_desc, *grp_start;
721 int slot_cnt, slots_per_op;
726 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
727 __func__, src_cnt, len);
729 spin_lock_bh(&iop_chan->lock);
730 slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
731 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
733 grp_start = sw_desc->group_head;
734 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
735 iop_desc_set_zero_sum_byte_count(grp_start, len);
736 grp_start->xor_check_result = result;
737 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
738 __func__, grp_start->xor_check_result);
739 sw_desc->unmap_src_cnt = src_cnt;
740 sw_desc->unmap_len = len;
741 sw_desc->async_tx.flags = flags;
743 iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
746 spin_unlock_bh(&iop_chan->lock);
748 return sw_desc ? &sw_desc->async_tx : NULL;
751 static struct dma_async_tx_descriptor *
752 iop_adma_prep_dma_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
753 unsigned int src_cnt, const unsigned char *scf, size_t len,
756 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
757 struct iop_adma_desc_slot *sw_desc, *g;
758 int slot_cnt, slots_per_op;
763 BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
765 dev_dbg(iop_chan->device->common.dev,
766 "%s src_cnt: %d len: %u flags: %lx\n",
767 __func__, src_cnt, len, flags);
769 if (dmaf_p_disabled_continue(flags))
770 continue_srcs = 1+src_cnt;
771 else if (dmaf_continue(flags))
772 continue_srcs = 3+src_cnt;
774 continue_srcs = 0+src_cnt;
776 spin_lock_bh(&iop_chan->lock);
777 slot_cnt = iop_chan_pq_slot_count(len, continue_srcs, &slots_per_op);
778 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
782 g = sw_desc->group_head;
783 iop_desc_set_byte_count(g, iop_chan, len);
785 /* even if P is disabled its destination address (bits
786 * [3:0]) must match Q. It is ok if P points to an
787 * invalid address, it won't be written.
789 if (flags & DMA_PREP_PQ_DISABLE_P)
790 dst[0] = dst[1] & 0x7;
792 iop_desc_set_pq_addr(g, dst);
793 sw_desc->unmap_src_cnt = src_cnt;
794 sw_desc->unmap_len = len;
795 sw_desc->async_tx.flags = flags;
796 for (i = 0; i < src_cnt; i++)
797 iop_desc_set_pq_src_addr(g, i, src[i], scf[i]);
799 /* if we are continuing a previous operation factor in
800 * the old p and q values, see the comment for dma_maxpq
801 * in include/linux/dmaengine.h
803 if (dmaf_p_disabled_continue(flags))
804 iop_desc_set_pq_src_addr(g, i++, dst[1], 1);
805 else if (dmaf_continue(flags)) {
806 iop_desc_set_pq_src_addr(g, i++, dst[0], 0);
807 iop_desc_set_pq_src_addr(g, i++, dst[1], 1);
808 iop_desc_set_pq_src_addr(g, i++, dst[1], 0);
810 iop_desc_init_pq(g, i, flags);
812 spin_unlock_bh(&iop_chan->lock);
814 return sw_desc ? &sw_desc->async_tx : NULL;
817 static struct dma_async_tx_descriptor *
818 iop_adma_prep_dma_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
819 unsigned int src_cnt, const unsigned char *scf,
820 size_t len, enum sum_check_flags *pqres,
823 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
824 struct iop_adma_desc_slot *sw_desc, *g;
825 int slot_cnt, slots_per_op;
829 BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
831 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
832 __func__, src_cnt, len);
834 spin_lock_bh(&iop_chan->lock);
835 slot_cnt = iop_chan_pq_zero_sum_slot_count(len, src_cnt + 2, &slots_per_op);
836 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
838 /* for validate operations p and q are tagged onto the
839 * end of the source list
841 int pq_idx = src_cnt;
843 g = sw_desc->group_head;
844 iop_desc_init_pq_zero_sum(g, src_cnt+2, flags);
845 iop_desc_set_pq_zero_sum_byte_count(g, len);
846 g->pq_check_result = pqres;
847 pr_debug("\t%s: g->pq_check_result: %p\n",
848 __func__, g->pq_check_result);
849 sw_desc->unmap_src_cnt = src_cnt+2;
850 sw_desc->unmap_len = len;
851 sw_desc->async_tx.flags = flags;
853 iop_desc_set_pq_zero_sum_src_addr(g, src_cnt,
856 iop_desc_set_pq_zero_sum_addr(g, pq_idx, src);
858 spin_unlock_bh(&iop_chan->lock);
860 return sw_desc ? &sw_desc->async_tx : NULL;
863 static void iop_adma_free_chan_resources(struct dma_chan *chan)
865 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
866 struct iop_adma_desc_slot *iter, *_iter;
867 int in_use_descs = 0;
869 iop_adma_slot_cleanup(iop_chan);
871 spin_lock_bh(&iop_chan->lock);
872 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
875 list_del(&iter->chain_node);
877 list_for_each_entry_safe_reverse(
878 iter, _iter, &iop_chan->all_slots, slot_node) {
879 list_del(&iter->slot_node);
881 iop_chan->slots_allocated--;
883 iop_chan->last_used = NULL;
885 dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
886 __func__, iop_chan->slots_allocated);
887 spin_unlock_bh(&iop_chan->lock);
889 /* one is ok since we left it on there on purpose */
890 if (in_use_descs > 1)
891 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
896 * iop_adma_status - poll the status of an ADMA transaction
897 * @chan: ADMA channel handle
898 * @cookie: ADMA transaction identifier
899 * @txstate: a holder for the current state of the channel or NULL
901 static enum dma_status iop_adma_status(struct dma_chan *chan,
903 struct dma_tx_state *txstate)
905 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
906 dma_cookie_t last_used;
907 dma_cookie_t last_complete;
910 last_used = chan->cookie;
911 last_complete = iop_chan->completed_cookie;
914 txstate->last = last_complete;
915 txstate->used = last_used;
916 txstate->residue = 0;
919 ret = dma_async_is_complete(cookie, last_complete, last_used);
920 if (ret == DMA_SUCCESS)
923 iop_adma_slot_cleanup(iop_chan);
925 last_used = chan->cookie;
926 last_complete = iop_chan->completed_cookie;
929 txstate->last = last_complete;
930 txstate->used = last_used;
931 txstate->residue = 0;
934 return dma_async_is_complete(cookie, last_complete, last_used);
937 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
939 struct iop_adma_chan *chan = data;
941 dev_dbg(chan->device->common.dev, "%s\n", __func__);
943 tasklet_schedule(&chan->irq_tasklet);
945 iop_adma_device_clear_eot_status(chan);
950 static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
952 struct iop_adma_chan *chan = data;
954 dev_dbg(chan->device->common.dev, "%s\n", __func__);
956 tasklet_schedule(&chan->irq_tasklet);
958 iop_adma_device_clear_eoc_status(chan);
963 static irqreturn_t iop_adma_err_handler(int irq, void *data)
965 struct iop_adma_chan *chan = data;
966 unsigned long status = iop_chan_get_status(chan);
968 dev_printk(KERN_ERR, chan->device->common.dev,
969 "error ( %s%s%s%s%s%s%s)\n",
970 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
971 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
972 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
973 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
974 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
975 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
976 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
978 iop_adma_device_clear_err_status(chan);
985 static void iop_adma_issue_pending(struct dma_chan *chan)
987 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
989 if (iop_chan->pending) {
990 iop_chan->pending = 0;
991 iop_chan_append(iop_chan);
996 * Perform a transaction to verify the HW works.
998 #define IOP_ADMA_TEST_SIZE 2000
1000 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
1004 dma_addr_t src_dma, dest_dma;
1005 struct dma_chan *dma_chan;
1006 dma_cookie_t cookie;
1007 struct dma_async_tx_descriptor *tx;
1009 struct iop_adma_chan *iop_chan;
1011 dev_dbg(device->common.dev, "%s\n", __func__);
1013 src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
1016 dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
1022 /* Fill in src buffer */
1023 for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
1024 ((u8 *) src)[i] = (u8)i;
1026 /* Start copy, using first DMA channel */
1027 dma_chan = container_of(device->common.channels.next,
1030 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
1035 dest_dma = dma_map_single(dma_chan->device->dev, dest,
1036 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
1037 src_dma = dma_map_single(dma_chan->device->dev, src,
1038 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
1039 tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
1041 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1043 cookie = iop_adma_tx_submit(tx);
1044 iop_adma_issue_pending(dma_chan);
1047 if (iop_adma_status(dma_chan, cookie, NULL) !=
1049 dev_printk(KERN_ERR, dma_chan->device->dev,
1050 "Self-test copy timed out, disabling\n");
1052 goto free_resources;
1055 iop_chan = to_iop_adma_chan(dma_chan);
1056 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
1057 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
1058 if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
1059 dev_printk(KERN_ERR, dma_chan->device->dev,
1060 "Self-test copy failed compare, disabling\n");
1062 goto free_resources;
1066 iop_adma_free_chan_resources(dma_chan);
1073 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
1074 static int __devinit
1075 iop_adma_xor_val_self_test(struct iop_adma_device *device)
1079 struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
1080 struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
1081 dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
1082 dma_addr_t dma_addr, dest_dma;
1083 struct dma_async_tx_descriptor *tx;
1084 struct dma_chan *dma_chan;
1085 dma_cookie_t cookie;
1088 u32 zero_sum_result;
1090 struct iop_adma_chan *iop_chan;
1092 dev_dbg(device->common.dev, "%s\n", __func__);
1094 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
1095 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
1096 if (!xor_srcs[src_idx]) {
1098 __free_page(xor_srcs[src_idx]);
1103 dest = alloc_page(GFP_KERNEL);
1106 __free_page(xor_srcs[src_idx]);
1110 /* Fill in src buffers */
1111 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
1112 u8 *ptr = page_address(xor_srcs[src_idx]);
1113 for (i = 0; i < PAGE_SIZE; i++)
1114 ptr[i] = (1 << src_idx);
1117 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
1118 cmp_byte ^= (u8) (1 << src_idx);
1120 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
1121 (cmp_byte << 8) | cmp_byte;
1123 memset(page_address(dest), 0, PAGE_SIZE);
1125 dma_chan = container_of(device->common.channels.next,
1128 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
1134 dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
1135 PAGE_SIZE, DMA_FROM_DEVICE);
1136 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1137 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
1138 0, PAGE_SIZE, DMA_TO_DEVICE);
1139 tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
1140 IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
1141 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1143 cookie = iop_adma_tx_submit(tx);
1144 iop_adma_issue_pending(dma_chan);
1147 if (iop_adma_status(dma_chan, cookie, NULL) !=
1149 dev_printk(KERN_ERR, dma_chan->device->dev,
1150 "Self-test xor timed out, disabling\n");
1152 goto free_resources;
1155 iop_chan = to_iop_adma_chan(dma_chan);
1156 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
1157 PAGE_SIZE, DMA_FROM_DEVICE);
1158 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
1159 u32 *ptr = page_address(dest);
1160 if (ptr[i] != cmp_word) {
1161 dev_printk(KERN_ERR, dma_chan->device->dev,
1162 "Self-test xor failed compare, disabling\n");
1164 goto free_resources;
1167 dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
1168 PAGE_SIZE, DMA_TO_DEVICE);
1170 /* skip zero sum if the capability is not present */
1171 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
1172 goto free_resources;
1174 /* zero sum the sources with the destintation page */
1175 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1176 zero_sum_srcs[i] = xor_srcs[i];
1177 zero_sum_srcs[i] = dest;
1179 zero_sum_result = 1;
1181 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1182 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1183 zero_sum_srcs[i], 0, PAGE_SIZE,
1185 tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs,
1186 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1188 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1190 cookie = iop_adma_tx_submit(tx);
1191 iop_adma_issue_pending(dma_chan);
1194 if (iop_adma_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
1195 dev_printk(KERN_ERR, dma_chan->device->dev,
1196 "Self-test zero sum timed out, disabling\n");
1198 goto free_resources;
1201 if (zero_sum_result != 0) {
1202 dev_printk(KERN_ERR, dma_chan->device->dev,
1203 "Self-test zero sum failed compare, disabling\n");
1205 goto free_resources;
1209 dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1210 PAGE_SIZE, DMA_FROM_DEVICE);
1211 tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
1212 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1214 cookie = iop_adma_tx_submit(tx);
1215 iop_adma_issue_pending(dma_chan);
1218 if (iop_adma_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
1219 dev_printk(KERN_ERR, dma_chan->device->dev,
1220 "Self-test memset timed out, disabling\n");
1222 goto free_resources;
1225 for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1226 u32 *ptr = page_address(dest);
1228 dev_printk(KERN_ERR, dma_chan->device->dev,
1229 "Self-test memset failed compare, disabling\n");
1231 goto free_resources;
1235 /* test for non-zero parity sum */
1236 zero_sum_result = 0;
1237 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1238 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1239 zero_sum_srcs[i], 0, PAGE_SIZE,
1241 tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs,
1242 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1244 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1246 cookie = iop_adma_tx_submit(tx);
1247 iop_adma_issue_pending(dma_chan);
1250 if (iop_adma_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
1251 dev_printk(KERN_ERR, dma_chan->device->dev,
1252 "Self-test non-zero sum timed out, disabling\n");
1254 goto free_resources;
1257 if (zero_sum_result != 1) {
1258 dev_printk(KERN_ERR, dma_chan->device->dev,
1259 "Self-test non-zero sum failed compare, disabling\n");
1261 goto free_resources;
1265 iop_adma_free_chan_resources(dma_chan);
1267 src_idx = IOP_ADMA_NUM_SRC_TEST;
1269 __free_page(xor_srcs[src_idx]);
1274 #ifdef CONFIG_MD_RAID6_PQ
1275 static int __devinit
1276 iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device)
1278 /* combined sources, software pq results, and extra hw pq results */
1279 struct page *pq[IOP_ADMA_NUM_SRC_TEST+2+2];
1280 /* ptr to the extra hw pq buffers defined above */
1281 struct page **pq_hw = &pq[IOP_ADMA_NUM_SRC_TEST+2];
1282 /* address conversion buffers (dma_map / page_address) */
1283 void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2];
1284 dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST];
1285 dma_addr_t pq_dest[2];
1288 struct dma_async_tx_descriptor *tx;
1289 struct dma_chan *dma_chan;
1290 dma_cookie_t cookie;
1291 u32 zero_sum_result;
1295 dev_dbg(device->common.dev, "%s\n", __func__);
1297 for (i = 0; i < ARRAY_SIZE(pq); i++) {
1298 pq[i] = alloc_page(GFP_KERNEL);
1306 /* Fill in src buffers */
1307 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) {
1308 pq_sw[i] = page_address(pq[i]);
1309 memset(pq_sw[i], 0x11111111 * (1<<i), PAGE_SIZE);
1311 pq_sw[i] = page_address(pq[i]);
1312 pq_sw[i+1] = page_address(pq[i+1]);
1314 dma_chan = container_of(device->common.channels.next,
1317 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
1322 dev = dma_chan->device->dev;
1324 /* initialize the dests */
1325 memset(page_address(pq_hw[0]), 0 , PAGE_SIZE);
1326 memset(page_address(pq_hw[1]), 0 , PAGE_SIZE);
1329 pq_dest[0] = dma_map_page(dev, pq_hw[0], 0, PAGE_SIZE, DMA_FROM_DEVICE);
1330 pq_dest[1] = dma_map_page(dev, pq_hw[1], 0, PAGE_SIZE, DMA_FROM_DEVICE);
1331 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1332 pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
1335 tx = iop_adma_prep_dma_pq(dma_chan, pq_dest, pq_src,
1336 IOP_ADMA_NUM_SRC_TEST, (u8 *)raid6_gfexp,
1338 DMA_PREP_INTERRUPT |
1341 cookie = iop_adma_tx_submit(tx);
1342 iop_adma_issue_pending(dma_chan);
1345 if (iop_adma_status(dma_chan, cookie, NULL) !=
1347 dev_err(dev, "Self-test pq timed out, disabling\n");
1349 goto free_resources;
1352 raid6_call.gen_syndrome(IOP_ADMA_NUM_SRC_TEST+2, PAGE_SIZE, pq_sw);
1354 if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST],
1355 page_address(pq_hw[0]), PAGE_SIZE) != 0) {
1356 dev_err(dev, "Self-test p failed compare, disabling\n");
1358 goto free_resources;
1360 if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST+1],
1361 page_address(pq_hw[1]), PAGE_SIZE) != 0) {
1362 dev_err(dev, "Self-test q failed compare, disabling\n");
1364 goto free_resources;
1367 /* test correct zero sum using the software generated pq values */
1368 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++)
1369 pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
1372 zero_sum_result = ~0;
1373 tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST],
1374 pq_src, IOP_ADMA_NUM_SRC_TEST,
1375 raid6_gfexp, PAGE_SIZE, &zero_sum_result,
1376 DMA_PREP_INTERRUPT|DMA_CTRL_ACK);
1378 cookie = iop_adma_tx_submit(tx);
1379 iop_adma_issue_pending(dma_chan);
1382 if (iop_adma_status(dma_chan, cookie, NULL) !=
1384 dev_err(dev, "Self-test pq-zero-sum timed out, disabling\n");
1386 goto free_resources;
1389 if (zero_sum_result != 0) {
1390 dev_err(dev, "Self-test pq-zero-sum failed to validate: %x\n",
1393 goto free_resources;
1396 /* test incorrect zero sum */
1397 i = IOP_ADMA_NUM_SRC_TEST;
1398 memset(pq_sw[i] + 100, 0, 100);
1399 memset(pq_sw[i+1] + 200, 0, 200);
1400 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++)
1401 pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
1404 zero_sum_result = 0;
1405 tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST],
1406 pq_src, IOP_ADMA_NUM_SRC_TEST,
1407 raid6_gfexp, PAGE_SIZE, &zero_sum_result,
1408 DMA_PREP_INTERRUPT|DMA_CTRL_ACK);
1410 cookie = iop_adma_tx_submit(tx);
1411 iop_adma_issue_pending(dma_chan);
1414 if (iop_adma_status(dma_chan, cookie, NULL) !=
1416 dev_err(dev, "Self-test !pq-zero-sum timed out, disabling\n");
1418 goto free_resources;
1421 if (zero_sum_result != (SUM_CHECK_P_RESULT | SUM_CHECK_Q_RESULT)) {
1422 dev_err(dev, "Self-test !pq-zero-sum failed to validate: %x\n",
1425 goto free_resources;
1429 iop_adma_free_chan_resources(dma_chan);
1438 static int __devexit iop_adma_remove(struct platform_device *dev)
1440 struct iop_adma_device *device = platform_get_drvdata(dev);
1441 struct dma_chan *chan, *_chan;
1442 struct iop_adma_chan *iop_chan;
1443 struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1445 dma_async_device_unregister(&device->common);
1447 dma_free_coherent(&dev->dev, plat_data->pool_size,
1448 device->dma_desc_pool_virt, device->dma_desc_pool);
1450 list_for_each_entry_safe(chan, _chan, &device->common.channels,
1452 iop_chan = to_iop_adma_chan(chan);
1453 list_del(&chan->device_node);
1461 static int __devinit iop_adma_probe(struct platform_device *pdev)
1463 struct resource *res;
1465 struct iop_adma_device *adev;
1466 struct iop_adma_chan *iop_chan;
1467 struct dma_device *dma_dev;
1468 struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1470 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1474 if (!devm_request_mem_region(&pdev->dev, res->start,
1475 resource_size(res), pdev->name))
1478 adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1481 dma_dev = &adev->common;
1483 /* allocate coherent memory for hardware descriptors
1484 * note: writecombine gives slightly better performance, but
1485 * requires that we explicitly flush the writes
1487 if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1488 plat_data->pool_size,
1489 &adev->dma_desc_pool,
1490 GFP_KERNEL)) == NULL) {
1495 dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
1496 __func__, adev->dma_desc_pool_virt,
1497 (void *) adev->dma_desc_pool);
1499 adev->id = plat_data->hw_id;
1501 /* discover transaction capabilites from the platform data */
1502 dma_dev->cap_mask = plat_data->cap_mask;
1505 platform_set_drvdata(pdev, adev);
1507 INIT_LIST_HEAD(&dma_dev->channels);
1509 /* set base routines */
1510 dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1511 dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1512 dma_dev->device_tx_status = iop_adma_status;
1513 dma_dev->device_issue_pending = iop_adma_issue_pending;
1514 dma_dev->dev = &pdev->dev;
1516 /* set prep routines based on capability */
1517 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1518 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1519 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1520 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1521 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1522 dma_dev->max_xor = iop_adma_get_max_xor();
1523 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1525 if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask))
1526 dma_dev->device_prep_dma_xor_val =
1527 iop_adma_prep_dma_xor_val;
1528 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1529 dma_set_maxpq(dma_dev, iop_adma_get_max_pq(), 0);
1530 dma_dev->device_prep_dma_pq = iop_adma_prep_dma_pq;
1532 if (dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask))
1533 dma_dev->device_prep_dma_pq_val =
1534 iop_adma_prep_dma_pq_val;
1535 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1536 dma_dev->device_prep_dma_interrupt =
1537 iop_adma_prep_dma_interrupt;
1539 iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1544 iop_chan->device = adev;
1546 iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1547 resource_size(res));
1548 if (!iop_chan->mmr_base) {
1550 goto err_free_iop_chan;
1552 tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1555 /* clear errors before enabling interrupts */
1556 iop_adma_device_clear_err_status(iop_chan);
1558 for (i = 0; i < 3; i++) {
1559 irq_handler_t handler[] = { iop_adma_eot_handler,
1560 iop_adma_eoc_handler,
1561 iop_adma_err_handler };
1562 int irq = platform_get_irq(pdev, i);
1565 goto err_free_iop_chan;
1567 ret = devm_request_irq(&pdev->dev, irq,
1568 handler[i], 0, pdev->name, iop_chan);
1570 goto err_free_iop_chan;
1574 spin_lock_init(&iop_chan->lock);
1575 INIT_LIST_HEAD(&iop_chan->chain);
1576 INIT_LIST_HEAD(&iop_chan->all_slots);
1577 iop_chan->common.device = dma_dev;
1578 list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1580 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1581 ret = iop_adma_memcpy_self_test(adev);
1582 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1584 goto err_free_iop_chan;
1587 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1588 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1589 ret = iop_adma_xor_val_self_test(adev);
1590 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1592 goto err_free_iop_chan;
1595 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask) &&
1596 dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) {
1597 #ifdef CONFIG_MD_RAID6_PQ
1598 ret = iop_adma_pq_zero_sum_self_test(adev);
1599 dev_dbg(&pdev->dev, "pq self test returned %d\n", ret);
1601 /* can not test raid6, so do not publish capability */
1602 dma_cap_clear(DMA_PQ, dma_dev->cap_mask);
1603 dma_cap_clear(DMA_PQ_VAL, dma_dev->cap_mask);
1607 goto err_free_iop_chan;
1610 dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1611 "( %s%s%s%s%s%s%s)\n",
1612 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "",
1613 dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "",
1614 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1615 dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask) ? "xor_val " : "",
1616 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "",
1617 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1618 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1620 dma_async_device_register(dma_dev);
1626 dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1627 adev->dma_desc_pool_virt, adev->dma_desc_pool);
1634 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1636 struct iop_adma_desc_slot *sw_desc, *grp_start;
1637 dma_cookie_t cookie;
1638 int slot_cnt, slots_per_op;
1640 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1642 spin_lock_bh(&iop_chan->lock);
1643 slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1644 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1646 grp_start = sw_desc->group_head;
1648 list_splice_init(&sw_desc->tx_list, &iop_chan->chain);
1649 async_tx_ack(&sw_desc->async_tx);
1650 iop_desc_init_memcpy(grp_start, 0);
1651 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1652 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1653 iop_desc_set_memcpy_src_addr(grp_start, 0);
1655 cookie = iop_chan->common.cookie;
1660 /* initialize the completed cookie to be less than
1661 * the most recently used cookie
1663 iop_chan->completed_cookie = cookie - 1;
1664 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1666 /* channel should not be busy */
1667 BUG_ON(iop_chan_is_busy(iop_chan));
1669 /* clear any prior error-status bits */
1670 iop_adma_device_clear_err_status(iop_chan);
1672 /* disable operation */
1673 iop_chan_disable(iop_chan);
1675 /* set the descriptor address */
1676 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1678 /* 1/ don't add pre-chained descriptors
1679 * 2/ dummy read to flush next_desc write
1681 BUG_ON(iop_desc_get_next_desc(sw_desc));
1683 /* run the descriptor */
1684 iop_chan_enable(iop_chan);
1686 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1687 "failed to allocate null descriptor\n");
1688 spin_unlock_bh(&iop_chan->lock);
1691 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1693 struct iop_adma_desc_slot *sw_desc, *grp_start;
1694 dma_cookie_t cookie;
1695 int slot_cnt, slots_per_op;
1697 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1699 spin_lock_bh(&iop_chan->lock);
1700 slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1701 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1703 grp_start = sw_desc->group_head;
1704 list_splice_init(&sw_desc->tx_list, &iop_chan->chain);
1705 async_tx_ack(&sw_desc->async_tx);
1706 iop_desc_init_null_xor(grp_start, 2, 0);
1707 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1708 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1709 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1710 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1712 cookie = iop_chan->common.cookie;
1717 /* initialize the completed cookie to be less than
1718 * the most recently used cookie
1720 iop_chan->completed_cookie = cookie - 1;
1721 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1723 /* channel should not be busy */
1724 BUG_ON(iop_chan_is_busy(iop_chan));
1726 /* clear any prior error-status bits */
1727 iop_adma_device_clear_err_status(iop_chan);
1729 /* disable operation */
1730 iop_chan_disable(iop_chan);
1732 /* set the descriptor address */
1733 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1735 /* 1/ don't add pre-chained descriptors
1736 * 2/ dummy read to flush next_desc write
1738 BUG_ON(iop_desc_get_next_desc(sw_desc));
1740 /* run the descriptor */
1741 iop_chan_enable(iop_chan);
1743 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1744 "failed to allocate null descriptor\n");
1745 spin_unlock_bh(&iop_chan->lock);
1748 MODULE_ALIAS("platform:iop-adma");
1750 static struct platform_driver iop_adma_driver = {
1751 .probe = iop_adma_probe,
1752 .remove = __devexit_p(iop_adma_remove),
1754 .owner = THIS_MODULE,
1759 static int __init iop_adma_init (void)
1761 return platform_driver_register(&iop_adma_driver);
1764 static void __exit iop_adma_exit (void)
1766 platform_driver_unregister(&iop_adma_driver);
1769 module_exit(iop_adma_exit);
1770 module_init(iop_adma_init);
1772 MODULE_AUTHOR("Intel Corporation");
1773 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1774 MODULE_LICENSE("GPL");