3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
5 * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/dma-mapping.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
16 #include <linux/spinlock.h>
17 #include <linux/delay.h>
18 #include <linux/list.h>
19 #include <linux/clk.h>
20 #include <linux/vmalloc.h>
21 #include <linux/string.h>
22 #include <linux/interrupt.h>
27 #include "ipu_intern.h"
29 #define FS_VF_IN_VALID 0x00000002
30 #define FS_ENC_IN_VALID 0x00000001
32 static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
36 * There can be only one, we could allocate it dynamically, but then we'd have
37 * to add an extra parameter to some functions, and use something as ugly as
38 * struct ipu *ipu = to_ipu(to_idmac(ichan->dma_chan.device));
41 static struct ipu ipu_data;
43 #define to_ipu(id) container_of(id, struct ipu, idmac)
45 static u32 __idmac_read_icreg(struct ipu *ipu, unsigned long reg)
47 return __raw_readl(ipu->reg_ic + reg);
50 #define idmac_read_icreg(ipu, reg) __idmac_read_icreg(ipu, reg - IC_CONF)
52 static void __idmac_write_icreg(struct ipu *ipu, u32 value, unsigned long reg)
54 __raw_writel(value, ipu->reg_ic + reg);
57 #define idmac_write_icreg(ipu, v, reg) __idmac_write_icreg(ipu, v, reg - IC_CONF)
59 static u32 idmac_read_ipureg(struct ipu *ipu, unsigned long reg)
61 return __raw_readl(ipu->reg_ipu + reg);
64 static void idmac_write_ipureg(struct ipu *ipu, u32 value, unsigned long reg)
66 __raw_writel(value, ipu->reg_ipu + reg);
69 /*****************************************************************************
70 * IPU / IC common functions
72 static void dump_idmac_reg(struct ipu *ipu)
74 dev_dbg(ipu->dev, "IDMAC_CONF 0x%x, IC_CONF 0x%x, IDMAC_CHA_EN 0x%x, "
75 "IDMAC_CHA_PRI 0x%x, IDMAC_CHA_BUSY 0x%x\n",
76 idmac_read_icreg(ipu, IDMAC_CONF),
77 idmac_read_icreg(ipu, IC_CONF),
78 idmac_read_icreg(ipu, IDMAC_CHA_EN),
79 idmac_read_icreg(ipu, IDMAC_CHA_PRI),
80 idmac_read_icreg(ipu, IDMAC_CHA_BUSY));
81 dev_dbg(ipu->dev, "BUF0_RDY 0x%x, BUF1_RDY 0x%x, CUR_BUF 0x%x, "
82 "DB_MODE 0x%x, TASKS_STAT 0x%x\n",
83 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
84 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
85 idmac_read_ipureg(ipu, IPU_CHA_CUR_BUF),
86 idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL),
87 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
90 static uint32_t bytes_per_pixel(enum pixel_fmt fmt)
93 case IPU_PIX_FMT_GENERIC: /* generic data */
94 case IPU_PIX_FMT_RGB332:
95 case IPU_PIX_FMT_YUV420P:
96 case IPU_PIX_FMT_YUV422P:
99 case IPU_PIX_FMT_RGB565:
100 case IPU_PIX_FMT_YUYV:
101 case IPU_PIX_FMT_UYVY:
103 case IPU_PIX_FMT_BGR24:
104 case IPU_PIX_FMT_RGB24:
106 case IPU_PIX_FMT_GENERIC_32: /* generic data */
107 case IPU_PIX_FMT_BGR32:
108 case IPU_PIX_FMT_RGB32:
109 case IPU_PIX_FMT_ABGR32:
114 /* Enable direct write to memory by the Camera Sensor Interface */
115 static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel)
117 uint32_t ic_conf, mask;
121 mask = IC_CONF_PRPENC_EN;
124 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
129 ic_conf = idmac_read_icreg(ipu, IC_CONF) | mask;
130 idmac_write_icreg(ipu, ic_conf, IC_CONF);
133 /* Called under spin_lock_irqsave(&ipu_data.lock) */
134 static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel)
136 uint32_t ic_conf, mask;
140 mask = IC_CONF_PRPENC_EN;
143 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
148 ic_conf = idmac_read_icreg(ipu, IC_CONF) & ~mask;
149 idmac_write_icreg(ipu, ic_conf, IC_CONF);
152 static uint32_t ipu_channel_status(struct ipu *ipu, enum ipu_channel channel)
154 uint32_t stat = TASK_STAT_IDLE;
155 uint32_t task_stat_reg = idmac_read_ipureg(ipu, IPU_TASKS_STAT);
159 stat = (task_stat_reg & TSTAT_CSI2MEM_MASK) >>
160 TSTAT_CSI2MEM_OFFSET;
171 struct chan_param_mem_planar {
209 } __attribute__ ((packed));
211 struct chan_param_mem_interleaved {
268 } __attribute__ ((packed));
270 union chan_param_mem {
271 struct chan_param_mem_planar pp;
272 struct chan_param_mem_interleaved ip;
275 static void ipu_ch_param_set_plane_offset(union chan_param_mem *params,
276 u32 u_offset, u32 v_offset)
278 params->pp.ubo_l = u_offset & 0x7ff;
279 params->pp.ubo_h = u_offset >> 11;
280 params->pp.vbo_l = v_offset & 0x1ffff;
281 params->pp.vbo_h = v_offset >> 17;
284 static void ipu_ch_param_set_size(union chan_param_mem *params,
285 uint32_t pixel_fmt, uint16_t width,
286 uint16_t height, uint16_t stride)
291 params->pp.fw = width - 1;
292 params->pp.fh_l = height - 1;
293 params->pp.fh_h = (height - 1) >> 8;
294 params->pp.sl = stride - 1;
297 case IPU_PIX_FMT_GENERIC:
298 /*Represents 8-bit Generic data */
302 params->pp.sat = 2; /* SAT = use 32-bit access */
304 case IPU_PIX_FMT_GENERIC_32:
305 /*Represents 32-bit Generic data */
309 params->pp.sat = 2; /* SAT = use 32-bit access */
311 case IPU_PIX_FMT_RGB565:
315 params->ip.sat = 2; /* SAT = 32-bit access */
316 params->ip.ofs0 = 0; /* Red bit offset */
317 params->ip.ofs1 = 5; /* Green bit offset */
318 params->ip.ofs2 = 11; /* Blue bit offset */
319 params->ip.ofs3 = 16; /* Alpha bit offset */
320 params->ip.wid0 = 4; /* Red bit width - 1 */
321 params->ip.wid1 = 5; /* Green bit width - 1 */
322 params->ip.wid2 = 4; /* Blue bit width - 1 */
324 case IPU_PIX_FMT_BGR24:
325 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
328 params->ip.sat = 2; /* SAT = 32-bit access */
329 params->ip.ofs0 = 0; /* Red bit offset */
330 params->ip.ofs1 = 8; /* Green bit offset */
331 params->ip.ofs2 = 16; /* Blue bit offset */
332 params->ip.ofs3 = 24; /* Alpha bit offset */
333 params->ip.wid0 = 7; /* Red bit width - 1 */
334 params->ip.wid1 = 7; /* Green bit width - 1 */
335 params->ip.wid2 = 7; /* Blue bit width - 1 */
337 case IPU_PIX_FMT_RGB24:
338 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
341 params->ip.sat = 2; /* SAT = 32-bit access */
342 params->ip.ofs0 = 16; /* Red bit offset */
343 params->ip.ofs1 = 8; /* Green bit offset */
344 params->ip.ofs2 = 0; /* Blue bit offset */
345 params->ip.ofs3 = 24; /* Alpha bit offset */
346 params->ip.wid0 = 7; /* Red bit width - 1 */
347 params->ip.wid1 = 7; /* Green bit width - 1 */
348 params->ip.wid2 = 7; /* Blue bit width - 1 */
350 case IPU_PIX_FMT_BGRA32:
351 case IPU_PIX_FMT_BGR32:
352 case IPU_PIX_FMT_ABGR32:
356 params->ip.sat = 2; /* SAT = 32-bit access */
357 params->ip.ofs0 = 8; /* Red bit offset */
358 params->ip.ofs1 = 16; /* Green bit offset */
359 params->ip.ofs2 = 24; /* Blue bit offset */
360 params->ip.ofs3 = 0; /* Alpha bit offset */
361 params->ip.wid0 = 7; /* Red bit width - 1 */
362 params->ip.wid1 = 7; /* Green bit width - 1 */
363 params->ip.wid2 = 7; /* Blue bit width - 1 */
364 params->ip.wid3 = 7; /* Alpha bit width - 1 */
366 case IPU_PIX_FMT_RGBA32:
367 case IPU_PIX_FMT_RGB32:
371 params->ip.sat = 2; /* SAT = 32-bit access */
372 params->ip.ofs0 = 24; /* Red bit offset */
373 params->ip.ofs1 = 16; /* Green bit offset */
374 params->ip.ofs2 = 8; /* Blue bit offset */
375 params->ip.ofs3 = 0; /* Alpha bit offset */
376 params->ip.wid0 = 7; /* Red bit width - 1 */
377 params->ip.wid1 = 7; /* Green bit width - 1 */
378 params->ip.wid2 = 7; /* Blue bit width - 1 */
379 params->ip.wid3 = 7; /* Alpha bit width - 1 */
381 case IPU_PIX_FMT_UYVY:
385 params->ip.sat = 2; /* SAT = 32-bit access */
387 case IPU_PIX_FMT_YUV420P2:
388 case IPU_PIX_FMT_YUV420P:
392 params->ip.sat = 2; /* SAT = 32-bit access */
393 u_offset = stride * height;
394 v_offset = u_offset + u_offset / 4;
395 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
397 case IPU_PIX_FMT_YVU422P:
401 params->ip.sat = 2; /* SAT = 32-bit access */
402 v_offset = stride * height;
403 u_offset = v_offset + v_offset / 2;
404 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
406 case IPU_PIX_FMT_YUV422P:
410 params->ip.sat = 2; /* SAT = 32-bit access */
411 u_offset = stride * height;
412 v_offset = u_offset + u_offset / 2;
413 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
416 dev_err(ipu_data.dev,
417 "mx3 ipu: unimplemented pixel format %d\n", pixel_fmt);
424 static void ipu_ch_param_set_burst_size(union chan_param_mem *params,
425 uint16_t burst_pixels)
427 params->pp.npb = burst_pixels - 1;
430 static void ipu_ch_param_set_buffer(union chan_param_mem *params,
431 dma_addr_t buf0, dma_addr_t buf1)
433 params->pp.eba0 = buf0;
434 params->pp.eba1 = buf1;
437 static void ipu_ch_param_set_rotation(union chan_param_mem *params,
438 enum ipu_rotate_mode rotate)
440 params->pp.bam = rotate;
443 static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
446 for (; num_words > 0; num_words--) {
447 dev_dbg(ipu_data.dev,
448 "write param mem - addr = 0x%08X, data = 0x%08X\n",
450 idmac_write_ipureg(&ipu_data, addr, IPU_IMA_ADDR);
451 idmac_write_ipureg(&ipu_data, *data++, IPU_IMA_DATA);
453 if ((addr & 0x7) == 5) {
454 addr &= ~0x7; /* set to word 0 */
455 addr += 8; /* increment to next row */
460 static int calc_resize_coeffs(uint32_t in_size, uint32_t out_size,
461 uint32_t *resize_coeff,
462 uint32_t *downsize_coeff)
465 uint32_t temp_downsize;
467 *resize_coeff = 1 << 13;
468 *downsize_coeff = 1 << 13;
470 /* Cannot downsize more than 8:1 */
471 if (out_size << 3 < in_size)
474 /* compute downsizing coefficient */
477 while (temp_size >= out_size * 2 && temp_downsize < 2) {
481 *downsize_coeff = temp_downsize;
484 * compute resizing coefficient using the following formula:
485 * resize_coeff = M*(SI -1)/(SO - 1)
486 * where M = 2^13, SI - input size, SO - output size
488 *resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
489 if (*resize_coeff >= 16384L) {
490 dev_err(ipu_data.dev, "Warning! Overflow on resize coeff.\n");
491 *resize_coeff = 0x3FFF;
494 dev_dbg(ipu_data.dev, "resizing from %u -> %u pixels, "
495 "downsize=%u, resize=%u.%lu (reg=%u)\n", in_size, out_size,
496 *downsize_coeff, *resize_coeff >= 8192L ? 1 : 0,
497 ((*resize_coeff & 0x1FFF) * 10000L) / 8192L, *resize_coeff);
502 static enum ipu_color_space format_to_colorspace(enum pixel_fmt fmt)
505 case IPU_PIX_FMT_RGB565:
506 case IPU_PIX_FMT_BGR24:
507 case IPU_PIX_FMT_RGB24:
508 case IPU_PIX_FMT_BGR32:
509 case IPU_PIX_FMT_RGB32:
510 return IPU_COLORSPACE_RGB;
512 return IPU_COLORSPACE_YCBCR;
516 static int ipu_ic_init_prpenc(struct ipu *ipu,
517 union ipu_channel_param *params, bool src_is_csi)
519 uint32_t reg, ic_conf;
520 uint32_t downsize_coeff, resize_coeff;
521 enum ipu_color_space in_fmt, out_fmt;
523 /* Setup vertical resizing */
524 calc_resize_coeffs(params->video.in_height,
525 params->video.out_height,
526 &resize_coeff, &downsize_coeff);
527 reg = (downsize_coeff << 30) | (resize_coeff << 16);
529 /* Setup horizontal resizing */
530 calc_resize_coeffs(params->video.in_width,
531 params->video.out_width,
532 &resize_coeff, &downsize_coeff);
533 reg |= (downsize_coeff << 14) | resize_coeff;
535 /* Setup color space conversion */
536 in_fmt = format_to_colorspace(params->video.in_pixel_fmt);
537 out_fmt = format_to_colorspace(params->video.out_pixel_fmt);
540 * Colourspace conversion unsupported yet - see _init_csc() in
543 if (in_fmt != out_fmt) {
544 dev_err(ipu->dev, "Colourspace conversion unsupported!\n");
548 idmac_write_icreg(ipu, reg, IC_PRP_ENC_RSC);
550 ic_conf = idmac_read_icreg(ipu, IC_CONF);
553 ic_conf &= ~IC_CONF_RWS_EN;
555 ic_conf |= IC_CONF_RWS_EN;
557 idmac_write_icreg(ipu, ic_conf, IC_CONF);
562 static uint32_t dma_param_addr(uint32_t dma_ch)
564 /* Channel Parameter Memory */
565 return 0x10000 | (dma_ch << 4);
568 static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel,
571 u32 reg = idmac_read_icreg(ipu, IDMAC_CHA_PRI);
574 reg |= 1UL << channel;
576 reg &= ~(1UL << channel);
578 idmac_write_icreg(ipu, reg, IDMAC_CHA_PRI);
583 static uint32_t ipu_channel_conf_mask(enum ipu_channel channel)
590 mask = IPU_CONF_CSI_EN | IPU_CONF_IC_EN;
594 mask = IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
605 * ipu_enable_channel() - enable an IPU channel.
606 * @idmac: IPU DMAC context.
607 * @ichan: IDMAC channel.
608 * @return: 0 on success or negative error code on failure.
610 static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan)
612 struct ipu *ipu = to_ipu(idmac);
613 enum ipu_channel channel = ichan->dma_chan.chan_id;
617 spin_lock_irqsave(&ipu->lock, flags);
619 /* Reset to buffer 0 */
620 idmac_write_ipureg(ipu, 1UL << channel, IPU_CHA_CUR_BUF);
621 ichan->active_buffer = 0;
622 ichan->status = IPU_CHANNEL_ENABLED;
628 ipu_channel_set_priority(ipu, channel, true);
633 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
635 idmac_write_icreg(ipu, reg | (1UL << channel), IDMAC_CHA_EN);
637 ipu_ic_enable_task(ipu, channel);
639 spin_unlock_irqrestore(&ipu->lock, flags);
644 * ipu_init_channel_buffer() - initialize a buffer for logical IPU channel.
645 * @ichan: IDMAC channel.
646 * @pixel_fmt: pixel format of buffer. Pixel format is a FOURCC ASCII code.
647 * @width: width of buffer in pixels.
648 * @height: height of buffer in pixels.
649 * @stride: stride length of buffer in pixels.
650 * @rot_mode: rotation mode of buffer. A rotation setting other than
651 * IPU_ROTATE_VERT_FLIP should only be used for input buffers of
653 * @phyaddr_0: buffer 0 physical address.
654 * @phyaddr_1: buffer 1 physical address. Setting this to a value other than
655 * NULL enables double buffering mode.
656 * @return: 0 on success or negative error code on failure.
658 static int ipu_init_channel_buffer(struct idmac_channel *ichan,
659 enum pixel_fmt pixel_fmt,
660 uint16_t width, uint16_t height,
662 enum ipu_rotate_mode rot_mode,
663 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1)
665 enum ipu_channel channel = ichan->dma_chan.chan_id;
666 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
667 struct ipu *ipu = to_ipu(idmac);
668 union chan_param_mem params = {};
671 uint32_t stride_bytes;
673 stride_bytes = stride * bytes_per_pixel(pixel_fmt);
675 if (stride_bytes % 4) {
677 "Stride length must be 32-bit aligned, stride = %d, bytes = %d\n",
678 stride, stride_bytes);
682 /* IC channel's stride must be a multiple of 8 pixels */
683 if ((channel <= IDMAC_IC_13) && (stride % 8)) {
684 dev_err(ipu->dev, "Stride must be 8 pixel multiple\n");
688 /* Build parameter memory data for DMA channel */
689 ipu_ch_param_set_size(¶ms, pixel_fmt, width, height, stride_bytes);
690 ipu_ch_param_set_buffer(¶ms, phyaddr_0, phyaddr_1);
691 ipu_ch_param_set_rotation(¶ms, rot_mode);
692 /* Some channels (rotation) have restriction on burst length */
694 case IDMAC_IC_7: /* Hangs with burst 8, 16, other values
695 invalid - Table 44-30 */
697 ipu_ch_param_set_burst_size(¶ms, 8);
702 /* In original code only IPU_PIX_FMT_RGB565 was setting burst */
703 ipu_ch_param_set_burst_size(¶ms, 16);
710 spin_lock_irqsave(&ipu->lock, flags);
712 ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10);
714 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
717 reg |= 1UL << channel;
719 reg &= ~(1UL << channel);
721 idmac_write_ipureg(ipu, reg, IPU_CHA_DB_MODE_SEL);
723 ichan->status = IPU_CHANNEL_READY;
725 spin_unlock_irqrestore(&ipu->lock, flags);
731 * ipu_select_buffer() - mark a channel's buffer as ready.
732 * @channel: channel ID.
733 * @buffer_n: buffer number to mark ready.
735 static void ipu_select_buffer(enum ipu_channel channel, int buffer_n)
737 /* No locking - this is a write-one-to-set register, cleared by IPU */
739 /* Mark buffer 0 as ready. */
740 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF0_RDY);
742 /* Mark buffer 1 as ready. */
743 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF1_RDY);
747 * ipu_update_channel_buffer() - update physical address of a channel buffer.
748 * @ichan: IDMAC channel.
749 * @buffer_n: buffer number to update.
750 * 0 or 1 are the only valid values.
751 * @phyaddr: buffer physical address.
753 /* Called under spin_lock(_irqsave)(&ichan->lock) */
754 static void ipu_update_channel_buffer(struct idmac_channel *ichan,
755 int buffer_n, dma_addr_t phyaddr)
757 enum ipu_channel channel = ichan->dma_chan.chan_id;
761 spin_lock_irqsave(&ipu_data.lock, flags);
764 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
765 if (reg & (1UL << channel)) {
766 ipu_ic_disable_task(&ipu_data, channel);
767 ichan->status = IPU_CHANNEL_READY;
770 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
771 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
772 0x0008UL, IPU_IMA_ADDR);
773 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
775 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
776 if (reg & (1UL << channel)) {
777 ipu_ic_disable_task(&ipu_data, channel);
778 ichan->status = IPU_CHANNEL_READY;
781 /* Check if double-buffering is already enabled */
782 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_DB_MODE_SEL);
784 if (!(reg & (1UL << channel)))
785 idmac_write_ipureg(&ipu_data, reg | (1UL << channel),
786 IPU_CHA_DB_MODE_SEL);
788 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 1) */
789 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
790 0x0009UL, IPU_IMA_ADDR);
791 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
794 spin_unlock_irqrestore(&ipu_data.lock, flags);
797 /* Called under spin_lock_irqsave(&ichan->lock) */
798 static int ipu_submit_buffer(struct idmac_channel *ichan,
799 struct idmac_tx_desc *desc, struct scatterlist *sg, int buf_idx)
801 unsigned int chan_id = ichan->dma_chan.chan_id;
802 struct device *dev = &ichan->dma_chan.dev->device;
804 if (async_tx_test_ack(&desc->txd))
808 * On first invocation this shouldn't be necessary, the call to
809 * ipu_init_channel_buffer() above will set addresses for us, so we
810 * could make it conditional on status >= IPU_CHANNEL_ENABLED, but
811 * doing it again shouldn't hurt either.
813 ipu_update_channel_buffer(ichan, buf_idx, sg_dma_address(sg));
815 ipu_select_buffer(chan_id, buf_idx);
816 dev_dbg(dev, "Updated sg %p on channel 0x%x buffer %d\n",
817 sg, chan_id, buf_idx);
822 /* Called under spin_lock_irqsave(&ichan->lock) */
823 static int ipu_submit_channel_buffers(struct idmac_channel *ichan,
824 struct idmac_tx_desc *desc)
826 struct scatterlist *sg;
829 for (i = 0, sg = desc->sg; i < 2 && sg; i++) {
833 ret = ipu_submit_buffer(ichan, desc, sg, i);
844 static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
846 struct idmac_tx_desc *desc = to_tx_desc(tx);
847 struct idmac_channel *ichan = to_idmac_chan(tx->chan);
848 struct idmac *idmac = to_idmac(tx->chan->device);
849 struct ipu *ipu = to_ipu(idmac);
850 struct device *dev = &ichan->dma_chan.dev->device;
856 if (!list_empty(&desc->list)) {
857 /* The descriptor doesn't belong to client */
858 dev_err(dev, "Descriptor %p not prepared!\n", tx);
862 mutex_lock(&ichan->chan_mutex);
864 async_tx_clear_ack(tx);
866 if (ichan->status < IPU_CHANNEL_READY) {
867 struct idmac_video_param *video = &ichan->params.video;
869 * Initial buffer assignment - the first two sg-entries from
870 * the descriptor will end up in the IDMAC buffers
872 dma_addr_t dma_1 = sg_is_last(desc->sg) ? 0 :
873 sg_dma_address(&desc->sg[1]);
875 WARN_ON(ichan->sg[0] || ichan->sg[1]);
877 cookie = ipu_init_channel_buffer(ichan,
878 video->out_pixel_fmt,
883 sg_dma_address(&desc->sg[0]),
889 dev_dbg(dev, "Submitting sg %p\n", &desc->sg[0]);
891 cookie = ichan->dma_chan.cookie;
896 /* from dmaengine.h: "last cookie value returned to client" */
897 ichan->dma_chan.cookie = cookie;
900 /* ipu->lock can be taken under ichan->lock, but not v.v. */
901 spin_lock_irqsave(&ichan->lock, flags);
903 list_add_tail(&desc->list, &ichan->queue);
904 /* submit_buffers() atomically verifies and fills empty sg slots */
905 ret = ipu_submit_channel_buffers(ichan, desc);
907 spin_unlock_irqrestore(&ichan->lock, flags);
914 if (ichan->status < IPU_CHANNEL_ENABLED) {
915 ret = ipu_enable_channel(idmac, ichan);
926 spin_lock_irqsave(&ichan->lock, flags);
927 list_del_init(&desc->list);
928 spin_unlock_irqrestore(&ichan->lock, flags);
930 ichan->dma_chan.cookie = cookie;
934 mutex_unlock(&ichan->chan_mutex);
939 /* Called with ichan->chan_mutex held */
940 static int idmac_desc_alloc(struct idmac_channel *ichan, int n)
942 struct idmac_tx_desc *desc = vmalloc(n * sizeof(struct idmac_tx_desc));
943 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
948 /* No interrupts, just disable the tasklet for a moment */
949 tasklet_disable(&to_ipu(idmac)->tasklet);
951 ichan->n_tx_desc = n;
953 INIT_LIST_HEAD(&ichan->queue);
954 INIT_LIST_HEAD(&ichan->free_list);
957 struct dma_async_tx_descriptor *txd = &desc->txd;
959 memset(txd, 0, sizeof(*txd));
960 dma_async_tx_descriptor_init(txd, &ichan->dma_chan);
961 txd->tx_submit = idmac_tx_submit;
963 list_add(&desc->list, &ichan->free_list);
968 tasklet_enable(&to_ipu(idmac)->tasklet);
974 * ipu_init_channel() - initialize an IPU channel.
975 * @idmac: IPU DMAC context.
976 * @ichan: pointer to the channel object.
977 * @return 0 on success or negative error code on failure.
979 static int ipu_init_channel(struct idmac *idmac, struct idmac_channel *ichan)
981 union ipu_channel_param *params = &ichan->params;
983 enum ipu_channel channel = ichan->dma_chan.chan_id;
986 struct ipu *ipu = to_ipu(idmac);
987 int ret = 0, n_desc = 0;
989 dev_dbg(ipu->dev, "init channel = %d\n", channel);
991 if (channel != IDMAC_SDC_0 && channel != IDMAC_SDC_1 &&
992 channel != IDMAC_IC_7)
995 spin_lock_irqsave(&ipu->lock, flags);
1000 reg = idmac_read_icreg(ipu, IC_CONF);
1001 idmac_write_icreg(ipu, reg & ~IC_CONF_CSI_MEM_WR_EN, IC_CONF);
1005 reg = idmac_read_ipureg(ipu, IPU_FS_PROC_FLOW);
1006 idmac_write_ipureg(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW);
1007 ret = ipu_ic_init_prpenc(ipu, params, true);
1016 ipu->channel_init_mask |= 1L << channel;
1018 /* Enable IPU sub module */
1019 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) |
1020 ipu_channel_conf_mask(channel);
1021 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1023 spin_unlock_irqrestore(&ipu->lock, flags);
1025 if (n_desc && !ichan->desc)
1026 ret = idmac_desc_alloc(ichan, n_desc);
1028 dump_idmac_reg(ipu);
1034 * ipu_uninit_channel() - uninitialize an IPU channel.
1035 * @idmac: IPU DMAC context.
1036 * @ichan: pointer to the channel object.
1038 static void ipu_uninit_channel(struct idmac *idmac, struct idmac_channel *ichan)
1040 enum ipu_channel channel = ichan->dma_chan.chan_id;
1041 unsigned long flags;
1043 unsigned long chan_mask = 1UL << channel;
1045 struct ipu *ipu = to_ipu(idmac);
1047 spin_lock_irqsave(&ipu->lock, flags);
1049 if (!(ipu->channel_init_mask & chan_mask)) {
1050 dev_err(ipu->dev, "Channel already uninitialized %d\n",
1052 spin_unlock_irqrestore(&ipu->lock, flags);
1056 /* Reset the double buffer */
1057 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
1058 idmac_write_ipureg(ipu, reg & ~chan_mask, IPU_CHA_DB_MODE_SEL);
1060 ichan->sec_chan_en = false;
1064 reg = idmac_read_icreg(ipu, IC_CONF);
1065 idmac_write_icreg(ipu, reg & ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN),
1069 reg = idmac_read_icreg(ipu, IC_CONF);
1070 idmac_write_icreg(ipu, reg & ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1),
1079 ipu->channel_init_mask &= ~(1L << channel);
1081 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) &
1082 ~ipu_channel_conf_mask(channel);
1083 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1085 spin_unlock_irqrestore(&ipu->lock, flags);
1087 ichan->n_tx_desc = 0;
1093 * ipu_disable_channel() - disable an IPU channel.
1094 * @idmac: IPU DMAC context.
1095 * @ichan: channel object pointer.
1096 * @wait_for_stop: flag to set whether to wait for channel end of frame or
1097 * return immediately.
1098 * @return: 0 on success or negative error code on failure.
1100 static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
1103 enum ipu_channel channel = ichan->dma_chan.chan_id;
1104 struct ipu *ipu = to_ipu(idmac);
1106 unsigned long flags;
1107 unsigned long chan_mask = 1UL << channel;
1108 unsigned int timeout;
1110 if (wait_for_stop && channel != IDMAC_SDC_1 && channel != IDMAC_SDC_0) {
1112 /* This waiting always fails. Related to spurious irq problem */
1113 while ((idmac_read_icreg(ipu, IDMAC_CHA_BUSY) & chan_mask) ||
1114 (ipu_channel_status(ipu, channel) == TASK_STAT_ACTIVE)) {
1120 "Warning: timeout waiting for channel %u to "
1121 "stop: buf0_rdy = 0x%08X, buf1_rdy = 0x%08X, "
1122 "busy = 0x%08X, tstat = 0x%08X\n", channel,
1123 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
1124 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
1125 idmac_read_icreg(ipu, IDMAC_CHA_BUSY),
1126 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
1130 dev_dbg(ipu->dev, "timeout = %d * 10ms\n", 40 - timeout);
1132 /* SDC BG and FG must be disabled before DMA is disabled */
1133 if (wait_for_stop && (channel == IDMAC_SDC_0 ||
1134 channel == IDMAC_SDC_1)) {
1136 timeout && !ipu_irq_status(ichan->eof_irq); timeout--)
1140 spin_lock_irqsave(&ipu->lock, flags);
1142 /* Disable IC task */
1143 ipu_ic_disable_task(ipu, channel);
1145 /* Disable DMA channel(s) */
1146 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
1147 idmac_write_icreg(ipu, reg & ~chan_mask, IDMAC_CHA_EN);
1149 spin_unlock_irqrestore(&ipu->lock, flags);
1154 static struct scatterlist *idmac_sg_next(struct idmac_channel *ichan,
1155 struct idmac_tx_desc **desc, struct scatterlist *sg)
1157 struct scatterlist *sgnew = sg ? sg_next(sg) : NULL;
1160 /* next sg-element in this list */
1163 if ((*desc)->list.next == &ichan->queue)
1164 /* No more descriptors on the queue */
1167 /* Fetch next descriptor */
1168 *desc = list_entry((*desc)->list.next, struct idmac_tx_desc, list);
1173 * We have several possibilities here:
1174 * current BUF next BUF
1176 * not last sg next not last sg
1177 * not last sg next last sg
1178 * last sg first sg from next descriptor
1181 * Besides, the descriptor queue might be empty or not. We process all these
1184 static irqreturn_t idmac_interrupt(int irq, void *dev_id)
1186 struct idmac_channel *ichan = dev_id;
1187 struct device *dev = &ichan->dma_chan.dev->device;
1188 unsigned int chan_id = ichan->dma_chan.chan_id;
1189 struct scatterlist **sg, *sgnext, *sgnew = NULL;
1190 /* Next transfer descriptor */
1191 struct idmac_tx_desc *desc, *descnew;
1192 dma_async_tx_callback callback;
1193 void *callback_param;
1195 u32 ready0, ready1, curbuf, err;
1196 unsigned long flags;
1198 /* IDMAC has cleared the respective BUFx_RDY bit, we manage the buffer */
1200 dev_dbg(dev, "IDMAC irq %d, buf %d\n", irq, ichan->active_buffer);
1202 spin_lock_irqsave(&ipu_data.lock, flags);
1204 ready0 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
1205 ready1 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
1206 curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
1207 err = idmac_read_ipureg(&ipu_data, IPU_INT_STAT_4);
1209 if (err & (1 << chan_id)) {
1210 idmac_write_ipureg(&ipu_data, 1 << chan_id, IPU_INT_STAT_4);
1211 spin_unlock_irqrestore(&ipu_data.lock, flags);
1214 * ichan->sg[0] = ichan->sg[1] = NULL;
1215 * you can force channel re-enable on the next tx_submit(), but
1216 * this is dirty - think about descriptors with multiple
1219 dev_warn(dev, "NFB4EOF on channel %d, ready %x, %x, cur %x\n",
1220 chan_id, ready0, ready1, curbuf);
1223 spin_unlock_irqrestore(&ipu_data.lock, flags);
1225 /* Other interrupts do not interfere with this channel */
1226 spin_lock(&ichan->lock);
1227 if (unlikely((ichan->active_buffer && (ready1 >> chan_id) & 1) ||
1228 (!ichan->active_buffer && (ready0 >> chan_id) & 1)
1230 spin_unlock(&ichan->lock);
1232 "IRQ with active buffer still ready on channel %x, "
1233 "active %d, ready %x, %x!\n", chan_id,
1234 ichan->active_buffer, ready0, ready1);
1238 if (unlikely(list_empty(&ichan->queue))) {
1239 ichan->sg[ichan->active_buffer] = NULL;
1240 spin_unlock(&ichan->lock);
1242 "IRQ without queued buffers on channel %x, active %d, "
1243 "ready %x, %x!\n", chan_id,
1244 ichan->active_buffer, ready0, ready1);
1249 * active_buffer is a software flag, it shows which buffer we are
1250 * currently expecting back from the hardware, IDMAC should be
1251 * processing the other buffer already
1253 sg = &ichan->sg[ichan->active_buffer];
1254 sgnext = ichan->sg[!ichan->active_buffer];
1257 spin_unlock(&ichan->lock);
1261 desc = list_entry(ichan->queue.next, struct idmac_tx_desc, list);
1264 dev_dbg(dev, "IDMAC irq %d, dma 0x%08x, next dma 0x%08x, current %d, curbuf 0x%08x\n",
1265 irq, sg_dma_address(*sg), sgnext ? sg_dma_address(sgnext) : 0, ichan->active_buffer, curbuf);
1267 /* Find the descriptor of sgnext */
1268 sgnew = idmac_sg_next(ichan, &descnew, *sg);
1269 if (sgnext != sgnew)
1270 dev_err(dev, "Submitted buffer %p, next buffer %p\n", sgnext, sgnew);
1273 * if sgnext == NULL sg must be the last element in a scatterlist and
1274 * queue must be empty
1276 if (unlikely(!sgnext)) {
1277 if (!WARN_ON(sg_next(*sg)))
1278 dev_dbg(dev, "Underrun on channel %x\n", chan_id);
1279 ichan->sg[!ichan->active_buffer] = sgnew;
1281 if (unlikely(sgnew)) {
1282 ipu_submit_buffer(ichan, descnew, sgnew, !ichan->active_buffer);
1284 spin_lock_irqsave(&ipu_data.lock, flags);
1285 ipu_ic_disable_task(&ipu_data, chan_id);
1286 spin_unlock_irqrestore(&ipu_data.lock, flags);
1287 ichan->status = IPU_CHANNEL_READY;
1288 /* Continue to check for complete descriptor */
1292 /* Calculate and submit the next sg element */
1293 sgnew = idmac_sg_next(ichan, &descnew, sgnew);
1295 if (unlikely(!sg_next(*sg)) || !sgnext) {
1297 * Last element in scatterlist done, remove from the queue,
1298 * _init for debugging
1300 list_del_init(&desc->list);
1306 if (likely(sgnew) &&
1307 ipu_submit_buffer(ichan, descnew, sgnew, ichan->active_buffer) < 0) {
1308 callback = descnew->txd.callback;
1309 callback_param = descnew->txd.callback_param;
1310 list_del_init(&descnew->list);
1311 spin_unlock(&ichan->lock);
1313 callback(callback_param);
1314 spin_lock(&ichan->lock);
1317 /* Flip the active buffer - even if update above failed */
1318 ichan->active_buffer = !ichan->active_buffer;
1320 ichan->completed = desc->txd.cookie;
1322 callback = desc->txd.callback;
1323 callback_param = desc->txd.callback_param;
1325 spin_unlock(&ichan->lock);
1327 if (done && (desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
1328 callback(callback_param);
1333 static void ipu_gc_tasklet(unsigned long arg)
1335 struct ipu *ipu = (struct ipu *)arg;
1338 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1339 struct idmac_channel *ichan = ipu->channel + i;
1340 struct idmac_tx_desc *desc;
1341 unsigned long flags;
1342 struct scatterlist *sg;
1345 for (j = 0; j < ichan->n_tx_desc; j++) {
1346 desc = ichan->desc + j;
1347 spin_lock_irqsave(&ichan->lock, flags);
1348 if (async_tx_test_ack(&desc->txd)) {
1349 list_move(&desc->list, &ichan->free_list);
1350 for_each_sg(desc->sg, sg, desc->sg_len, k) {
1351 if (ichan->sg[0] == sg)
1352 ichan->sg[0] = NULL;
1353 else if (ichan->sg[1] == sg)
1354 ichan->sg[1] = NULL;
1356 async_tx_clear_ack(&desc->txd);
1358 spin_unlock_irqrestore(&ichan->lock, flags);
1363 /* Allocate and initialise a transfer descriptor. */
1364 static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
1365 struct scatterlist *sgl, unsigned int sg_len,
1366 enum dma_data_direction direction, unsigned long tx_flags)
1368 struct idmac_channel *ichan = to_idmac_chan(chan);
1369 struct idmac_tx_desc *desc = NULL;
1370 struct dma_async_tx_descriptor *txd = NULL;
1371 unsigned long flags;
1373 /* We only can handle these three channels so far */
1374 if (chan->chan_id != IDMAC_SDC_0 && chan->chan_id != IDMAC_SDC_1 &&
1375 chan->chan_id != IDMAC_IC_7)
1378 if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) {
1379 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction);
1383 mutex_lock(&ichan->chan_mutex);
1385 spin_lock_irqsave(&ichan->lock, flags);
1386 if (!list_empty(&ichan->free_list)) {
1387 desc = list_entry(ichan->free_list.next,
1388 struct idmac_tx_desc, list);
1390 list_del_init(&desc->list);
1392 desc->sg_len = sg_len;
1395 txd->flags = tx_flags;
1397 spin_unlock_irqrestore(&ichan->lock, flags);
1399 mutex_unlock(&ichan->chan_mutex);
1401 tasklet_schedule(&to_ipu(to_idmac(chan->device))->tasklet);
1406 /* Re-select the current buffer and re-activate the channel */
1407 static void idmac_issue_pending(struct dma_chan *chan)
1409 struct idmac_channel *ichan = to_idmac_chan(chan);
1410 struct idmac *idmac = to_idmac(chan->device);
1411 struct ipu *ipu = to_ipu(idmac);
1412 unsigned long flags;
1414 /* This is not always needed, but doesn't hurt either */
1415 spin_lock_irqsave(&ipu->lock, flags);
1416 ipu_select_buffer(chan->chan_id, ichan->active_buffer);
1417 spin_unlock_irqrestore(&ipu->lock, flags);
1420 * Might need to perform some parts of initialisation from
1421 * ipu_enable_channel(), but not all, we do not want to reset to buffer
1422 * 0, don't need to set priority again either, but re-enabling the task
1423 * and the channel might be a good idea.
1427 static int __idmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1430 struct idmac_channel *ichan = to_idmac_chan(chan);
1431 struct idmac *idmac = to_idmac(chan->device);
1432 struct ipu *ipu = to_ipu(idmac);
1433 struct list_head *list, *tmp;
1434 unsigned long flags;
1439 spin_lock_irqsave(&ipu->lock, flags);
1440 ipu_ic_disable_task(ipu, chan->chan_id);
1442 /* Return all descriptors into "prepared" state */
1443 list_for_each_safe(list, tmp, &ichan->queue)
1444 list_del_init(list);
1446 ichan->sg[0] = NULL;
1447 ichan->sg[1] = NULL;
1449 spin_unlock_irqrestore(&ipu->lock, flags);
1451 ichan->status = IPU_CHANNEL_INITIALIZED;
1453 case DMA_TERMINATE_ALL:
1454 ipu_disable_channel(idmac, ichan,
1455 ichan->status >= IPU_CHANNEL_ENABLED);
1457 tasklet_disable(&ipu->tasklet);
1459 /* ichan->queue is modified in ISR, have to spinlock */
1460 spin_lock_irqsave(&ichan->lock, flags);
1461 list_splice_init(&ichan->queue, &ichan->free_list);
1464 for (i = 0; i < ichan->n_tx_desc; i++) {
1465 struct idmac_tx_desc *desc = ichan->desc + i;
1466 if (list_empty(&desc->list))
1467 /* Descriptor was prepared, but not submitted */
1468 list_add(&desc->list, &ichan->free_list);
1470 async_tx_clear_ack(&desc->txd);
1473 ichan->sg[0] = NULL;
1474 ichan->sg[1] = NULL;
1475 spin_unlock_irqrestore(&ichan->lock, flags);
1477 tasklet_enable(&ipu->tasklet);
1479 ichan->status = IPU_CHANNEL_INITIALIZED;
1488 static int idmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1491 struct idmac_channel *ichan = to_idmac_chan(chan);
1494 mutex_lock(&ichan->chan_mutex);
1496 ret = __idmac_control(chan, cmd, arg);
1498 mutex_unlock(&ichan->chan_mutex);
1504 static irqreturn_t ic_sof_irq(int irq, void *dev_id)
1506 struct idmac_channel *ichan = dev_id;
1507 printk(KERN_DEBUG "Got SOF IRQ %d on Channel %d\n",
1508 irq, ichan->dma_chan.chan_id);
1509 disable_irq_nosync(irq);
1513 static irqreturn_t ic_eof_irq(int irq, void *dev_id)
1515 struct idmac_channel *ichan = dev_id;
1516 printk(KERN_DEBUG "Got EOF IRQ %d on Channel %d\n",
1517 irq, ichan->dma_chan.chan_id);
1518 disable_irq_nosync(irq);
1522 static int ic_sof = -EINVAL, ic_eof = -EINVAL;
1525 static int idmac_alloc_chan_resources(struct dma_chan *chan)
1527 struct idmac_channel *ichan = to_idmac_chan(chan);
1528 struct idmac *idmac = to_idmac(chan->device);
1531 /* dmaengine.c now guarantees to only offer free channels */
1532 BUG_ON(chan->client_count > 1);
1533 WARN_ON(ichan->status != IPU_CHANNEL_FREE);
1536 ichan->completed = -ENXIO;
1538 ret = ipu_irq_map(chan->chan_id);
1542 ichan->eof_irq = ret;
1545 * Important to first disable the channel, because maybe someone
1546 * used it before us, e.g., the bootloader
1548 ipu_disable_channel(idmac, ichan, true);
1550 ret = ipu_init_channel(idmac, ichan);
1554 ret = request_irq(ichan->eof_irq, idmac_interrupt, 0,
1555 ichan->eof_name, ichan);
1560 if (chan->chan_id == IDMAC_IC_7) {
1561 ic_sof = ipu_irq_map(69);
1563 request_irq(ic_sof, ic_sof_irq, 0, "IC SOF", ichan);
1564 ic_eof = ipu_irq_map(70);
1566 request_irq(ic_eof, ic_eof_irq, 0, "IC EOF", ichan);
1570 ichan->status = IPU_CHANNEL_INITIALIZED;
1572 dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
1573 chan->chan_id, ichan->eof_irq);
1578 ipu_uninit_channel(idmac, ichan);
1580 ipu_irq_unmap(chan->chan_id);
1585 static void idmac_free_chan_resources(struct dma_chan *chan)
1587 struct idmac_channel *ichan = to_idmac_chan(chan);
1588 struct idmac *idmac = to_idmac(chan->device);
1590 mutex_lock(&ichan->chan_mutex);
1592 __idmac_control(chan, DMA_TERMINATE_ALL, 0);
1594 if (ichan->status > IPU_CHANNEL_FREE) {
1596 if (chan->chan_id == IDMAC_IC_7) {
1598 free_irq(ic_sof, ichan);
1603 free_irq(ic_eof, ichan);
1609 free_irq(ichan->eof_irq, ichan);
1610 ipu_irq_unmap(chan->chan_id);
1613 ichan->status = IPU_CHANNEL_FREE;
1615 ipu_uninit_channel(idmac, ichan);
1617 mutex_unlock(&ichan->chan_mutex);
1619 tasklet_schedule(&to_ipu(idmac)->tasklet);
1622 static enum dma_status idmac_tx_status(struct dma_chan *chan,
1623 dma_cookie_t cookie, struct dma_tx_state *txstate)
1625 struct idmac_channel *ichan = to_idmac_chan(chan);
1627 dma_set_tx_state(txstate, ichan->completed, chan->cookie, 0);
1628 if (cookie != chan->cookie)
1633 static int __init ipu_idmac_init(struct ipu *ipu)
1635 struct idmac *idmac = &ipu->idmac;
1636 struct dma_device *dma = &idmac->dma;
1639 dma_cap_set(DMA_SLAVE, dma->cap_mask);
1640 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1642 /* Compulsory common fields */
1643 dma->dev = ipu->dev;
1644 dma->device_alloc_chan_resources = idmac_alloc_chan_resources;
1645 dma->device_free_chan_resources = idmac_free_chan_resources;
1646 dma->device_tx_status = idmac_tx_status;
1647 dma->device_issue_pending = idmac_issue_pending;
1649 /* Compulsory for DMA_SLAVE fields */
1650 dma->device_prep_slave_sg = idmac_prep_slave_sg;
1651 dma->device_control = idmac_control;
1653 INIT_LIST_HEAD(&dma->channels);
1654 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1655 struct idmac_channel *ichan = ipu->channel + i;
1656 struct dma_chan *dma_chan = &ichan->dma_chan;
1658 spin_lock_init(&ichan->lock);
1659 mutex_init(&ichan->chan_mutex);
1661 ichan->status = IPU_CHANNEL_FREE;
1662 ichan->sec_chan_en = false;
1663 ichan->completed = -ENXIO;
1664 snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
1666 dma_chan->device = &idmac->dma;
1667 dma_chan->cookie = 1;
1668 dma_chan->chan_id = i;
1669 list_add_tail(&dma_chan->device_node, &dma->channels);
1672 idmac_write_icreg(ipu, 0x00000070, IDMAC_CONF);
1674 return dma_async_device_register(&idmac->dma);
1677 static void __exit ipu_idmac_exit(struct ipu *ipu)
1680 struct idmac *idmac = &ipu->idmac;
1682 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1683 struct idmac_channel *ichan = ipu->channel + i;
1685 idmac_control(&ichan->dma_chan, DMA_TERMINATE_ALL, 0);
1688 dma_async_device_unregister(&idmac->dma);
1691 /*****************************************************************************
1692 * IPU common probe / remove
1695 static int __init ipu_probe(struct platform_device *pdev)
1697 struct ipu_platform_data *pdata = pdev->dev.platform_data;
1698 struct resource *mem_ipu, *mem_ic;
1701 spin_lock_init(&ipu_data.lock);
1703 mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1704 mem_ic = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1705 if (!pdata || !mem_ipu || !mem_ic)
1708 ipu_data.dev = &pdev->dev;
1710 platform_set_drvdata(pdev, &ipu_data);
1712 ret = platform_get_irq(pdev, 0);
1716 ipu_data.irq_fn = ret;
1717 ret = platform_get_irq(pdev, 1);
1721 ipu_data.irq_err = ret;
1722 ipu_data.irq_base = pdata->irq_base;
1724 dev_dbg(&pdev->dev, "fn irq %u, err irq %u, irq-base %u\n",
1725 ipu_data.irq_fn, ipu_data.irq_err, ipu_data.irq_base);
1727 /* Remap IPU common registers */
1728 ipu_data.reg_ipu = ioremap(mem_ipu->start, resource_size(mem_ipu));
1729 if (!ipu_data.reg_ipu) {
1731 goto err_ioremap_ipu;
1734 /* Remap Image Converter and Image DMA Controller registers */
1735 ipu_data.reg_ic = ioremap(mem_ic->start, resource_size(mem_ic));
1736 if (!ipu_data.reg_ic) {
1738 goto err_ioremap_ic;
1742 ipu_data.ipu_clk = clk_get(&pdev->dev, NULL);
1743 if (IS_ERR(ipu_data.ipu_clk)) {
1744 ret = PTR_ERR(ipu_data.ipu_clk);
1748 /* Make sure IPU HSP clock is running */
1749 clk_enable(ipu_data.ipu_clk);
1751 /* Disable all interrupts */
1752 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_1);
1753 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_2);
1754 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_3);
1755 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_4);
1756 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_5);
1758 dev_dbg(&pdev->dev, "%s @ 0x%08lx, fn irq %u, err irq %u\n", pdev->name,
1759 (unsigned long)mem_ipu->start, ipu_data.irq_fn, ipu_data.irq_err);
1761 ret = ipu_irq_attach_irq(&ipu_data, pdev);
1763 goto err_attach_irq;
1765 /* Initialize DMA engine */
1766 ret = ipu_idmac_init(&ipu_data);
1768 goto err_idmac_init;
1770 tasklet_init(&ipu_data.tasklet, ipu_gc_tasklet, (unsigned long)&ipu_data);
1772 ipu_data.dev = &pdev->dev;
1774 dev_dbg(ipu_data.dev, "IPU initialized\n");
1780 ipu_irq_detach_irq(&ipu_data, pdev);
1781 clk_disable(ipu_data.ipu_clk);
1782 clk_put(ipu_data.ipu_clk);
1784 iounmap(ipu_data.reg_ic);
1786 iounmap(ipu_data.reg_ipu);
1789 dev_err(&pdev->dev, "Failed to probe IPU: %d\n", ret);
1793 static int __exit ipu_remove(struct platform_device *pdev)
1795 struct ipu *ipu = platform_get_drvdata(pdev);
1797 ipu_idmac_exit(ipu);
1798 ipu_irq_detach_irq(ipu, pdev);
1799 clk_disable(ipu->ipu_clk);
1800 clk_put(ipu->ipu_clk);
1801 iounmap(ipu->reg_ic);
1802 iounmap(ipu->reg_ipu);
1803 tasklet_kill(&ipu->tasklet);
1804 platform_set_drvdata(pdev, NULL);
1810 * We need two MEM resources - with IPU-common and Image Converter registers,
1811 * including PF_CONF and IDMAC_* registers, and two IRQs - function and error
1813 static struct platform_driver ipu_platform_driver = {
1816 .owner = THIS_MODULE,
1818 .remove = __exit_p(ipu_remove),
1821 static int __init ipu_init(void)
1823 return platform_driver_probe(&ipu_platform_driver, ipu_probe);
1825 subsys_initcall(ipu_init);
1827 MODULE_DESCRIPTION("IPU core driver");
1828 MODULE_LICENSE("GPL v2");
1829 MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1830 MODULE_ALIAS("platform:ipu-core");