2 * Driver For Marvell Two-channel DMA Engine
4 * Copyright: Marvell International Ltd.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
12 #include <linux/err.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/interrupt.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
19 #include <linux/dmaengine.h>
20 #include <linux/platform_device.h>
21 #include <linux/device.h>
22 #include <mach/regs-icu.h>
23 #include <linux/platform_data/dma-mmp_tdma.h>
24 #include <linux/of_device.h>
26 #include "dmaengine.h"
29 * Two-Channel DMA registers
31 #define TDBCR 0x00 /* Byte Count */
32 #define TDSAR 0x10 /* Src Addr */
33 #define TDDAR 0x20 /* Dst Addr */
34 #define TDNDPR 0x30 /* Next Desc */
35 #define TDCR 0x40 /* Control */
36 #define TDCP 0x60 /* Priority*/
37 #define TDCDPR 0x70 /* Current Desc */
38 #define TDIMR 0x80 /* Int Mask */
39 #define TDISR 0xa0 /* Int Status */
41 /* Two-Channel DMA Control Register */
42 #define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */
43 #define TDCR_SSZ_12_BITS (0x1 << 22)
44 #define TDCR_SSZ_16_BITS (0x2 << 22)
45 #define TDCR_SSZ_20_BITS (0x3 << 22)
46 #define TDCR_SSZ_24_BITS (0x4 << 22)
47 #define TDCR_SSZ_32_BITS (0x5 << 22)
48 #define TDCR_SSZ_SHIFT (0x1 << 22)
49 #define TDCR_SSZ_MASK (0x7 << 22)
50 #define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */
51 #define TDCR_ABR (0x1 << 20) /* Channel Abort */
52 #define TDCR_CDE (0x1 << 17) /* Close Desc Enable */
53 #define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */
54 #define TDCR_CHANACT (0x1 << 14) /* Channel Active */
55 #define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */
56 #define TDCR_CHANEN (0x1 << 12) /* Channel Enable */
57 #define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */
58 #define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */
59 #define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */
60 #define TDCR_BURSTSZ_4B (0x0 << 6)
61 #define TDCR_BURSTSZ_8B (0x1 << 6)
62 #define TDCR_BURSTSZ_16B (0x3 << 6)
63 #define TDCR_BURSTSZ_32B (0x6 << 6)
64 #define TDCR_BURSTSZ_64B (0x7 << 6)
65 #define TDCR_BURSTSZ_SQU_1B (0x5 << 6)
66 #define TDCR_BURSTSZ_SQU_2B (0x6 << 6)
67 #define TDCR_BURSTSZ_SQU_4B (0x0 << 6)
68 #define TDCR_BURSTSZ_SQU_8B (0x1 << 6)
69 #define TDCR_BURSTSZ_SQU_16B (0x3 << 6)
70 #define TDCR_BURSTSZ_SQU_32B (0x7 << 6)
71 #define TDCR_BURSTSZ_128B (0x5 << 6)
72 #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */
73 #define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */
74 #define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */
75 #define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */
76 #define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */
77 #define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */
78 #define TDCR_DSTDESCCONT (0x1 << 1)
79 #define TDCR_SRCDESTCONT (0x1 << 0)
81 /* Two-Channel DMA Int Mask Register */
82 #define TDIMR_COMP (0x1 << 0)
84 /* Two-Channel DMA Int Status Register */
85 #define TDISR_COMP (0x1 << 0)
88 * Two-Channel DMA Descriptor Struct
89 * NOTE: desc's buf must be aligned to 16 bytes.
91 struct mmp_tdma_desc {
103 #define TDMA_ALIGNMENT 3
104 #define TDMA_MAX_XFER_BYTES SZ_64K
106 struct mmp_tdma_chan {
108 struct dma_chan chan;
109 struct dma_async_tx_descriptor desc;
110 struct tasklet_struct tasklet;
112 struct mmp_tdma_desc *desc_arr;
113 phys_addr_t desc_arr_phys;
115 enum dma_transfer_direction dir;
118 enum dma_slave_buswidth buswidth;
119 enum dma_status status;
122 enum mmp_tdma_type type;
124 unsigned long reg_base;
131 #define TDMA_CHANNEL_NUM 2
132 struct mmp_tdma_device {
135 struct dma_device device;
136 struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM];
139 #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
141 static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
143 writel(phys, tdmac->reg_base + TDNDPR);
144 writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
145 tdmac->reg_base + TDCR);
148 static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
151 writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
152 /* enable dma chan */
153 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
154 tdmac->reg_base + TDCR);
155 tdmac->status = DMA_IN_PROGRESS;
158 static void mmp_tdma_disable_chan(struct mmp_tdma_chan *tdmac)
160 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
161 tdmac->reg_base + TDCR);
164 writel(0, tdmac->reg_base + TDIMR);
166 tdmac->status = DMA_COMPLETE;
169 static void mmp_tdma_resume_chan(struct mmp_tdma_chan *tdmac)
171 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
172 tdmac->reg_base + TDCR);
173 tdmac->status = DMA_IN_PROGRESS;
176 static void mmp_tdma_pause_chan(struct mmp_tdma_chan *tdmac)
178 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
179 tdmac->reg_base + TDCR);
180 tdmac->status = DMA_PAUSED;
183 static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac)
187 mmp_tdma_disable_chan(tdmac);
189 if (tdmac->dir == DMA_MEM_TO_DEV)
190 tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
191 else if (tdmac->dir == DMA_DEV_TO_MEM)
192 tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
194 if (tdmac->type == MMP_AUD_TDMA) {
195 tdcr |= TDCR_PACKMOD;
197 switch (tdmac->burst_sz) {
199 tdcr |= TDCR_BURSTSZ_4B;
202 tdcr |= TDCR_BURSTSZ_8B;
205 tdcr |= TDCR_BURSTSZ_16B;
208 tdcr |= TDCR_BURSTSZ_32B;
211 tdcr |= TDCR_BURSTSZ_64B;
214 tdcr |= TDCR_BURSTSZ_128B;
217 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
221 switch (tdmac->buswidth) {
222 case DMA_SLAVE_BUSWIDTH_1_BYTE:
223 tdcr |= TDCR_SSZ_8_BITS;
225 case DMA_SLAVE_BUSWIDTH_2_BYTES:
226 tdcr |= TDCR_SSZ_16_BITS;
228 case DMA_SLAVE_BUSWIDTH_4_BYTES:
229 tdcr |= TDCR_SSZ_32_BITS;
232 dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n");
235 } else if (tdmac->type == PXA910_SQU) {
238 switch (tdmac->burst_sz) {
240 tdcr |= TDCR_BURSTSZ_SQU_1B;
243 tdcr |= TDCR_BURSTSZ_SQU_2B;
246 tdcr |= TDCR_BURSTSZ_SQU_4B;
249 tdcr |= TDCR_BURSTSZ_SQU_8B;
252 tdcr |= TDCR_BURSTSZ_SQU_16B;
255 tdcr |= TDCR_BURSTSZ_SQU_32B;
258 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
263 writel(tdcr, tdmac->reg_base + TDCR);
267 static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac)
269 u32 reg = readl(tdmac->reg_base + TDISR);
271 if (reg & TDISR_COMP) {
274 writel(reg, tdmac->reg_base + TDISR);
281 static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id)
283 struct mmp_tdma_chan *tdmac = dev_id;
285 if (mmp_tdma_clear_chan_irq(tdmac) == 0) {
286 tdmac->pos = (tdmac->pos + tdmac->period_len) % tdmac->buf_len;
287 tasklet_schedule(&tdmac->tasklet);
293 static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id)
295 struct mmp_tdma_device *tdev = dev_id;
299 for (i = 0; i < TDMA_CHANNEL_NUM; i++) {
300 struct mmp_tdma_chan *tdmac = tdev->tdmac[i];
302 ret = mmp_tdma_chan_handler(irq, tdmac);
303 if (ret == IRQ_HANDLED)
313 static void dma_do_tasklet(unsigned long data)
315 struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data;
317 if (tdmac->desc.callback)
318 tdmac->desc.callback(tdmac->desc.callback_param);
322 static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
324 struct gen_pool *gpool;
325 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
327 gpool = sram_get_gpool("asram");
329 gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
331 tdmac->desc_arr = NULL;
336 static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx)
338 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan);
340 mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys);
345 static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
347 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
350 dma_async_tx_descriptor_init(&tdmac->desc, chan);
351 tdmac->desc.tx_submit = mmp_tdma_tx_submit;
354 ret = devm_request_irq(tdmac->dev, tdmac->irq,
355 mmp_tdma_chan_handler, 0, "tdma", tdmac);
362 static void mmp_tdma_free_chan_resources(struct dma_chan *chan)
364 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
367 devm_free_irq(tdmac->dev, tdmac->irq, tdmac);
368 mmp_tdma_free_descriptor(tdmac);
372 struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac)
374 struct gen_pool *gpool;
375 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
377 gpool = sram_get_gpool("asram");
381 tdmac->desc_arr = (void *)gen_pool_alloc(gpool, size);
382 if (!tdmac->desc_arr)
385 tdmac->desc_arr_phys = gen_pool_virt_to_phys(gpool,
386 (unsigned long)tdmac->desc_arr);
388 return tdmac->desc_arr;
391 static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
392 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
393 size_t period_len, enum dma_transfer_direction direction,
394 unsigned long flags, void *context)
396 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
397 struct mmp_tdma_desc *desc;
398 int num_periods = buf_len / period_len;
401 if (tdmac->status != DMA_COMPLETE)
404 if (period_len > TDMA_MAX_XFER_BYTES) {
406 "maximum period size exceeded: %d > %d\n",
407 period_len, TDMA_MAX_XFER_BYTES);
411 tdmac->status = DMA_IN_PROGRESS;
412 tdmac->desc_num = num_periods;
413 desc = mmp_tdma_alloc_descriptor(tdmac);
417 while (buf < buf_len) {
418 desc = &tdmac->desc_arr[i];
420 if (i + 1 == num_periods)
421 desc->nxt_desc = tdmac->desc_arr_phys;
423 desc->nxt_desc = tdmac->desc_arr_phys +
424 sizeof(*desc) * (i + 1);
426 if (direction == DMA_MEM_TO_DEV) {
427 desc->src_addr = dma_addr;
428 desc->dst_addr = tdmac->dev_addr;
430 desc->src_addr = tdmac->dev_addr;
431 desc->dst_addr = dma_addr;
433 desc->byte_cnt = period_len;
434 dma_addr += period_len;
439 tdmac->buf_len = buf_len;
440 tdmac->period_len = period_len;
446 tdmac->status = DMA_ERROR;
450 static int mmp_tdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
453 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
454 struct dma_slave_config *dmaengine_cfg = (void *)arg;
458 case DMA_TERMINATE_ALL:
459 mmp_tdma_disable_chan(tdmac);
462 mmp_tdma_pause_chan(tdmac);
465 mmp_tdma_resume_chan(tdmac);
467 case DMA_SLAVE_CONFIG:
468 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
469 tdmac->dev_addr = dmaengine_cfg->src_addr;
470 tdmac->burst_sz = dmaengine_cfg->src_maxburst;
471 tdmac->buswidth = dmaengine_cfg->src_addr_width;
473 tdmac->dev_addr = dmaengine_cfg->dst_addr;
474 tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
475 tdmac->buswidth = dmaengine_cfg->dst_addr_width;
477 tdmac->dir = dmaengine_cfg->direction;
478 return mmp_tdma_config_chan(tdmac);
486 static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan,
487 dma_cookie_t cookie, struct dma_tx_state *txstate)
489 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
491 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
492 tdmac->buf_len - tdmac->pos);
494 return tdmac->status;
497 static void mmp_tdma_issue_pending(struct dma_chan *chan)
499 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
501 mmp_tdma_enable_chan(tdmac);
504 static int mmp_tdma_remove(struct platform_device *pdev)
506 struct mmp_tdma_device *tdev = platform_get_drvdata(pdev);
508 dma_async_device_unregister(&tdev->device);
512 static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
513 int idx, int irq, int type)
515 struct mmp_tdma_chan *tdmac;
517 if (idx >= TDMA_CHANNEL_NUM) {
518 dev_err(tdev->dev, "too many channels for device!\n");
523 tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL);
525 dev_err(tdev->dev, "no free memory for DMA channels!\n");
530 tdmac->dev = tdev->dev;
531 tdmac->chan.device = &tdev->device;
534 tdmac->reg_base = (unsigned long)tdev->base + idx * 4;
535 tdmac->status = DMA_COMPLETE;
536 tdev->tdmac[tdmac->idx] = tdmac;
537 tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac);
539 /* add the channel to tdma_chan list */
540 list_add_tail(&tdmac->chan.device_node,
541 &tdev->device.channels);
545 static struct of_device_id mmp_tdma_dt_ids[] = {
546 { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
547 { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
550 MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
552 static int mmp_tdma_probe(struct platform_device *pdev)
554 enum mmp_tdma_type type;
555 const struct of_device_id *of_id;
556 struct mmp_tdma_device *tdev;
557 struct resource *iores;
559 int irq = 0, irq_num = 0;
560 int chan_num = TDMA_CHANNEL_NUM;
562 of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
564 type = (enum mmp_tdma_type) of_id->data;
566 type = platform_get_device_id(pdev)->driver_data;
568 /* always have couple channels */
569 tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
573 tdev->dev = &pdev->dev;
575 for (i = 0; i < chan_num; i++) {
576 if (platform_get_irq(pdev, i) > 0)
580 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
581 tdev->base = devm_ioremap_resource(&pdev->dev, iores);
582 if (IS_ERR(tdev->base))
583 return PTR_ERR(tdev->base);
585 INIT_LIST_HEAD(&tdev->device.channels);
587 if (irq_num != chan_num) {
588 irq = platform_get_irq(pdev, 0);
589 ret = devm_request_irq(&pdev->dev, irq,
590 mmp_tdma_int_handler, 0, "tdma", tdev);
595 /* initialize channel parameters */
596 for (i = 0; i < chan_num; i++) {
597 irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
598 ret = mmp_tdma_chan_init(tdev, i, irq, type);
603 dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
604 dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
605 tdev->device.dev = &pdev->dev;
606 tdev->device.device_alloc_chan_resources =
607 mmp_tdma_alloc_chan_resources;
608 tdev->device.device_free_chan_resources =
609 mmp_tdma_free_chan_resources;
610 tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic;
611 tdev->device.device_tx_status = mmp_tdma_tx_status;
612 tdev->device.device_issue_pending = mmp_tdma_issue_pending;
613 tdev->device.device_control = mmp_tdma_control;
614 tdev->device.copy_align = TDMA_ALIGNMENT;
616 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
617 platform_set_drvdata(pdev, tdev);
619 ret = dma_async_device_register(&tdev->device);
621 dev_err(tdev->device.dev, "unable to register\n");
625 dev_info(tdev->device.dev, "initialized\n");
629 static const struct platform_device_id mmp_tdma_id_table[] = {
630 { "mmp-adma", MMP_AUD_TDMA },
631 { "pxa910-squ", PXA910_SQU },
635 static struct platform_driver mmp_tdma_driver = {
638 .owner = THIS_MODULE,
639 .of_match_table = mmp_tdma_dt_ids,
641 .id_table = mmp_tdma_id_table,
642 .probe = mmp_tdma_probe,
643 .remove = mmp_tdma_remove,
646 module_platform_driver(mmp_tdma_driver);
648 MODULE_LICENSE("GPL");
649 MODULE_DESCRIPTION("MMP Two-Channel DMA Driver");
650 MODULE_ALIAS("platform:mmp-tdma");
651 MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
652 MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");