2 * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
3 * Copyright (C) Semihalf 2009
5 * Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
6 * (defines, structures and comments) was taken from MPC5121 DMA driver
7 * written by Hongjun Chen <hong-jun.chen@freescale.com>.
9 * Approved as OSADL project by a majority of OSADL members and funded
10 * by OSADL membership fees in 2009; for details see www.osadl.org.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the Free
14 * Software Foundation; either version 2 of the License, or (at your option)
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * You should have received a copy of the GNU General Public License along with
23 * this program; if not, write to the Free Software Foundation, Inc., 59
24 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 * The full GNU General Public License is included in this distribution in the
27 * file called COPYING.
31 * This is initial version of MPC5121 DMA driver. Only memory to memory
32 * transfers are supported (tested using dmatest module).
35 #include <linux/module.h>
36 #include <linux/dmaengine.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/interrupt.h>
40 #include <linux/slab.h>
41 #include <linux/of_device.h>
42 #include <linux/of_platform.h>
44 #include <linux/random.h>
46 /* Number of DMA Transfer descriptors allocated per channel */
47 #define MPC_DMA_DESCRIPTORS 64
49 /* Macro definitions */
50 #define MPC_DMA_CHANNELS 64
51 #define MPC_DMA_TCD_OFFSET 0x1000
53 /* Arbitration mode of group and channel */
54 #define MPC_DMA_DMACR_EDCG (1 << 31)
55 #define MPC_DMA_DMACR_ERGA (1 << 3)
56 #define MPC_DMA_DMACR_ERCA (1 << 2)
59 #define MPC_DMA_DMAES_VLD (1 << 31)
60 #define MPC_DMA_DMAES_GPE (1 << 15)
61 #define MPC_DMA_DMAES_CPE (1 << 14)
62 #define MPC_DMA_DMAES_ERRCHN(err) \
64 #define MPC_DMA_DMAES_SAE (1 << 7)
65 #define MPC_DMA_DMAES_SOE (1 << 6)
66 #define MPC_DMA_DMAES_DAE (1 << 5)
67 #define MPC_DMA_DMAES_DOE (1 << 4)
68 #define MPC_DMA_DMAES_NCE (1 << 3)
69 #define MPC_DMA_DMAES_SGE (1 << 2)
70 #define MPC_DMA_DMAES_SBE (1 << 1)
71 #define MPC_DMA_DMAES_DBE (1 << 0)
73 #define MPC_DMA_TSIZE_1 0x00
74 #define MPC_DMA_TSIZE_2 0x01
75 #define MPC_DMA_TSIZE_4 0x02
76 #define MPC_DMA_TSIZE_16 0x04
77 #define MPC_DMA_TSIZE_32 0x05
79 /* MPC5121 DMA engine registers */
80 struct __attribute__ ((__packed__)) mpc_dma_regs {
82 u32 dmacr; /* DMA control register */
83 u32 dmaes; /* DMA error status */
85 u32 dmaerqh; /* DMA enable request high(channels 63~32) */
86 u32 dmaerql; /* DMA enable request low(channels 31~0) */
87 u32 dmaeeih; /* DMA enable error interrupt high(ch63~32) */
88 u32 dmaeeil; /* DMA enable error interrupt low(ch31~0) */
90 u8 dmaserq; /* DMA set enable request */
91 u8 dmacerq; /* DMA clear enable request */
92 u8 dmaseei; /* DMA set enable error interrupt */
93 u8 dmaceei; /* DMA clear enable error interrupt */
95 u8 dmacint; /* DMA clear interrupt request */
96 u8 dmacerr; /* DMA clear error */
97 u8 dmassrt; /* DMA set start bit */
98 u8 dmacdne; /* DMA clear DONE status bit */
100 u32 dmainth; /* DMA interrupt request high(ch63~32) */
101 u32 dmaintl; /* DMA interrupt request low(ch31~0) */
102 u32 dmaerrh; /* DMA error high(ch63~32) */
103 u32 dmaerrl; /* DMA error low(ch31~0) */
105 u32 dmahrsh; /* DMA hw request status high(ch63~32) */
106 u32 dmahrsl; /* DMA hardware request status low(ch31~0) */
107 u32 dmaihsa; /* DMA interrupt high select AXE(ch63~32) */
108 u32 dmailsa; /* DMA interrupt low select AXE(ch31~0) */
110 u32 reserve0[48]; /* Reserved */
112 u8 dchpri[MPC_DMA_CHANNELS];
113 /* DMA channels(0~63) priority */
116 struct __attribute__ ((__packed__)) mpc_dma_tcd {
118 u32 saddr; /* Source address */
120 u32 smod:5; /* Source address modulo */
121 u32 ssize:3; /* Source data transfer size */
122 u32 dmod:5; /* Destination address modulo */
123 u32 dsize:3; /* Destination data transfer size */
124 u32 soff:16; /* Signed source address offset */
127 u32 nbytes; /* Inner "minor" byte count */
128 u32 slast; /* Last source address adjustment */
129 u32 daddr; /* Destination address */
132 u32 citer_elink:1; /* Enable channel-to-channel linking on
133 * minor loop complete
135 u32 citer_linkch:6; /* Link channel for minor loop complete */
136 u32 citer:9; /* Current "major" iteration count */
137 u32 doff:16; /* Signed destination address offset */
140 u32 dlast_sga; /* Last Destination address adjustment/scatter
145 u32 biter_elink:1; /* Enable channel-to-channel linking on major
149 u32 biter:9; /* Beginning "major" iteration count */
150 u32 bwc:2; /* Bandwidth control */
151 u32 major_linkch:6; /* Link channel number */
152 u32 done:1; /* Channel done */
153 u32 active:1; /* Channel active */
154 u32 major_elink:1; /* Enable channel-to-channel linking on major
157 u32 e_sg:1; /* Enable scatter/gather processing */
158 u32 d_req:1; /* Disable request */
159 u32 int_half:1; /* Enable an interrupt when major counter is
162 u32 int_maj:1; /* Enable an interrupt when major iteration
165 u32 start:1; /* Channel start */
168 struct mpc_dma_desc {
169 struct dma_async_tx_descriptor desc;
170 struct mpc_dma_tcd *tcd;
171 dma_addr_t tcd_paddr;
173 struct list_head node;
176 struct mpc_dma_chan {
177 struct dma_chan chan;
178 struct list_head free;
179 struct list_head prepared;
180 struct list_head queued;
181 struct list_head active;
182 struct list_head completed;
183 struct mpc_dma_tcd *tcd;
184 dma_addr_t tcd_paddr;
185 dma_cookie_t completed_cookie;
187 /* Lock for this structure */
192 struct dma_device dma;
193 struct tasklet_struct tasklet;
194 struct mpc_dma_chan channels[MPC_DMA_CHANNELS];
195 struct mpc_dma_regs __iomem *regs;
196 struct mpc_dma_tcd __iomem *tcd;
200 /* Lock for error_status field in this structure */
201 spinlock_t error_status_lock;
204 #define DRV_NAME "mpc512x_dma"
206 /* Convert struct dma_chan to struct mpc_dma_chan */
207 static inline struct mpc_dma_chan *dma_chan_to_mpc_dma_chan(struct dma_chan *c)
209 return container_of(c, struct mpc_dma_chan, chan);
212 /* Convert struct dma_chan to struct mpc_dma */
213 static inline struct mpc_dma *dma_chan_to_mpc_dma(struct dma_chan *c)
215 struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(c);
216 return container_of(mchan, struct mpc_dma, channels[c->chan_id]);
220 * Execute all queued DMA descriptors.
222 * Following requirements must be met while calling mpc_dma_execute():
223 * a) mchan->lock is acquired,
224 * b) mchan->active list is empty,
225 * c) mchan->queued list contains at least one entry.
227 static void mpc_dma_execute(struct mpc_dma_chan *mchan)
229 struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan);
230 struct mpc_dma_desc *first = NULL;
231 struct mpc_dma_desc *prev = NULL;
232 struct mpc_dma_desc *mdesc;
233 int cid = mchan->chan.chan_id;
235 /* Move all queued descriptors to active list */
236 list_splice_tail_init(&mchan->queued, &mchan->active);
238 /* Chain descriptors into one transaction */
239 list_for_each_entry(mdesc, &mchan->active, node) {
248 prev->tcd->dlast_sga = mdesc->tcd_paddr;
250 mdesc->tcd->start = 1;
255 prev->tcd->int_maj = 1;
257 /* Send first descriptor in chain into hardware */
258 memcpy_toio(&mdma->tcd[cid], first->tcd, sizeof(struct mpc_dma_tcd));
261 mdma->tcd[cid].e_sg = 1;
262 out_8(&mdma->regs->dmassrt, cid);
265 /* Handle interrupt on one half of DMA controller (32 channels) */
266 static void mpc_dma_irq_process(struct mpc_dma *mdma, u32 is, u32 es, int off)
268 struct mpc_dma_chan *mchan;
269 struct mpc_dma_desc *mdesc;
270 u32 status = is | es;
273 while ((ch = fls(status) - 1) >= 0) {
274 status &= ~(1 << ch);
275 mchan = &mdma->channels[ch + off];
277 spin_lock(&mchan->lock);
279 /* Check error status */
281 list_for_each_entry(mdesc, &mchan->active, node)
284 /* Execute queued descriptors */
285 list_splice_tail_init(&mchan->active, &mchan->completed);
286 if (!list_empty(&mchan->queued))
287 mpc_dma_execute(mchan);
289 spin_unlock(&mchan->lock);
293 /* Interrupt handler */
294 static irqreturn_t mpc_dma_irq(int irq, void *data)
296 struct mpc_dma *mdma = data;
299 /* Save error status register */
300 es = in_be32(&mdma->regs->dmaes);
301 spin_lock(&mdma->error_status_lock);
302 if ((es & MPC_DMA_DMAES_VLD) && mdma->error_status == 0)
303 mdma->error_status = es;
304 spin_unlock(&mdma->error_status_lock);
306 /* Handle interrupt on each channel */
307 mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmainth),
308 in_be32(&mdma->regs->dmaerrh), 32);
309 mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmaintl),
310 in_be32(&mdma->regs->dmaerrl), 0);
312 /* Ack interrupt on all channels */
313 out_be32(&mdma->regs->dmainth, 0xFFFFFFFF);
314 out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF);
315 out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF);
316 out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF);
318 /* Schedule tasklet */
319 tasklet_schedule(&mdma->tasklet);
325 static void mpc_dma_tasklet(unsigned long data)
327 struct mpc_dma *mdma = (void *)data;
328 dma_cookie_t last_cookie = 0;
329 struct mpc_dma_chan *mchan;
330 struct mpc_dma_desc *mdesc;
331 struct dma_async_tx_descriptor *desc;
337 spin_lock_irqsave(&mdma->error_status_lock, flags);
338 es = mdma->error_status;
339 mdma->error_status = 0;
340 spin_unlock_irqrestore(&mdma->error_status_lock, flags);
342 /* Print nice error report */
344 dev_err(mdma->dma.dev,
345 "Hardware reported following error(s) on channel %u:\n",
346 MPC_DMA_DMAES_ERRCHN(es));
348 if (es & MPC_DMA_DMAES_GPE)
349 dev_err(mdma->dma.dev, "- Group Priority Error\n");
350 if (es & MPC_DMA_DMAES_CPE)
351 dev_err(mdma->dma.dev, "- Channel Priority Error\n");
352 if (es & MPC_DMA_DMAES_SAE)
353 dev_err(mdma->dma.dev, "- Source Address Error\n");
354 if (es & MPC_DMA_DMAES_SOE)
355 dev_err(mdma->dma.dev, "- Source Offset"
356 " Configuration Error\n");
357 if (es & MPC_DMA_DMAES_DAE)
358 dev_err(mdma->dma.dev, "- Destination Address"
360 if (es & MPC_DMA_DMAES_DOE)
361 dev_err(mdma->dma.dev, "- Destination Offset"
362 " Configuration Error\n");
363 if (es & MPC_DMA_DMAES_NCE)
364 dev_err(mdma->dma.dev, "- NBytes/Citter"
365 " Configuration Error\n");
366 if (es & MPC_DMA_DMAES_SGE)
367 dev_err(mdma->dma.dev, "- Scatter/Gather"
368 " Configuration Error\n");
369 if (es & MPC_DMA_DMAES_SBE)
370 dev_err(mdma->dma.dev, "- Source Bus Error\n");
371 if (es & MPC_DMA_DMAES_DBE)
372 dev_err(mdma->dma.dev, "- Destination Bus Error\n");
375 for (i = 0; i < mdma->dma.chancnt; i++) {
376 mchan = &mdma->channels[i];
378 /* Get all completed descriptors */
379 spin_lock_irqsave(&mchan->lock, flags);
380 if (!list_empty(&mchan->completed))
381 list_splice_tail_init(&mchan->completed, &list);
382 spin_unlock_irqrestore(&mchan->lock, flags);
384 if (list_empty(&list))
387 /* Execute callbacks and run dependencies */
388 list_for_each_entry(mdesc, &list, node) {
392 desc->callback(desc->callback_param);
394 last_cookie = desc->cookie;
395 dma_run_dependencies(desc);
398 /* Free descriptors */
399 spin_lock_irqsave(&mchan->lock, flags);
400 list_splice_tail_init(&list, &mchan->free);
401 mchan->completed_cookie = last_cookie;
402 spin_unlock_irqrestore(&mchan->lock, flags);
406 /* Submit descriptor to hardware */
407 static dma_cookie_t mpc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
409 struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(txd->chan);
410 struct mpc_dma_desc *mdesc;
414 mdesc = container_of(txd, struct mpc_dma_desc, desc);
416 spin_lock_irqsave(&mchan->lock, flags);
418 /* Move descriptor to queue */
419 list_move_tail(&mdesc->node, &mchan->queued);
421 /* If channel is idle, execute all queued descriptors */
422 if (list_empty(&mchan->active))
423 mpc_dma_execute(mchan);
426 cookie = mchan->chan.cookie + 1;
430 mchan->chan.cookie = cookie;
431 mdesc->desc.cookie = cookie;
433 spin_unlock_irqrestore(&mchan->lock, flags);
438 /* Alloc channel resources */
439 static int mpc_dma_alloc_chan_resources(struct dma_chan *chan)
441 struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
442 struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
443 struct mpc_dma_desc *mdesc;
444 struct mpc_dma_tcd *tcd;
445 dma_addr_t tcd_paddr;
450 /* Alloc DMA memory for Transfer Control Descriptors */
451 tcd = dma_alloc_coherent(mdma->dma.dev,
452 MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
453 &tcd_paddr, GFP_KERNEL);
457 /* Alloc descriptors for this channel */
458 for (i = 0; i < MPC_DMA_DESCRIPTORS; i++) {
459 mdesc = kzalloc(sizeof(struct mpc_dma_desc), GFP_KERNEL);
461 dev_notice(mdma->dma.dev, "Memory allocation error. "
462 "Allocated only %u descriptors\n", i);
466 dma_async_tx_descriptor_init(&mdesc->desc, chan);
467 mdesc->desc.flags = DMA_CTRL_ACK;
468 mdesc->desc.tx_submit = mpc_dma_tx_submit;
470 mdesc->tcd = &tcd[i];
471 mdesc->tcd_paddr = tcd_paddr + (i * sizeof(struct mpc_dma_tcd));
473 list_add_tail(&mdesc->node, &descs);
476 /* Return error only if no descriptors were allocated */
478 dma_free_coherent(mdma->dma.dev,
479 MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
484 spin_lock_irqsave(&mchan->lock, flags);
486 mchan->tcd_paddr = tcd_paddr;
487 list_splice_tail_init(&descs, &mchan->free);
488 spin_unlock_irqrestore(&mchan->lock, flags);
490 /* Enable Error Interrupt */
491 out_8(&mdma->regs->dmaseei, chan->chan_id);
496 /* Free channel resources */
497 static void mpc_dma_free_chan_resources(struct dma_chan *chan)
499 struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
500 struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
501 struct mpc_dma_desc *mdesc, *tmp;
502 struct mpc_dma_tcd *tcd;
503 dma_addr_t tcd_paddr;
507 spin_lock_irqsave(&mchan->lock, flags);
509 /* Channel must be idle */
510 BUG_ON(!list_empty(&mchan->prepared));
511 BUG_ON(!list_empty(&mchan->queued));
512 BUG_ON(!list_empty(&mchan->active));
513 BUG_ON(!list_empty(&mchan->completed));
516 list_splice_tail_init(&mchan->free, &descs);
518 tcd_paddr = mchan->tcd_paddr;
520 spin_unlock_irqrestore(&mchan->lock, flags);
522 /* Free DMA memory used by descriptors */
523 dma_free_coherent(mdma->dma.dev,
524 MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
527 /* Free descriptors */
528 list_for_each_entry_safe(mdesc, tmp, &descs, node)
531 /* Disable Error Interrupt */
532 out_8(&mdma->regs->dmaceei, chan->chan_id);
535 /* Send all pending descriptor to hardware */
536 static void mpc_dma_issue_pending(struct dma_chan *chan)
539 * We are posting descriptors to the hardware as soon as
540 * they are ready, so this function does nothing.
544 /* Check request completion status */
545 static enum dma_status
546 mpc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
547 struct dma_tx_state *txstate)
549 struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
551 dma_cookie_t last_used;
552 dma_cookie_t last_complete;
554 spin_lock_irqsave(&mchan->lock, flags);
555 last_used = mchan->chan.cookie;
556 last_complete = mchan->completed_cookie;
557 spin_unlock_irqrestore(&mchan->lock, flags);
559 dma_set_tx_state(txstate, last_complete, last_used, 0);
560 return dma_async_is_complete(cookie, last_complete, last_used);
563 /* Prepare descriptor for memory to memory copy */
564 static struct dma_async_tx_descriptor *
565 mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
566 size_t len, unsigned long flags)
568 struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
569 struct mpc_dma_desc *mdesc = NULL;
570 struct mpc_dma_tcd *tcd;
571 unsigned long iflags;
573 /* Get free descriptor */
574 spin_lock_irqsave(&mchan->lock, iflags);
575 if (!list_empty(&mchan->free)) {
576 mdesc = list_first_entry(&mchan->free, struct mpc_dma_desc,
578 list_del(&mdesc->node);
580 spin_unlock_irqrestore(&mchan->lock, iflags);
588 /* Prepare Transfer Control Descriptor for this transaction */
589 memset(tcd, 0, sizeof(struct mpc_dma_tcd));
591 if (IS_ALIGNED(src | dst | len, 32)) {
592 tcd->ssize = MPC_DMA_TSIZE_32;
593 tcd->dsize = MPC_DMA_TSIZE_32;
596 } else if (IS_ALIGNED(src | dst | len, 16)) {
597 tcd->ssize = MPC_DMA_TSIZE_16;
598 tcd->dsize = MPC_DMA_TSIZE_16;
601 } else if (IS_ALIGNED(src | dst | len, 4)) {
602 tcd->ssize = MPC_DMA_TSIZE_4;
603 tcd->dsize = MPC_DMA_TSIZE_4;
606 } else if (IS_ALIGNED(src | dst | len, 2)) {
607 tcd->ssize = MPC_DMA_TSIZE_2;
608 tcd->dsize = MPC_DMA_TSIZE_2;
612 tcd->ssize = MPC_DMA_TSIZE_1;
613 tcd->dsize = MPC_DMA_TSIZE_1;
624 /* Place descriptor in prepared list */
625 spin_lock_irqsave(&mchan->lock, iflags);
626 list_add_tail(&mdesc->node, &mchan->prepared);
627 spin_unlock_irqrestore(&mchan->lock, iflags);
632 static int __devinit mpc_dma_probe(struct platform_device *op,
633 const struct of_device_id *match)
635 struct device_node *dn = op->dev.of_node;
636 struct device *dev = &op->dev;
637 struct dma_device *dma;
638 struct mpc_dma *mdma;
639 struct mpc_dma_chan *mchan;
641 ulong regs_start, regs_size;
644 mdma = devm_kzalloc(dev, sizeof(struct mpc_dma), GFP_KERNEL);
646 dev_err(dev, "Memory exhausted!\n");
650 mdma->irq = irq_of_parse_and_map(dn, 0);
651 if (mdma->irq == NO_IRQ) {
652 dev_err(dev, "Error mapping IRQ!\n");
656 retval = of_address_to_resource(dn, 0, &res);
658 dev_err(dev, "Error parsing memory region!\n");
662 regs_start = res.start;
663 regs_size = resource_size(&res);
665 if (!devm_request_mem_region(dev, regs_start, regs_size, DRV_NAME)) {
666 dev_err(dev, "Error requesting memory region!\n");
670 mdma->regs = devm_ioremap(dev, regs_start, regs_size);
672 dev_err(dev, "Error mapping memory region!\n");
676 mdma->tcd = (struct mpc_dma_tcd *)((u8 *)(mdma->regs)
677 + MPC_DMA_TCD_OFFSET);
679 retval = devm_request_irq(dev, mdma->irq, &mpc_dma_irq, 0, DRV_NAME,
682 dev_err(dev, "Error requesting IRQ!\n");
686 spin_lock_init(&mdma->error_status_lock);
690 dma->chancnt = MPC_DMA_CHANNELS;
691 dma->device_alloc_chan_resources = mpc_dma_alloc_chan_resources;
692 dma->device_free_chan_resources = mpc_dma_free_chan_resources;
693 dma->device_issue_pending = mpc_dma_issue_pending;
694 dma->device_tx_status = mpc_dma_tx_status;
695 dma->device_prep_dma_memcpy = mpc_dma_prep_memcpy;
697 INIT_LIST_HEAD(&dma->channels);
698 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
700 for (i = 0; i < dma->chancnt; i++) {
701 mchan = &mdma->channels[i];
703 mchan->chan.device = dma;
704 mchan->chan.chan_id = i;
705 mchan->chan.cookie = 1;
706 mchan->completed_cookie = mchan->chan.cookie;
708 INIT_LIST_HEAD(&mchan->free);
709 INIT_LIST_HEAD(&mchan->prepared);
710 INIT_LIST_HEAD(&mchan->queued);
711 INIT_LIST_HEAD(&mchan->active);
712 INIT_LIST_HEAD(&mchan->completed);
714 spin_lock_init(&mchan->lock);
715 list_add_tail(&mchan->chan.device_node, &dma->channels);
718 tasklet_init(&mdma->tasklet, mpc_dma_tasklet, (unsigned long)mdma);
721 * Configure DMA Engine:
723 * - Round-robin group arbitration,
724 * - Round-robin channel arbitration.
726 out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG |
727 MPC_DMA_DMACR_ERGA | MPC_DMA_DMACR_ERCA);
729 /* Disable hardware DMA requests */
730 out_be32(&mdma->regs->dmaerqh, 0);
731 out_be32(&mdma->regs->dmaerql, 0);
733 /* Disable error interrupts */
734 out_be32(&mdma->regs->dmaeeih, 0);
735 out_be32(&mdma->regs->dmaeeil, 0);
737 /* Clear interrupts status */
738 out_be32(&mdma->regs->dmainth, 0xFFFFFFFF);
739 out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF);
740 out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF);
741 out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF);
743 /* Route interrupts to IPIC */
744 out_be32(&mdma->regs->dmaihsa, 0);
745 out_be32(&mdma->regs->dmailsa, 0);
747 /* Register DMA engine */
748 dev_set_drvdata(dev, mdma);
749 retval = dma_async_device_register(dma);
751 devm_free_irq(dev, mdma->irq, mdma);
752 irq_dispose_mapping(mdma->irq);
758 static int __devexit mpc_dma_remove(struct platform_device *op)
760 struct device *dev = &op->dev;
761 struct mpc_dma *mdma = dev_get_drvdata(dev);
763 dma_async_device_unregister(&mdma->dma);
764 devm_free_irq(dev, mdma->irq, mdma);
765 irq_dispose_mapping(mdma->irq);
770 static struct of_device_id mpc_dma_match[] = {
771 { .compatible = "fsl,mpc5121-dma", },
775 static struct of_platform_driver mpc_dma_driver = {
776 .probe = mpc_dma_probe,
777 .remove = __devexit_p(mpc_dma_remove),
780 .owner = THIS_MODULE,
781 .of_match_table = mpc_dma_match,
785 static int __init mpc_dma_init(void)
787 return of_register_platform_driver(&mpc_dma_driver);
789 module_init(mpc_dma_init);
791 static void __exit mpc_dma_exit(void)
793 of_unregister_platform_driver(&mpc_dma_driver);
795 module_exit(mpc_dma_exit);
797 MODULE_LICENSE("GPL");
798 MODULE_AUTHOR("Piotr Ziecik <kosmo@semihalf.com>");