drivers/dma/pl330.c

   1 /*
   2  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   6  *      Jaswinder Singh <jassi.brar@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/io.h>
  16 #include <linux/init.h>
  17 #include <linux/slab.h>
  18 #include <linux/module.h>
  19 #include <linux/string.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/amba/bus.h>
  25 #include <linux/amba/pl330.h>
  26 #include <linux/scatterlist.h>
  27 #include <linux/of.h>
  28 #include <linux/of_dma.h>
  29 #include <linux/err.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "dmaengine.h"
  33 #define PL330_MAX_CHAN          8
  34 #define PL330_MAX_IRQS          32
  35 #define PL330_MAX_PERI          32
  36 #define PL330_MAX_BURST         16
  37
  38 #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
  39
  40 enum pl330_cachectrl {
  41         CCTRL0,         /* Noncacheable and nonbufferable */
  42         CCTRL1,         /* Bufferable only */
  43         CCTRL2,         /* Cacheable, but do not allocate */
  44         CCTRL3,         /* Cacheable and bufferable, but do not allocate */
  45         INVALID1,       /* AWCACHE = 0x1000 */
  46         INVALID2,
  47         CCTRL6,         /* Cacheable write-through, allocate on writes only */
  48         CCTRL7,         /* Cacheable write-back, allocate on writes only */
  49 };
  50
  51 enum pl330_byteswap {
  52         SWAP_NO,
  53         SWAP_2,
  54         SWAP_4,
  55         SWAP_8,
  56         SWAP_16,
  57 };
  58
  59 /* Register and Bit field Definitions */
  60 #define DS                      0x0
  61 #define DS_ST_STOP              0x0
  62 #define DS_ST_EXEC              0x1
  63 #define DS_ST_CMISS             0x2
  64 #define DS_ST_UPDTPC            0x3
  65 #define DS_ST_WFE               0x4
  66 #define DS_ST_ATBRR             0x5
  67 #define DS_ST_QBUSY             0x6
  68 #define DS_ST_WFP               0x7
  69 #define DS_ST_KILL              0x8
  70 #define DS_ST_CMPLT             0x9
  71 #define DS_ST_FLTCMP            0xe
  72 #define DS_ST_FAULT             0xf
  73
  74 #define DPC                     0x4
  75 #define INTEN                   0x20
  76 #define ES                      0x24
  77 #define INTSTATUS               0x28
  78 #define INTCLR                  0x2c
  79 #define FSM                     0x30
  80 #define FSC                     0x34
  81 #define FTM                     0x38
  82
  83 #define _FTC                    0x40
  84 #define FTC(n)                  (_FTC + (n)*0x4)
  85
  86 #define _CS                     0x100
  87 #define CS(n)                   (_CS + (n)*0x8)
  88 #define CS_CNS                  (1 << 21)
  89
  90 #define _CPC                    0x104
  91 #define CPC(n)                  (_CPC + (n)*0x8)
  92
  93 #define _SA                     0x400
  94 #define SA(n)                   (_SA + (n)*0x20)
  95
  96 #define _DA                     0x404
  97 #define DA(n)                   (_DA + (n)*0x20)
  98
  99 #define _CC                     0x408
 100 #define CC(n)                   (_CC + (n)*0x20)
 101
 102 #define CC_SRCINC               (1 << 0)
 103 #define CC_DSTINC               (1 << 14)
 104 #define CC_SRCPRI               (1 << 8)
 105 #define CC_DSTPRI               (1 << 22)
 106 #define CC_SRCNS                (1 << 9)
 107 #define CC_DSTNS                (1 << 23)
 108 #define CC_SRCIA                (1 << 10)
 109 #define CC_DSTIA                (1 << 24)
 110 #define CC_SRCBRSTLEN_SHFT      4
 111 #define CC_DSTBRSTLEN_SHFT      18
 112 #define CC_SRCBRSTSIZE_SHFT     1
 113 #define CC_DSTBRSTSIZE_SHFT     15
 114 #define CC_SRCCCTRL_SHFT        11
 115 #define CC_SRCCCTRL_MASK        0x7
 116 #define CC_DSTCCTRL_SHFT        25
 117 #define CC_DRCCCTRL_MASK        0x7
 118 #define CC_SWAP_SHFT            28
 119
 120 #define _LC0                    0x40c
 121 #define LC0(n)                  (_LC0 + (n)*0x20)
 122
 123 #define _LC1                    0x410
 124 #define LC1(n)                  (_LC1 + (n)*0x20)
 125
 126 #define DBGSTATUS               0xd00
 127 #define DBG_BUSY                (1 << 0)
 128
 129 #define DBGCMD                  0xd04
 130 #define DBGINST0                0xd08
 131 #define DBGINST1                0xd0c
 132
 133 #define CR0                     0xe00
 134 #define CR1                     0xe04
 135 #define CR2                     0xe08
 136 #define CR3                     0xe0c
 137 #define CR4                     0xe10
 138 #define CRD                     0xe14
 139
 140 #define PERIPH_ID               0xfe0
 141 #define PERIPH_REV_SHIFT        20
 142 #define PERIPH_REV_MASK         0xf
 143 #define PERIPH_REV_R0P0         0
 144 #define PERIPH_REV_R1P0         1
 145 #define PERIPH_REV_R1P1         2
 146
 147 #define CR0_PERIPH_REQ_SET      (1 << 0)
 148 #define CR0_BOOT_EN_SET         (1 << 1)
 149 #define CR0_BOOT_MAN_NS         (1 << 2)
 150 #define CR0_NUM_CHANS_SHIFT     4
 151 #define CR0_NUM_CHANS_MASK      0x7
 152 #define CR0_NUM_PERIPH_SHIFT    12
 153 #define CR0_NUM_PERIPH_MASK     0x1f
 154 #define CR0_NUM_EVENTS_SHIFT    17
 155 #define CR0_NUM_EVENTS_MASK     0x1f
 156
 157 #define CR1_ICACHE_LEN_SHIFT    0
 158 #define CR1_ICACHE_LEN_MASK     0x7
 159 #define CR1_NUM_ICACHELINES_SHIFT       4
 160 #define CR1_NUM_ICACHELINES_MASK        0xf
 161
 162 #define CRD_DATA_WIDTH_SHIFT    0
 163 #define CRD_DATA_WIDTH_MASK     0x7
 164 #define CRD_WR_CAP_SHIFT        4
 165 #define CRD_WR_CAP_MASK         0x7
 166 #define CRD_WR_Q_DEP_SHIFT      8
 167 #define CRD_WR_Q_DEP_MASK       0xf
 168 #define CRD_RD_CAP_SHIFT        12
 169 #define CRD_RD_CAP_MASK         0x7
 170 #define CRD_RD_Q_DEP_SHIFT      16
 171 #define CRD_RD_Q_DEP_MASK       0xf
 172 #define CRD_DATA_BUFF_SHIFT     20
 173 #define CRD_DATA_BUFF_MASK      0x3ff
 174
 175 #define PART                    0x330
 176 #define DESIGNER                0x41
 177 #define REVISION                0x0
 178 #define INTEG_CFG               0x0
 179 #define PERIPH_ID_VAL           ((PART << 0) | (DESIGNER << 12))
 180
 181 #define PL330_STATE_STOPPED             (1 << 0)
 182 #define PL330_STATE_EXECUTING           (1 << 1)
 183 #define PL330_STATE_WFE                 (1 << 2)
 184 #define PL330_STATE_FAULTING            (1 << 3)
 185 #define PL330_STATE_COMPLETING          (1 << 4)
 186 #define PL330_STATE_WFP                 (1 << 5)
 187 #define PL330_STATE_KILLING             (1 << 6)
 188 #define PL330_STATE_FAULT_COMPLETING    (1 << 7)
 189 #define PL330_STATE_CACHEMISS           (1 << 8)
 190 #define PL330_STATE_UPDTPC              (1 << 9)
 191 #define PL330_STATE_ATBARRIER           (1 << 10)
 192 #define PL330_STATE_QUEUEBUSY           (1 << 11)
 193 #define PL330_STATE_INVALID             (1 << 15)
 194
 195 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
 196                                 | PL330_STATE_WFE | PL330_STATE_FAULTING)
 197
 198 #define CMD_DMAADDH             0x54
 199 #define CMD_DMAEND              0x00
 200 #define CMD_DMAFLUSHP           0x35
 201 #define CMD_DMAGO               0xa0
 202 #define CMD_DMALD               0x04
 203 #define CMD_DMALDP              0x25
 204 #define CMD_DMALP               0x20
 205 #define CMD_DMALPEND            0x28
 206 #define CMD_DMAKILL             0x01
 207 #define CMD_DMAMOV              0xbc
 208 #define CMD_DMANOP              0x18
 209 #define CMD_DMARMB              0x12
 210 #define CMD_DMASEV              0x34
 211 #define CMD_DMAST               0x08
 212 #define CMD_DMASTP              0x29
 213 #define CMD_DMASTZ              0x0c
 214 #define CMD_DMAWFE              0x36
 215 #define CMD_DMAWFP              0x30
 216 #define CMD_DMAWMB              0x13
 217
 218 #define SZ_DMAADDH              3
 219 #define SZ_DMAEND               1
 220 #define SZ_DMAFLUSHP            2
 221 #define SZ_DMALD                1
 222 #define SZ_DMALDP               2
 223 #define SZ_DMALP                2
 224 #define SZ_DMALPEND             2
 225 #define SZ_DMAKILL              1
 226 #define SZ_DMAMOV               6
 227 #define SZ_DMANOP               1
 228 #define SZ_DMARMB               1
 229 #define SZ_DMASEV               2
 230 #define SZ_DMAST                1
 231 #define SZ_DMASTP               2
 232 #define SZ_DMASTZ               1
 233 #define SZ_DMAWFE               2
 234 #define SZ_DMAWFP               2
 235 #define SZ_DMAWMB               1
 236 #define SZ_DMAGO                6
 237
 238 #define BRST_LEN(ccr)           ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
 239 #define BRST_SIZE(ccr)          (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
 240
 241 #define BYTE_TO_BURST(b, ccr)   ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
 242 #define BURST_TO_BYTE(c, ccr)   ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
 243
 244 /*
 245  * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
 246  * at 1byte/burst for P<->M and M<->M respectively.
 247  * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
 248  * should be enough for P<->M and M<->M respectively.
 249  */
 250 #define MCODE_BUFF_PER_REQ      256
 251
 252 /* Use this _only_ to wait on transient states */
 253 #define UNTIL(t, s)     while (!(_state(t) & (s))) cpu_relax();
 254
 255 #ifdef PL330_DEBUG_MCGEN
 256 static unsigned cmd_line;
 257 #define PL330_DBGCMD_DUMP(off, x...)    do { \
 258                                                 printk("%x:", cmd_line); \
 259                                                 printk(x); \
 260                                                 cmd_line += off; \
 261                                         } while (0)
 262 #define PL330_DBGMC_START(addr)         (cmd_line = addr)
 263 #else
 264 #define PL330_DBGCMD_DUMP(off, x...)    do {} while (0)
 265 #define PL330_DBGMC_START(addr)         do {} while (0)
 266 #endif
 267
 268 /* The number of default descriptors */
 269
 270 #define NR_DEFAULT_DESC 16
 271
 272 /* Delay for runtime PM autosuspend, ms */
 273 #define PL330_AUTOSUSPEND_DELAY 20
 274
 275 /* Populated by the PL330 core driver for DMA API driver's info */
 276 struct pl330_config {
 277         u32     periph_id;
 278 #define DMAC_MODE_NS    (1 << 0)
 279         unsigned int    mode;
 280         unsigned int    data_bus_width:10; /* In number of bits */
 281         unsigned int    data_buf_dep:11;
 282         unsigned int    num_chan:4;
 283         unsigned int    num_peri:6;
 284         u32             peri_ns;
 285         unsigned int    num_events:6;
 286         u32             irq_ns;
 287 };
 288
 289 /**
 290  * Request Configuration.
 291  * The PL330 core does not modify this and uses the last
 292  * working configuration if the request doesn't provide any.
 293  *
 294  * The Client may want to provide this info only for the
 295  * first request and a request with new settings.
 296  */
 297 struct pl330_reqcfg {
 298         /* Address Incrementing */
 299         unsigned dst_inc:1;
 300         unsigned src_inc:1;
 301
 302         /*
 303          * For now, the SRC & DST protection levels
 304          * and burst size/length are assumed same.
 305          */
 306         bool nonsecure;
 307         bool privileged;
 308         bool insnaccess;
 309         unsigned brst_len:5;
 310         unsigned brst_size:3; /* in power of 2 */
 311
 312         enum pl330_cachectrl dcctl;
 313         enum pl330_cachectrl scctl;
 314         enum pl330_byteswap swap;
 315         struct pl330_config *pcfg;
 316 };
 317
 318 /*
 319  * One cycle of DMAC operation.
 320  * There may be more than one xfer in a request.
 321  */
 322 struct pl330_xfer {
 323         u32 src_addr;
 324         u32 dst_addr;
 325         /* Size to xfer */
 326         u32 bytes;
 327 };
 328
 329 /* The xfer callbacks are made with one of these arguments. */
 330 enum pl330_op_err {
 331         /* The all xfers in the request were success. */
 332         PL330_ERR_NONE,
 333         /* If req aborted due to global error. */
 334         PL330_ERR_ABORT,
 335         /* If req failed due to problem with Channel. */
 336         PL330_ERR_FAIL,
 337 };
 338
 339 enum dmamov_dst {
 340         SAR = 0,
 341         CCR,
 342         DAR,
 343 };
 344
 345 enum pl330_dst {
 346         SRC = 0,
 347         DST,
 348 };
 349
 350 enum pl330_cond {
 351         SINGLE,
 352         BURST,
 353         ALWAYS,
 354 };
 355
 356 struct dma_pl330_desc;
 357
 358 struct _pl330_req {
 359         u32 mc_bus;
 360         void *mc_cpu;
 361         struct dma_pl330_desc *desc;
 362 };
 363
 364 /* ToBeDone for tasklet */
 365 struct _pl330_tbd {
 366         bool reset_dmac;
 367         bool reset_mngr;
 368         u8 reset_chan;
 369 };
 370
 371 /* A DMAC Thread */
 372 struct pl330_thread {
 373         u8 id;
 374         int ev;
 375         /* If the channel is not yet acquired by any client */
 376         bool free;
 377         /* Parent DMAC */
 378         struct pl330_dmac *dmac;
 379         /* Only two at a time */
 380         struct _pl330_req req[2];
 381         /* Index of the last enqueued request */
 382         unsigned lstenq;
 383         /* Index of the last submitted request or -1 if the DMA is stopped */
 384         int req_running;
 385 };
 386
 387 enum pl330_dmac_state {
 388         UNINIT,
 389         INIT,
 390         DYING,
 391 };
 392
 393 enum desc_status {
 394         /* In the DMAC pool */
 395         FREE,
 396         /*
 397          * Allocated to some channel during prep_xxx
 398          * Also may be sitting on the work_list.
 399          */
 400         PREP,
 401         /*
 402          * Sitting on the work_list and already submitted
 403          * to the PL330 core. Not more than two descriptors
 404          * of a channel can be BUSY at any time.
 405          */
 406         BUSY,
 407         /*
 408          * Sitting on the channel work_list but xfer done
 409          * by PL330 core
 410          */
 411         DONE,
 412 };
 413
 414 struct dma_pl330_chan {
 415         /* Schedule desc completion */
 416         struct tasklet_struct task;
 417
 418         /* DMA-Engine Channel */
 419         struct dma_chan chan;
 420
 421         /* List of submitted descriptors */
 422         struct list_head submitted_list;
 423         /* List of issued descriptors */
 424         struct list_head work_list;
 425         /* List of completed descriptors */
 426         struct list_head completed_list;
 427
 428         /* Pointer to the DMAC that manages this channel,
 429          * NULL if the channel is available to be acquired.
 430          * As the parent, this DMAC also provides descriptors
 431          * to the channel.
 432          */
 433         struct pl330_dmac *dmac;
 434
 435         /* To protect channel manipulation */
 436         spinlock_t lock;
 437
 438         /*
 439          * Hardware channel thread of PL330 DMAC. NULL if the channel is
 440          * available.
 441          */
 442         struct pl330_thread *thread;
 443
 444         /* For D-to-M and M-to-D channels */
 445         int burst_sz; /* the peripheral fifo width */
 446         int burst_len; /* the number of burst */
 447         dma_addr_t fifo_addr;
 448
 449         /* for cyclic capability */
 450         bool cyclic;
 451
 452         /* for runtime pm tracking */
 453         bool active;
 454 };
 455
 456 struct pl330_dmac {
 457         /* DMA-Engine Device */
 458         struct dma_device ddma;
 459
 460         /* Holds info about sg limitations */
 461         struct device_dma_parameters dma_parms;
 462
 463         /* Pool of descriptors available for the DMAC's channels */
 464         struct list_head desc_pool;
 465         /* To protect desc_pool manipulation */
 466         spinlock_t pool_lock;
 467
 468         /* Size of MicroCode buffers for each channel. */
 469         unsigned mcbufsz;
 470         /* ioremap'ed address of PL330 registers. */
 471         void __iomem    *base;
 472         /* Populated by the PL330 core driver during pl330_add */
 473         struct pl330_config     pcfg;
 474
 475         spinlock_t              lock;
 476         /* Maximum possible events/irqs */
 477         int                     events[32];
 478         /* BUS address of MicroCode buffer */
 479         dma_addr_t              mcode_bus;
 480         /* CPU address of MicroCode buffer */
 481         void                    *mcode_cpu;
 482         /* List of all Channel threads */
 483         struct pl330_thread     *channels;
 484         /* Pointer to the MANAGER thread */
 485         struct pl330_thread     *manager;
 486         /* To handle bad news in interrupt */
 487         struct tasklet_struct   tasks;
 488         struct _pl330_tbd       dmac_tbd;
 489         /* State of DMAC operation */
 490         enum pl330_dmac_state   state;
 491         /* Holds list of reqs with due callbacks */
 492         struct list_head        req_done;
 493
 494         /* Peripheral channels connected to this DMAC */
 495         unsigned int num_peripherals;
 496         struct dma_pl330_chan *peripherals; /* keep at end */
 497         int quirks;
 498 };
 499
 500 static struct pl330_of_quirks {
 501         char *quirk;
 502         int id;
 503 } of_quirks[] = {
 504         {
 505                 .quirk = "arm,pl330-broken-no-flushp",
 506                 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
 507         }
 508 };
 509
 510 struct dma_pl330_desc {
 511         /* To attach to a queue as child */
 512         struct list_head node;
 513
 514         /* Descriptor for the DMA Engine API */
 515         struct dma_async_tx_descriptor txd;
 516
 517         /* Xfer for PL330 core */
 518         struct pl330_xfer px;
 519
 520         struct pl330_reqcfg rqcfg;
 521
 522         enum desc_status status;
 523
 524         int bytes_requested;
 525         bool last;
 526
 527         /* The channel which currently holds this desc */
 528         struct dma_pl330_chan *pchan;
 529
 530         enum dma_transfer_direction rqtype;
 531         /* Index of peripheral for the xfer. */
 532         unsigned peri:5;
 533         /* Hook to attach to DMAC's list of reqs with due callback */
 534         struct list_head rqd;
 535 };
 536
 537 struct _xfer_spec {
 538         u32 ccr;
 539         struct dma_pl330_desc *desc;
 540 };
 541
 542 static inline bool _queue_empty(struct pl330_thread *thrd)
 543 {
 544         return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
 545 }
 546
 547 static inline bool _queue_full(struct pl330_thread *thrd)
 548 {
 549         return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
 550 }
 551
 552 static inline bool is_manager(struct pl330_thread *thrd)
 553 {
 554         return thrd->dmac->manager == thrd;
 555 }
 556
 557 /* If manager of the thread is in Non-Secure mode */
 558 static inline bool _manager_ns(struct pl330_thread *thrd)
 559 {
 560         return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
 561 }
 562
 563 static inline u32 get_revision(u32 periph_id)
 564 {
 565         return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
 566 }
 567
 568 static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
 569                 enum pl330_dst da, u16 val)
 570 {
 571         if (dry_run)
 572                 return SZ_DMAADDH;
 573
 574         buf[0] = CMD_DMAADDH;
 575         buf[0] |= (da << 1);
 576         buf[1] = val;
 577         buf[2] = val >> 8;
 578
 579         PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
 580                 da == 1 ? "DA" : "SA", val);
 581
 582         return SZ_DMAADDH;
 583 }
 584
 585 static inline u32 _emit_END(unsigned dry_run, u8 buf[])
 586 {
 587         if (dry_run)
 588                 return SZ_DMAEND;
 589
 590         buf[0] = CMD_DMAEND;
 591
 592         PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
 593
 594         return SZ_DMAEND;
 595 }
 596
 597 static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
 598 {
 599         if (dry_run)
 600                 return SZ_DMAFLUSHP;
 601
 602         buf[0] = CMD_DMAFLUSHP;
 603
 604         peri &= 0x1f;
 605         peri <<= 3;
 606         buf[1] = peri;
 607
 608         PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
 609
 610         return SZ_DMAFLUSHP;
 611 }
 612
 613 static inline u32 _emit_LD(unsigned dry_run, u8 buf[],  enum pl330_cond cond)
 614 {
 615         if (dry_run)
 616                 return SZ_DMALD;
 617
 618         buf[0] = CMD_DMALD;
 619
 620         if (cond == SINGLE)
 621                 buf[0] |= (0 << 1) | (1 << 0);
 622         else if (cond == BURST)
 623                 buf[0] |= (1 << 1) | (1 << 0);
 624
 625         PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
 626                 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
 627
 628         return SZ_DMALD;
 629 }
 630
 631 static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
 632                 enum pl330_cond cond, u8 peri)
 633 {
 634         if (dry_run)
 635                 return SZ_DMALDP;
 636
 637         buf[0] = CMD_DMALDP;
 638
 639         if (cond == BURST)
 640                 buf[0] |= (1 << 1);
 641
 642         peri &= 0x1f;
 643         peri <<= 3;
 644         buf[1] = peri;
 645
 646         PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
 647                 cond == SINGLE ? 'S' : 'B', peri >> 3);
 648
 649         return SZ_DMALDP;
 650 }
 651
 652 static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
 653                 unsigned loop, u8 cnt)
 654 {
 655         if (dry_run)
 656                 return SZ_DMALP;
 657
 658         buf[0] = CMD_DMALP;
 659
 660         if (loop)
 661                 buf[0] |= (1 << 1);
 662
 663         cnt--; /* DMAC increments by 1 internally */
 664         buf[1] = cnt;
 665
 666         PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
 667
 668         return SZ_DMALP;
 669 }
 670
 671 struct _arg_LPEND {
 672         enum pl330_cond cond;
 673         bool forever;
 674         unsigned loop;
 675         u8 bjump;
 676 };
 677
 678 static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
 679                 const struct _arg_LPEND *arg)
 680 {
 681         enum pl330_cond cond = arg->cond;
 682         bool forever = arg->forever;
 683         unsigned loop = arg->loop;
 684         u8 bjump = arg->bjump;
 685
 686         if (dry_run)
 687                 return SZ_DMALPEND;
 688
 689         buf[0] = CMD_DMALPEND;
 690
 691         if (loop)
 692                 buf[0] |= (1 << 2);
 693
 694         if (!forever)
 695                 buf[0] |= (1 << 4);
 696
 697         if (cond == SINGLE)
 698                 buf[0] |= (0 << 1) | (1 << 0);
 699         else if (cond == BURST)
 700                 buf[0] |= (1 << 1) | (1 << 0);
 701
 702         buf[1] = bjump;
 703
 704         PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
 705                         forever ? "FE" : "END",
 706                         cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
 707                         loop ? '1' : '0',
 708                         bjump);
 709
 710         return SZ_DMALPEND;
 711 }
 712
 713 static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
 714 {
 715         if (dry_run)
 716                 return SZ_DMAKILL;
 717
 718         buf[0] = CMD_DMAKILL;
 719
 720         return SZ_DMAKILL;
 721 }
 722
 723 static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
 724                 enum dmamov_dst dst, u32 val)
 725 {
 726         if (dry_run)
 727                 return SZ_DMAMOV;
 728
 729         buf[0] = CMD_DMAMOV;
 730         buf[1] = dst;
 731         buf[2] = val;
 732         buf[3] = val >> 8;
 733         buf[4] = val >> 16;
 734         buf[5] = val >> 24;
 735
 736         PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
 737                 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
 738
 739         return SZ_DMAMOV;
 740 }
 741
 742 static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
 743 {
 744         if (dry_run)
 745                 return SZ_DMANOP;
 746
 747         buf[0] = CMD_DMANOP;
 748
 749         PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
 750
 751         return SZ_DMANOP;
 752 }
 753
 754 static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
 755 {
 756         if (dry_run)
 757                 return SZ_DMARMB;
 758
 759         buf[0] = CMD_DMARMB;
 760
 761         PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
 762
 763         return SZ_DMARMB;
 764 }
 765
 766 static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
 767 {
 768         if (dry_run)
 769                 return SZ_DMASEV;
 770
 771         buf[0] = CMD_DMASEV;
 772
 773         ev &= 0x1f;
 774         ev <<= 3;
 775         buf[1] = ev;
 776
 777         PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
 778
 779         return SZ_DMASEV;
 780 }
 781
 782 static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
 783 {
 784         if (dry_run)
 785                 return SZ_DMAST;
 786
 787         buf[0] = CMD_DMAST;
 788
 789         if (cond == SINGLE)
 790                 buf[0] |= (0 << 1) | (1 << 0);
 791         else if (cond == BURST)
 792                 buf[0] |= (1 << 1) | (1 << 0);
 793
 794         PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
 795                 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
 796
 797         return SZ_DMAST;
 798 }
 799
 800 static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
 801                 enum pl330_cond cond, u8 peri)
 802 {
 803         if (dry_run)
 804                 return SZ_DMASTP;
 805
 806         buf[0] = CMD_DMASTP;
 807
 808         if (cond == BURST)
 809                 buf[0] |= (1 << 1);
 810
 811         peri &= 0x1f;
 812         peri <<= 3;
 813         buf[1] = peri;
 814
 815         PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
 816                 cond == SINGLE ? 'S' : 'B', peri >> 3);
 817
 818         return SZ_DMASTP;
 819 }
 820
 821 static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
 822 {
 823         if (dry_run)
 824                 return SZ_DMASTZ;
 825
 826         buf[0] = CMD_DMASTZ;
 827
 828         PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
 829
 830         return SZ_DMASTZ;
 831 }
 832
 833 static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
 834                 unsigned invalidate)
 835 {
 836         if (dry_run)
 837                 return SZ_DMAWFE;
 838
 839         buf[0] = CMD_DMAWFE;
 840
 841         ev &= 0x1f;
 842         ev <<= 3;
 843         buf[1] = ev;
 844
 845         if (invalidate)
 846                 buf[1] |= (1 << 1);
 847
 848         PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
 849                 ev >> 3, invalidate ? ", I" : "");
 850
 851         return SZ_DMAWFE;
 852 }
 853
 854 static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
 855                 enum pl330_cond cond, u8 peri)
 856 {
 857         if (dry_run)
 858                 return SZ_DMAWFP;
 859
 860         buf[0] = CMD_DMAWFP;
 861
 862         if (cond == SINGLE)
 863                 buf[0] |= (0 << 1) | (0 << 0);
 864         else if (cond == BURST)
 865                 buf[0] |= (1 << 1) | (0 << 0);
 866         else
 867                 buf[0] |= (0 << 1) | (1 << 0);
 868
 869         peri &= 0x1f;
 870         peri <<= 3;
 871         buf[1] = peri;
 872
 873         PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
 874                 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
 875
 876         return SZ_DMAWFP;
 877 }
 878
 879 static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
 880 {
 881         if (dry_run)
 882                 return SZ_DMAWMB;
 883
 884         buf[0] = CMD_DMAWMB;
 885
 886         PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
 887
 888         return SZ_DMAWMB;
 889 }
 890
 891 struct _arg_GO {
 892         u8 chan;
 893         u32 addr;
 894         unsigned ns;
 895 };
 896
 897 static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
 898                 const struct _arg_GO *arg)
 899 {
 900         u8 chan = arg->chan;
 901         u32 addr = arg->addr;
 902         unsigned ns = arg->ns;
 903
 904         if (dry_run)
 905                 return SZ_DMAGO;
 906
 907         buf[0] = CMD_DMAGO;
 908         buf[0] |= (ns << 1);
 909         buf[1] = chan & 0x7;
 910         buf[2] = addr;
 911         buf[3] = addr >> 8;
 912         buf[4] = addr >> 16;
 913         buf[5] = addr >> 24;
 914
 915         return SZ_DMAGO;
 916 }
 917
 918 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 919
 920 /* Returns Time-Out */
 921 static bool _until_dmac_idle(struct pl330_thread *thrd)
 922 {
 923         void __iomem *regs = thrd->dmac->base;
 924         unsigned long loops = msecs_to_loops(5);
 925
 926         do {
 927                 /* Until Manager is Idle */
 928                 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
 929                         break;
 930
 931                 cpu_relax();
 932         } while (--loops);
 933
 934         if (!loops)
 935                 return true;
 936
 937         return false;
 938 }
 939
 940 static inline void _execute_DBGINSN(struct pl330_thread *thrd,
 941                 u8 insn[], bool as_manager)
 942 {
 943         void __iomem *regs = thrd->dmac->base;
 944         u32 val;
 945
 946         val = (insn[0] << 16) | (insn[1] << 24);
 947         if (!as_manager) {
 948                 val |= (1 << 0);
 949                 val |= (thrd->id << 8); /* Channel Number */
 950         }
 951         writel(val, regs + DBGINST0);
 952
 953         val = le32_to_cpu(*((__le32 *)&insn[2]));
 954         writel(val, regs + DBGINST1);
 955
 956         /* If timed out due to halted state-machine */
 957         if (_until_dmac_idle(thrd)) {
 958                 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
 959                 return;
 960         }
 961
 962         /* Get going */
 963         writel(0, regs + DBGCMD);
 964 }
 965
 966 static inline u32 _state(struct pl330_thread *thrd)
 967 {
 968         void __iomem *regs = thrd->dmac->base;
 969         u32 val;
 970
 971         if (is_manager(thrd))
 972                 val = readl(regs + DS) & 0xf;
 973         else
 974                 val = readl(regs + CS(thrd->id)) & 0xf;
 975
 976         switch (val) {
 977         case DS_ST_STOP:
 978                 return PL330_STATE_STOPPED;
 979         case DS_ST_EXEC:
 980                 return PL330_STATE_EXECUTING;
 981         case DS_ST_CMISS:
 982                 return PL330_STATE_CACHEMISS;
 983         case DS_ST_UPDTPC:
 984                 return PL330_STATE_UPDTPC;
 985         case DS_ST_WFE:
 986                 return PL330_STATE_WFE;
 987         case DS_ST_FAULT:
 988                 return PL330_STATE_FAULTING;
 989         case DS_ST_ATBRR:
 990                 if (is_manager(thrd))
 991                         return PL330_STATE_INVALID;
 992                 else
 993                         return PL330_STATE_ATBARRIER;
 994         case DS_ST_QBUSY:
 995                 if (is_manager(thrd))
 996                         return PL330_STATE_INVALID;
 997                 else
 998                         return PL330_STATE_QUEUEBUSY;
 999         case DS_ST_WFP:
1000                 if (is_manager(thrd))
1001                         return PL330_STATE_INVALID;
1002                 else
1003                         return PL330_STATE_WFP;
1004         case DS_ST_KILL:
1005                 if (is_manager(thrd))
1006                         return PL330_STATE_INVALID;
1007                 else
1008                         return PL330_STATE_KILLING;
1009         case DS_ST_CMPLT:
1010                 if (is_manager(thrd))
1011                         return PL330_STATE_INVALID;
1012                 else
1013                         return PL330_STATE_COMPLETING;
1014         case DS_ST_FLTCMP:
1015                 if (is_manager(thrd))
1016                         return PL330_STATE_INVALID;
1017                 else
1018                         return PL330_STATE_FAULT_COMPLETING;
1019         default:
1020                 return PL330_STATE_INVALID;
1021         }
1022 }
1023
1024 static void _stop(struct pl330_thread *thrd)
1025 {
1026         void __iomem *regs = thrd->dmac->base;
1027         u8 insn[6] = {0, 0, 0, 0, 0, 0};
1028
1029         if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1030                 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1031
1032         /* Return if nothing needs to be done */
1033         if (_state(thrd) == PL330_STATE_COMPLETING
1034                   || _state(thrd) == PL330_STATE_KILLING
1035                   || _state(thrd) == PL330_STATE_STOPPED)
1036                 return;
1037
1038         _emit_KILL(0, insn);
1039
1040         /* Stop generating interrupts for SEV */
1041         writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1042
1043         _execute_DBGINSN(thrd, insn, is_manager(thrd));
1044 }
1045
1046 /* Start doing req 'idx' of thread 'thrd' */
1047 static bool _trigger(struct pl330_thread *thrd)
1048 {
1049         void __iomem *regs = thrd->dmac->base;
1050         struct _pl330_req *req;
1051         struct dma_pl330_desc *desc;
1052         struct _arg_GO go;
1053         unsigned ns;
1054         u8 insn[6] = {0, 0, 0, 0, 0, 0};
1055         int idx;
1056
1057         /* Return if already ACTIVE */
1058         if (_state(thrd) != PL330_STATE_STOPPED)
1059                 return true;
1060
1061         idx = 1 - thrd->lstenq;
1062         if (thrd->req[idx].desc != NULL) {
1063                 req = &thrd->req[idx];
1064         } else {
1065                 idx = thrd->lstenq;
1066                 if (thrd->req[idx].desc != NULL)
1067                         req = &thrd->req[idx];
1068                 else
1069                         req = NULL;
1070         }
1071
1072         /* Return if no request */
1073         if (!req)
1074                 return true;
1075
1076         /* Return if req is running */
1077         if (idx == thrd->req_running)
1078                 return true;
1079
1080         desc = req->desc;
1081
1082         ns = desc->rqcfg.nonsecure ? 1 : 0;
1083
1084         /* See 'Abort Sources' point-4 at Page 2-25 */
1085         if (_manager_ns(thrd) && !ns)
1086                 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1087                         __func__, __LINE__);
1088
1089         go.chan = thrd->id;
1090         go.addr = req->mc_bus;
1091         go.ns = ns;
1092         _emit_GO(0, insn, &go);
1093
1094         /* Set to generate interrupts for SEV */
1095         writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1096
1097         /* Only manager can execute GO */
1098         _execute_DBGINSN(thrd, insn, true);
1099
1100         thrd->req_running = idx;
1101
1102         return true;
1103 }
1104
1105 static bool _start(struct pl330_thread *thrd)
1106 {
1107         switch (_state(thrd)) {
1108         case PL330_STATE_FAULT_COMPLETING:
1109                 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1110
1111                 if (_state(thrd) == PL330_STATE_KILLING)
1112                         UNTIL(thrd, PL330_STATE_STOPPED)
1113
1114         case PL330_STATE_FAULTING:
1115                 _stop(thrd);
1116
1117         case PL330_STATE_KILLING:
1118         case PL330_STATE_COMPLETING:
1119                 UNTIL(thrd, PL330_STATE_STOPPED)
1120
1121         case PL330_STATE_STOPPED:
1122                 return _trigger(thrd);
1123
1124         case PL330_STATE_WFP:
1125         case PL330_STATE_QUEUEBUSY:
1126         case PL330_STATE_ATBARRIER:
1127         case PL330_STATE_UPDTPC:
1128         case PL330_STATE_CACHEMISS:
1129         case PL330_STATE_EXECUTING:
1130                 return true;
1131
1132         case PL330_STATE_WFE: /* For RESUME, nothing yet */
1133         default:
1134                 return false;
1135         }
1136 }
1137
1138 static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1139                 const struct _xfer_spec *pxs, int cyc)
1140 {
1141         int off = 0;
1142         struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1143
1144         /* check lock-up free version */
1145         if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1146                 while (cyc--) {
1147                         off += _emit_LD(dry_run, &buf[off], ALWAYS);
1148                         off += _emit_ST(dry_run, &buf[off], ALWAYS);
1149                 }
1150         } else {
1151                 while (cyc--) {
1152                         off += _emit_LD(dry_run, &buf[off], ALWAYS);
1153                         off += _emit_RMB(dry_run, &buf[off]);
1154                         off += _emit_ST(dry_run, &buf[off], ALWAYS);
1155                         off += _emit_WMB(dry_run, &buf[off]);
1156                 }
1157         }
1158
1159         return off;
1160 }
1161
1162 static inline int _ldst_devtomem(struct pl330_dmac *pl330, unsigned dry_run,
1163                                  u8 buf[], const struct _xfer_spec *pxs,
1164                                  int cyc)
1165 {
1166         int off = 0;
1167         enum pl330_cond cond;
1168
1169         if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1170                 cond = BURST;
1171         else
1172                 cond = SINGLE;
1173
1174         while (cyc--) {
1175                 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1176                 off += _emit_LDP(dry_run, &buf[off], cond, pxs->desc->peri);
1177                 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1178
1179                 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1180                         off += _emit_FLUSHP(dry_run, &buf[off],
1181                                             pxs->desc->peri);
1182         }
1183
1184         return off;
1185 }
1186
1187 static inline int _ldst_memtodev(struct pl330_dmac *pl330,
1188                                  unsigned dry_run, u8 buf[],
1189                                  const struct _xfer_spec *pxs, int cyc)
1190 {
1191         int off = 0;
1192         enum pl330_cond cond;
1193
1194         if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1195                 cond = BURST;
1196         else
1197                 cond = SINGLE;
1198
1199         while (cyc--) {
1200                 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1201                 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1202                 off += _emit_STP(dry_run, &buf[off], cond, pxs->desc->peri);
1203
1204                 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1205                         off += _emit_FLUSHP(dry_run, &buf[off],
1206                                             pxs->desc->peri);
1207         }
1208
1209         return off;
1210 }
1211
1212 static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1213                 const struct _xfer_spec *pxs, int cyc)
1214 {
1215         int off = 0;
1216
1217         switch (pxs->desc->rqtype) {
1218         case DMA_MEM_TO_DEV:
1219                 off += _ldst_memtodev(pl330, dry_run, &buf[off], pxs, cyc);
1220                 break;
1221         case DMA_DEV_TO_MEM:
1222                 off += _ldst_devtomem(pl330, dry_run, &buf[off], pxs, cyc);
1223                 break;
1224         case DMA_MEM_TO_MEM:
1225                 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1226                 break;
1227         default:
1228                 off += 0x40000000; /* Scare off the Client */
1229                 break;
1230         }
1231
1232         return off;
1233 }
1234
1235 /* Returns bytes consumed and updates bursts */
1236 static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1237                 unsigned long *bursts, const struct _xfer_spec *pxs)
1238 {
1239         int cyc, cycmax, szlp, szlpend, szbrst, off;
1240         unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1241         struct _arg_LPEND lpend;
1242
1243         if (*bursts == 1)
1244                 return _bursts(pl330, dry_run, buf, pxs, 1);
1245
1246         /* Max iterations possible in DMALP is 256 */
1247         if (*bursts >= 256*256) {
1248                 lcnt1 = 256;
1249                 lcnt0 = 256;
1250                 cyc = *bursts / lcnt1 / lcnt0;
1251         } else if (*bursts > 256) {
1252                 lcnt1 = 256;
1253                 lcnt0 = *bursts / lcnt1;
1254                 cyc = 1;
1255         } else {
1256                 lcnt1 = *bursts;
1257                 lcnt0 = 0;
1258                 cyc = 1;
1259         }
1260
1261         szlp = _emit_LP(1, buf, 0, 0);
1262         szbrst = _bursts(pl330, 1, buf, pxs, 1);
1263
1264         lpend.cond = ALWAYS;
1265         lpend.forever = false;
1266         lpend.loop = 0;
1267         lpend.bjump = 0;
1268         szlpend = _emit_LPEND(1, buf, &lpend);
1269
1270         if (lcnt0) {
1271                 szlp *= 2;
1272                 szlpend *= 2;
1273         }
1274
1275         /*
1276          * Max bursts that we can unroll due to limit on the
1277          * size of backward jump that can be encoded in DMALPEND
1278          * which is 8-bits and hence 255
1279          */
1280         cycmax = (255 - (szlp + szlpend)) / szbrst;
1281
1282         cyc = (cycmax < cyc) ? cycmax : cyc;
1283
1284         off = 0;
1285
1286         if (lcnt0) {
1287                 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1288                 ljmp0 = off;
1289         }
1290
1291         off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1292         ljmp1 = off;
1293
1294         off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1295
1296         lpend.cond = ALWAYS;
1297         lpend.forever = false;
1298         lpend.loop = 1;
1299         lpend.bjump = off - ljmp1;
1300         off += _emit_LPEND(dry_run, &buf[off], &lpend);
1301
1302         if (lcnt0) {
1303                 lpend.cond = ALWAYS;
1304                 lpend.forever = false;
1305                 lpend.loop = 0;
1306                 lpend.bjump = off - ljmp0;
1307                 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1308         }
1309
1310         *bursts = lcnt1 * cyc;
1311         if (lcnt0)
1312                 *bursts *= lcnt0;
1313
1314         return off;
1315 }
1316
1317 static inline int _setup_loops(struct pl330_dmac *pl330,
1318                                unsigned dry_run, u8 buf[],
1319                                const struct _xfer_spec *pxs)
1320 {
1321         struct pl330_xfer *x = &pxs->desc->px;
1322         u32 ccr = pxs->ccr;
1323         unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1324         int off = 0;
1325
1326         while (bursts) {
1327                 c = bursts;
1328                 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1329                 bursts -= c;
1330         }
1331
1332         return off;
1333 }
1334
1335 static inline int _setup_xfer(struct pl330_dmac *pl330,
1336                               unsigned dry_run, u8 buf[],
1337                               const struct _xfer_spec *pxs)
1338 {
1339         struct pl330_xfer *x = &pxs->desc->px;
1340         int off = 0;
1341
1342         /* DMAMOV SAR, x->src_addr */
1343         off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1344         /* DMAMOV DAR, x->dst_addr */
1345         off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1346
1347         /* Setup Loop(s) */
1348         off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1349
1350         return off;
1351 }
1352
1353 /*
1354  * A req is a sequence of one or more xfer units.
1355  * Returns the number of bytes taken to setup the MC for the req.
1356  */
1357 static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1358                       struct pl330_thread *thrd, unsigned index,
1359                       struct _xfer_spec *pxs)
1360 {
1361         struct _pl330_req *req = &thrd->req[index];
1362         struct pl330_xfer *x;
1363         u8 *buf = req->mc_cpu;
1364         int off = 0;
1365
1366         PL330_DBGMC_START(req->mc_bus);
1367
1368         /* DMAMOV CCR, ccr */
1369         off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1370
1371         x = &pxs->desc->px;
1372         /* Error if xfer length is not aligned at burst size */
1373         if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1374                 return -EINVAL;
1375
1376         off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1377
1378         /* DMASEV peripheral/event */
1379         off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1380         /* DMAEND */
1381         off += _emit_END(dry_run, &buf[off]);
1382
1383         return off;
1384 }
1385
1386 static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1387 {
1388         u32 ccr = 0;
1389
1390         if (rqc->src_inc)
1391                 ccr |= CC_SRCINC;
1392
1393         if (rqc->dst_inc)
1394                 ccr |= CC_DSTINC;
1395
1396         /* We set same protection levels for Src and DST for now */
1397         if (rqc->privileged)
1398                 ccr |= CC_SRCPRI | CC_DSTPRI;
1399         if (rqc->nonsecure)
1400                 ccr |= CC_SRCNS | CC_DSTNS;
1401         if (rqc->insnaccess)
1402                 ccr |= CC_SRCIA | CC_DSTIA;
1403
1404         ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1405         ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1406
1407         ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1408         ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1409
1410         ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1411         ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1412
1413         ccr |= (rqc->swap << CC_SWAP_SHFT);
1414
1415         return ccr;
1416 }
1417
1418 /*
1419  * Submit a list of xfers after which the client wants notification.
1420  * Client is not notified after each xfer unit, just once after all
1421  * xfer units are done or some error occurs.
1422  */
1423 static int pl330_submit_req(struct pl330_thread *thrd,
1424         struct dma_pl330_desc *desc)
1425 {
1426         struct pl330_dmac *pl330 = thrd->dmac;
1427         struct _xfer_spec xs;
1428         unsigned long flags;
1429         unsigned idx;
1430         u32 ccr;
1431         int ret = 0;
1432
1433         if (pl330->state == DYING
1434                 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1435                 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1436                         __func__, __LINE__);
1437                 return -EAGAIN;
1438         }
1439
1440         /* If request for non-existing peripheral */
1441         if (desc->rqtype != DMA_MEM_TO_MEM &&
1442             desc->peri >= pl330->pcfg.num_peri) {
1443                 dev_info(thrd->dmac->ddma.dev,
1444                                 "%s:%d Invalid peripheral(%u)!\n",
1445                                 __func__, __LINE__, desc->peri);
1446                 return -EINVAL;
1447         }
1448
1449         spin_lock_irqsave(&pl330->lock, flags);
1450
1451         if (_queue_full(thrd)) {
1452                 ret = -EAGAIN;
1453                 goto xfer_exit;
1454         }
1455
1456         /* Prefer Secure Channel */
1457         if (!_manager_ns(thrd))
1458                 desc->rqcfg.nonsecure = 0;
1459         else
1460                 desc->rqcfg.nonsecure = 1;
1461
1462         ccr = _prepare_ccr(&desc->rqcfg);
1463
1464         idx = thrd->req[0].desc == NULL ? 0 : 1;
1465
1466         xs.ccr = ccr;
1467         xs.desc = desc;
1468
1469         /* First dry run to check if req is acceptable */
1470         ret = _setup_req(pl330, 1, thrd, idx, &xs);
1471         if (ret < 0)
1472                 goto xfer_exit;
1473
1474         if (ret > pl330->mcbufsz / 2) {
1475                 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1476                                 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1477                 ret = -ENOMEM;
1478                 goto xfer_exit;
1479         }
1480
1481         /* Hook the request */
1482         thrd->lstenq = idx;
1483         thrd->req[idx].desc = desc;
1484         _setup_req(pl330, 0, thrd, idx, &xs);
1485
1486         ret = 0;
1487
1488 xfer_exit:
1489         spin_unlock_irqrestore(&pl330->lock, flags);
1490
1491         return ret;
1492 }
1493
1494 static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1495 {
1496         struct dma_pl330_chan *pch;
1497         unsigned long flags;
1498
1499         if (!desc)
1500                 return;
1501
1502         pch = desc->pchan;
1503
1504         /* If desc aborted */
1505         if (!pch)
1506                 return;
1507
1508         spin_lock_irqsave(&pch->lock, flags);
1509
1510         desc->status = DONE;
1511
1512         spin_unlock_irqrestore(&pch->lock, flags);
1513
1514         tasklet_schedule(&pch->task);
1515 }
1516
1517 static void pl330_dotask(unsigned long data)
1518 {
1519         struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1520         unsigned long flags;
1521         int i;
1522
1523         spin_lock_irqsave(&pl330->lock, flags);
1524
1525         /* The DMAC itself gone nuts */
1526         if (pl330->dmac_tbd.reset_dmac) {
1527                 pl330->state = DYING;
1528                 /* Reset the manager too */
1529                 pl330->dmac_tbd.reset_mngr = true;
1530                 /* Clear the reset flag */
1531                 pl330->dmac_tbd.reset_dmac = false;
1532         }
1533
1534         if (pl330->dmac_tbd.reset_mngr) {
1535                 _stop(pl330->manager);
1536                 /* Reset all channels */
1537                 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1538                 /* Clear the reset flag */
1539                 pl330->dmac_tbd.reset_mngr = false;
1540         }
1541
1542         for (i = 0; i < pl330->pcfg.num_chan; i++) {
1543
1544                 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1545                         struct pl330_thread *thrd = &pl330->channels[i];
1546                         void __iomem *regs = pl330->base;
1547                         enum pl330_op_err err;
1548
1549                         _stop(thrd);
1550
1551                         if (readl(regs + FSC) & (1 << thrd->id))
1552                                 err = PL330_ERR_FAIL;
1553                         else
1554                                 err = PL330_ERR_ABORT;
1555
1556                         spin_unlock_irqrestore(&pl330->lock, flags);
1557                         dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1558                         dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1559                         spin_lock_irqsave(&pl330->lock, flags);
1560
1561                         thrd->req[0].desc = NULL;
1562                         thrd->req[1].desc = NULL;
1563                         thrd->req_running = -1;
1564
1565                         /* Clear the reset flag */
1566                         pl330->dmac_tbd.reset_chan &= ~(1 << i);
1567                 }
1568         }
1569
1570         spin_unlock_irqrestore(&pl330->lock, flags);
1571
1572         return;
1573 }
1574
1575 /* Returns 1 if state was updated, 0 otherwise */
1576 static int pl330_update(struct pl330_dmac *pl330)
1577 {
1578         struct dma_pl330_desc *descdone, *tmp;
1579         unsigned long flags;
1580         void __iomem *regs;
1581         u32 val;
1582         int id, ev, ret = 0;
1583
1584         regs = pl330->base;
1585
1586         spin_lock_irqsave(&pl330->lock, flags);
1587
1588         val = readl(regs + FSM) & 0x1;
1589         if (val)
1590                 pl330->dmac_tbd.reset_mngr = true;
1591         else
1592                 pl330->dmac_tbd.reset_mngr = false;
1593
1594         val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1595         pl330->dmac_tbd.reset_chan |= val;
1596         if (val) {
1597                 int i = 0;
1598                 while (i < pl330->pcfg.num_chan) {
1599                         if (val & (1 << i)) {
1600                                 dev_info(pl330->ddma.dev,
1601                                         "Reset Channel-%d\t CS-%x FTC-%x\n",
1602                                                 i, readl(regs + CS(i)),
1603                                                 readl(regs + FTC(i)));
1604                                 _stop(&pl330->channels[i]);
1605                         }
1606                         i++;
1607                 }
1608         }
1609
1610         /* Check which event happened i.e, thread notified */
1611         val = readl(regs + ES);
1612         if (pl330->pcfg.num_events < 32
1613                         && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1614                 pl330->dmac_tbd.reset_dmac = true;
1615                 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1616                         __LINE__);
1617                 ret = 1;
1618                 goto updt_exit;
1619         }
1620
1621         for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1622                 if (val & (1 << ev)) { /* Event occurred */
1623                         struct pl330_thread *thrd;
1624                         u32 inten = readl(regs + INTEN);
1625                         int active;
1626
1627                         /* Clear the event */
1628                         if (inten & (1 << ev))
1629                                 writel(1 << ev, regs + INTCLR);
1630
1631                         ret = 1;
1632
1633                         id = pl330->events[ev];
1634
1635                         thrd = &pl330->channels[id];
1636
1637                         active = thrd->req_running;
1638                         if (active == -1) /* Aborted */
1639                                 continue;
1640
1641                         /* Detach the req */
1642                         descdone = thrd->req[active].desc;
1643                         thrd->req[active].desc = NULL;
1644
1645                         thrd->req_running = -1;
1646
1647                         /* Get going again ASAP */
1648                         _start(thrd);
1649
1650                         /* For now, just make a list of callbacks to be done */
1651                         list_add_tail(&descdone->rqd, &pl330->req_done);
1652                 }
1653         }
1654
1655         /* Now that we are in no hurry, do the callbacks */
1656         list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1657                 list_del(&descdone->rqd);
1658                 spin_unlock_irqrestore(&pl330->lock, flags);
1659                 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1660                 spin_lock_irqsave(&pl330->lock, flags);
1661         }
1662
1663 updt_exit:
1664         spin_unlock_irqrestore(&pl330->lock, flags);
1665
1666         if (pl330->dmac_tbd.reset_dmac
1667                         || pl330->dmac_tbd.reset_mngr
1668                         || pl330->dmac_tbd.reset_chan) {
1669                 ret = 1;
1670                 tasklet_schedule(&pl330->tasks);
1671         }
1672
1673         return ret;
1674 }
1675
1676 /* Reserve an event */
1677 static inline int _alloc_event(struct pl330_thread *thrd)
1678 {
1679         struct pl330_dmac *pl330 = thrd->dmac;
1680         int ev;
1681
1682         for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1683                 if (pl330->events[ev] == -1) {
1684                         pl330->events[ev] = thrd->id;
1685                         return ev;
1686                 }
1687
1688         return -1;
1689 }
1690
1691 static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1692 {
1693         return pl330->pcfg.irq_ns & (1 << i);
1694 }
1695
1696 /* Upon success, returns IdentityToken for the
1697  * allocated channel, NULL otherwise.
1698  */
1699 static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1700 {
1701         struct pl330_thread *thrd = NULL;
1702         int chans, i;
1703
1704         if (pl330->state == DYING)
1705                 return NULL;
1706
1707         chans = pl330->pcfg.num_chan;
1708
1709         for (i = 0; i < chans; i++) {
1710                 thrd = &pl330->channels[i];
1711                 if ((thrd->free) && (!_manager_ns(thrd) ||
1712                                         _chan_ns(pl330, i))) {
1713                         thrd->ev = _alloc_event(thrd);
1714                         if (thrd->ev >= 0) {
1715                                 thrd->free = false;
1716                                 thrd->lstenq = 1;
1717                                 thrd->req[0].desc = NULL;
1718                                 thrd->req[1].desc = NULL;
1719                                 thrd->req_running = -1;
1720                                 break;
1721                         }
1722                 }
1723                 thrd = NULL;
1724         }
1725
1726         return thrd;
1727 }
1728
1729 /* Release an event */
1730 static inline void _free_event(struct pl330_thread *thrd, int ev)
1731 {
1732         struct pl330_dmac *pl330 = thrd->dmac;
1733
1734         /* If the event is valid and was held by the thread */
1735         if (ev >= 0 && ev < pl330->pcfg.num_events
1736                         && pl330->events[ev] == thrd->id)
1737                 pl330->events[ev] = -1;
1738 }
1739
1740 static void pl330_release_channel(struct pl330_thread *thrd)
1741 {
1742         struct pl330_dmac *pl330;
1743
1744         if (!thrd || thrd->free)
1745                 return;
1746
1747         _stop(thrd);
1748
1749         dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1750         dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1751
1752         pl330 = thrd->dmac;
1753
1754         _free_event(thrd, thrd->ev);
1755         thrd->free = true;
1756 }
1757
1758 /* Initialize the structure for PL330 configuration, that can be used
1759  * by the client driver the make best use of the DMAC
1760  */
1761 static void read_dmac_config(struct pl330_dmac *pl330)
1762 {
1763         void __iomem *regs = pl330->base;
1764         u32 val;
1765
1766         val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1767         val &= CRD_DATA_WIDTH_MASK;
1768         pl330->pcfg.data_bus_width = 8 * (1 << val);
1769
1770         val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1771         val &= CRD_DATA_BUFF_MASK;
1772         pl330->pcfg.data_buf_dep = val + 1;
1773
1774         val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1775         val &= CR0_NUM_CHANS_MASK;
1776         val += 1;
1777         pl330->pcfg.num_chan = val;
1778
1779         val = readl(regs + CR0);
1780         if (val & CR0_PERIPH_REQ_SET) {
1781                 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1782                 val += 1;
1783                 pl330->pcfg.num_peri = val;
1784                 pl330->pcfg.peri_ns = readl(regs + CR4);
1785         } else {
1786                 pl330->pcfg.num_peri = 0;
1787         }
1788
1789         val = readl(regs + CR0);
1790         if (val & CR0_BOOT_MAN_NS)
1791                 pl330->pcfg.mode |= DMAC_MODE_NS;
1792         else
1793                 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1794
1795         val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1796         val &= CR0_NUM_EVENTS_MASK;
1797         val += 1;
1798         pl330->pcfg.num_events = val;
1799
1800         pl330->pcfg.irq_ns = readl(regs + CR3);
1801 }
1802
1803 static inline void _reset_thread(struct pl330_thread *thrd)
1804 {
1805         struct pl330_dmac *pl330 = thrd->dmac;
1806
1807         thrd->req[0].mc_cpu = pl330->mcode_cpu
1808                                 + (thrd->id * pl330->mcbufsz);
1809         thrd->req[0].mc_bus = pl330->mcode_bus
1810                                 + (thrd->id * pl330->mcbufsz);
1811         thrd->req[0].desc = NULL;
1812
1813         thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1814                                 + pl330->mcbufsz / 2;
1815         thrd->req[1].mc_bus = thrd->req[0].mc_bus
1816                                 + pl330->mcbufsz / 2;
1817         thrd->req[1].desc = NULL;
1818
1819         thrd->req_running = -1;
1820 }
1821
1822 static int dmac_alloc_threads(struct pl330_dmac *pl330)
1823 {
1824         int chans = pl330->pcfg.num_chan;
1825         struct pl330_thread *thrd;
1826         int i;
1827
1828         /* Allocate 1 Manager and 'chans' Channel threads */
1829         pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1830                                         GFP_KERNEL);
1831         if (!pl330->channels)
1832                 return -ENOMEM;
1833
1834         /* Init Channel threads */
1835         for (i = 0; i < chans; i++) {
1836                 thrd = &pl330->channels[i];
1837                 thrd->id = i;
1838                 thrd->dmac = pl330;
1839                 _reset_thread(thrd);
1840                 thrd->free = true;
1841         }
1842
1843         /* MANAGER is indexed at the end */
1844         thrd = &pl330->channels[chans];
1845         thrd->id = chans;
1846         thrd->dmac = pl330;
1847         thrd->free = false;
1848         pl330->manager = thrd;
1849
1850         return 0;
1851 }
1852
1853 static int dmac_alloc_resources(struct pl330_dmac *pl330)
1854 {
1855         int chans = pl330->pcfg.num_chan;
1856         int ret;
1857
1858         /*
1859          * Alloc MicroCode buffer for 'chans' Channel threads.
1860          * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1861          */
1862         pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
1863                                 chans * pl330->mcbufsz,
1864                                 &pl330->mcode_bus, GFP_KERNEL,
1865                                 DMA_ATTR_PRIVILEGED);
1866         if (!pl330->mcode_cpu) {
1867                 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1868                         __func__, __LINE__);
1869                 return -ENOMEM;
1870         }
1871
1872         ret = dmac_alloc_threads(pl330);
1873         if (ret) {
1874                 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1875                         __func__, __LINE__);
1876                 dma_free_coherent(pl330->ddma.dev,
1877                                 chans * pl330->mcbufsz,
1878                                 pl330->mcode_cpu, pl330->mcode_bus);
1879                 return ret;
1880         }
1881
1882         return 0;
1883 }
1884
1885 static int pl330_add(struct pl330_dmac *pl330)
1886 {
1887         int i, ret;
1888
1889         /* Check if we can handle this DMAC */
1890         if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1891                 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1892                         pl330->pcfg.periph_id);
1893                 return -EINVAL;
1894         }
1895
1896         /* Read the configuration of the DMAC */
1897         read_dmac_config(pl330);
1898
1899         if (pl330->pcfg.num_events == 0) {
1900                 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1901                         __func__, __LINE__);
1902                 return -EINVAL;
1903         }
1904
1905         spin_lock_init(&pl330->lock);
1906
1907         INIT_LIST_HEAD(&pl330->req_done);
1908
1909         /* Use default MC buffer size if not provided */
1910         if (!pl330->mcbufsz)
1911                 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1912
1913         /* Mark all events as free */
1914         for (i = 0; i < pl330->pcfg.num_events; i++)
1915                 pl330->events[i] = -1;
1916
1917         /* Allocate resources needed by the DMAC */
1918         ret = dmac_alloc_resources(pl330);
1919         if (ret) {
1920                 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1921                 return ret;
1922         }
1923
1924         tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1925
1926         pl330->state = INIT;
1927
1928         return 0;
1929 }
1930
1931 static int dmac_free_threads(struct pl330_dmac *pl330)
1932 {
1933         struct pl330_thread *thrd;
1934         int i;
1935
1936         /* Release Channel threads */
1937         for (i = 0; i < pl330->pcfg.num_chan; i++) {
1938                 thrd = &pl330->channels[i];
1939                 pl330_release_channel(thrd);
1940         }
1941
1942         /* Free memory */
1943         kfree(pl330->channels);
1944
1945         return 0;
1946 }
1947
1948 static void pl330_del(struct pl330_dmac *pl330)
1949 {
1950         pl330->state = UNINIT;
1951
1952         tasklet_kill(&pl330->tasks);
1953
1954         /* Free DMAC resources */
1955         dmac_free_threads(pl330);
1956
1957         dma_free_coherent(pl330->ddma.dev,
1958                 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1959                 pl330->mcode_bus);
1960 }
1961
1962 /* forward declaration */
1963 static struct amba_driver pl330_driver;
1964
1965 static inline struct dma_pl330_chan *
1966 to_pchan(struct dma_chan *ch)
1967 {
1968         if (!ch)
1969                 return NULL;
1970
1971         return container_of(ch, struct dma_pl330_chan, chan);
1972 }
1973
1974 static inline struct dma_pl330_desc *
1975 to_desc(struct dma_async_tx_descriptor *tx)
1976 {
1977         return container_of(tx, struct dma_pl330_desc, txd);
1978 }
1979
1980 static inline void fill_queue(struct dma_pl330_chan *pch)
1981 {
1982         struct dma_pl330_desc *desc;
1983         int ret;
1984
1985         list_for_each_entry(desc, &pch->work_list, node) {
1986
1987                 /* If already submitted */
1988                 if (desc->status == BUSY)
1989                         continue;
1990
1991                 ret = pl330_submit_req(pch->thread, desc);
1992                 if (!ret) {
1993                         desc->status = BUSY;
1994                 } else if (ret == -EAGAIN) {
1995                         /* QFull or DMAC Dying */
1996                         break;
1997                 } else {
1998                         /* Unacceptable request */
1999                         desc->status = DONE;
2000                         dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2001                                         __func__, __LINE__, desc->txd.cookie);
2002                         tasklet_schedule(&pch->task);
2003                 }
2004         }
2005 }
2006
2007 static void pl330_tasklet(unsigned long data)
2008 {
2009         struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2010         struct dma_pl330_desc *desc, *_dt;
2011         unsigned long flags;
2012         bool power_down = false;
2013
2014         spin_lock_irqsave(&pch->lock, flags);
2015
2016         /* Pick up ripe tomatoes */
2017         list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2018                 if (desc->status == DONE) {
2019                         if (!pch->cyclic)
2020                                 dma_cookie_complete(&desc->txd);
2021                         list_move_tail(&desc->node, &pch->completed_list);
2022                 }
2023
2024         /* Try to submit a req imm. next to the last completed cookie */
2025         fill_queue(pch);
2026
2027         if (list_empty(&pch->work_list)) {
2028                 spin_lock(&pch->thread->dmac->lock);
2029                 _stop(pch->thread);
2030                 spin_unlock(&pch->thread->dmac->lock);
2031                 power_down = true;
2032                 pch->active = false;
2033         } else {
2034                 /* Make sure the PL330 Channel thread is active */
2035                 spin_lock(&pch->thread->dmac->lock);
2036                 _start(pch->thread);
2037                 spin_unlock(&pch->thread->dmac->lock);
2038         }
2039
2040         while (!list_empty(&pch->completed_list)) {
2041                 struct dmaengine_desc_callback cb;
2042
2043                 desc = list_first_entry(&pch->completed_list,
2044                                         struct dma_pl330_desc, node);
2045
2046                 dmaengine_desc_get_callback(&desc->txd, &cb);
2047
2048                 if (pch->cyclic) {
2049                         desc->status = PREP;
2050                         list_move_tail(&desc->node, &pch->work_list);
2051                         if (power_down) {
2052                                 pch->active = true;
2053                                 spin_lock(&pch->thread->dmac->lock);
2054                                 _start(pch->thread);
2055                                 spin_unlock(&pch->thread->dmac->lock);
2056                                 power_down = false;
2057                         }
2058                 } else {
2059                         desc->status = FREE;
2060                         list_move_tail(&desc->node, &pch->dmac->desc_pool);
2061                 }
2062
2063                 dma_descriptor_unmap(&desc->txd);
2064
2065                 if (dmaengine_desc_callback_valid(&cb)) {
2066                         spin_unlock_irqrestore(&pch->lock, flags);
2067                         dmaengine_desc_callback_invoke(&cb, NULL);
2068                         spin_lock_irqsave(&pch->lock, flags);
2069                 }
2070         }
2071         spin_unlock_irqrestore(&pch->lock, flags);
2072
2073         /* If work list empty, power down */
2074         if (power_down) {
2075                 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2076                 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2077         }
2078 }
2079
2080 bool pl330_filter(struct dma_chan *chan, void *param)
2081 {
2082         u8 *peri_id;
2083
2084         if (chan->device->dev->driver != &pl330_driver.drv)
2085                 return false;
2086
2087         peri_id = chan->private;
2088         return *peri_id == (unsigned long)param;
2089 }
2090 EXPORT_SYMBOL(pl330_filter);
2091
2092 static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2093                                                 struct of_dma *ofdma)
2094 {
2095         int count = dma_spec->args_count;
2096         struct pl330_dmac *pl330 = ofdma->of_dma_data;
2097         unsigned int chan_id;
2098
2099         if (!pl330)
2100                 return NULL;
2101
2102         if (count != 1)
2103                 return NULL;
2104
2105         chan_id = dma_spec->args[0];
2106         if (chan_id >= pl330->num_peripherals)
2107                 return NULL;
2108
2109         return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2110 }
2111
2112 static int pl330_alloc_chan_resources(struct dma_chan *chan)
2113 {
2114         struct dma_pl330_chan *pch = to_pchan(chan);
2115         struct pl330_dmac *pl330 = pch->dmac;
2116         unsigned long flags;
2117
2118         spin_lock_irqsave(&pl330->lock, flags);
2119
2120         dma_cookie_init(chan);
2121         pch->cyclic = false;
2122
2123         pch->thread = pl330_request_channel(pl330);
2124         if (!pch->thread) {
2125                 spin_unlock_irqrestore(&pl330->lock, flags);
2126                 return -ENOMEM;
2127         }
2128
2129         tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2130
2131         spin_unlock_irqrestore(&pl330->lock, flags);
2132
2133         return 1;
2134 }
2135
2136 static int pl330_config(struct dma_chan *chan,
2137                         struct dma_slave_config *slave_config)
2138 {
2139         struct dma_pl330_chan *pch = to_pchan(chan);
2140
2141         if (slave_config->direction == DMA_MEM_TO_DEV) {
2142                 if (slave_config->dst_addr)
2143                         pch->fifo_addr = slave_config->dst_addr;
2144                 if (slave_config->dst_addr_width)
2145                         pch->burst_sz = __ffs(slave_config->dst_addr_width);
2146                 if (slave_config->dst_maxburst)
2147                         pch->burst_len = slave_config->dst_maxburst;
2148         } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2149                 if (slave_config->src_addr)
2150                         pch->fifo_addr = slave_config->src_addr;
2151                 if (slave_config->src_addr_width)
2152                         pch->burst_sz = __ffs(slave_config->src_addr_width);
2153                 if (slave_config->src_maxburst)
2154                         pch->burst_len = slave_config->src_maxburst;
2155         }
2156
2157         return 0;
2158 }
2159
2160 static int pl330_terminate_all(struct dma_chan *chan)
2161 {
2162         struct dma_pl330_chan *pch = to_pchan(chan);
2163         struct dma_pl330_desc *desc;
2164         unsigned long flags;
2165         struct pl330_dmac *pl330 = pch->dmac;
2166         LIST_HEAD(list);
2167         bool power_down = false;
2168
2169         pm_runtime_get_sync(pl330->ddma.dev);
2170         spin_lock_irqsave(&pch->lock, flags);
2171         spin_lock(&pl330->lock);
2172         _stop(pch->thread);
2173         spin_unlock(&pl330->lock);
2174
2175         pch->thread->req[0].desc = NULL;
2176         pch->thread->req[1].desc = NULL;
2177         pch->thread->req_running = -1;
2178         power_down = pch->active;
2179         pch->active = false;
2180
2181         /* Mark all desc done */
2182         list_for_each_entry(desc, &pch->submitted_list, node) {
2183                 desc->status = FREE;
2184                 dma_cookie_complete(&desc->txd);
2185         }
2186
2187         list_for_each_entry(desc, &pch->work_list , node) {
2188                 desc->status = FREE;
2189                 dma_cookie_complete(&desc->txd);
2190         }
2191
2192         list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2193         list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2194         list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2195         spin_unlock_irqrestore(&pch->lock, flags);
2196         pm_runtime_mark_last_busy(pl330->ddma.dev);
2197         if (power_down)
2198                 pm_runtime_put_autosuspend(pl330->ddma.dev);
2199         pm_runtime_put_autosuspend(pl330->ddma.dev);
2200
2201         return 0;
2202 }
2203
2204 /*
2205  * We don't support DMA_RESUME command because of hardware
2206  * limitations, so after pausing the channel we cannot restore
2207  * it to active state. We have to terminate channel and setup
2208  * DMA transfer again. This pause feature was implemented to
2209  * allow safely read residue before channel termination.
2210  */
2211 static int pl330_pause(struct dma_chan *chan)
2212 {
2213         struct dma_pl330_chan *pch = to_pchan(chan);
2214         struct pl330_dmac *pl330 = pch->dmac;
2215         unsigned long flags;
2216
2217         pm_runtime_get_sync(pl330->ddma.dev);
2218         spin_lock_irqsave(&pch->lock, flags);
2219
2220         spin_lock(&pl330->lock);
2221         _stop(pch->thread);
2222         spin_unlock(&pl330->lock);
2223
2224         spin_unlock_irqrestore(&pch->lock, flags);
2225         pm_runtime_mark_last_busy(pl330->ddma.dev);
2226         pm_runtime_put_autosuspend(pl330->ddma.dev);
2227
2228         return 0;
2229 }
2230
2231 static void pl330_free_chan_resources(struct dma_chan *chan)
2232 {
2233         struct dma_pl330_chan *pch = to_pchan(chan);
2234         struct pl330_dmac *pl330 = pch->dmac;
2235         unsigned long flags;
2236
2237         tasklet_kill(&pch->task);
2238
2239         pm_runtime_get_sync(pch->dmac->ddma.dev);
2240         spin_lock_irqsave(&pl330->lock, flags);
2241
2242         pl330_release_channel(pch->thread);
2243         pch->thread = NULL;
2244
2245         if (pch->cyclic)
2246                 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2247
2248         spin_unlock_irqrestore(&pl330->lock, flags);
2249         pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2250         pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2251 }
2252
2253 static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2254                                            struct dma_pl330_desc *desc)
2255 {
2256         struct pl330_thread *thrd = pch->thread;
2257         struct pl330_dmac *pl330 = pch->dmac;
2258         void __iomem *regs = thrd->dmac->base;
2259         u32 val, addr;
2260
2261         pm_runtime_get_sync(pl330->ddma.dev);
2262         val = addr = 0;
2263         if (desc->rqcfg.src_inc) {
2264                 val = readl(regs + SA(thrd->id));
2265                 addr = desc->px.src_addr;
2266         } else {
2267                 val = readl(regs + DA(thrd->id));
2268                 addr = desc->px.dst_addr;
2269         }
2270         pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2271         pm_runtime_put_autosuspend(pl330->ddma.dev);
2272
2273         /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
2274         if (!val)
2275                 return 0;
2276
2277         return val - addr;
2278 }
2279
2280 static enum dma_status
2281 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2282                  struct dma_tx_state *txstate)
2283 {
2284         enum dma_status ret;
2285         unsigned long flags;
2286         struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
2287         struct dma_pl330_chan *pch = to_pchan(chan);
2288         unsigned int transferred, residual = 0;
2289
2290         ret = dma_cookie_status(chan, cookie, txstate);
2291
2292         if (!txstate)
2293                 return ret;
2294
2295         if (ret == DMA_COMPLETE)
2296                 goto out;
2297
2298         spin_lock_irqsave(&pch->lock, flags);
2299         spin_lock(&pch->thread->dmac->lock);
2300
2301         if (pch->thread->req_running != -1)
2302                 running = pch->thread->req[pch->thread->req_running].desc;
2303
2304         last_enq = pch->thread->req[pch->thread->lstenq].desc;
2305
2306         /* Check in pending list */
2307         list_for_each_entry(desc, &pch->work_list, node) {
2308                 if (desc->status == DONE)
2309                         transferred = desc->bytes_requested;
2310                 else if (running && desc == running)
2311                         transferred =
2312                                 pl330_get_current_xferred_count(pch, desc);
2313                 else if (desc->status == BUSY)
2314                         /*
2315                          * Busy but not running means either just enqueued,
2316                          * or finished and not yet marked done
2317                          */
2318                         if (desc == last_enq)
2319                                 transferred = 0;
2320                         else
2321                                 transferred = desc->bytes_requested;
2322                 else
2323                         transferred = 0;
2324                 residual += desc->bytes_requested - transferred;
2325                 if (desc->txd.cookie == cookie) {
2326                         switch (desc->status) {
2327                         case DONE:
2328                                 ret = DMA_COMPLETE;
2329                                 break;
2330                         case PREP:
2331                         case BUSY:
2332                                 ret = DMA_IN_PROGRESS;
2333                                 break;
2334                         default:
2335                                 WARN_ON(1);
2336                         }
2337                         break;
2338                 }
2339                 if (desc->last)
2340                         residual = 0;
2341         }
2342         spin_unlock(&pch->thread->dmac->lock);
2343         spin_unlock_irqrestore(&pch->lock, flags);
2344
2345 out:
2346         dma_set_residue(txstate, residual);
2347
2348         return ret;
2349 }
2350
2351 static void pl330_issue_pending(struct dma_chan *chan)
2352 {
2353         struct dma_pl330_chan *pch = to_pchan(chan);
2354         unsigned long flags;
2355
2356         spin_lock_irqsave(&pch->lock, flags);
2357         if (list_empty(&pch->work_list)) {
2358                 /*
2359                  * Warn on nothing pending. Empty submitted_list may
2360                  * break our pm_runtime usage counter as it is
2361                  * updated on work_list emptiness status.
2362                  */
2363                 WARN_ON(list_empty(&pch->submitted_list));
2364                 pch->active = true;
2365                 pm_runtime_get_sync(pch->dmac->ddma.dev);
2366         }
2367         list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2368         spin_unlock_irqrestore(&pch->lock, flags);
2369
2370         pl330_tasklet((unsigned long)pch);
2371 }
2372
2373 /*
2374  * We returned the last one of the circular list of descriptor(s)
2375  * from prep_xxx, so the argument to submit corresponds to the last
2376  * descriptor of the list.
2377  */
2378 static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2379 {
2380         struct dma_pl330_desc *desc, *last = to_desc(tx);
2381         struct dma_pl330_chan *pch = to_pchan(tx->chan);
2382         dma_cookie_t cookie;
2383         unsigned long flags;
2384
2385         spin_lock_irqsave(&pch->lock, flags);
2386
2387         /* Assign cookies to all nodes */
2388         while (!list_empty(&last->node)) {
2389                 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2390                 if (pch->cyclic) {
2391                         desc->txd.callback = last->txd.callback;
2392                         desc->txd.callback_param = last->txd.callback_param;
2393                 }
2394                 desc->last = false;
2395
2396                 dma_cookie_assign(&desc->txd);
2397
2398                 list_move_tail(&desc->node, &pch->submitted_list);
2399         }
2400
2401         last->last = true;
2402         cookie = dma_cookie_assign(&last->txd);
2403         list_add_tail(&last->node, &pch->submitted_list);
2404         spin_unlock_irqrestore(&pch->lock, flags);
2405
2406         return cookie;
2407 }
2408
2409 static inline void _init_desc(struct dma_pl330_desc *desc)
2410 {
2411         desc->rqcfg.swap = SWAP_NO;
2412         desc->rqcfg.scctl = CCTRL0;
2413         desc->rqcfg.dcctl = CCTRL0;
2414         desc->txd.tx_submit = pl330_tx_submit;
2415
2416         INIT_LIST_HEAD(&desc->node);
2417 }
2418
2419 /* Returns the number of descriptors added to the DMAC pool */
2420 static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
2421 {
2422         struct dma_pl330_desc *desc;
2423         unsigned long flags;
2424         int i;
2425
2426         desc = kcalloc(count, sizeof(*desc), flg);
2427         if (!desc)
2428                 return 0;
2429
2430         spin_lock_irqsave(&pl330->pool_lock, flags);
2431
2432         for (i = 0; i < count; i++) {
2433                 _init_desc(&desc[i]);
2434                 list_add_tail(&desc[i].node, &pl330->desc_pool);
2435         }
2436
2437         spin_unlock_irqrestore(&pl330->pool_lock, flags);
2438
2439         return count;
2440 }
2441
2442 static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
2443 {
2444         struct dma_pl330_desc *desc = NULL;
2445         unsigned long flags;
2446
2447         spin_lock_irqsave(&pl330->pool_lock, flags);
2448
2449         if (!list_empty(&pl330->desc_pool)) {
2450                 desc = list_entry(pl330->desc_pool.next,
2451                                 struct dma_pl330_desc, node);
2452
2453                 list_del_init(&desc->node);
2454
2455                 desc->status = PREP;
2456                 desc->txd.callback = NULL;
2457         }
2458
2459         spin_unlock_irqrestore(&pl330->pool_lock, flags);
2460
2461         return desc;
2462 }
2463
2464 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2465 {
2466         struct pl330_dmac *pl330 = pch->dmac;
2467         u8 *peri_id = pch->chan.private;
2468         struct dma_pl330_desc *desc;
2469
2470         /* Pluck one desc from the pool of DMAC */
2471         desc = pluck_desc(pl330);
2472
2473         /* If the DMAC pool is empty, alloc new */
2474         if (!desc) {
2475                 if (!add_desc(pl330, GFP_ATOMIC, 1))
2476                         return NULL;
2477
2478                 /* Try again */
2479                 desc = pluck_desc(pl330);
2480                 if (!desc) {
2481                         dev_err(pch->dmac->ddma.dev,
2482                                 "%s:%d ALERT!\n", __func__, __LINE__);
2483                         return NULL;
2484                 }
2485         }
2486
2487         /* Initialize the descriptor */
2488         desc->pchan = pch;
2489         desc->txd.cookie = 0;
2490         async_tx_ack(&desc->txd);
2491
2492         desc->peri = peri_id ? pch->chan.chan_id : 0;
2493         desc->rqcfg.pcfg = &pch->dmac->pcfg;
2494
2495         dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2496
2497         return desc;
2498 }
2499
2500 static inline void fill_px(struct pl330_xfer *px,
2501                 dma_addr_t dst, dma_addr_t src, size_t len)
2502 {
2503         px->bytes = len;
2504         px->dst_addr = dst;
2505         px->src_addr = src;
2506 }
2507
2508 static struct dma_pl330_desc *
2509 __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2510                 dma_addr_t src, size_t len)
2511 {
2512         struct dma_pl330_desc *desc = pl330_get_desc(pch);
2513
2514         if (!desc) {
2515                 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2516                         __func__, __LINE__);
2517                 return NULL;
2518         }
2519
2520         /*
2521          * Ideally we should lookout for reqs bigger than
2522          * those that can be programmed with 256 bytes of
2523          * MC buffer, but considering a req size is seldom
2524          * going to be word-unaligned and more than 200MB,
2525          * we take it easy.
2526          * Also, should the limit is reached we'd rather
2527          * have the platform increase MC buffer size than
2528          * complicating this API driver.
2529          */
2530         fill_px(&desc->px, dst, src, len);
2531
2532         return desc;
2533 }
2534
2535 /* Call after fixing burst size */
2536 static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2537 {
2538         struct dma_pl330_chan *pch = desc->pchan;
2539         struct pl330_dmac *pl330 = pch->dmac;
2540         int burst_len;
2541
2542         burst_len = pl330->pcfg.data_bus_width / 8;
2543         burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2544         burst_len >>= desc->rqcfg.brst_size;
2545
2546         /* src/dst_burst_len can't be more than 16 */
2547         if (burst_len > 16)
2548                 burst_len = 16;
2549
2550         while (burst_len > 1) {
2551                 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2552                         break;
2553                 burst_len--;
2554         }
2555
2556         return burst_len;
2557 }
2558
2559 static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2560                 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2561                 size_t period_len, enum dma_transfer_direction direction,
2562                 unsigned long flags)
2563 {
2564         struct dma_pl330_desc *desc = NULL, *first = NULL;
2565         struct dma_pl330_chan *pch = to_pchan(chan);
2566         struct pl330_dmac *pl330 = pch->dmac;
2567         unsigned int i;
2568         dma_addr_t dst;
2569         dma_addr_t src;
2570
2571         if (len % period_len != 0)
2572                 return NULL;
2573
2574         if (!is_slave_direction(direction)) {
2575                 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2576                 __func__, __LINE__);
2577                 return NULL;
2578         }
2579
2580         for (i = 0; i < len / period_len; i++) {
2581                 desc = pl330_get_desc(pch);
2582                 if (!desc) {
2583                         dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2584                                 __func__, __LINE__);
2585
2586                         if (!first)
2587                                 return NULL;
2588
2589                         spin_lock_irqsave(&pl330->pool_lock, flags);
2590
2591                         while (!list_empty(&first->node)) {
2592                                 desc = list_entry(first->node.next,
2593                                                 struct dma_pl330_desc, node);
2594                                 list_move_tail(&desc->node, &pl330->desc_pool);
2595                         }
2596
2597                         list_move_tail(&first->node, &pl330->desc_pool);
2598
2599                         spin_unlock_irqrestore(&pl330->pool_lock, flags);
2600
2601                         return NULL;
2602                 }
2603
2604                 switch (direction) {
2605                 case DMA_MEM_TO_DEV:
2606                         desc->rqcfg.src_inc = 1;
2607                         desc->rqcfg.dst_inc = 0;
2608                         src = dma_addr;
2609                         dst = pch->fifo_addr;
2610                         break;
2611                 case DMA_DEV_TO_MEM:
2612                         desc->rqcfg.src_inc = 0;
2613                         desc->rqcfg.dst_inc = 1;
2614                         src = pch->fifo_addr;
2615                         dst = dma_addr;
2616                         break;
2617                 default:
2618                         break;
2619                 }
2620
2621                 desc->rqtype = direction;
2622                 desc->rqcfg.brst_size = pch->burst_sz;
2623                 desc->rqcfg.brst_len = 1;
2624                 desc->bytes_requested = period_len;
2625                 fill_px(&desc->px, dst, src, period_len);
2626
2627                 if (!first)
2628                         first = desc;
2629                 else
2630                         list_add_tail(&desc->node, &first->node);
2631
2632                 dma_addr += period_len;
2633         }
2634
2635         if (!desc)
2636                 return NULL;
2637
2638         pch->cyclic = true;
2639         desc->txd.flags = flags;
2640
2641         return &desc->txd;
2642 }
2643
2644 static struct dma_async_tx_descriptor *
2645 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2646                 dma_addr_t src, size_t len, unsigned long flags)
2647 {
2648         struct dma_pl330_desc *desc;
2649         struct dma_pl330_chan *pch = to_pchan(chan);
2650         struct pl330_dmac *pl330;
2651         int burst;
2652
2653         if (unlikely(!pch || !len))
2654                 return NULL;
2655
2656         pl330 = pch->dmac;
2657
2658         desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2659         if (!desc)
2660                 return NULL;
2661
2662         desc->rqcfg.src_inc = 1;
2663         desc->rqcfg.dst_inc = 1;
2664         desc->rqtype = DMA_MEM_TO_MEM;
2665
2666         /* Select max possible burst size */
2667         burst = pl330->pcfg.data_bus_width / 8;
2668
2669         /*
2670          * Make sure we use a burst size that aligns with all the memcpy
2671          * parameters because our DMA programming algorithm doesn't cope with
2672          * transfers which straddle an entry in the DMA device's MFIFO.
2673          */
2674         while ((src | dst | len) & (burst - 1))
2675                 burst /= 2;
2676
2677         desc->rqcfg.brst_size = 0;
2678         while (burst != (1 << desc->rqcfg.brst_size))
2679                 desc->rqcfg.brst_size++;
2680
2681         /*
2682          * If burst size is smaller than bus width then make sure we only
2683          * transfer one at a time to avoid a burst stradling an MFIFO entry.
2684          */
2685         if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2686                 desc->rqcfg.brst_len = 1;
2687
2688         desc->rqcfg.brst_len = get_burst_len(desc, len);
2689         desc->bytes_requested = len;
2690
2691         desc->txd.flags = flags;
2692
2693         return &desc->txd;
2694 }
2695
2696 static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2697                                   struct dma_pl330_desc *first)
2698 {
2699         unsigned long flags;
2700         struct dma_pl330_desc *desc;
2701
2702         if (!first)
2703                 return;
2704
2705         spin_lock_irqsave(&pl330->pool_lock, flags);
2706
2707         while (!list_empty(&first->node)) {
2708                 desc = list_entry(first->node.next,
2709                                 struct dma_pl330_desc, node);
2710                 list_move_tail(&desc->node, &pl330->desc_pool);
2711         }
2712
2713         list_move_tail(&first->node, &pl330->desc_pool);
2714
2715         spin_unlock_irqrestore(&pl330->pool_lock, flags);
2716 }
2717
2718 static struct dma_async_tx_descriptor *
2719 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2720                 unsigned int sg_len, enum dma_transfer_direction direction,
2721                 unsigned long flg, void *context)
2722 {
2723         struct dma_pl330_desc *first, *desc = NULL;
2724         struct dma_pl330_chan *pch = to_pchan(chan);
2725         struct scatterlist *sg;
2726         int i;
2727         dma_addr_t addr;
2728
2729         if (unlikely(!pch || !sgl || !sg_len))
2730                 return NULL;
2731
2732         addr = pch->fifo_addr;
2733
2734         first = NULL;
2735
2736         for_each_sg(sgl, sg, sg_len, i) {
2737
2738                 desc = pl330_get_desc(pch);
2739                 if (!desc) {
2740                         struct pl330_dmac *pl330 = pch->dmac;
2741
2742                         dev_err(pch->dmac->ddma.dev,
2743                                 "%s:%d Unable to fetch desc\n",
2744                                 __func__, __LINE__);
2745                         __pl330_giveback_desc(pl330, first);
2746
2747                         return NULL;
2748                 }
2749
2750                 if (!first)
2751                         first = desc;
2752                 else
2753                         list_add_tail(&desc->node, &first->node);
2754
2755                 if (direction == DMA_MEM_TO_DEV) {
2756                         desc->rqcfg.src_inc = 1;
2757                         desc->rqcfg.dst_inc = 0;
2758                         fill_px(&desc->px,
2759                                 addr, sg_dma_address(sg), sg_dma_len(sg));
2760                 } else {
2761                         desc->rqcfg.src_inc = 0;
2762                         desc->rqcfg.dst_inc = 1;
2763                         fill_px(&desc->px,
2764                                 sg_dma_address(sg), addr, sg_dma_len(sg));
2765                 }
2766
2767                 desc->rqcfg.brst_size = pch->burst_sz;
2768                 desc->rqcfg.brst_len = 1;
2769                 desc->rqtype = direction;
2770                 desc->bytes_requested = sg_dma_len(sg);
2771         }
2772
2773         /* Return the last desc in the chain */
2774         desc->txd.flags = flg;
2775         return &desc->txd;
2776 }
2777
2778 static irqreturn_t pl330_irq_handler(int irq, void *data)
2779 {
2780         if (pl330_update(data))
2781                 return IRQ_HANDLED;
2782         else
2783                 return IRQ_NONE;
2784 }
2785
2786 #define PL330_DMA_BUSWIDTHS \
2787         BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2788         BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2789         BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2790         BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2791         BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2792
2793 /*
2794  * Runtime PM callbacks are provided by amba/bus.c driver.
2795  *
2796  * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2797  * bus driver will only disable/enable the clock in runtime PM callbacks.
2798  */
2799 static int __maybe_unused pl330_suspend(struct device *dev)
2800 {
2801         struct amba_device *pcdev = to_amba_device(dev);
2802
2803         pm_runtime_disable(dev);
2804
2805         if (!pm_runtime_status_suspended(dev)) {
2806                 /* amba did not disable the clock */
2807                 amba_pclk_disable(pcdev);
2808         }
2809         amba_pclk_unprepare(pcdev);
2810
2811         return 0;
2812 }
2813
2814 static int __maybe_unused pl330_resume(struct device *dev)
2815 {
2816         struct amba_device *pcdev = to_amba_device(dev);
2817         int ret;
2818
2819         ret = amba_pclk_prepare(pcdev);
2820         if (ret)
2821                 return ret;
2822
2823         if (!pm_runtime_status_suspended(dev))
2824                 ret = amba_pclk_enable(pcdev);
2825
2826         pm_runtime_enable(dev);
2827
2828         return ret;
2829 }
2830
2831 static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2832
2833 static int
2834 pl330_probe(struct amba_device *adev, const struct amba_id *id)
2835 {
2836         struct dma_pl330_platdata *pdat;
2837         struct pl330_config *pcfg;
2838         struct pl330_dmac *pl330;
2839         struct dma_pl330_chan *pch, *_p;
2840         struct dma_device *pd;
2841         struct resource *res;
2842         int i, ret, irq;
2843         int num_chan;
2844         struct device_node *np = adev->dev.of_node;
2845
2846         pdat = dev_get_platdata(&adev->dev);
2847
2848         ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2849         if (ret)
2850                 return ret;
2851
2852         /* Allocate a new DMAC and its Channels */
2853         pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2854         if (!pl330)
2855                 return -ENOMEM;
2856
2857         pd = &pl330->ddma;
2858         pd->dev = &adev->dev;
2859
2860         pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
2861
2862         /* get quirk */
2863         for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
2864                 if (of_property_read_bool(np, of_quirks[i].quirk))
2865                         pl330->quirks |= of_quirks[i].id;
2866
2867         res = &adev->res;
2868         pl330->base = devm_ioremap_resource(&adev->dev, res);
2869         if (IS_ERR(pl330->base))
2870                 return PTR_ERR(pl330->base);
2871
2872         amba_set_drvdata(adev, pl330);
2873
2874         for (i = 0; i < AMBA_NR_IRQS; i++) {
2875                 irq = adev->irq[i];
2876                 if (irq) {
2877                         ret = devm_request_irq(&adev->dev, irq,
2878                                                pl330_irq_handler, 0,
2879                                                dev_name(&adev->dev), pl330);
2880                         if (ret)
2881                                 return ret;
2882                 } else {
2883                         break;
2884                 }
2885         }
2886
2887         pcfg = &pl330->pcfg;
2888
2889         pcfg->periph_id = adev->periphid;
2890         ret = pl330_add(pl330);
2891         if (ret)
2892                 return ret;
2893
2894         INIT_LIST_HEAD(&pl330->desc_pool);
2895         spin_lock_init(&pl330->pool_lock);
2896
2897         /* Create a descriptor pool of default size */
2898         if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
2899                 dev_warn(&adev->dev, "unable to allocate desc\n");
2900
2901         INIT_LIST_HEAD(&pd->channels);
2902
2903         /* Initialize channel parameters */
2904         if (pdat)
2905                 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
2906         else
2907                 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
2908
2909         pl330->num_peripherals = num_chan;
2910
2911         pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2912         if (!pl330->peripherals) {
2913                 ret = -ENOMEM;
2914                 goto probe_err2;
2915         }
2916
2917         for (i = 0; i < num_chan; i++) {
2918                 pch = &pl330->peripherals[i];
2919                 if (!adev->dev.of_node)
2920                         pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2921                 else
2922                         pch->chan.private = adev->dev.of_node;
2923
2924                 INIT_LIST_HEAD(&pch->submitted_list);
2925                 INIT_LIST_HEAD(&pch->work_list);
2926                 INIT_LIST_HEAD(&pch->completed_list);
2927                 spin_lock_init(&pch->lock);
2928                 pch->thread = NULL;
2929                 pch->chan.device = pd;
2930                 pch->dmac = pl330;
2931
2932                 /* Add the channel to the DMAC list */
2933                 list_add_tail(&pch->chan.device_node, &pd->channels);
2934         }
2935
2936         if (pdat) {
2937                 pd->cap_mask = pdat->cap_mask;
2938         } else {
2939                 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
2940                 if (pcfg->num_peri) {
2941                         dma_cap_set(DMA_SLAVE, pd->cap_mask);
2942                         dma_cap_set(DMA_CYCLIC, pd->cap_mask);
2943                         dma_cap_set(DMA_PRIVATE, pd->cap_mask);
2944                 }
2945         }
2946
2947         pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2948         pd->device_free_chan_resources = pl330_free_chan_resources;
2949         pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
2950         pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
2951         pd->device_tx_status = pl330_tx_status;
2952         pd->device_prep_slave_sg = pl330_prep_slave_sg;
2953         pd->device_config = pl330_config;
2954         pd->device_pause = pl330_pause;
2955         pd->device_terminate_all = pl330_terminate_all;
2956         pd->device_issue_pending = pl330_issue_pending;
2957         pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
2958         pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
2959         pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2960         pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2961         pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ?
2962                          1 : PL330_MAX_BURST);
2963
2964         ret = dma_async_device_register(pd);
2965         if (ret) {
2966                 dev_err(&adev->dev, "unable to register DMAC\n");
2967                 goto probe_err3;
2968         }
2969
2970         if (adev->dev.of_node) {
2971                 ret = of_dma_controller_register(adev->dev.of_node,
2972                                          of_dma_pl330_xlate, pl330);
2973                 if (ret) {
2974                         dev_err(&adev->dev,
2975                         "unable to register DMA to the generic DT DMA helpers\n");
2976                 }
2977         }
2978
2979         adev->dev.dma_parms = &pl330->dma_parms;
2980
2981         /*
2982          * This is the limit for transfers with a buswidth of 1, larger
2983          * buswidths will have larger limits.
2984          */
2985         ret = dma_set_max_seg_size(&adev->dev, 1900800);
2986         if (ret)
2987                 dev_err(&adev->dev, "unable to set the seg size\n");
2988
2989
2990         dev_info(&adev->dev,
2991                 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
2992         dev_info(&adev->dev,
2993                 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2994                 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2995                 pcfg->num_peri, pcfg->num_events);
2996
2997         pm_runtime_irq_safe(&adev->dev);
2998         pm_runtime_use_autosuspend(&adev->dev);
2999         pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
3000         pm_runtime_mark_last_busy(&adev->dev);
3001         pm_runtime_put_autosuspend(&adev->dev);
3002
3003         return 0;
3004 probe_err3:
3005         /* Idle the DMAC */
3006         list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3007                         chan.device_node) {
3008
3009                 /* Remove the channel */
3010                 list_del(&pch->chan.device_node);
3011
3012                 /* Flush the channel */
3013                 if (pch->thread) {
3014                         pl330_terminate_all(&pch->chan);
3015                         pl330_free_chan_resources(&pch->chan);
3016                 }
3017         }
3018 probe_err2:
3019         pl330_del(pl330);
3020
3021         return ret;
3022 }
3023
3024 static int pl330_remove(struct amba_device *adev)
3025 {
3026         struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3027         struct dma_pl330_chan *pch, *_p;
3028         int i, irq;
3029
3030         pm_runtime_get_noresume(pl330->ddma.dev);
3031
3032         if (adev->dev.of_node)
3033                 of_dma_controller_free(adev->dev.of_node);
3034
3035         for (i = 0; i < AMBA_NR_IRQS; i++) {
3036                 irq = adev->irq[i];
3037                 devm_free_irq(&adev->dev, irq, pl330);
3038         }
3039
3040         dma_async_device_unregister(&pl330->ddma);
3041
3042         /* Idle the DMAC */
3043         list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3044                         chan.device_node) {
3045
3046                 /* Remove the channel */
3047                 list_del(&pch->chan.device_node);
3048
3049                 /* Flush the channel */
3050                 if (pch->thread) {
3051                         pl330_terminate_all(&pch->chan);
3052                         pl330_free_chan_resources(&pch->chan);
3053                 }
3054         }
3055
3056         pl330_del(pl330);
3057
3058         return 0;
3059 }
3060
3061 static struct amba_id pl330_ids[] = {
3062         {
3063                 .id     = 0x00041330,
3064                 .mask   = 0x000fffff,
3065         },
3066         { 0, 0 },
3067 };
3068
3069 MODULE_DEVICE_TABLE(amba, pl330_ids);
3070
3071 static struct amba_driver pl330_driver = {
3072         .drv = {
3073                 .owner = THIS_MODULE,
3074                 .name = "dma-pl330",
3075                 .pm = &pl330_pm,
3076         },
3077         .id_table = pl330_ids,
3078         .probe = pl330_probe,
3079         .remove = pl330_remove,
3080 };
3081
3082 module_amba_driver(pl330_driver);
3083
3084 MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3085 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3086 MODULE_LICENSE("GPL");