2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/amba/pl330.h>
26 #include <linux/scatterlist.h>
28 #include <linux/of_dma.h>
29 #include <linux/err.h>
30 #include <linux/pm_runtime.h>
32 #include "dmaengine.h"
33 #define PL330_MAX_CHAN 8
34 #define PL330_MAX_IRQS 32
35 #define PL330_MAX_PERI 32
37 enum pl330_cachectrl {
38 CCTRL0, /* Noncacheable and nonbufferable */
39 CCTRL1, /* Bufferable only */
40 CCTRL2, /* Cacheable, but do not allocate */
41 CCTRL3, /* Cacheable and bufferable, but do not allocate */
42 INVALID1, /* AWCACHE = 0x1000 */
44 CCTRL6, /* Cacheable write-through, allocate on writes only */
45 CCTRL7, /* Cacheable write-back, allocate on writes only */
56 /* Register and Bit field Definitions */
58 #define DS_ST_STOP 0x0
59 #define DS_ST_EXEC 0x1
60 #define DS_ST_CMISS 0x2
61 #define DS_ST_UPDTPC 0x3
63 #define DS_ST_ATBRR 0x5
64 #define DS_ST_QBUSY 0x6
66 #define DS_ST_KILL 0x8
67 #define DS_ST_CMPLT 0x9
68 #define DS_ST_FLTCMP 0xe
69 #define DS_ST_FAULT 0xf
74 #define INTSTATUS 0x28
81 #define FTC(n) (_FTC + (n)*0x4)
84 #define CS(n) (_CS + (n)*0x8)
85 #define CS_CNS (1 << 21)
88 #define CPC(n) (_CPC + (n)*0x8)
91 #define SA(n) (_SA + (n)*0x20)
94 #define DA(n) (_DA + (n)*0x20)
97 #define CC(n) (_CC + (n)*0x20)
99 #define CC_SRCINC (1 << 0)
100 #define CC_DSTINC (1 << 14)
101 #define CC_SRCPRI (1 << 8)
102 #define CC_DSTPRI (1 << 22)
103 #define CC_SRCNS (1 << 9)
104 #define CC_DSTNS (1 << 23)
105 #define CC_SRCIA (1 << 10)
106 #define CC_DSTIA (1 << 24)
107 #define CC_SRCBRSTLEN_SHFT 4
108 #define CC_DSTBRSTLEN_SHFT 18
109 #define CC_SRCBRSTSIZE_SHFT 1
110 #define CC_DSTBRSTSIZE_SHFT 15
111 #define CC_SRCCCTRL_SHFT 11
112 #define CC_SRCCCTRL_MASK 0x7
113 #define CC_DSTCCTRL_SHFT 25
114 #define CC_DRCCCTRL_MASK 0x7
115 #define CC_SWAP_SHFT 28
118 #define LC0(n) (_LC0 + (n)*0x20)
121 #define LC1(n) (_LC1 + (n)*0x20)
123 #define DBGSTATUS 0xd00
124 #define DBG_BUSY (1 << 0)
127 #define DBGINST0 0xd08
128 #define DBGINST1 0xd0c
137 #define PERIPH_ID 0xfe0
138 #define PERIPH_REV_SHIFT 20
139 #define PERIPH_REV_MASK 0xf
140 #define PERIPH_REV_R0P0 0
141 #define PERIPH_REV_R1P0 1
142 #define PERIPH_REV_R1P1 2
144 #define CR0_PERIPH_REQ_SET (1 << 0)
145 #define CR0_BOOT_EN_SET (1 << 1)
146 #define CR0_BOOT_MAN_NS (1 << 2)
147 #define CR0_NUM_CHANS_SHIFT 4
148 #define CR0_NUM_CHANS_MASK 0x7
149 #define CR0_NUM_PERIPH_SHIFT 12
150 #define CR0_NUM_PERIPH_MASK 0x1f
151 #define CR0_NUM_EVENTS_SHIFT 17
152 #define CR0_NUM_EVENTS_MASK 0x1f
154 #define CR1_ICACHE_LEN_SHIFT 0
155 #define CR1_ICACHE_LEN_MASK 0x7
156 #define CR1_NUM_ICACHELINES_SHIFT 4
157 #define CR1_NUM_ICACHELINES_MASK 0xf
159 #define CRD_DATA_WIDTH_SHIFT 0
160 #define CRD_DATA_WIDTH_MASK 0x7
161 #define CRD_WR_CAP_SHIFT 4
162 #define CRD_WR_CAP_MASK 0x7
163 #define CRD_WR_Q_DEP_SHIFT 8
164 #define CRD_WR_Q_DEP_MASK 0xf
165 #define CRD_RD_CAP_SHIFT 12
166 #define CRD_RD_CAP_MASK 0x7
167 #define CRD_RD_Q_DEP_SHIFT 16
168 #define CRD_RD_Q_DEP_MASK 0xf
169 #define CRD_DATA_BUFF_SHIFT 20
170 #define CRD_DATA_BUFF_MASK 0x3ff
173 #define DESIGNER 0x41
175 #define INTEG_CFG 0x0
176 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
178 #define PL330_STATE_STOPPED (1 << 0)
179 #define PL330_STATE_EXECUTING (1 << 1)
180 #define PL330_STATE_WFE (1 << 2)
181 #define PL330_STATE_FAULTING (1 << 3)
182 #define PL330_STATE_COMPLETING (1 << 4)
183 #define PL330_STATE_WFP (1 << 5)
184 #define PL330_STATE_KILLING (1 << 6)
185 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
186 #define PL330_STATE_CACHEMISS (1 << 8)
187 #define PL330_STATE_UPDTPC (1 << 9)
188 #define PL330_STATE_ATBARRIER (1 << 10)
189 #define PL330_STATE_QUEUEBUSY (1 << 11)
190 #define PL330_STATE_INVALID (1 << 15)
192 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
193 | PL330_STATE_WFE | PL330_STATE_FAULTING)
195 #define CMD_DMAADDH 0x54
196 #define CMD_DMAEND 0x00
197 #define CMD_DMAFLUSHP 0x35
198 #define CMD_DMAGO 0xa0
199 #define CMD_DMALD 0x04
200 #define CMD_DMALDP 0x25
201 #define CMD_DMALP 0x20
202 #define CMD_DMALPEND 0x28
203 #define CMD_DMAKILL 0x01
204 #define CMD_DMAMOV 0xbc
205 #define CMD_DMANOP 0x18
206 #define CMD_DMARMB 0x12
207 #define CMD_DMASEV 0x34
208 #define CMD_DMAST 0x08
209 #define CMD_DMASTP 0x29
210 #define CMD_DMASTZ 0x0c
211 #define CMD_DMAWFE 0x36
212 #define CMD_DMAWFP 0x30
213 #define CMD_DMAWMB 0x13
217 #define SZ_DMAFLUSHP 2
221 #define SZ_DMALPEND 2
235 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
236 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
238 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
239 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
242 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
243 * at 1byte/burst for P<->M and M<->M respectively.
244 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
245 * should be enough for P<->M and M<->M respectively.
247 #define MCODE_BUFF_PER_REQ 256
249 /* Use this _only_ to wait on transient states */
250 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
252 #ifdef PL330_DEBUG_MCGEN
253 static unsigned cmd_line;
254 #define PL330_DBGCMD_DUMP(off, x...) do { \
255 printk("%x:", cmd_line); \
259 #define PL330_DBGMC_START(addr) (cmd_line = addr)
261 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
262 #define PL330_DBGMC_START(addr) do {} while (0)
265 /* The number of default descriptors */
267 #define NR_DEFAULT_DESC 16
269 /* Delay for runtime PM autosuspend, ms */
270 #define PL330_AUTOSUSPEND_DELAY 20
272 /* Populated by the PL330 core driver for DMA API driver's info */
273 struct pl330_config {
275 #define DMAC_MODE_NS (1 << 0)
277 unsigned int data_bus_width:10; /* In number of bits */
278 unsigned int data_buf_dep:11;
279 unsigned int num_chan:4;
280 unsigned int num_peri:6;
282 unsigned int num_events:6;
287 * Request Configuration.
288 * The PL330 core does not modify this and uses the last
289 * working configuration if the request doesn't provide any.
291 * The Client may want to provide this info only for the
292 * first request and a request with new settings.
294 struct pl330_reqcfg {
295 /* Address Incrementing */
300 * For now, the SRC & DST protection levels
301 * and burst size/length are assumed same.
307 unsigned brst_size:3; /* in power of 2 */
309 enum pl330_cachectrl dcctl;
310 enum pl330_cachectrl scctl;
311 enum pl330_byteswap swap;
312 struct pl330_config *pcfg;
316 * One cycle of DMAC operation.
317 * There may be more than one xfer in a request.
326 /* The xfer callbacks are made with one of these arguments. */
328 /* The all xfers in the request were success. */
330 /* If req aborted due to global error. */
332 /* If req failed due to problem with Channel. */
353 struct dma_pl330_desc;
358 struct dma_pl330_desc *desc;
361 /* ToBeDone for tasklet */
369 struct pl330_thread {
372 /* If the channel is not yet acquired by any client */
375 struct pl330_dmac *dmac;
376 /* Only two at a time */
377 struct _pl330_req req[2];
378 /* Index of the last enqueued request */
380 /* Index of the last submitted request or -1 if the DMA is stopped */
384 enum pl330_dmac_state {
391 /* In the DMAC pool */
394 * Allocated to some channel during prep_xxx
395 * Also may be sitting on the work_list.
399 * Sitting on the work_list and already submitted
400 * to the PL330 core. Not more than two descriptors
401 * of a channel can be BUSY at any time.
405 * Sitting on the channel work_list but xfer done
411 struct dma_pl330_chan {
412 /* Schedule desc completion */
413 struct tasklet_struct task;
415 /* DMA-Engine Channel */
416 struct dma_chan chan;
418 /* List of submitted descriptors */
419 struct list_head submitted_list;
420 /* List of issued descriptors */
421 struct list_head work_list;
422 /* List of completed descriptors */
423 struct list_head completed_list;
425 /* Pointer to the DMAC that manages this channel,
426 * NULL if the channel is available to be acquired.
427 * As the parent, this DMAC also provides descriptors
430 struct pl330_dmac *dmac;
432 /* To protect channel manipulation */
436 * Hardware channel thread of PL330 DMAC. NULL if the channel is
439 struct pl330_thread *thread;
441 /* For D-to-M and M-to-D channels */
442 int burst_sz; /* the peripheral fifo width */
443 int burst_len; /* the number of burst */
444 dma_addr_t fifo_addr;
446 /* for cyclic capability */
451 /* DMA-Engine Device */
452 struct dma_device ddma;
454 /* Holds info about sg limitations */
455 struct device_dma_parameters dma_parms;
457 /* Pool of descriptors available for the DMAC's channels */
458 struct list_head desc_pool;
459 /* To protect desc_pool manipulation */
460 spinlock_t pool_lock;
462 /* Size of MicroCode buffers for each channel. */
464 /* ioremap'ed address of PL330 registers. */
466 /* Populated by the PL330 core driver during pl330_add */
467 struct pl330_config pcfg;
470 /* Maximum possible events/irqs */
472 /* BUS address of MicroCode buffer */
473 dma_addr_t mcode_bus;
474 /* CPU address of MicroCode buffer */
476 /* List of all Channel threads */
477 struct pl330_thread *channels;
478 /* Pointer to the MANAGER thread */
479 struct pl330_thread *manager;
480 /* To handle bad news in interrupt */
481 struct tasklet_struct tasks;
482 struct _pl330_tbd dmac_tbd;
483 /* State of DMAC operation */
484 enum pl330_dmac_state state;
485 /* Holds list of reqs with due callbacks */
486 struct list_head req_done;
488 /* Peripheral channels connected to this DMAC */
489 unsigned int num_peripherals;
490 struct dma_pl330_chan *peripherals; /* keep at end */
493 struct dma_pl330_desc {
494 /* To attach to a queue as child */
495 struct list_head node;
497 /* Descriptor for the DMA Engine API */
498 struct dma_async_tx_descriptor txd;
500 /* Xfer for PL330 core */
501 struct pl330_xfer px;
503 struct pl330_reqcfg rqcfg;
505 enum desc_status status;
510 /* The channel which currently holds this desc */
511 struct dma_pl330_chan *pchan;
513 enum dma_transfer_direction rqtype;
514 /* Index of peripheral for the xfer. */
516 /* Hook to attach to DMAC's list of reqs with due callback */
517 struct list_head rqd;
522 struct dma_pl330_desc *desc;
525 static inline bool _queue_empty(struct pl330_thread *thrd)
527 return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
530 static inline bool _queue_full(struct pl330_thread *thrd)
532 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
535 static inline bool is_manager(struct pl330_thread *thrd)
537 return thrd->dmac->manager == thrd;
540 /* If manager of the thread is in Non-Secure mode */
541 static inline bool _manager_ns(struct pl330_thread *thrd)
543 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
546 static inline u32 get_revision(u32 periph_id)
548 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
551 static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
552 enum pl330_dst da, u16 val)
557 buf[0] = CMD_DMAADDH;
559 *((__le16 *)&buf[1]) = cpu_to_le16(val);
561 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
562 da == 1 ? "DA" : "SA", val);
567 static inline u32 _emit_END(unsigned dry_run, u8 buf[])
574 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
579 static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
584 buf[0] = CMD_DMAFLUSHP;
590 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
595 static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
603 buf[0] |= (0 << 1) | (1 << 0);
604 else if (cond == BURST)
605 buf[0] |= (1 << 1) | (1 << 0);
607 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
608 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
613 static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
614 enum pl330_cond cond, u8 peri)
628 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
629 cond == SINGLE ? 'S' : 'B', peri >> 3);
634 static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
635 unsigned loop, u8 cnt)
645 cnt--; /* DMAC increments by 1 internally */
648 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
654 enum pl330_cond cond;
660 static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
661 const struct _arg_LPEND *arg)
663 enum pl330_cond cond = arg->cond;
664 bool forever = arg->forever;
665 unsigned loop = arg->loop;
666 u8 bjump = arg->bjump;
671 buf[0] = CMD_DMALPEND;
680 buf[0] |= (0 << 1) | (1 << 0);
681 else if (cond == BURST)
682 buf[0] |= (1 << 1) | (1 << 0);
686 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
687 forever ? "FE" : "END",
688 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
695 static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
700 buf[0] = CMD_DMAKILL;
705 static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
706 enum dmamov_dst dst, u32 val)
713 *((__le32 *)&buf[2]) = cpu_to_le32(val);
715 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
716 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
721 static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
728 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
733 static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
740 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
745 static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
756 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
761 static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
769 buf[0] |= (0 << 1) | (1 << 0);
770 else if (cond == BURST)
771 buf[0] |= (1 << 1) | (1 << 0);
773 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
774 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
779 static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
780 enum pl330_cond cond, u8 peri)
794 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
795 cond == SINGLE ? 'S' : 'B', peri >> 3);
800 static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
807 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
812 static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
827 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
828 ev >> 3, invalidate ? ", I" : "");
833 static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
834 enum pl330_cond cond, u8 peri)
842 buf[0] |= (0 << 1) | (0 << 0);
843 else if (cond == BURST)
844 buf[0] |= (1 << 1) | (0 << 0);
846 buf[0] |= (0 << 1) | (1 << 0);
852 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
853 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
858 static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
865 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
876 static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
877 const struct _arg_GO *arg)
880 u32 addr = arg->addr;
881 unsigned ns = arg->ns;
891 *((__le32 *)&buf[2]) = cpu_to_le32(addr);
896 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
898 /* Returns Time-Out */
899 static bool _until_dmac_idle(struct pl330_thread *thrd)
901 void __iomem *regs = thrd->dmac->base;
902 unsigned long loops = msecs_to_loops(5);
905 /* Until Manager is Idle */
906 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
918 static inline void _execute_DBGINSN(struct pl330_thread *thrd,
919 u8 insn[], bool as_manager)
921 void __iomem *regs = thrd->dmac->base;
924 val = (insn[0] << 16) | (insn[1] << 24);
927 val |= (thrd->id << 8); /* Channel Number */
929 writel(val, regs + DBGINST0);
931 val = le32_to_cpu(*((__le32 *)&insn[2]));
932 writel(val, regs + DBGINST1);
934 /* If timed out due to halted state-machine */
935 if (_until_dmac_idle(thrd)) {
936 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
941 writel(0, regs + DBGCMD);
944 static inline u32 _state(struct pl330_thread *thrd)
946 void __iomem *regs = thrd->dmac->base;
949 if (is_manager(thrd))
950 val = readl(regs + DS) & 0xf;
952 val = readl(regs + CS(thrd->id)) & 0xf;
956 return PL330_STATE_STOPPED;
958 return PL330_STATE_EXECUTING;
960 return PL330_STATE_CACHEMISS;
962 return PL330_STATE_UPDTPC;
964 return PL330_STATE_WFE;
966 return PL330_STATE_FAULTING;
968 if (is_manager(thrd))
969 return PL330_STATE_INVALID;
971 return PL330_STATE_ATBARRIER;
973 if (is_manager(thrd))
974 return PL330_STATE_INVALID;
976 return PL330_STATE_QUEUEBUSY;
978 if (is_manager(thrd))
979 return PL330_STATE_INVALID;
981 return PL330_STATE_WFP;
983 if (is_manager(thrd))
984 return PL330_STATE_INVALID;
986 return PL330_STATE_KILLING;
988 if (is_manager(thrd))
989 return PL330_STATE_INVALID;
991 return PL330_STATE_COMPLETING;
993 if (is_manager(thrd))
994 return PL330_STATE_INVALID;
996 return PL330_STATE_FAULT_COMPLETING;
998 return PL330_STATE_INVALID;
1002 static void _stop(struct pl330_thread *thrd)
1004 void __iomem *regs = thrd->dmac->base;
1005 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1007 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1008 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1010 /* Return if nothing needs to be done */
1011 if (_state(thrd) == PL330_STATE_COMPLETING
1012 || _state(thrd) == PL330_STATE_KILLING
1013 || _state(thrd) == PL330_STATE_STOPPED)
1016 _emit_KILL(0, insn);
1018 /* Stop generating interrupts for SEV */
1019 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1021 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1024 /* Start doing req 'idx' of thread 'thrd' */
1025 static bool _trigger(struct pl330_thread *thrd)
1027 void __iomem *regs = thrd->dmac->base;
1028 struct _pl330_req *req;
1029 struct dma_pl330_desc *desc;
1032 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1035 /* Return if already ACTIVE */
1036 if (_state(thrd) != PL330_STATE_STOPPED)
1039 idx = 1 - thrd->lstenq;
1040 if (thrd->req[idx].desc != NULL) {
1041 req = &thrd->req[idx];
1044 if (thrd->req[idx].desc != NULL)
1045 req = &thrd->req[idx];
1050 /* Return if no request */
1054 /* Return if req is running */
1055 if (idx == thrd->req_running)
1060 ns = desc->rqcfg.nonsecure ? 1 : 0;
1062 /* See 'Abort Sources' point-4 at Page 2-25 */
1063 if (_manager_ns(thrd) && !ns)
1064 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1065 __func__, __LINE__);
1068 go.addr = req->mc_bus;
1070 _emit_GO(0, insn, &go);
1072 /* Set to generate interrupts for SEV */
1073 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1075 /* Only manager can execute GO */
1076 _execute_DBGINSN(thrd, insn, true);
1078 thrd->req_running = idx;
1083 static bool _start(struct pl330_thread *thrd)
1085 switch (_state(thrd)) {
1086 case PL330_STATE_FAULT_COMPLETING:
1087 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1089 if (_state(thrd) == PL330_STATE_KILLING)
1090 UNTIL(thrd, PL330_STATE_STOPPED)
1092 case PL330_STATE_FAULTING:
1095 case PL330_STATE_KILLING:
1096 case PL330_STATE_COMPLETING:
1097 UNTIL(thrd, PL330_STATE_STOPPED)
1099 case PL330_STATE_STOPPED:
1100 return _trigger(thrd);
1102 case PL330_STATE_WFP:
1103 case PL330_STATE_QUEUEBUSY:
1104 case PL330_STATE_ATBARRIER:
1105 case PL330_STATE_UPDTPC:
1106 case PL330_STATE_CACHEMISS:
1107 case PL330_STATE_EXECUTING:
1110 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1116 static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1117 const struct _xfer_spec *pxs, int cyc)
1120 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1122 /* check lock-up free version */
1123 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1125 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1126 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1130 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1131 off += _emit_RMB(dry_run, &buf[off]);
1132 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1133 off += _emit_WMB(dry_run, &buf[off]);
1140 static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
1141 const struct _xfer_spec *pxs, int cyc)
1146 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1147 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1148 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1149 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1155 static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
1156 const struct _xfer_spec *pxs, int cyc)
1161 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1162 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1163 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1164 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1170 static int _bursts(unsigned dry_run, u8 buf[],
1171 const struct _xfer_spec *pxs, int cyc)
1175 switch (pxs->desc->rqtype) {
1176 case DMA_MEM_TO_DEV:
1177 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1179 case DMA_DEV_TO_MEM:
1180 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1182 case DMA_MEM_TO_MEM:
1183 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1186 off += 0x40000000; /* Scare off the Client */
1193 /* Returns bytes consumed and updates bursts */
1194 static inline int _loop(unsigned dry_run, u8 buf[],
1195 unsigned long *bursts, const struct _xfer_spec *pxs)
1197 int cyc, cycmax, szlp, szlpend, szbrst, off;
1198 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1199 struct _arg_LPEND lpend;
1201 /* Max iterations possible in DMALP is 256 */
1202 if (*bursts >= 256*256) {
1205 cyc = *bursts / lcnt1 / lcnt0;
1206 } else if (*bursts > 256) {
1208 lcnt0 = *bursts / lcnt1;
1216 szlp = _emit_LP(1, buf, 0, 0);
1217 szbrst = _bursts(1, buf, pxs, 1);
1219 lpend.cond = ALWAYS;
1220 lpend.forever = false;
1223 szlpend = _emit_LPEND(1, buf, &lpend);
1231 * Max bursts that we can unroll due to limit on the
1232 * size of backward jump that can be encoded in DMALPEND
1233 * which is 8-bits and hence 255
1235 cycmax = (255 - (szlp + szlpend)) / szbrst;
1237 cyc = (cycmax < cyc) ? cycmax : cyc;
1242 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1246 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1249 off += _bursts(dry_run, &buf[off], pxs, cyc);
1251 lpend.cond = ALWAYS;
1252 lpend.forever = false;
1254 lpend.bjump = off - ljmp1;
1255 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1258 lpend.cond = ALWAYS;
1259 lpend.forever = false;
1261 lpend.bjump = off - ljmp0;
1262 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1265 *bursts = lcnt1 * cyc;
1272 static inline int _setup_loops(unsigned dry_run, u8 buf[],
1273 const struct _xfer_spec *pxs)
1275 struct pl330_xfer *x = &pxs->desc->px;
1277 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1282 off += _loop(dry_run, &buf[off], &c, pxs);
1289 static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1290 const struct _xfer_spec *pxs)
1292 struct pl330_xfer *x = &pxs->desc->px;
1295 /* DMAMOV SAR, x->src_addr */
1296 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1297 /* DMAMOV DAR, x->dst_addr */
1298 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1301 off += _setup_loops(dry_run, &buf[off], pxs);
1307 * A req is a sequence of one or more xfer units.
1308 * Returns the number of bytes taken to setup the MC for the req.
1310 static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1311 unsigned index, struct _xfer_spec *pxs)
1313 struct _pl330_req *req = &thrd->req[index];
1314 struct pl330_xfer *x;
1315 u8 *buf = req->mc_cpu;
1318 PL330_DBGMC_START(req->mc_bus);
1320 /* DMAMOV CCR, ccr */
1321 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1324 /* Error if xfer length is not aligned at burst size */
1325 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1328 off += _setup_xfer(dry_run, &buf[off], pxs);
1330 /* DMASEV peripheral/event */
1331 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1333 off += _emit_END(dry_run, &buf[off]);
1338 static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1348 /* We set same protection levels for Src and DST for now */
1349 if (rqc->privileged)
1350 ccr |= CC_SRCPRI | CC_DSTPRI;
1352 ccr |= CC_SRCNS | CC_DSTNS;
1353 if (rqc->insnaccess)
1354 ccr |= CC_SRCIA | CC_DSTIA;
1356 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1357 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1359 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1360 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1362 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1363 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1365 ccr |= (rqc->swap << CC_SWAP_SHFT);
1371 * Submit a list of xfers after which the client wants notification.
1372 * Client is not notified after each xfer unit, just once after all
1373 * xfer units are done or some error occurs.
1375 static int pl330_submit_req(struct pl330_thread *thrd,
1376 struct dma_pl330_desc *desc)
1378 struct pl330_dmac *pl330 = thrd->dmac;
1379 struct _xfer_spec xs;
1380 unsigned long flags;
1385 if (pl330->state == DYING
1386 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1387 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1388 __func__, __LINE__);
1392 /* If request for non-existing peripheral */
1393 if (desc->rqtype != DMA_MEM_TO_MEM &&
1394 desc->peri >= pl330->pcfg.num_peri) {
1395 dev_info(thrd->dmac->ddma.dev,
1396 "%s:%d Invalid peripheral(%u)!\n",
1397 __func__, __LINE__, desc->peri);
1401 spin_lock_irqsave(&pl330->lock, flags);
1403 if (_queue_full(thrd)) {
1408 /* Prefer Secure Channel */
1409 if (!_manager_ns(thrd))
1410 desc->rqcfg.nonsecure = 0;
1412 desc->rqcfg.nonsecure = 1;
1414 ccr = _prepare_ccr(&desc->rqcfg);
1416 idx = thrd->req[0].desc == NULL ? 0 : 1;
1421 /* First dry run to check if req is acceptable */
1422 ret = _setup_req(1, thrd, idx, &xs);
1426 if (ret > pl330->mcbufsz / 2) {
1427 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1428 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1433 /* Hook the request */
1435 thrd->req[idx].desc = desc;
1436 _setup_req(0, thrd, idx, &xs);
1441 spin_unlock_irqrestore(&pl330->lock, flags);
1446 static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1448 struct dma_pl330_chan *pch;
1449 unsigned long flags;
1456 /* If desc aborted */
1460 spin_lock_irqsave(&pch->lock, flags);
1462 desc->status = DONE;
1464 spin_unlock_irqrestore(&pch->lock, flags);
1466 tasklet_schedule(&pch->task);
1469 static void pl330_dotask(unsigned long data)
1471 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1472 unsigned long flags;
1475 spin_lock_irqsave(&pl330->lock, flags);
1477 /* The DMAC itself gone nuts */
1478 if (pl330->dmac_tbd.reset_dmac) {
1479 pl330->state = DYING;
1480 /* Reset the manager too */
1481 pl330->dmac_tbd.reset_mngr = true;
1482 /* Clear the reset flag */
1483 pl330->dmac_tbd.reset_dmac = false;
1486 if (pl330->dmac_tbd.reset_mngr) {
1487 _stop(pl330->manager);
1488 /* Reset all channels */
1489 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1490 /* Clear the reset flag */
1491 pl330->dmac_tbd.reset_mngr = false;
1494 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1496 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1497 struct pl330_thread *thrd = &pl330->channels[i];
1498 void __iomem *regs = pl330->base;
1499 enum pl330_op_err err;
1503 if (readl(regs + FSC) & (1 << thrd->id))
1504 err = PL330_ERR_FAIL;
1506 err = PL330_ERR_ABORT;
1508 spin_unlock_irqrestore(&pl330->lock, flags);
1509 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1510 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1511 spin_lock_irqsave(&pl330->lock, flags);
1513 thrd->req[0].desc = NULL;
1514 thrd->req[1].desc = NULL;
1515 thrd->req_running = -1;
1517 /* Clear the reset flag */
1518 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1522 spin_unlock_irqrestore(&pl330->lock, flags);
1527 /* Returns 1 if state was updated, 0 otherwise */
1528 static int pl330_update(struct pl330_dmac *pl330)
1530 struct dma_pl330_desc *descdone, *tmp;
1531 unsigned long flags;
1534 int id, ev, ret = 0;
1538 spin_lock_irqsave(&pl330->lock, flags);
1540 val = readl(regs + FSM) & 0x1;
1542 pl330->dmac_tbd.reset_mngr = true;
1544 pl330->dmac_tbd.reset_mngr = false;
1546 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1547 pl330->dmac_tbd.reset_chan |= val;
1550 while (i < pl330->pcfg.num_chan) {
1551 if (val & (1 << i)) {
1552 dev_info(pl330->ddma.dev,
1553 "Reset Channel-%d\t CS-%x FTC-%x\n",
1554 i, readl(regs + CS(i)),
1555 readl(regs + FTC(i)));
1556 _stop(&pl330->channels[i]);
1562 /* Check which event happened i.e, thread notified */
1563 val = readl(regs + ES);
1564 if (pl330->pcfg.num_events < 32
1565 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1566 pl330->dmac_tbd.reset_dmac = true;
1567 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1573 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1574 if (val & (1 << ev)) { /* Event occurred */
1575 struct pl330_thread *thrd;
1576 u32 inten = readl(regs + INTEN);
1579 /* Clear the event */
1580 if (inten & (1 << ev))
1581 writel(1 << ev, regs + INTCLR);
1585 id = pl330->events[ev];
1587 thrd = &pl330->channels[id];
1589 active = thrd->req_running;
1590 if (active == -1) /* Aborted */
1593 /* Detach the req */
1594 descdone = thrd->req[active].desc;
1595 thrd->req[active].desc = NULL;
1597 thrd->req_running = -1;
1599 /* Get going again ASAP */
1602 /* For now, just make a list of callbacks to be done */
1603 list_add_tail(&descdone->rqd, &pl330->req_done);
1607 /* Now that we are in no hurry, do the callbacks */
1608 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1609 list_del(&descdone->rqd);
1610 spin_unlock_irqrestore(&pl330->lock, flags);
1611 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1612 spin_lock_irqsave(&pl330->lock, flags);
1616 spin_unlock_irqrestore(&pl330->lock, flags);
1618 if (pl330->dmac_tbd.reset_dmac
1619 || pl330->dmac_tbd.reset_mngr
1620 || pl330->dmac_tbd.reset_chan) {
1622 tasklet_schedule(&pl330->tasks);
1628 /* Reserve an event */
1629 static inline int _alloc_event(struct pl330_thread *thrd)
1631 struct pl330_dmac *pl330 = thrd->dmac;
1634 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1635 if (pl330->events[ev] == -1) {
1636 pl330->events[ev] = thrd->id;
1643 static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1645 return pl330->pcfg.irq_ns & (1 << i);
1648 /* Upon success, returns IdentityToken for the
1649 * allocated channel, NULL otherwise.
1651 static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1653 struct pl330_thread *thrd = NULL;
1654 unsigned long flags;
1657 if (pl330->state == DYING)
1660 chans = pl330->pcfg.num_chan;
1662 spin_lock_irqsave(&pl330->lock, flags);
1664 for (i = 0; i < chans; i++) {
1665 thrd = &pl330->channels[i];
1666 if ((thrd->free) && (!_manager_ns(thrd) ||
1667 _chan_ns(pl330, i))) {
1668 thrd->ev = _alloc_event(thrd);
1669 if (thrd->ev >= 0) {
1672 thrd->req[0].desc = NULL;
1673 thrd->req[1].desc = NULL;
1674 thrd->req_running = -1;
1681 spin_unlock_irqrestore(&pl330->lock, flags);
1686 /* Release an event */
1687 static inline void _free_event(struct pl330_thread *thrd, int ev)
1689 struct pl330_dmac *pl330 = thrd->dmac;
1691 /* If the event is valid and was held by the thread */
1692 if (ev >= 0 && ev < pl330->pcfg.num_events
1693 && pl330->events[ev] == thrd->id)
1694 pl330->events[ev] = -1;
1697 static void pl330_release_channel(struct pl330_thread *thrd)
1699 struct pl330_dmac *pl330;
1700 unsigned long flags;
1702 if (!thrd || thrd->free)
1707 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1708 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1712 spin_lock_irqsave(&pl330->lock, flags);
1713 _free_event(thrd, thrd->ev);
1715 spin_unlock_irqrestore(&pl330->lock, flags);
1718 /* Initialize the structure for PL330 configuration, that can be used
1719 * by the client driver the make best use of the DMAC
1721 static void read_dmac_config(struct pl330_dmac *pl330)
1723 void __iomem *regs = pl330->base;
1726 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1727 val &= CRD_DATA_WIDTH_MASK;
1728 pl330->pcfg.data_bus_width = 8 * (1 << val);
1730 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1731 val &= CRD_DATA_BUFF_MASK;
1732 pl330->pcfg.data_buf_dep = val + 1;
1734 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1735 val &= CR0_NUM_CHANS_MASK;
1737 pl330->pcfg.num_chan = val;
1739 val = readl(regs + CR0);
1740 if (val & CR0_PERIPH_REQ_SET) {
1741 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1743 pl330->pcfg.num_peri = val;
1744 pl330->pcfg.peri_ns = readl(regs + CR4);
1746 pl330->pcfg.num_peri = 0;
1749 val = readl(regs + CR0);
1750 if (val & CR0_BOOT_MAN_NS)
1751 pl330->pcfg.mode |= DMAC_MODE_NS;
1753 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1755 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1756 val &= CR0_NUM_EVENTS_MASK;
1758 pl330->pcfg.num_events = val;
1760 pl330->pcfg.irq_ns = readl(regs + CR3);
1763 static inline void _reset_thread(struct pl330_thread *thrd)
1765 struct pl330_dmac *pl330 = thrd->dmac;
1767 thrd->req[0].mc_cpu = pl330->mcode_cpu
1768 + (thrd->id * pl330->mcbufsz);
1769 thrd->req[0].mc_bus = pl330->mcode_bus
1770 + (thrd->id * pl330->mcbufsz);
1771 thrd->req[0].desc = NULL;
1773 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1774 + pl330->mcbufsz / 2;
1775 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1776 + pl330->mcbufsz / 2;
1777 thrd->req[1].desc = NULL;
1779 thrd->req_running = -1;
1782 static int dmac_alloc_threads(struct pl330_dmac *pl330)
1784 int chans = pl330->pcfg.num_chan;
1785 struct pl330_thread *thrd;
1788 /* Allocate 1 Manager and 'chans' Channel threads */
1789 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1791 if (!pl330->channels)
1794 /* Init Channel threads */
1795 for (i = 0; i < chans; i++) {
1796 thrd = &pl330->channels[i];
1799 _reset_thread(thrd);
1803 /* MANAGER is indexed at the end */
1804 thrd = &pl330->channels[chans];
1808 pl330->manager = thrd;
1813 static int dmac_alloc_resources(struct pl330_dmac *pl330)
1815 int chans = pl330->pcfg.num_chan;
1819 * Alloc MicroCode buffer for 'chans' Channel threads.
1820 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1822 pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
1823 chans * pl330->mcbufsz,
1824 &pl330->mcode_bus, GFP_KERNEL);
1825 if (!pl330->mcode_cpu) {
1826 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1827 __func__, __LINE__);
1831 ret = dmac_alloc_threads(pl330);
1833 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1834 __func__, __LINE__);
1835 dma_free_coherent(pl330->ddma.dev,
1836 chans * pl330->mcbufsz,
1837 pl330->mcode_cpu, pl330->mcode_bus);
1844 static int pl330_add(struct pl330_dmac *pl330)
1851 /* Check if we can handle this DMAC */
1852 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1853 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1854 pl330->pcfg.periph_id);
1858 /* Read the configuration of the DMAC */
1859 read_dmac_config(pl330);
1861 if (pl330->pcfg.num_events == 0) {
1862 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1863 __func__, __LINE__);
1867 spin_lock_init(&pl330->lock);
1869 INIT_LIST_HEAD(&pl330->req_done);
1871 /* Use default MC buffer size if not provided */
1872 if (!pl330->mcbufsz)
1873 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1875 /* Mark all events as free */
1876 for (i = 0; i < pl330->pcfg.num_events; i++)
1877 pl330->events[i] = -1;
1879 /* Allocate resources needed by the DMAC */
1880 ret = dmac_alloc_resources(pl330);
1882 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1886 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1888 pl330->state = INIT;
1893 static int dmac_free_threads(struct pl330_dmac *pl330)
1895 struct pl330_thread *thrd;
1898 /* Release Channel threads */
1899 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1900 thrd = &pl330->channels[i];
1901 pl330_release_channel(thrd);
1905 kfree(pl330->channels);
1910 static void pl330_del(struct pl330_dmac *pl330)
1912 pl330->state = UNINIT;
1914 tasklet_kill(&pl330->tasks);
1916 /* Free DMAC resources */
1917 dmac_free_threads(pl330);
1919 dma_free_coherent(pl330->ddma.dev,
1920 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1924 /* forward declaration */
1925 static struct amba_driver pl330_driver;
1927 static inline struct dma_pl330_chan *
1928 to_pchan(struct dma_chan *ch)
1933 return container_of(ch, struct dma_pl330_chan, chan);
1936 static inline struct dma_pl330_desc *
1937 to_desc(struct dma_async_tx_descriptor *tx)
1939 return container_of(tx, struct dma_pl330_desc, txd);
1942 static inline void fill_queue(struct dma_pl330_chan *pch)
1944 struct dma_pl330_desc *desc;
1947 list_for_each_entry(desc, &pch->work_list, node) {
1949 /* If already submitted */
1950 if (desc->status == BUSY)
1953 ret = pl330_submit_req(pch->thread, desc);
1955 desc->status = BUSY;
1956 } else if (ret == -EAGAIN) {
1957 /* QFull or DMAC Dying */
1960 /* Unacceptable request */
1961 desc->status = DONE;
1962 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
1963 __func__, __LINE__, desc->txd.cookie);
1964 tasklet_schedule(&pch->task);
1969 static void pl330_tasklet(unsigned long data)
1971 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
1972 struct dma_pl330_desc *desc, *_dt;
1973 unsigned long flags;
1974 bool power_down = false;
1976 spin_lock_irqsave(&pch->lock, flags);
1978 /* Pick up ripe tomatoes */
1979 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
1980 if (desc->status == DONE) {
1982 dma_cookie_complete(&desc->txd);
1983 list_move_tail(&desc->node, &pch->completed_list);
1986 /* Try to submit a req imm. next to the last completed cookie */
1989 if (list_empty(&pch->work_list)) {
1990 spin_lock(&pch->thread->dmac->lock);
1992 spin_unlock(&pch->thread->dmac->lock);
1995 /* Make sure the PL330 Channel thread is active */
1996 spin_lock(&pch->thread->dmac->lock);
1997 _start(pch->thread);
1998 spin_unlock(&pch->thread->dmac->lock);
2001 while (!list_empty(&pch->completed_list)) {
2002 dma_async_tx_callback callback;
2003 void *callback_param;
2005 desc = list_first_entry(&pch->completed_list,
2006 struct dma_pl330_desc, node);
2008 callback = desc->txd.callback;
2009 callback_param = desc->txd.callback_param;
2012 desc->status = PREP;
2013 list_move_tail(&desc->node, &pch->work_list);
2015 spin_lock(&pch->thread->dmac->lock);
2016 _start(pch->thread);
2017 spin_unlock(&pch->thread->dmac->lock);
2021 desc->status = FREE;
2022 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2025 dma_descriptor_unmap(&desc->txd);
2028 spin_unlock_irqrestore(&pch->lock, flags);
2029 callback(callback_param);
2030 spin_lock_irqsave(&pch->lock, flags);
2033 spin_unlock_irqrestore(&pch->lock, flags);
2035 /* If work list empty, power down */
2037 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2038 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2042 bool pl330_filter(struct dma_chan *chan, void *param)
2046 if (chan->device->dev->driver != &pl330_driver.drv)
2049 peri_id = chan->private;
2050 return *peri_id == (unsigned long)param;
2052 EXPORT_SYMBOL(pl330_filter);
2054 static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2055 struct of_dma *ofdma)
2057 int count = dma_spec->args_count;
2058 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2059 unsigned int chan_id;
2067 chan_id = dma_spec->args[0];
2068 if (chan_id >= pl330->num_peripherals)
2071 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2074 static int pl330_alloc_chan_resources(struct dma_chan *chan)
2076 struct dma_pl330_chan *pch = to_pchan(chan);
2077 struct pl330_dmac *pl330 = pch->dmac;
2078 unsigned long flags;
2080 spin_lock_irqsave(&pch->lock, flags);
2082 dma_cookie_init(chan);
2083 pch->cyclic = false;
2085 pch->thread = pl330_request_channel(pl330);
2087 spin_unlock_irqrestore(&pch->lock, flags);
2091 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2093 spin_unlock_irqrestore(&pch->lock, flags);
2098 static int pl330_config(struct dma_chan *chan,
2099 struct dma_slave_config *slave_config)
2101 struct dma_pl330_chan *pch = to_pchan(chan);
2103 if (slave_config->direction == DMA_MEM_TO_DEV) {
2104 if (slave_config->dst_addr)
2105 pch->fifo_addr = slave_config->dst_addr;
2106 if (slave_config->dst_addr_width)
2107 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2108 if (slave_config->dst_maxburst)
2109 pch->burst_len = slave_config->dst_maxburst;
2110 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2111 if (slave_config->src_addr)
2112 pch->fifo_addr = slave_config->src_addr;
2113 if (slave_config->src_addr_width)
2114 pch->burst_sz = __ffs(slave_config->src_addr_width);
2115 if (slave_config->src_maxburst)
2116 pch->burst_len = slave_config->src_maxburst;
2122 static int pl330_terminate_all(struct dma_chan *chan)
2124 struct dma_pl330_chan *pch = to_pchan(chan);
2125 struct dma_pl330_desc *desc;
2126 unsigned long flags;
2127 struct pl330_dmac *pl330 = pch->dmac;
2130 pm_runtime_get_sync(pl330->ddma.dev);
2131 spin_lock_irqsave(&pch->lock, flags);
2132 spin_lock(&pl330->lock);
2134 spin_unlock(&pl330->lock);
2136 pch->thread->req[0].desc = NULL;
2137 pch->thread->req[1].desc = NULL;
2138 pch->thread->req_running = -1;
2140 /* Mark all desc done */
2141 list_for_each_entry(desc, &pch->submitted_list, node) {
2142 desc->status = FREE;
2143 dma_cookie_complete(&desc->txd);
2146 list_for_each_entry(desc, &pch->work_list , node) {
2147 desc->status = FREE;
2148 dma_cookie_complete(&desc->txd);
2151 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2152 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2153 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2154 spin_unlock_irqrestore(&pch->lock, flags);
2155 pm_runtime_mark_last_busy(pl330->ddma.dev);
2156 pm_runtime_put_autosuspend(pl330->ddma.dev);
2162 * We don't support DMA_RESUME command because of hardware
2163 * limitations, so after pausing the channel we cannot restore
2164 * it to active state. We have to terminate channel and setup
2165 * DMA transfer again. This pause feature was implemented to
2166 * allow safely read residue before channel termination.
2168 static int pl330_pause(struct dma_chan *chan)
2170 struct dma_pl330_chan *pch = to_pchan(chan);
2171 struct pl330_dmac *pl330 = pch->dmac;
2172 unsigned long flags;
2174 pm_runtime_get_sync(pl330->ddma.dev);
2175 spin_lock_irqsave(&pch->lock, flags);
2177 spin_lock(&pl330->lock);
2179 spin_unlock(&pl330->lock);
2181 spin_unlock_irqrestore(&pch->lock, flags);
2182 pm_runtime_mark_last_busy(pl330->ddma.dev);
2183 pm_runtime_put_autosuspend(pl330->ddma.dev);
2188 static void pl330_free_chan_resources(struct dma_chan *chan)
2190 struct dma_pl330_chan *pch = to_pchan(chan);
2191 unsigned long flags;
2193 tasklet_kill(&pch->task);
2195 pm_runtime_get_sync(pch->dmac->ddma.dev);
2196 spin_lock_irqsave(&pch->lock, flags);
2198 pl330_release_channel(pch->thread);
2202 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2204 spin_unlock_irqrestore(&pch->lock, flags);
2205 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2206 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2209 static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2210 struct dma_pl330_desc *desc)
2212 struct pl330_thread *thrd = pch->thread;
2213 struct pl330_dmac *pl330 = pch->dmac;
2214 void __iomem *regs = thrd->dmac->base;
2217 pm_runtime_get_sync(pl330->ddma.dev);
2219 if (desc->rqcfg.src_inc) {
2220 val = readl(regs + SA(thrd->id));
2221 addr = desc->px.src_addr;
2223 val = readl(regs + DA(thrd->id));
2224 addr = desc->px.dst_addr;
2226 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2227 pm_runtime_put_autosuspend(pl330->ddma.dev);
2231 static enum dma_status
2232 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2233 struct dma_tx_state *txstate)
2235 enum dma_status ret;
2236 unsigned long flags;
2237 struct dma_pl330_desc *desc, *running = NULL;
2238 struct dma_pl330_chan *pch = to_pchan(chan);
2239 unsigned int transferred, residual = 0;
2241 ret = dma_cookie_status(chan, cookie, txstate);
2246 if (ret == DMA_COMPLETE)
2249 spin_lock_irqsave(&pch->lock, flags);
2251 if (pch->thread->req_running != -1)
2252 running = pch->thread->req[pch->thread->req_running].desc;
2254 /* Check in pending list */
2255 list_for_each_entry(desc, &pch->work_list, node) {
2256 if (desc->status == DONE)
2257 transferred = desc->bytes_requested;
2258 else if (running && desc == running)
2260 pl330_get_current_xferred_count(pch, desc);
2263 residual += desc->bytes_requested - transferred;
2264 if (desc->txd.cookie == cookie) {
2265 switch (desc->status) {
2271 ret = DMA_IN_PROGRESS;
2281 spin_unlock_irqrestore(&pch->lock, flags);
2284 dma_set_residue(txstate, residual);
2289 static void pl330_issue_pending(struct dma_chan *chan)
2291 struct dma_pl330_chan *pch = to_pchan(chan);
2292 unsigned long flags;
2294 spin_lock_irqsave(&pch->lock, flags);
2295 if (list_empty(&pch->work_list)) {
2297 * Warn on nothing pending. Empty submitted_list may
2298 * break our pm_runtime usage counter as it is
2299 * updated on work_list emptiness status.
2301 WARN_ON(list_empty(&pch->submitted_list));
2302 pm_runtime_get_sync(pch->dmac->ddma.dev);
2304 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2305 spin_unlock_irqrestore(&pch->lock, flags);
2307 pl330_tasklet((unsigned long)pch);
2311 * We returned the last one of the circular list of descriptor(s)
2312 * from prep_xxx, so the argument to submit corresponds to the last
2313 * descriptor of the list.
2315 static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2317 struct dma_pl330_desc *desc, *last = to_desc(tx);
2318 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2319 dma_cookie_t cookie;
2320 unsigned long flags;
2322 spin_lock_irqsave(&pch->lock, flags);
2324 /* Assign cookies to all nodes */
2325 while (!list_empty(&last->node)) {
2326 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2328 desc->txd.callback = last->txd.callback;
2329 desc->txd.callback_param = last->txd.callback_param;
2333 dma_cookie_assign(&desc->txd);
2335 list_move_tail(&desc->node, &pch->submitted_list);
2339 cookie = dma_cookie_assign(&last->txd);
2340 list_add_tail(&last->node, &pch->submitted_list);
2341 spin_unlock_irqrestore(&pch->lock, flags);
2346 static inline void _init_desc(struct dma_pl330_desc *desc)
2348 desc->rqcfg.swap = SWAP_NO;
2349 desc->rqcfg.scctl = CCTRL0;
2350 desc->rqcfg.dcctl = CCTRL0;
2351 desc->txd.tx_submit = pl330_tx_submit;
2353 INIT_LIST_HEAD(&desc->node);
2356 /* Returns the number of descriptors added to the DMAC pool */
2357 static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
2359 struct dma_pl330_desc *desc;
2360 unsigned long flags;
2363 desc = kcalloc(count, sizeof(*desc), flg);
2367 spin_lock_irqsave(&pl330->pool_lock, flags);
2369 for (i = 0; i < count; i++) {
2370 _init_desc(&desc[i]);
2371 list_add_tail(&desc[i].node, &pl330->desc_pool);
2374 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2379 static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
2381 struct dma_pl330_desc *desc = NULL;
2382 unsigned long flags;
2384 spin_lock_irqsave(&pl330->pool_lock, flags);
2386 if (!list_empty(&pl330->desc_pool)) {
2387 desc = list_entry(pl330->desc_pool.next,
2388 struct dma_pl330_desc, node);
2390 list_del_init(&desc->node);
2392 desc->status = PREP;
2393 desc->txd.callback = NULL;
2396 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2401 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2403 struct pl330_dmac *pl330 = pch->dmac;
2404 u8 *peri_id = pch->chan.private;
2405 struct dma_pl330_desc *desc;
2407 /* Pluck one desc from the pool of DMAC */
2408 desc = pluck_desc(pl330);
2410 /* If the DMAC pool is empty, alloc new */
2412 if (!add_desc(pl330, GFP_ATOMIC, 1))
2416 desc = pluck_desc(pl330);
2418 dev_err(pch->dmac->ddma.dev,
2419 "%s:%d ALERT!\n", __func__, __LINE__);
2424 /* Initialize the descriptor */
2426 desc->txd.cookie = 0;
2427 async_tx_ack(&desc->txd);
2429 desc->peri = peri_id ? pch->chan.chan_id : 0;
2430 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2432 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2437 static inline void fill_px(struct pl330_xfer *px,
2438 dma_addr_t dst, dma_addr_t src, size_t len)
2445 static struct dma_pl330_desc *
2446 __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2447 dma_addr_t src, size_t len)
2449 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2452 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2453 __func__, __LINE__);
2458 * Ideally we should lookout for reqs bigger than
2459 * those that can be programmed with 256 bytes of
2460 * MC buffer, but considering a req size is seldom
2461 * going to be word-unaligned and more than 200MB,
2463 * Also, should the limit is reached we'd rather
2464 * have the platform increase MC buffer size than
2465 * complicating this API driver.
2467 fill_px(&desc->px, dst, src, len);
2472 /* Call after fixing burst size */
2473 static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2475 struct dma_pl330_chan *pch = desc->pchan;
2476 struct pl330_dmac *pl330 = pch->dmac;
2479 burst_len = pl330->pcfg.data_bus_width / 8;
2480 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2481 burst_len >>= desc->rqcfg.brst_size;
2483 /* src/dst_burst_len can't be more than 16 */
2487 while (burst_len > 1) {
2488 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2496 static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2497 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2498 size_t period_len, enum dma_transfer_direction direction,
2499 unsigned long flags)
2501 struct dma_pl330_desc *desc = NULL, *first = NULL;
2502 struct dma_pl330_chan *pch = to_pchan(chan);
2503 struct pl330_dmac *pl330 = pch->dmac;
2508 if (len % period_len != 0)
2511 if (!is_slave_direction(direction)) {
2512 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2513 __func__, __LINE__);
2517 for (i = 0; i < len / period_len; i++) {
2518 desc = pl330_get_desc(pch);
2520 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2521 __func__, __LINE__);
2526 spin_lock_irqsave(&pl330->pool_lock, flags);
2528 while (!list_empty(&first->node)) {
2529 desc = list_entry(first->node.next,
2530 struct dma_pl330_desc, node);
2531 list_move_tail(&desc->node, &pl330->desc_pool);
2534 list_move_tail(&first->node, &pl330->desc_pool);
2536 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2541 switch (direction) {
2542 case DMA_MEM_TO_DEV:
2543 desc->rqcfg.src_inc = 1;
2544 desc->rqcfg.dst_inc = 0;
2546 dst = pch->fifo_addr;
2548 case DMA_DEV_TO_MEM:
2549 desc->rqcfg.src_inc = 0;
2550 desc->rqcfg.dst_inc = 1;
2551 src = pch->fifo_addr;
2558 desc->rqtype = direction;
2559 desc->rqcfg.brst_size = pch->burst_sz;
2560 desc->rqcfg.brst_len = 1;
2561 desc->bytes_requested = period_len;
2562 fill_px(&desc->px, dst, src, period_len);
2567 list_add_tail(&desc->node, &first->node);
2569 dma_addr += period_len;
2576 desc->txd.flags = flags;
2581 static struct dma_async_tx_descriptor *
2582 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2583 dma_addr_t src, size_t len, unsigned long flags)
2585 struct dma_pl330_desc *desc;
2586 struct dma_pl330_chan *pch = to_pchan(chan);
2587 struct pl330_dmac *pl330;
2590 if (unlikely(!pch || !len))
2595 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2599 desc->rqcfg.src_inc = 1;
2600 desc->rqcfg.dst_inc = 1;
2601 desc->rqtype = DMA_MEM_TO_MEM;
2603 /* Select max possible burst size */
2604 burst = pl330->pcfg.data_bus_width / 8;
2607 * Make sure we use a burst size that aligns with all the memcpy
2608 * parameters because our DMA programming algorithm doesn't cope with
2609 * transfers which straddle an entry in the DMA device's MFIFO.
2611 while ((src | dst | len) & (burst - 1))
2614 desc->rqcfg.brst_size = 0;
2615 while (burst != (1 << desc->rqcfg.brst_size))
2616 desc->rqcfg.brst_size++;
2619 * If burst size is smaller than bus width then make sure we only
2620 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2622 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2623 desc->rqcfg.brst_len = 1;
2625 desc->rqcfg.brst_len = get_burst_len(desc, len);
2626 desc->bytes_requested = len;
2628 desc->txd.flags = flags;
2633 static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2634 struct dma_pl330_desc *first)
2636 unsigned long flags;
2637 struct dma_pl330_desc *desc;
2642 spin_lock_irqsave(&pl330->pool_lock, flags);
2644 while (!list_empty(&first->node)) {
2645 desc = list_entry(first->node.next,
2646 struct dma_pl330_desc, node);
2647 list_move_tail(&desc->node, &pl330->desc_pool);
2650 list_move_tail(&first->node, &pl330->desc_pool);
2652 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2655 static struct dma_async_tx_descriptor *
2656 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2657 unsigned int sg_len, enum dma_transfer_direction direction,
2658 unsigned long flg, void *context)
2660 struct dma_pl330_desc *first, *desc = NULL;
2661 struct dma_pl330_chan *pch = to_pchan(chan);
2662 struct scatterlist *sg;
2666 if (unlikely(!pch || !sgl || !sg_len))
2669 addr = pch->fifo_addr;
2673 for_each_sg(sgl, sg, sg_len, i) {
2675 desc = pl330_get_desc(pch);
2677 struct pl330_dmac *pl330 = pch->dmac;
2679 dev_err(pch->dmac->ddma.dev,
2680 "%s:%d Unable to fetch desc\n",
2681 __func__, __LINE__);
2682 __pl330_giveback_desc(pl330, first);
2690 list_add_tail(&desc->node, &first->node);
2692 if (direction == DMA_MEM_TO_DEV) {
2693 desc->rqcfg.src_inc = 1;
2694 desc->rqcfg.dst_inc = 0;
2696 addr, sg_dma_address(sg), sg_dma_len(sg));
2698 desc->rqcfg.src_inc = 0;
2699 desc->rqcfg.dst_inc = 1;
2701 sg_dma_address(sg), addr, sg_dma_len(sg));
2704 desc->rqcfg.brst_size = pch->burst_sz;
2705 desc->rqcfg.brst_len = 1;
2706 desc->rqtype = direction;
2707 desc->bytes_requested = sg_dma_len(sg);
2710 /* Return the last desc in the chain */
2711 desc->txd.flags = flg;
2715 static irqreturn_t pl330_irq_handler(int irq, void *data)
2717 if (pl330_update(data))
2723 #define PL330_DMA_BUSWIDTHS \
2724 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2725 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2726 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2727 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2728 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2731 * Runtime PM callbacks are provided by amba/bus.c driver.
2733 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2734 * bus driver will only disable/enable the clock in runtime PM callbacks.
2736 static int __maybe_unused pl330_suspend(struct device *dev)
2738 struct amba_device *pcdev = to_amba_device(dev);
2740 pm_runtime_disable(dev);
2742 if (!pm_runtime_status_suspended(dev)) {
2743 /* amba did not disable the clock */
2744 amba_pclk_disable(pcdev);
2746 amba_pclk_unprepare(pcdev);
2751 static int __maybe_unused pl330_resume(struct device *dev)
2753 struct amba_device *pcdev = to_amba_device(dev);
2756 ret = amba_pclk_prepare(pcdev);
2760 if (!pm_runtime_status_suspended(dev))
2761 ret = amba_pclk_enable(pcdev);
2763 pm_runtime_enable(dev);
2768 static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2771 pl330_probe(struct amba_device *adev, const struct amba_id *id)
2773 struct dma_pl330_platdata *pdat;
2774 struct pl330_config *pcfg;
2775 struct pl330_dmac *pl330;
2776 struct dma_pl330_chan *pch, *_p;
2777 struct dma_device *pd;
2778 struct resource *res;
2782 pdat = dev_get_platdata(&adev->dev);
2784 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2788 /* Allocate a new DMAC and its Channels */
2789 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2791 dev_err(&adev->dev, "unable to allocate mem\n");
2796 pd->dev = &adev->dev;
2798 pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
2801 pl330->base = devm_ioremap_resource(&adev->dev, res);
2802 if (IS_ERR(pl330->base))
2803 return PTR_ERR(pl330->base);
2805 amba_set_drvdata(adev, pl330);
2807 for (i = 0; i < AMBA_NR_IRQS; i++) {
2810 ret = devm_request_irq(&adev->dev, irq,
2811 pl330_irq_handler, 0,
2812 dev_name(&adev->dev), pl330);
2820 pcfg = &pl330->pcfg;
2822 pcfg->periph_id = adev->periphid;
2823 ret = pl330_add(pl330);
2827 INIT_LIST_HEAD(&pl330->desc_pool);
2828 spin_lock_init(&pl330->pool_lock);
2830 /* Create a descriptor pool of default size */
2831 if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
2832 dev_warn(&adev->dev, "unable to allocate desc\n");
2834 INIT_LIST_HEAD(&pd->channels);
2836 /* Initialize channel parameters */
2838 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
2840 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
2842 pl330->num_peripherals = num_chan;
2844 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2845 if (!pl330->peripherals) {
2847 dev_err(&adev->dev, "unable to allocate pl330->peripherals\n");
2851 for (i = 0; i < num_chan; i++) {
2852 pch = &pl330->peripherals[i];
2853 if (!adev->dev.of_node)
2854 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2856 pch->chan.private = adev->dev.of_node;
2858 INIT_LIST_HEAD(&pch->submitted_list);
2859 INIT_LIST_HEAD(&pch->work_list);
2860 INIT_LIST_HEAD(&pch->completed_list);
2861 spin_lock_init(&pch->lock);
2863 pch->chan.device = pd;
2866 /* Add the channel to the DMAC list */
2867 list_add_tail(&pch->chan.device_node, &pd->channels);
2871 pd->cap_mask = pdat->cap_mask;
2873 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
2874 if (pcfg->num_peri) {
2875 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2876 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
2877 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
2881 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2882 pd->device_free_chan_resources = pl330_free_chan_resources;
2883 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
2884 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
2885 pd->device_tx_status = pl330_tx_status;
2886 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2887 pd->device_config = pl330_config;
2888 pd->device_pause = pl330_pause;
2889 pd->device_terminate_all = pl330_terminate_all;
2890 pd->device_issue_pending = pl330_issue_pending;
2891 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
2892 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
2893 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2894 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2896 ret = dma_async_device_register(pd);
2898 dev_err(&adev->dev, "unable to register DMAC\n");
2902 if (adev->dev.of_node) {
2903 ret = of_dma_controller_register(adev->dev.of_node,
2904 of_dma_pl330_xlate, pl330);
2907 "unable to register DMA to the generic DT DMA helpers\n");
2911 adev->dev.dma_parms = &pl330->dma_parms;
2914 * This is the limit for transfers with a buswidth of 1, larger
2915 * buswidths will have larger limits.
2917 ret = dma_set_max_seg_size(&adev->dev, 1900800);
2919 dev_err(&adev->dev, "unable to set the seg size\n");
2922 dev_info(&adev->dev,
2923 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
2924 dev_info(&adev->dev,
2925 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2926 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2927 pcfg->num_peri, pcfg->num_events);
2929 pm_runtime_irq_safe(&adev->dev);
2930 pm_runtime_use_autosuspend(&adev->dev);
2931 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
2932 pm_runtime_mark_last_busy(&adev->dev);
2933 pm_runtime_put_autosuspend(&adev->dev);
2938 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
2941 /* Remove the channel */
2942 list_del(&pch->chan.device_node);
2944 /* Flush the channel */
2946 pl330_terminate_all(&pch->chan);
2947 pl330_free_chan_resources(&pch->chan);
2956 static int pl330_remove(struct amba_device *adev)
2958 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
2959 struct dma_pl330_chan *pch, *_p;
2961 pm_runtime_get_noresume(pl330->ddma.dev);
2963 if (adev->dev.of_node)
2964 of_dma_controller_free(adev->dev.of_node);
2966 dma_async_device_unregister(&pl330->ddma);
2969 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
2972 /* Remove the channel */
2973 list_del(&pch->chan.device_node);
2975 /* Flush the channel */
2977 pl330_terminate_all(&pch->chan);
2978 pl330_free_chan_resources(&pch->chan);
2987 static struct amba_id pl330_ids[] = {
2995 MODULE_DEVICE_TABLE(amba, pl330_ids);
2997 static struct amba_driver pl330_driver = {
2999 .owner = THIS_MODULE,
3000 .name = "dma-pl330",
3003 .id_table = pl330_ids,
3004 .probe = pl330_probe,
3005 .remove = pl330_remove,
3008 module_amba_driver(pl330_driver);
3010 MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3011 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3012 MODULE_LICENSE("GPL");