2 * Renesas R-Car Gen2 DMA Controller Driver
4 * Copyright (C) 2014 Renesas Electronics Inc.
6 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
8 * This is free software; you can redistribute it and/or modify
9 * it under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
13 #include <linux/dma-mapping.h>
14 #include <linux/dmaengine.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
20 #include <linux/of_dma.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
27 #include "../dmaengine.h"
30 * struct rcar_dmac_xfer_chunk - Descriptor for a hardware transfer
31 * @node: entry in the parent's chunks list
32 * @src_addr: device source address
33 * @dst_addr: device destination address
34 * @size: transfer size in bytes
36 struct rcar_dmac_xfer_chunk {
37 struct list_head node;
45 * struct rcar_dmac_hw_desc - Hardware descriptor for a transfer chunk
46 * @sar: value of the SAR register (source address)
47 * @dar: value of the DAR register (destination address)
48 * @tcr: value of the TCR register (transfer count)
50 struct rcar_dmac_hw_desc {
55 } __attribute__((__packed__));
58 * struct rcar_dmac_desc - R-Car Gen2 DMA Transfer Descriptor
59 * @async_tx: base DMA asynchronous transaction descriptor
60 * @direction: direction of the DMA transfer
61 * @xfer_shift: log2 of the transfer size
62 * @chcr: value of the channel configuration register for this transfer
63 * @node: entry in the channel's descriptors lists
64 * @chunks: list of transfer chunks for this transfer
65 * @running: the transfer chunk being currently processed
66 * @nchunks: number of transfer chunks for this transfer
67 * @hwdescs.use: whether the transfer descriptor uses hardware descriptors
68 * @hwdescs.mem: hardware descriptors memory for the transfer
69 * @hwdescs.dma: device address of the hardware descriptors memory
70 * @hwdescs.size: size of the hardware descriptors in bytes
71 * @size: transfer size in bytes
72 * @cyclic: when set indicates that the DMA transfer is cyclic
74 struct rcar_dmac_desc {
75 struct dma_async_tx_descriptor async_tx;
76 enum dma_transfer_direction direction;
77 unsigned int xfer_shift;
80 struct list_head node;
81 struct list_head chunks;
82 struct rcar_dmac_xfer_chunk *running;
87 struct rcar_dmac_hw_desc *mem;
96 #define to_rcar_dmac_desc(d) container_of(d, struct rcar_dmac_desc, async_tx)
99 * struct rcar_dmac_desc_page - One page worth of descriptors
100 * @node: entry in the channel's pages list
101 * @descs: array of DMA descriptors
102 * @chunks: array of transfer chunk descriptors
104 struct rcar_dmac_desc_page {
105 struct list_head node;
108 struct rcar_dmac_desc descs[0];
109 struct rcar_dmac_xfer_chunk chunks[0];
113 #define RCAR_DMAC_DESCS_PER_PAGE \
114 ((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, descs)) / \
115 sizeof(struct rcar_dmac_desc))
116 #define RCAR_DMAC_XFER_CHUNKS_PER_PAGE \
117 ((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, chunks)) / \
118 sizeof(struct rcar_dmac_xfer_chunk))
121 * struct rcar_dmac_chan_slave - Slave configuration
122 * @slave_addr: slave memory address
123 * @xfer_size: size (in bytes) of hardware transfers
125 struct rcar_dmac_chan_slave {
126 phys_addr_t slave_addr;
127 unsigned int xfer_size;
131 * struct rcar_dmac_chan_map - Map of slave device phys to dma address
132 * @addr: slave dma address
133 * @dir: direction of mapping
134 * @slave: slave configuration that is mapped
136 struct rcar_dmac_chan_map {
138 enum dma_data_direction dir;
139 struct rcar_dmac_chan_slave slave;
143 * struct rcar_dmac_chan - R-Car Gen2 DMA Controller Channel
144 * @chan: base DMA channel object
145 * @iomem: channel I/O memory base
146 * @index: index of this channel in the controller
147 * @src: slave memory address and size on the source side
148 * @dst: slave memory address and size on the destination side
149 * @mid_rid: hardware MID/RID for the DMA client using this channel
150 * @lock: protects the channel CHCR register and the desc members
151 * @desc.free: list of free descriptors
152 * @desc.pending: list of pending descriptors (submitted with tx_submit)
153 * @desc.active: list of active descriptors (activated with issue_pending)
154 * @desc.done: list of completed descriptors
155 * @desc.wait: list of descriptors waiting for an ack
156 * @desc.running: the descriptor being processed (a member of the active list)
157 * @desc.chunks_free: list of free transfer chunk descriptors
158 * @desc.pages: list of pages used by allocated descriptors
160 struct rcar_dmac_chan {
161 struct dma_chan chan;
165 struct rcar_dmac_chan_slave src;
166 struct rcar_dmac_chan_slave dst;
167 struct rcar_dmac_chan_map map;
173 struct list_head free;
174 struct list_head pending;
175 struct list_head active;
176 struct list_head done;
177 struct list_head wait;
178 struct rcar_dmac_desc *running;
180 struct list_head chunks_free;
182 struct list_head pages;
186 #define to_rcar_dmac_chan(c) container_of(c, struct rcar_dmac_chan, chan)
189 * struct rcar_dmac - R-Car Gen2 DMA Controller
190 * @engine: base DMA engine object
191 * @dev: the hardware device
192 * @iomem: remapped I/O memory base
193 * @n_channels: number of available channels
194 * @channels: array of DMAC channels
195 * @modules: bitmask of client modules in use
198 struct dma_device engine;
202 unsigned int n_channels;
203 struct rcar_dmac_chan *channels;
205 DECLARE_BITMAP(modules, 256);
208 #define to_rcar_dmac(d) container_of(d, struct rcar_dmac, engine)
210 /* -----------------------------------------------------------------------------
214 #define RCAR_DMAC_CHAN_OFFSET(i) (0x8000 + 0x80 * (i))
216 #define RCAR_DMAISTA 0x0020
217 #define RCAR_DMASEC 0x0030
218 #define RCAR_DMAOR 0x0060
219 #define RCAR_DMAOR_PRI_FIXED (0 << 8)
220 #define RCAR_DMAOR_PRI_ROUND_ROBIN (3 << 8)
221 #define RCAR_DMAOR_AE (1 << 2)
222 #define RCAR_DMAOR_DME (1 << 0)
223 #define RCAR_DMACHCLR 0x0080
224 #define RCAR_DMADPSEC 0x00a0
226 #define RCAR_DMASAR 0x0000
227 #define RCAR_DMADAR 0x0004
228 #define RCAR_DMATCR 0x0008
229 #define RCAR_DMATCR_MASK 0x00ffffff
230 #define RCAR_DMATSR 0x0028
231 #define RCAR_DMACHCR 0x000c
232 #define RCAR_DMACHCR_CAE (1 << 31)
233 #define RCAR_DMACHCR_CAIE (1 << 30)
234 #define RCAR_DMACHCR_DPM_DISABLED (0 << 28)
235 #define RCAR_DMACHCR_DPM_ENABLED (1 << 28)
236 #define RCAR_DMACHCR_DPM_REPEAT (2 << 28)
237 #define RCAR_DMACHCR_DPM_INFINITE (3 << 28)
238 #define RCAR_DMACHCR_RPT_SAR (1 << 27)
239 #define RCAR_DMACHCR_RPT_DAR (1 << 26)
240 #define RCAR_DMACHCR_RPT_TCR (1 << 25)
241 #define RCAR_DMACHCR_DPB (1 << 22)
242 #define RCAR_DMACHCR_DSE (1 << 19)
243 #define RCAR_DMACHCR_DSIE (1 << 18)
244 #define RCAR_DMACHCR_TS_1B ((0 << 20) | (0 << 3))
245 #define RCAR_DMACHCR_TS_2B ((0 << 20) | (1 << 3))
246 #define RCAR_DMACHCR_TS_4B ((0 << 20) | (2 << 3))
247 #define RCAR_DMACHCR_TS_16B ((0 << 20) | (3 << 3))
248 #define RCAR_DMACHCR_TS_32B ((1 << 20) | (0 << 3))
249 #define RCAR_DMACHCR_TS_64B ((1 << 20) | (1 << 3))
250 #define RCAR_DMACHCR_TS_8B ((1 << 20) | (3 << 3))
251 #define RCAR_DMACHCR_DM_FIXED (0 << 14)
252 #define RCAR_DMACHCR_DM_INC (1 << 14)
253 #define RCAR_DMACHCR_DM_DEC (2 << 14)
254 #define RCAR_DMACHCR_SM_FIXED (0 << 12)
255 #define RCAR_DMACHCR_SM_INC (1 << 12)
256 #define RCAR_DMACHCR_SM_DEC (2 << 12)
257 #define RCAR_DMACHCR_RS_AUTO (4 << 8)
258 #define RCAR_DMACHCR_RS_DMARS (8 << 8)
259 #define RCAR_DMACHCR_IE (1 << 2)
260 #define RCAR_DMACHCR_TE (1 << 1)
261 #define RCAR_DMACHCR_DE (1 << 0)
262 #define RCAR_DMATCRB 0x0018
263 #define RCAR_DMATSRB 0x0038
264 #define RCAR_DMACHCRB 0x001c
265 #define RCAR_DMACHCRB_DCNT(n) ((n) << 24)
266 #define RCAR_DMACHCRB_DPTR_MASK (0xff << 16)
267 #define RCAR_DMACHCRB_DPTR_SHIFT 16
268 #define RCAR_DMACHCRB_DRST (1 << 15)
269 #define RCAR_DMACHCRB_DTS (1 << 8)
270 #define RCAR_DMACHCRB_SLM_NORMAL (0 << 4)
271 #define RCAR_DMACHCRB_SLM_CLK(n) ((8 | (n)) << 4)
272 #define RCAR_DMACHCRB_PRI(n) ((n) << 0)
273 #define RCAR_DMARS 0x0040
274 #define RCAR_DMABUFCR 0x0048
275 #define RCAR_DMABUFCR_MBU(n) ((n) << 16)
276 #define RCAR_DMABUFCR_ULB(n) ((n) << 0)
277 #define RCAR_DMADPBASE 0x0050
278 #define RCAR_DMADPBASE_MASK 0xfffffff0
279 #define RCAR_DMADPBASE_SEL (1 << 0)
280 #define RCAR_DMADPCR 0x0054
281 #define RCAR_DMADPCR_DIPT(n) ((n) << 24)
282 #define RCAR_DMAFIXSAR 0x0010
283 #define RCAR_DMAFIXDAR 0x0014
284 #define RCAR_DMAFIXDPBASE 0x0060
286 /* Hardcode the MEMCPY transfer size to 4 bytes. */
287 #define RCAR_DMAC_MEMCPY_XFER_SIZE 4
289 /* -----------------------------------------------------------------------------
293 static void rcar_dmac_write(struct rcar_dmac *dmac, u32 reg, u32 data)
295 if (reg == RCAR_DMAOR)
296 writew(data, dmac->iomem + reg);
298 writel(data, dmac->iomem + reg);
301 static u32 rcar_dmac_read(struct rcar_dmac *dmac, u32 reg)
303 if (reg == RCAR_DMAOR)
304 return readw(dmac->iomem + reg);
306 return readl(dmac->iomem + reg);
309 static u32 rcar_dmac_chan_read(struct rcar_dmac_chan *chan, u32 reg)
311 if (reg == RCAR_DMARS)
312 return readw(chan->iomem + reg);
314 return readl(chan->iomem + reg);
317 static void rcar_dmac_chan_write(struct rcar_dmac_chan *chan, u32 reg, u32 data)
319 if (reg == RCAR_DMARS)
320 writew(data, chan->iomem + reg);
322 writel(data, chan->iomem + reg);
325 /* -----------------------------------------------------------------------------
326 * Initialization and configuration
329 static bool rcar_dmac_chan_is_busy(struct rcar_dmac_chan *chan)
331 u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
333 return !!(chcr & (RCAR_DMACHCR_DE | RCAR_DMACHCR_TE));
336 static void rcar_dmac_chan_start_xfer(struct rcar_dmac_chan *chan)
338 struct rcar_dmac_desc *desc = chan->desc.running;
339 u32 chcr = desc->chcr;
341 WARN_ON_ONCE(rcar_dmac_chan_is_busy(chan));
343 if (chan->mid_rid >= 0)
344 rcar_dmac_chan_write(chan, RCAR_DMARS, chan->mid_rid);
346 if (desc->hwdescs.use) {
347 struct rcar_dmac_xfer_chunk *chunk =
348 list_first_entry(&desc->chunks,
349 struct rcar_dmac_xfer_chunk, node);
351 dev_dbg(chan->chan.device->dev,
352 "chan%u: queue desc %p: %u@%pad\n",
353 chan->index, desc, desc->nchunks, &desc->hwdescs.dma);
355 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
356 rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR,
357 chunk->src_addr >> 32);
358 rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR,
359 chunk->dst_addr >> 32);
360 rcar_dmac_chan_write(chan, RCAR_DMAFIXDPBASE,
361 desc->hwdescs.dma >> 32);
363 rcar_dmac_chan_write(chan, RCAR_DMADPBASE,
364 (desc->hwdescs.dma & 0xfffffff0) |
366 rcar_dmac_chan_write(chan, RCAR_DMACHCRB,
367 RCAR_DMACHCRB_DCNT(desc->nchunks - 1) |
371 * Errata: When descriptor memory is accessed through an IOMMU
372 * the DMADAR register isn't initialized automatically from the
373 * first descriptor at beginning of transfer by the DMAC like it
374 * should. Initialize it manually with the destination address
375 * of the first chunk.
377 rcar_dmac_chan_write(chan, RCAR_DMADAR,
378 chunk->dst_addr & 0xffffffff);
381 * Program the descriptor stage interrupt to occur after the end
382 * of the first stage.
384 rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(1));
386 chcr |= RCAR_DMACHCR_RPT_SAR | RCAR_DMACHCR_RPT_DAR
387 | RCAR_DMACHCR_RPT_TCR | RCAR_DMACHCR_DPB;
390 * If the descriptor isn't cyclic enable normal descriptor mode
391 * and the transfer completion interrupt.
394 chcr |= RCAR_DMACHCR_DPM_ENABLED | RCAR_DMACHCR_IE;
396 * If the descriptor is cyclic and has a callback enable the
397 * descriptor stage interrupt in infinite repeat mode.
399 else if (desc->async_tx.callback)
400 chcr |= RCAR_DMACHCR_DPM_INFINITE | RCAR_DMACHCR_DSIE;
402 * Otherwise just select infinite repeat mode without any
406 chcr |= RCAR_DMACHCR_DPM_INFINITE;
408 struct rcar_dmac_xfer_chunk *chunk = desc->running;
410 dev_dbg(chan->chan.device->dev,
411 "chan%u: queue chunk %p: %u@%pad -> %pad\n",
412 chan->index, chunk, chunk->size, &chunk->src_addr,
415 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
416 rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR,
417 chunk->src_addr >> 32);
418 rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR,
419 chunk->dst_addr >> 32);
421 rcar_dmac_chan_write(chan, RCAR_DMASAR,
422 chunk->src_addr & 0xffffffff);
423 rcar_dmac_chan_write(chan, RCAR_DMADAR,
424 chunk->dst_addr & 0xffffffff);
425 rcar_dmac_chan_write(chan, RCAR_DMATCR,
426 chunk->size >> desc->xfer_shift);
428 chcr |= RCAR_DMACHCR_DPM_DISABLED | RCAR_DMACHCR_IE;
431 rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr | RCAR_DMACHCR_DE);
434 static int rcar_dmac_init(struct rcar_dmac *dmac)
438 /* Clear all channels and enable the DMAC globally. */
439 rcar_dmac_write(dmac, RCAR_DMACHCLR, GENMASK(dmac->n_channels - 1, 0));
440 rcar_dmac_write(dmac, RCAR_DMAOR,
441 RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME);
443 dmaor = rcar_dmac_read(dmac, RCAR_DMAOR);
444 if ((dmaor & (RCAR_DMAOR_AE | RCAR_DMAOR_DME)) != RCAR_DMAOR_DME) {
445 dev_warn(dmac->dev, "DMAOR initialization failed.\n");
452 /* -----------------------------------------------------------------------------
453 * Descriptors submission
456 static dma_cookie_t rcar_dmac_tx_submit(struct dma_async_tx_descriptor *tx)
458 struct rcar_dmac_chan *chan = to_rcar_dmac_chan(tx->chan);
459 struct rcar_dmac_desc *desc = to_rcar_dmac_desc(tx);
463 spin_lock_irqsave(&chan->lock, flags);
465 cookie = dma_cookie_assign(tx);
467 dev_dbg(chan->chan.device->dev, "chan%u: submit #%d@%p\n",
468 chan->index, tx->cookie, desc);
470 list_add_tail(&desc->node, &chan->desc.pending);
471 desc->running = list_first_entry(&desc->chunks,
472 struct rcar_dmac_xfer_chunk, node);
474 spin_unlock_irqrestore(&chan->lock, flags);
479 /* -----------------------------------------------------------------------------
480 * Descriptors allocation and free
484 * rcar_dmac_desc_alloc - Allocate a page worth of DMA descriptors
485 * @chan: the DMA channel
486 * @gfp: allocation flags
488 static int rcar_dmac_desc_alloc(struct rcar_dmac_chan *chan, gfp_t gfp)
490 struct rcar_dmac_desc_page *page;
495 page = (void *)get_zeroed_page(gfp);
499 for (i = 0; i < RCAR_DMAC_DESCS_PER_PAGE; ++i) {
500 struct rcar_dmac_desc *desc = &page->descs[i];
502 dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan);
503 desc->async_tx.tx_submit = rcar_dmac_tx_submit;
504 INIT_LIST_HEAD(&desc->chunks);
506 list_add_tail(&desc->node, &list);
509 spin_lock_irqsave(&chan->lock, flags);
510 list_splice_tail(&list, &chan->desc.free);
511 list_add_tail(&page->node, &chan->desc.pages);
512 spin_unlock_irqrestore(&chan->lock, flags);
518 * rcar_dmac_desc_put - Release a DMA transfer descriptor
519 * @chan: the DMA channel
520 * @desc: the descriptor
522 * Put the descriptor and its transfer chunk descriptors back in the channel's
523 * free descriptors lists. The descriptor's chunks list will be reinitialized to
524 * an empty list as a result.
526 * The descriptor must have been removed from the channel's lists before calling
529 static void rcar_dmac_desc_put(struct rcar_dmac_chan *chan,
530 struct rcar_dmac_desc *desc)
534 spin_lock_irqsave(&chan->lock, flags);
535 list_splice_tail_init(&desc->chunks, &chan->desc.chunks_free);
536 list_add(&desc->node, &chan->desc.free);
537 spin_unlock_irqrestore(&chan->lock, flags);
540 static void rcar_dmac_desc_recycle_acked(struct rcar_dmac_chan *chan)
542 struct rcar_dmac_desc *desc, *_desc;
547 * We have to temporarily move all descriptors from the wait list to a
548 * local list as iterating over the wait list, even with
549 * list_for_each_entry_safe, isn't safe if we release the channel lock
550 * around the rcar_dmac_desc_put() call.
552 spin_lock_irqsave(&chan->lock, flags);
553 list_splice_init(&chan->desc.wait, &list);
554 spin_unlock_irqrestore(&chan->lock, flags);
556 list_for_each_entry_safe(desc, _desc, &list, node) {
557 if (async_tx_test_ack(&desc->async_tx)) {
558 list_del(&desc->node);
559 rcar_dmac_desc_put(chan, desc);
563 if (list_empty(&list))
566 /* Put the remaining descriptors back in the wait list. */
567 spin_lock_irqsave(&chan->lock, flags);
568 list_splice(&list, &chan->desc.wait);
569 spin_unlock_irqrestore(&chan->lock, flags);
573 * rcar_dmac_desc_get - Allocate a descriptor for a DMA transfer
574 * @chan: the DMA channel
576 * Locking: This function must be called in a non-atomic context.
578 * Return: A pointer to the allocated descriptor or NULL if no descriptor can
581 static struct rcar_dmac_desc *rcar_dmac_desc_get(struct rcar_dmac_chan *chan)
583 struct rcar_dmac_desc *desc;
587 /* Recycle acked descriptors before attempting allocation. */
588 rcar_dmac_desc_recycle_acked(chan);
590 spin_lock_irqsave(&chan->lock, flags);
592 while (list_empty(&chan->desc.free)) {
594 * No free descriptors, allocate a page worth of them and try
595 * again, as someone else could race us to get the newly
596 * allocated descriptors. If the allocation fails return an
599 spin_unlock_irqrestore(&chan->lock, flags);
600 ret = rcar_dmac_desc_alloc(chan, GFP_NOWAIT);
603 spin_lock_irqsave(&chan->lock, flags);
606 desc = list_first_entry(&chan->desc.free, struct rcar_dmac_desc, node);
607 list_del(&desc->node);
609 spin_unlock_irqrestore(&chan->lock, flags);
615 * rcar_dmac_xfer_chunk_alloc - Allocate a page worth of transfer chunks
616 * @chan: the DMA channel
617 * @gfp: allocation flags
619 static int rcar_dmac_xfer_chunk_alloc(struct rcar_dmac_chan *chan, gfp_t gfp)
621 struct rcar_dmac_desc_page *page;
626 page = (void *)get_zeroed_page(gfp);
630 for (i = 0; i < RCAR_DMAC_XFER_CHUNKS_PER_PAGE; ++i) {
631 struct rcar_dmac_xfer_chunk *chunk = &page->chunks[i];
633 list_add_tail(&chunk->node, &list);
636 spin_lock_irqsave(&chan->lock, flags);
637 list_splice_tail(&list, &chan->desc.chunks_free);
638 list_add_tail(&page->node, &chan->desc.pages);
639 spin_unlock_irqrestore(&chan->lock, flags);
645 * rcar_dmac_xfer_chunk_get - Allocate a transfer chunk for a DMA transfer
646 * @chan: the DMA channel
648 * Locking: This function must be called in a non-atomic context.
650 * Return: A pointer to the allocated transfer chunk descriptor or NULL if no
651 * descriptor can be allocated.
653 static struct rcar_dmac_xfer_chunk *
654 rcar_dmac_xfer_chunk_get(struct rcar_dmac_chan *chan)
656 struct rcar_dmac_xfer_chunk *chunk;
660 spin_lock_irqsave(&chan->lock, flags);
662 while (list_empty(&chan->desc.chunks_free)) {
664 * No free descriptors, allocate a page worth of them and try
665 * again, as someone else could race us to get the newly
666 * allocated descriptors. If the allocation fails return an
669 spin_unlock_irqrestore(&chan->lock, flags);
670 ret = rcar_dmac_xfer_chunk_alloc(chan, GFP_NOWAIT);
673 spin_lock_irqsave(&chan->lock, flags);
676 chunk = list_first_entry(&chan->desc.chunks_free,
677 struct rcar_dmac_xfer_chunk, node);
678 list_del(&chunk->node);
680 spin_unlock_irqrestore(&chan->lock, flags);
685 static void rcar_dmac_realloc_hwdesc(struct rcar_dmac_chan *chan,
686 struct rcar_dmac_desc *desc, size_t size)
689 * dma_alloc_coherent() allocates memory in page size increments. To
690 * avoid reallocating the hardware descriptors when the allocated size
691 * wouldn't change align the requested size to a multiple of the page
694 size = PAGE_ALIGN(size);
696 if (desc->hwdescs.size == size)
699 if (desc->hwdescs.mem) {
700 dma_free_coherent(chan->chan.device->dev, desc->hwdescs.size,
701 desc->hwdescs.mem, desc->hwdescs.dma);
702 desc->hwdescs.mem = NULL;
703 desc->hwdescs.size = 0;
709 desc->hwdescs.mem = dma_alloc_coherent(chan->chan.device->dev, size,
710 &desc->hwdescs.dma, GFP_NOWAIT);
711 if (!desc->hwdescs.mem)
714 desc->hwdescs.size = size;
717 static int rcar_dmac_fill_hwdesc(struct rcar_dmac_chan *chan,
718 struct rcar_dmac_desc *desc)
720 struct rcar_dmac_xfer_chunk *chunk;
721 struct rcar_dmac_hw_desc *hwdesc;
723 rcar_dmac_realloc_hwdesc(chan, desc, desc->nchunks * sizeof(*hwdesc));
725 hwdesc = desc->hwdescs.mem;
729 list_for_each_entry(chunk, &desc->chunks, node) {
730 hwdesc->sar = chunk->src_addr;
731 hwdesc->dar = chunk->dst_addr;
732 hwdesc->tcr = chunk->size >> desc->xfer_shift;
739 /* -----------------------------------------------------------------------------
743 static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan)
745 u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
747 chcr &= ~(RCAR_DMACHCR_DSE | RCAR_DMACHCR_DSIE | RCAR_DMACHCR_IE |
748 RCAR_DMACHCR_TE | RCAR_DMACHCR_DE);
749 rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
752 static void rcar_dmac_chan_reinit(struct rcar_dmac_chan *chan)
754 struct rcar_dmac_desc *desc, *_desc;
758 spin_lock_irqsave(&chan->lock, flags);
760 /* Move all non-free descriptors to the local lists. */
761 list_splice_init(&chan->desc.pending, &descs);
762 list_splice_init(&chan->desc.active, &descs);
763 list_splice_init(&chan->desc.done, &descs);
764 list_splice_init(&chan->desc.wait, &descs);
766 chan->desc.running = NULL;
768 spin_unlock_irqrestore(&chan->lock, flags);
770 list_for_each_entry_safe(desc, _desc, &descs, node) {
771 list_del(&desc->node);
772 rcar_dmac_desc_put(chan, desc);
776 static void rcar_dmac_stop(struct rcar_dmac *dmac)
778 rcar_dmac_write(dmac, RCAR_DMAOR, 0);
781 static void rcar_dmac_abort(struct rcar_dmac *dmac)
785 /* Stop all channels. */
786 for (i = 0; i < dmac->n_channels; ++i) {
787 struct rcar_dmac_chan *chan = &dmac->channels[i];
789 /* Stop and reinitialize the channel. */
790 spin_lock(&chan->lock);
791 rcar_dmac_chan_halt(chan);
792 spin_unlock(&chan->lock);
794 rcar_dmac_chan_reinit(chan);
798 /* -----------------------------------------------------------------------------
799 * Descriptors preparation
802 static void rcar_dmac_chan_configure_desc(struct rcar_dmac_chan *chan,
803 struct rcar_dmac_desc *desc)
805 static const u32 chcr_ts[] = {
806 RCAR_DMACHCR_TS_1B, RCAR_DMACHCR_TS_2B,
807 RCAR_DMACHCR_TS_4B, RCAR_DMACHCR_TS_8B,
808 RCAR_DMACHCR_TS_16B, RCAR_DMACHCR_TS_32B,
812 unsigned int xfer_size;
815 switch (desc->direction) {
817 chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_FIXED
818 | RCAR_DMACHCR_RS_DMARS;
819 xfer_size = chan->src.xfer_size;
823 chcr = RCAR_DMACHCR_DM_FIXED | RCAR_DMACHCR_SM_INC
824 | RCAR_DMACHCR_RS_DMARS;
825 xfer_size = chan->dst.xfer_size;
830 chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_INC
831 | RCAR_DMACHCR_RS_AUTO;
832 xfer_size = RCAR_DMAC_MEMCPY_XFER_SIZE;
836 desc->xfer_shift = ilog2(xfer_size);
837 desc->chcr = chcr | chcr_ts[desc->xfer_shift];
841 * rcar_dmac_chan_prep_sg - prepare transfer descriptors from an SG list
843 * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
844 * converted to scatter-gather to guarantee consistent locking and a correct
845 * list manipulation. For slave DMA direction carries the usual meaning, and,
846 * logically, the SG list is RAM and the addr variable contains slave address,
847 * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM
848 * and the SG list contains only one element and points at the source buffer.
850 static struct dma_async_tx_descriptor *
851 rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl,
852 unsigned int sg_len, dma_addr_t dev_addr,
853 enum dma_transfer_direction dir, unsigned long dma_flags,
856 struct rcar_dmac_xfer_chunk *chunk;
857 struct rcar_dmac_desc *desc;
858 struct scatterlist *sg;
859 unsigned int nchunks = 0;
860 unsigned int max_chunk_size;
861 unsigned int full_size = 0;
862 bool cross_boundary = false;
864 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
869 desc = rcar_dmac_desc_get(chan);
873 desc->async_tx.flags = dma_flags;
874 desc->async_tx.cookie = -EBUSY;
876 desc->cyclic = cyclic;
877 desc->direction = dir;
879 rcar_dmac_chan_configure_desc(chan, desc);
881 max_chunk_size = (RCAR_DMATCR_MASK + 1) << desc->xfer_shift;
884 * Allocate and fill the transfer chunk descriptors. We own the only
885 * reference to the DMA descriptor, there's no need for locking.
887 for_each_sg(sgl, sg, sg_len, i) {
888 dma_addr_t mem_addr = sg_dma_address(sg);
889 unsigned int len = sg_dma_len(sg);
893 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
895 high_dev_addr = dev_addr >> 32;
896 high_mem_addr = mem_addr >> 32;
899 if ((dev_addr >> 32 != high_dev_addr) ||
900 (mem_addr >> 32 != high_mem_addr))
901 cross_boundary = true;
904 unsigned int size = min(len, max_chunk_size);
906 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
908 * Prevent individual transfers from crossing 4GB
911 if (dev_addr >> 32 != (dev_addr + size - 1) >> 32) {
912 size = ALIGN(dev_addr, 1ULL << 32) - dev_addr;
913 cross_boundary = true;
915 if (mem_addr >> 32 != (mem_addr + size - 1) >> 32) {
916 size = ALIGN(mem_addr, 1ULL << 32) - mem_addr;
917 cross_boundary = true;
921 chunk = rcar_dmac_xfer_chunk_get(chan);
923 rcar_dmac_desc_put(chan, desc);
927 if (dir == DMA_DEV_TO_MEM) {
928 chunk->src_addr = dev_addr;
929 chunk->dst_addr = mem_addr;
931 chunk->src_addr = mem_addr;
932 chunk->dst_addr = dev_addr;
937 dev_dbg(chan->chan.device->dev,
938 "chan%u: chunk %p/%p sgl %u@%p, %u/%u %pad -> %pad\n",
939 chan->index, chunk, desc, i, sg, size, len,
940 &chunk->src_addr, &chunk->dst_addr);
943 if (dir == DMA_MEM_TO_MEM)
948 list_add_tail(&chunk->node, &desc->chunks);
953 desc->nchunks = nchunks;
954 desc->size = full_size;
957 * Use hardware descriptor lists if possible when more than one chunk
958 * needs to be transferred (otherwise they don't make much sense).
960 * Source/Destination address should be located in same 4GiB region
961 * in the 40bit address space when it uses Hardware descriptor,
962 * and cross_boundary is checking it.
964 desc->hwdescs.use = !cross_boundary && nchunks > 1;
965 if (desc->hwdescs.use) {
966 if (rcar_dmac_fill_hwdesc(chan, desc) < 0)
967 desc->hwdescs.use = false;
970 return &desc->async_tx;
973 /* -----------------------------------------------------------------------------
974 * DMA engine operations
977 static int rcar_dmac_alloc_chan_resources(struct dma_chan *chan)
979 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
982 INIT_LIST_HEAD(&rchan->desc.chunks_free);
983 INIT_LIST_HEAD(&rchan->desc.pages);
985 /* Preallocate descriptors. */
986 ret = rcar_dmac_xfer_chunk_alloc(rchan, GFP_KERNEL);
990 ret = rcar_dmac_desc_alloc(rchan, GFP_KERNEL);
994 return pm_runtime_get_sync(chan->device->dev);
997 static void rcar_dmac_free_chan_resources(struct dma_chan *chan)
999 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1000 struct rcar_dmac *dmac = to_rcar_dmac(chan->device);
1001 struct rcar_dmac_chan_map *map = &rchan->map;
1002 struct rcar_dmac_desc_page *page, *_page;
1003 struct rcar_dmac_desc *desc;
1006 /* Protect against ISR */
1007 spin_lock_irq(&rchan->lock);
1008 rcar_dmac_chan_halt(rchan);
1009 spin_unlock_irq(&rchan->lock);
1011 /* Now no new interrupts will occur */
1013 if (rchan->mid_rid >= 0) {
1014 /* The caller is holding dma_list_mutex */
1015 clear_bit(rchan->mid_rid, dmac->modules);
1016 rchan->mid_rid = -EINVAL;
1019 list_splice_init(&rchan->desc.free, &list);
1020 list_splice_init(&rchan->desc.pending, &list);
1021 list_splice_init(&rchan->desc.active, &list);
1022 list_splice_init(&rchan->desc.done, &list);
1023 list_splice_init(&rchan->desc.wait, &list);
1025 rchan->desc.running = NULL;
1027 list_for_each_entry(desc, &list, node)
1028 rcar_dmac_realloc_hwdesc(rchan, desc, 0);
1030 list_for_each_entry_safe(page, _page, &rchan->desc.pages, node) {
1031 list_del(&page->node);
1032 free_page((unsigned long)page);
1035 /* Remove slave mapping if present. */
1036 if (map->slave.xfer_size) {
1037 dma_unmap_resource(chan->device->dev, map->addr,
1038 map->slave.xfer_size, map->dir, 0);
1039 map->slave.xfer_size = 0;
1042 pm_runtime_put(chan->device->dev);
1045 static struct dma_async_tx_descriptor *
1046 rcar_dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
1047 dma_addr_t dma_src, size_t len, unsigned long flags)
1049 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1050 struct scatterlist sgl;
1055 sg_init_table(&sgl, 1);
1056 sg_set_page(&sgl, pfn_to_page(PFN_DOWN(dma_src)), len,
1057 offset_in_page(dma_src));
1058 sg_dma_address(&sgl) = dma_src;
1059 sg_dma_len(&sgl) = len;
1061 return rcar_dmac_chan_prep_sg(rchan, &sgl, 1, dma_dest,
1062 DMA_MEM_TO_MEM, flags, false);
1065 static int rcar_dmac_map_slave_addr(struct dma_chan *chan,
1066 enum dma_transfer_direction dir)
1068 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1069 struct rcar_dmac_chan_map *map = &rchan->map;
1070 phys_addr_t dev_addr;
1072 enum dma_data_direction dev_dir;
1074 if (dir == DMA_DEV_TO_MEM) {
1075 dev_addr = rchan->src.slave_addr;
1076 dev_size = rchan->src.xfer_size;
1077 dev_dir = DMA_TO_DEVICE;
1079 dev_addr = rchan->dst.slave_addr;
1080 dev_size = rchan->dst.xfer_size;
1081 dev_dir = DMA_FROM_DEVICE;
1084 /* Reuse current map if possible. */
1085 if (dev_addr == map->slave.slave_addr &&
1086 dev_size == map->slave.xfer_size &&
1087 dev_dir == map->dir)
1090 /* Remove old mapping if present. */
1091 if (map->slave.xfer_size)
1092 dma_unmap_resource(chan->device->dev, map->addr,
1093 map->slave.xfer_size, map->dir, 0);
1094 map->slave.xfer_size = 0;
1096 /* Create new slave address map. */
1097 map->addr = dma_map_resource(chan->device->dev, dev_addr, dev_size,
1100 if (dma_mapping_error(chan->device->dev, map->addr)) {
1101 dev_err(chan->device->dev,
1102 "chan%u: failed to map %zx@%pap", rchan->index,
1103 dev_size, &dev_addr);
1107 dev_dbg(chan->device->dev, "chan%u: map %zx@%pap to %pad dir: %s\n",
1108 rchan->index, dev_size, &dev_addr, &map->addr,
1109 dev_dir == DMA_TO_DEVICE ? "DMA_TO_DEVICE" : "DMA_FROM_DEVICE");
1111 map->slave.slave_addr = dev_addr;
1112 map->slave.xfer_size = dev_size;
1118 static struct dma_async_tx_descriptor *
1119 rcar_dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1120 unsigned int sg_len, enum dma_transfer_direction dir,
1121 unsigned long flags, void *context)
1123 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1125 /* Someone calling slave DMA on a generic channel? */
1126 if (rchan->mid_rid < 0 || !sg_len) {
1127 dev_warn(chan->device->dev,
1128 "%s: bad parameter: len=%d, id=%d\n",
1129 __func__, sg_len, rchan->mid_rid);
1133 if (rcar_dmac_map_slave_addr(chan, dir))
1136 return rcar_dmac_chan_prep_sg(rchan, sgl, sg_len, rchan->map.addr,
1140 #define RCAR_DMAC_MAX_SG_LEN 32
1142 static struct dma_async_tx_descriptor *
1143 rcar_dmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
1144 size_t buf_len, size_t period_len,
1145 enum dma_transfer_direction dir, unsigned long flags)
1147 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1148 struct dma_async_tx_descriptor *desc;
1149 struct scatterlist *sgl;
1150 unsigned int sg_len;
1153 /* Someone calling slave DMA on a generic channel? */
1154 if (rchan->mid_rid < 0 || buf_len < period_len) {
1155 dev_warn(chan->device->dev,
1156 "%s: bad parameter: buf_len=%zu, period_len=%zu, id=%d\n",
1157 __func__, buf_len, period_len, rchan->mid_rid);
1161 if (rcar_dmac_map_slave_addr(chan, dir))
1164 sg_len = buf_len / period_len;
1165 if (sg_len > RCAR_DMAC_MAX_SG_LEN) {
1166 dev_err(chan->device->dev,
1167 "chan%u: sg length %d exceds limit %d",
1168 rchan->index, sg_len, RCAR_DMAC_MAX_SG_LEN);
1173 * Allocate the sg list dynamically as it would consume too much stack
1176 sgl = kcalloc(sg_len, sizeof(*sgl), GFP_NOWAIT);
1180 sg_init_table(sgl, sg_len);
1182 for (i = 0; i < sg_len; ++i) {
1183 dma_addr_t src = buf_addr + (period_len * i);
1185 sg_set_page(&sgl[i], pfn_to_page(PFN_DOWN(src)), period_len,
1186 offset_in_page(src));
1187 sg_dma_address(&sgl[i]) = src;
1188 sg_dma_len(&sgl[i]) = period_len;
1191 desc = rcar_dmac_chan_prep_sg(rchan, sgl, sg_len, rchan->map.addr,
1198 static int rcar_dmac_device_config(struct dma_chan *chan,
1199 struct dma_slave_config *cfg)
1201 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1204 * We could lock this, but you shouldn't be configuring the
1205 * channel, while using it...
1207 rchan->src.slave_addr = cfg->src_addr;
1208 rchan->dst.slave_addr = cfg->dst_addr;
1209 rchan->src.xfer_size = cfg->src_addr_width;
1210 rchan->dst.xfer_size = cfg->dst_addr_width;
1215 static int rcar_dmac_chan_terminate_all(struct dma_chan *chan)
1217 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1218 unsigned long flags;
1220 spin_lock_irqsave(&rchan->lock, flags);
1221 rcar_dmac_chan_halt(rchan);
1222 spin_unlock_irqrestore(&rchan->lock, flags);
1225 * FIXME: No new interrupt can occur now, but the IRQ thread might still
1229 rcar_dmac_chan_reinit(rchan);
1234 static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan,
1235 dma_cookie_t cookie)
1237 struct rcar_dmac_desc *desc = chan->desc.running;
1238 struct rcar_dmac_xfer_chunk *running = NULL;
1239 struct rcar_dmac_xfer_chunk *chunk;
1240 enum dma_status status;
1241 unsigned int residue = 0;
1242 unsigned int dptr = 0;
1248 * If the cookie corresponds to a descriptor that has been completed
1249 * there is no residue. The same check has already been performed by the
1250 * caller but without holding the channel lock, so the descriptor could
1253 status = dma_cookie_status(&chan->chan, cookie, NULL);
1254 if (status == DMA_COMPLETE)
1258 * If the cookie doesn't correspond to the currently running transfer
1259 * then the descriptor hasn't been processed yet, and the residue is
1260 * equal to the full descriptor size.
1262 if (cookie != desc->async_tx.cookie) {
1263 list_for_each_entry(desc, &chan->desc.pending, node) {
1264 if (cookie == desc->async_tx.cookie)
1267 list_for_each_entry(desc, &chan->desc.active, node) {
1268 if (cookie == desc->async_tx.cookie)
1273 * No descriptor found for the cookie, there's thus no residue.
1274 * This shouldn't happen if the calling driver passes a correct
1277 WARN(1, "No descriptor for cookie!");
1282 * In descriptor mode the descriptor running pointer is not maintained
1283 * by the interrupt handler, find the running descriptor from the
1284 * descriptor pointer field in the CHCRB register. In non-descriptor
1285 * mode just use the running descriptor pointer.
1287 if (desc->hwdescs.use) {
1288 dptr = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
1289 RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT;
1290 WARN_ON(dptr >= desc->nchunks);
1292 running = desc->running;
1295 /* Compute the size of all chunks still to be transferred. */
1296 list_for_each_entry_reverse(chunk, &desc->chunks, node) {
1297 if (chunk == running || ++dptr == desc->nchunks)
1300 residue += chunk->size;
1303 /* Add the residue for the current chunk. */
1304 residue += rcar_dmac_chan_read(chan, RCAR_DMATCR) << desc->xfer_shift;
1309 static enum dma_status rcar_dmac_tx_status(struct dma_chan *chan,
1310 dma_cookie_t cookie,
1311 struct dma_tx_state *txstate)
1313 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1314 enum dma_status status;
1315 unsigned long flags;
1316 unsigned int residue;
1318 status = dma_cookie_status(chan, cookie, txstate);
1319 if (status == DMA_COMPLETE || !txstate)
1322 spin_lock_irqsave(&rchan->lock, flags);
1323 residue = rcar_dmac_chan_get_residue(rchan, cookie);
1324 spin_unlock_irqrestore(&rchan->lock, flags);
1326 /* if there's no residue, the cookie is complete */
1328 return DMA_COMPLETE;
1330 dma_set_residue(txstate, residue);
1335 static void rcar_dmac_issue_pending(struct dma_chan *chan)
1337 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1338 unsigned long flags;
1340 spin_lock_irqsave(&rchan->lock, flags);
1342 if (list_empty(&rchan->desc.pending))
1345 /* Append the pending list to the active list. */
1346 list_splice_tail_init(&rchan->desc.pending, &rchan->desc.active);
1349 * If no transfer is running pick the first descriptor from the active
1350 * list and start the transfer.
1352 if (!rchan->desc.running) {
1353 struct rcar_dmac_desc *desc;
1355 desc = list_first_entry(&rchan->desc.active,
1356 struct rcar_dmac_desc, node);
1357 rchan->desc.running = desc;
1359 rcar_dmac_chan_start_xfer(rchan);
1363 spin_unlock_irqrestore(&rchan->lock, flags);
1366 /* -----------------------------------------------------------------------------
1370 static irqreturn_t rcar_dmac_isr_desc_stage_end(struct rcar_dmac_chan *chan)
1372 struct rcar_dmac_desc *desc = chan->desc.running;
1375 if (WARN_ON(!desc || !desc->cyclic)) {
1377 * This should never happen, there should always be a running
1378 * cyclic descriptor when a descriptor stage end interrupt is
1379 * triggered. Warn and return.
1384 /* Program the interrupt pointer to the next stage. */
1385 stage = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
1386 RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT;
1387 rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(stage));
1389 return IRQ_WAKE_THREAD;
1392 static irqreturn_t rcar_dmac_isr_transfer_end(struct rcar_dmac_chan *chan)
1394 struct rcar_dmac_desc *desc = chan->desc.running;
1395 irqreturn_t ret = IRQ_WAKE_THREAD;
1397 if (WARN_ON_ONCE(!desc)) {
1399 * This should never happen, there should always be a running
1400 * descriptor when a transfer end interrupt is triggered. Warn
1407 * The transfer end interrupt isn't generated for each chunk when using
1408 * descriptor mode. Only update the running chunk pointer in
1409 * non-descriptor mode.
1411 if (!desc->hwdescs.use) {
1413 * If we haven't completed the last transfer chunk simply move
1414 * to the next one. Only wake the IRQ thread if the transfer is
1417 if (!list_is_last(&desc->running->node, &desc->chunks)) {
1418 desc->running = list_next_entry(desc->running, node);
1425 * We've completed the last transfer chunk. If the transfer is
1426 * cyclic, move back to the first one.
1430 list_first_entry(&desc->chunks,
1431 struct rcar_dmac_xfer_chunk,
1437 /* The descriptor is complete, move it to the done list. */
1438 list_move_tail(&desc->node, &chan->desc.done);
1440 /* Queue the next descriptor, if any. */
1441 if (!list_empty(&chan->desc.active))
1442 chan->desc.running = list_first_entry(&chan->desc.active,
1443 struct rcar_dmac_desc,
1446 chan->desc.running = NULL;
1449 if (chan->desc.running)
1450 rcar_dmac_chan_start_xfer(chan);
1455 static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev)
1457 u32 mask = RCAR_DMACHCR_DSE | RCAR_DMACHCR_TE;
1458 struct rcar_dmac_chan *chan = dev;
1459 irqreturn_t ret = IRQ_NONE;
1462 spin_lock(&chan->lock);
1464 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
1465 if (chcr & RCAR_DMACHCR_TE)
1466 mask |= RCAR_DMACHCR_DE;
1467 rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr & ~mask);
1469 if (chcr & RCAR_DMACHCR_DSE)
1470 ret |= rcar_dmac_isr_desc_stage_end(chan);
1472 if (chcr & RCAR_DMACHCR_TE)
1473 ret |= rcar_dmac_isr_transfer_end(chan);
1475 spin_unlock(&chan->lock);
1480 static irqreturn_t rcar_dmac_isr_channel_thread(int irq, void *dev)
1482 struct rcar_dmac_chan *chan = dev;
1483 struct rcar_dmac_desc *desc;
1484 struct dmaengine_desc_callback cb;
1486 spin_lock_irq(&chan->lock);
1488 /* For cyclic transfers notify the user after every chunk. */
1489 if (chan->desc.running && chan->desc.running->cyclic) {
1490 desc = chan->desc.running;
1491 dmaengine_desc_get_callback(&desc->async_tx, &cb);
1493 if (dmaengine_desc_callback_valid(&cb)) {
1494 spin_unlock_irq(&chan->lock);
1495 dmaengine_desc_callback_invoke(&cb, NULL);
1496 spin_lock_irq(&chan->lock);
1501 * Call the callback function for all descriptors on the done list and
1502 * move them to the ack wait list.
1504 while (!list_empty(&chan->desc.done)) {
1505 desc = list_first_entry(&chan->desc.done, struct rcar_dmac_desc,
1507 dma_cookie_complete(&desc->async_tx);
1508 list_del(&desc->node);
1510 dmaengine_desc_get_callback(&desc->async_tx, &cb);
1511 if (dmaengine_desc_callback_valid(&cb)) {
1512 spin_unlock_irq(&chan->lock);
1514 * We own the only reference to this descriptor, we can
1515 * safely dereference it without holding the channel
1518 dmaengine_desc_callback_invoke(&cb, NULL);
1519 spin_lock_irq(&chan->lock);
1522 list_add_tail(&desc->node, &chan->desc.wait);
1525 spin_unlock_irq(&chan->lock);
1527 /* Recycle all acked descriptors. */
1528 rcar_dmac_desc_recycle_acked(chan);
1533 static irqreturn_t rcar_dmac_isr_error(int irq, void *data)
1535 struct rcar_dmac *dmac = data;
1537 if (!(rcar_dmac_read(dmac, RCAR_DMAOR) & RCAR_DMAOR_AE))
1541 * An unrecoverable error occurred on an unknown channel. Halt the DMAC,
1542 * abort transfers on all channels, and reinitialize the DMAC.
1544 rcar_dmac_stop(dmac);
1545 rcar_dmac_abort(dmac);
1546 rcar_dmac_init(dmac);
1551 /* -----------------------------------------------------------------------------
1552 * OF xlate and channel filter
1555 static bool rcar_dmac_chan_filter(struct dma_chan *chan, void *arg)
1557 struct rcar_dmac *dmac = to_rcar_dmac(chan->device);
1558 struct of_phandle_args *dma_spec = arg;
1561 * FIXME: Using a filter on OF platforms is a nonsense. The OF xlate
1562 * function knows from which device it wants to allocate a channel from,
1563 * and would be perfectly capable of selecting the channel it wants.
1564 * Forcing it to call dma_request_channel() and iterate through all
1565 * channels from all controllers is just pointless.
1567 if (chan->device->device_config != rcar_dmac_device_config ||
1568 dma_spec->np != chan->device->dev->of_node)
1571 return !test_and_set_bit(dma_spec->args[0], dmac->modules);
1574 static struct dma_chan *rcar_dmac_of_xlate(struct of_phandle_args *dma_spec,
1575 struct of_dma *ofdma)
1577 struct rcar_dmac_chan *rchan;
1578 struct dma_chan *chan;
1579 dma_cap_mask_t mask;
1581 if (dma_spec->args_count != 1)
1584 /* Only slave DMA channels can be allocated via DT */
1586 dma_cap_set(DMA_SLAVE, mask);
1588 chan = dma_request_channel(mask, rcar_dmac_chan_filter, dma_spec);
1592 rchan = to_rcar_dmac_chan(chan);
1593 rchan->mid_rid = dma_spec->args[0];
1598 /* -----------------------------------------------------------------------------
1602 #ifdef CONFIG_PM_SLEEP
1603 static int rcar_dmac_sleep_suspend(struct device *dev)
1606 * TODO: Wait for the current transfer to complete and stop the device.
1611 static int rcar_dmac_sleep_resume(struct device *dev)
1613 /* TODO: Resume transfers, if any. */
1619 static int rcar_dmac_runtime_suspend(struct device *dev)
1624 static int rcar_dmac_runtime_resume(struct device *dev)
1626 struct rcar_dmac *dmac = dev_get_drvdata(dev);
1628 return rcar_dmac_init(dmac);
1632 static const struct dev_pm_ops rcar_dmac_pm = {
1633 SET_SYSTEM_SLEEP_PM_OPS(rcar_dmac_sleep_suspend, rcar_dmac_sleep_resume)
1634 SET_RUNTIME_PM_OPS(rcar_dmac_runtime_suspend, rcar_dmac_runtime_resume,
1638 /* -----------------------------------------------------------------------------
1642 static int rcar_dmac_chan_probe(struct rcar_dmac *dmac,
1643 struct rcar_dmac_chan *rchan,
1646 struct platform_device *pdev = to_platform_device(dmac->dev);
1647 struct dma_chan *chan = &rchan->chan;
1648 char pdev_irqname[5];
1653 rchan->index = index;
1654 rchan->iomem = dmac->iomem + RCAR_DMAC_CHAN_OFFSET(index);
1655 rchan->mid_rid = -EINVAL;
1657 spin_lock_init(&rchan->lock);
1659 INIT_LIST_HEAD(&rchan->desc.free);
1660 INIT_LIST_HEAD(&rchan->desc.pending);
1661 INIT_LIST_HEAD(&rchan->desc.active);
1662 INIT_LIST_HEAD(&rchan->desc.done);
1663 INIT_LIST_HEAD(&rchan->desc.wait);
1665 /* Request the channel interrupt. */
1666 sprintf(pdev_irqname, "ch%u", index);
1667 irq = platform_get_irq_byname(pdev, pdev_irqname);
1669 dev_err(dmac->dev, "no IRQ specified for channel %u\n", index);
1673 irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:%u",
1674 dev_name(dmac->dev), index);
1678 ret = devm_request_threaded_irq(dmac->dev, irq, rcar_dmac_isr_channel,
1679 rcar_dmac_isr_channel_thread, 0,
1682 dev_err(dmac->dev, "failed to request IRQ %u (%d)\n", irq, ret);
1687 * Initialize the DMA engine channel and add it to the DMA engine
1690 chan->device = &dmac->engine;
1691 dma_cookie_init(chan);
1693 list_add_tail(&chan->device_node, &dmac->engine.channels);
1698 static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac)
1700 struct device_node *np = dev->of_node;
1703 ret = of_property_read_u32(np, "dma-channels", &dmac->n_channels);
1705 dev_err(dev, "unable to read dma-channels property\n");
1709 if (dmac->n_channels <= 0 || dmac->n_channels >= 100) {
1710 dev_err(dev, "invalid number of channels %u\n",
1718 static int rcar_dmac_probe(struct platform_device *pdev)
1720 const enum dma_slave_buswidth widths = DMA_SLAVE_BUSWIDTH_1_BYTE |
1721 DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES |
1722 DMA_SLAVE_BUSWIDTH_8_BYTES | DMA_SLAVE_BUSWIDTH_16_BYTES |
1723 DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES;
1724 unsigned int channels_offset = 0;
1725 struct dma_device *engine;
1726 struct rcar_dmac *dmac;
1727 struct resource *mem;
1733 dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL);
1737 dmac->dev = &pdev->dev;
1738 platform_set_drvdata(pdev, dmac);
1739 dma_set_mask_and_coherent(dmac->dev, DMA_BIT_MASK(40));
1741 ret = rcar_dmac_parse_of(&pdev->dev, dmac);
1746 * A still unconfirmed hardware bug prevents the IPMMU microTLB 0 to be
1747 * flushed correctly, resulting in memory corruption. DMAC 0 channel 0
1748 * is connected to microTLB 0 on currently supported platforms, so we
1749 * can't use it with the IPMMU. As the IOMMU API operates at the device
1750 * level we can't disable it selectively, so ignore channel 0 for now if
1751 * the device is part of an IOMMU group.
1753 if (pdev->dev.iommu_group) {
1755 channels_offset = 1;
1758 dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels,
1759 sizeof(*dmac->channels), GFP_KERNEL);
1760 if (!dmac->channels)
1763 /* Request resources. */
1764 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1765 dmac->iomem = devm_ioremap_resource(&pdev->dev, mem);
1766 if (IS_ERR(dmac->iomem))
1767 return PTR_ERR(dmac->iomem);
1769 irq = platform_get_irq_byname(pdev, "error");
1771 dev_err(&pdev->dev, "no error IRQ specified\n");
1775 irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:error",
1776 dev_name(dmac->dev));
1780 ret = devm_request_irq(&pdev->dev, irq, rcar_dmac_isr_error, 0,
1783 dev_err(&pdev->dev, "failed to request IRQ %u (%d)\n",
1788 /* Enable runtime PM and initialize the device. */
1789 pm_runtime_enable(&pdev->dev);
1790 ret = pm_runtime_get_sync(&pdev->dev);
1792 dev_err(&pdev->dev, "runtime PM get sync failed (%d)\n", ret);
1796 ret = rcar_dmac_init(dmac);
1797 pm_runtime_put(&pdev->dev);
1800 dev_err(&pdev->dev, "failed to reset device\n");
1804 /* Initialize the channels. */
1805 INIT_LIST_HEAD(&dmac->engine.channels);
1807 for (i = 0; i < dmac->n_channels; ++i) {
1808 ret = rcar_dmac_chan_probe(dmac, &dmac->channels[i],
1809 i + channels_offset);
1814 /* Register the DMAC as a DMA provider for DT. */
1815 ret = of_dma_controller_register(pdev->dev.of_node, rcar_dmac_of_xlate,
1821 * Register the DMA engine device.
1823 * Default transfer size of 32 bytes requires 32-byte alignment.
1825 engine = &dmac->engine;
1826 dma_cap_set(DMA_MEMCPY, engine->cap_mask);
1827 dma_cap_set(DMA_SLAVE, engine->cap_mask);
1829 engine->dev = &pdev->dev;
1830 engine->copy_align = ilog2(RCAR_DMAC_MEMCPY_XFER_SIZE);
1832 engine->src_addr_widths = widths;
1833 engine->dst_addr_widths = widths;
1834 engine->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1835 engine->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1837 engine->device_alloc_chan_resources = rcar_dmac_alloc_chan_resources;
1838 engine->device_free_chan_resources = rcar_dmac_free_chan_resources;
1839 engine->device_prep_dma_memcpy = rcar_dmac_prep_dma_memcpy;
1840 engine->device_prep_slave_sg = rcar_dmac_prep_slave_sg;
1841 engine->device_prep_dma_cyclic = rcar_dmac_prep_dma_cyclic;
1842 engine->device_config = rcar_dmac_device_config;
1843 engine->device_terminate_all = rcar_dmac_chan_terminate_all;
1844 engine->device_tx_status = rcar_dmac_tx_status;
1845 engine->device_issue_pending = rcar_dmac_issue_pending;
1847 ret = dma_async_device_register(engine);
1854 of_dma_controller_free(pdev->dev.of_node);
1855 pm_runtime_disable(&pdev->dev);
1859 static int rcar_dmac_remove(struct platform_device *pdev)
1861 struct rcar_dmac *dmac = platform_get_drvdata(pdev);
1863 of_dma_controller_free(pdev->dev.of_node);
1864 dma_async_device_unregister(&dmac->engine);
1866 pm_runtime_disable(&pdev->dev);
1871 static void rcar_dmac_shutdown(struct platform_device *pdev)
1873 struct rcar_dmac *dmac = platform_get_drvdata(pdev);
1875 rcar_dmac_stop(dmac);
1878 static const struct of_device_id rcar_dmac_of_ids[] = {
1879 { .compatible = "renesas,rcar-dmac", },
1882 MODULE_DEVICE_TABLE(of, rcar_dmac_of_ids);
1884 static struct platform_driver rcar_dmac_driver = {
1886 .pm = &rcar_dmac_pm,
1887 .name = "rcar-dmac",
1888 .of_match_table = rcar_dmac_of_ids,
1890 .probe = rcar_dmac_probe,
1891 .remove = rcar_dmac_remove,
1892 .shutdown = rcar_dmac_shutdown,
1895 module_platform_driver(rcar_dmac_driver);
1897 MODULE_DESCRIPTION("R-Car Gen2 DMA Controller Driver");
1898 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1899 MODULE_LICENSE("GPL v2");