drivers/dma/shdma.c

   1 /*
   2  * Renesas SuperH DMA Engine support
   3  *
   4  * base is drivers/dma/flsdma.c
   5  *
   6  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   7  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
   8  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
   9  *
  10  * This is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * - DMA of SuperH does not have Hardware DMA chain mode.
  16  * - MAX DMA size is 16MB.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/slab.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/dmaengine.h>
  25 #include <linux/delay.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/sh_dma.h>
  29 #include <linux/notifier.h>
  30 #include <linux/kdebug.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/rculist.h>
  33
  34 #include "dmaengine.h"
  35 #include "shdma.h"
  36
  37 /* DMA descriptor control */
  38 enum sh_dmae_desc_status {
  39         DESC_IDLE,
  40         DESC_PREPARED,
  41         DESC_SUBMITTED,
  42         DESC_COMPLETED, /* completed, have to call callback */
  43         DESC_WAITING,   /* callback called, waiting for ack / re-submit */
  44 };
  45
  46 #define NR_DESCS_PER_CHANNEL 32
  47 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
  48 #define LOG2_DEFAULT_XFER_SIZE  2
  49
  50 /*
  51  * Used for write-side mutual exclusion for the global device list,
  52  * read-side synchronization by way of RCU, and per-controller data.
  53  */
  54 static DEFINE_SPINLOCK(sh_dmae_lock);
  55 static LIST_HEAD(sh_dmae_devices);
  56
  57 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
  58 static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SH_DMA_SLAVE_NUMBER)];
  59
  60 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
  61 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan);
  62
  63 static void chclr_write(struct sh_dmae_chan *sh_dc, u32 data)
  64 {
  65         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
  66
  67         __raw_writel(data, shdev->chan_reg +
  68                      shdev->pdata->channel[sh_dc->id].chclr_offset);
  69 }
  70
  71 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
  72 {
  73         __raw_writel(data, sh_dc->base + reg / sizeof(u32));
  74 }
  75
  76 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
  77 {
  78         return __raw_readl(sh_dc->base + reg / sizeof(u32));
  79 }
  80
  81 static u16 dmaor_read(struct sh_dmae_device *shdev)
  82 {
  83         u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
  84
  85         if (shdev->pdata->dmaor_is_32bit)
  86                 return __raw_readl(addr);
  87         else
  88                 return __raw_readw(addr);
  89 }
  90
  91 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
  92 {
  93         u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
  94
  95         if (shdev->pdata->dmaor_is_32bit)
  96                 __raw_writel(data, addr);
  97         else
  98                 __raw_writew(data, addr);
  99 }
 100
 101 static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
 102 {
 103         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
 104
 105         __raw_writel(data, sh_dc->base + shdev->chcr_offset / sizeof(u32));
 106 }
 107
 108 static u32 chcr_read(struct sh_dmae_chan *sh_dc)
 109 {
 110         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
 111
 112         return __raw_readl(sh_dc->base + shdev->chcr_offset / sizeof(u32));
 113 }
 114
 115 /*
 116  * Reset DMA controller
 117  *
 118  * SH7780 has two DMAOR register
 119  */
 120 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
 121 {
 122         unsigned short dmaor;
 123         unsigned long flags;
 124
 125         spin_lock_irqsave(&sh_dmae_lock, flags);
 126
 127         dmaor = dmaor_read(shdev);
 128         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
 129
 130         spin_unlock_irqrestore(&sh_dmae_lock, flags);
 131 }
 132
 133 static int sh_dmae_rst(struct sh_dmae_device *shdev)
 134 {
 135         unsigned short dmaor;
 136         unsigned long flags;
 137
 138         spin_lock_irqsave(&sh_dmae_lock, flags);
 139
 140         dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
 141
 142         if (shdev->pdata->chclr_present) {
 143                 int i;
 144                 for (i = 0; i < shdev->pdata->channel_num; i++) {
 145                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
 146                         if (sh_chan)
 147                                 chclr_write(sh_chan, 0);
 148                 }
 149         }
 150
 151         dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
 152
 153         dmaor = dmaor_read(shdev);
 154
 155         spin_unlock_irqrestore(&sh_dmae_lock, flags);
 156
 157         if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
 158                 dev_warn(shdev->common.dev, "Can't initialize DMAOR.\n");
 159                 return -EIO;
 160         }
 161         if (shdev->pdata->dmaor_init & ~dmaor)
 162                 dev_warn(shdev->common.dev,
 163                          "DMAOR=0x%x hasn't latched the initial value 0x%x.\n",
 164                          dmaor, shdev->pdata->dmaor_init);
 165         return 0;
 166 }
 167
 168 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
 169 {
 170         u32 chcr = chcr_read(sh_chan);
 171
 172         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
 173                 return true; /* working */
 174
 175         return false; /* waiting */
 176 }
 177
 178 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
 179 {
 180         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 181         struct sh_dmae_pdata *pdata = shdev->pdata;
 182         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
 183                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
 184
 185         if (cnt >= pdata->ts_shift_num)
 186                 cnt = 0;
 187
 188         return pdata->ts_shift[cnt];
 189 }
 190
 191 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
 192 {
 193         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 194         struct sh_dmae_pdata *pdata = shdev->pdata;
 195         int i;
 196
 197         for (i = 0; i < pdata->ts_shift_num; i++)
 198                 if (pdata->ts_shift[i] == l2size)
 199                         break;
 200
 201         if (i == pdata->ts_shift_num)
 202                 i = 0;
 203
 204         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
 205                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
 206 }
 207
 208 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
 209 {
 210         sh_dmae_writel(sh_chan, hw->sar, SAR);
 211         sh_dmae_writel(sh_chan, hw->dar, DAR);
 212         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
 213 }
 214
 215 static void dmae_start(struct sh_dmae_chan *sh_chan)
 216 {
 217         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 218         u32 chcr = chcr_read(sh_chan);
 219
 220         if (shdev->pdata->needs_tend_set)
 221                 sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
 222
 223         chcr |= CHCR_DE | shdev->chcr_ie_bit;
 224         chcr_write(sh_chan, chcr & ~CHCR_TE);
 225 }
 226
 227 static void dmae_halt(struct sh_dmae_chan *sh_chan)
 228 {
 229         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 230         u32 chcr = chcr_read(sh_chan);
 231
 232         chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
 233         chcr_write(sh_chan, chcr);
 234 }
 235
 236 static void dmae_init(struct sh_dmae_chan *sh_chan)
 237 {
 238         /*
 239          * Default configuration for dual address memory-memory transfer.
 240          * 0x400 represents auto-request.
 241          */
 242         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
 243                                                    LOG2_DEFAULT_XFER_SIZE);
 244         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
 245         chcr_write(sh_chan, chcr);
 246 }
 247
 248 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
 249 {
 250         /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
 251         if (dmae_is_busy(sh_chan))
 252                 return -EBUSY;
 253
 254         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
 255         chcr_write(sh_chan, val);
 256
 257         return 0;
 258 }
 259
 260 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
 261 {
 262         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 263         struct sh_dmae_pdata *pdata = shdev->pdata;
 264         const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
 265         u16 __iomem *addr = shdev->dmars;
 266         unsigned int shift = chan_pdata->dmars_bit;
 267
 268         if (dmae_is_busy(sh_chan))
 269                 return -EBUSY;
 270
 271         if (pdata->no_dmars)
 272                 return 0;
 273
 274         /* in the case of a missing DMARS resource use first memory window */
 275         if (!addr)
 276                 addr = (u16 __iomem *)shdev->chan_reg;
 277         addr += chan_pdata->dmars / sizeof(u16);
 278
 279         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
 280                      addr);
 281
 282         return 0;
 283 }
 284
 285 static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
 286 {
 287         struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
 288         struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
 289         struct sh_dmae_slave *param = tx->chan->private;
 290         dma_async_tx_callback callback = tx->callback;
 291         dma_cookie_t cookie;
 292         bool power_up;
 293
 294         spin_lock_irq(&sh_chan->desc_lock);
 295
 296         if (list_empty(&sh_chan->ld_queue))
 297                 power_up = true;
 298         else
 299                 power_up = false;
 300
 301         cookie = dma_cookie_assign(tx);
 302
 303         /* Mark all chunks of this descriptor as submitted, move to the queue */
 304         list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
 305                 /*
 306                  * All chunks are on the global ld_free, so, we have to find
 307                  * the end of the chain ourselves
 308                  */
 309                 if (chunk != desc && (chunk->mark == DESC_IDLE ||
 310                                       chunk->async_tx.cookie > 0 ||
 311                                       chunk->async_tx.cookie == -EBUSY ||
 312                                       &chunk->node == &sh_chan->ld_free))
 313                         break;
 314                 chunk->mark = DESC_SUBMITTED;
 315                 /* Callback goes to the last chunk */
 316                 chunk->async_tx.callback = NULL;
 317                 chunk->cookie = cookie;
 318                 list_move_tail(&chunk->node, &sh_chan->ld_queue);
 319                 last = chunk;
 320         }
 321
 322         last->async_tx.callback = callback;
 323         last->async_tx.callback_param = tx->callback_param;
 324
 325         dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
 326                 tx->cookie, &last->async_tx, sh_chan->id,
 327                 desc->hw.sar, desc->hw.tcr, desc->hw.dar);
 328
 329         if (power_up) {
 330                 sh_chan->pm_state = DMAE_PM_BUSY;
 331
 332                 pm_runtime_get(sh_chan->dev);
 333
 334                 spin_unlock_irq(&sh_chan->desc_lock);
 335
 336                 pm_runtime_barrier(sh_chan->dev);
 337
 338                 spin_lock_irq(&sh_chan->desc_lock);
 339
 340                 /* Have we been reset, while waiting? */
 341                 if (sh_chan->pm_state != DMAE_PM_ESTABLISHED) {
 342                         dev_dbg(sh_chan->dev, "Bring up channel %d\n",
 343                                 sh_chan->id);
 344                         if (param) {
 345                                 const struct sh_dmae_slave_config *cfg =
 346                                         param->config;
 347
 348                                 dmae_set_dmars(sh_chan, cfg->mid_rid);
 349                                 dmae_set_chcr(sh_chan, cfg->chcr);
 350                         } else {
 351                                 dmae_init(sh_chan);
 352                         }
 353
 354                         if (sh_chan->pm_state == DMAE_PM_PENDING)
 355                                 sh_chan_xfer_ld_queue(sh_chan);
 356                         sh_chan->pm_state = DMAE_PM_ESTABLISHED;
 357                 }
 358         } else {
 359                 sh_chan->pm_state = DMAE_PM_PENDING;
 360         }
 361
 362         spin_unlock_irq(&sh_chan->desc_lock);
 363
 364         return cookie;
 365 }
 366
 367 /* Called with desc_lock held */
 368 static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
 369 {
 370         struct sh_desc *desc;
 371
 372         list_for_each_entry(desc, &sh_chan->ld_free, node)
 373                 if (desc->mark != DESC_PREPARED) {
 374                         BUG_ON(desc->mark != DESC_IDLE);
 375                         list_del(&desc->node);
 376                         return desc;
 377                 }
 378
 379         return NULL;
 380 }
 381
 382 static const struct sh_dmae_slave_config *sh_dmae_find_slave(
 383         struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param)
 384 {
 385         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 386         struct sh_dmae_pdata *pdata = shdev->pdata;
 387         int i;
 388
 389         if (param->slave_id >= SH_DMA_SLAVE_NUMBER)
 390                 return NULL;
 391
 392         for (i = 0; i < pdata->slave_num; i++)
 393                 if (pdata->slave[i].slave_id == param->slave_id)
 394                         return pdata->slave + i;
 395
 396         return NULL;
 397 }
 398
 399 static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
 400 {
 401         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 402         struct sh_desc *desc;
 403         struct sh_dmae_slave *param = chan->private;
 404         int ret;
 405
 406         /*
 407          * This relies on the guarantee from dmaengine that alloc_chan_resources
 408          * never runs concurrently with itself or free_chan_resources.
 409          */
 410         if (param) {
 411                 const struct sh_dmae_slave_config *cfg;
 412
 413                 cfg = sh_dmae_find_slave(sh_chan, param);
 414                 if (!cfg) {
 415                         ret = -EINVAL;
 416                         goto efindslave;
 417                 }
 418
 419                 if (test_and_set_bit(param->slave_id, sh_dmae_slave_used)) {
 420                         ret = -EBUSY;
 421                         goto etestused;
 422                 }
 423
 424                 param->config = cfg;
 425         }
 426
 427         while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
 428                 desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
 429                 if (!desc)
 430                         break;
 431                 dma_async_tx_descriptor_init(&desc->async_tx,
 432                                         &sh_chan->common);
 433                 desc->async_tx.tx_submit = sh_dmae_tx_submit;
 434                 desc->mark = DESC_IDLE;
 435
 436                 list_add(&desc->node, &sh_chan->ld_free);
 437                 sh_chan->descs_allocated++;
 438         }
 439
 440         if (!sh_chan->descs_allocated) {
 441                 ret = -ENOMEM;
 442                 goto edescalloc;
 443         }
 444
 445         return sh_chan->descs_allocated;
 446
 447 edescalloc:
 448         if (param)
 449                 clear_bit(param->slave_id, sh_dmae_slave_used);
 450 etestused:
 451 efindslave:
 452         chan->private = NULL;
 453         return ret;
 454 }
 455
 456 /*
 457  * sh_dma_free_chan_resources - Free all resources of the channel.
 458  */
 459 static void sh_dmae_free_chan_resources(struct dma_chan *chan)
 460 {
 461         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 462         struct sh_desc *desc, *_desc;
 463         LIST_HEAD(list);
 464
 465         /* Protect against ISR */
 466         spin_lock_irq(&sh_chan->desc_lock);
 467         dmae_halt(sh_chan);
 468         spin_unlock_irq(&sh_chan->desc_lock);
 469
 470         /* Now no new interrupts will occur */
 471
 472         /* Prepared and not submitted descriptors can still be on the queue */
 473         if (!list_empty(&sh_chan->ld_queue))
 474                 sh_dmae_chan_ld_cleanup(sh_chan, true);
 475
 476         if (chan->private) {
 477                 /* The caller is holding dma_list_mutex */
 478                 struct sh_dmae_slave *param = chan->private;
 479                 clear_bit(param->slave_id, sh_dmae_slave_used);
 480                 chan->private = NULL;
 481         }
 482
 483         spin_lock_irq(&sh_chan->desc_lock);
 484
 485         list_splice_init(&sh_chan->ld_free, &list);
 486         sh_chan->descs_allocated = 0;
 487
 488         spin_unlock_irq(&sh_chan->desc_lock);
 489
 490         list_for_each_entry_safe(desc, _desc, &list, node)
 491                 kfree(desc);
 492 }
 493
 494 /**
 495  * sh_dmae_add_desc - get, set up and return one transfer descriptor
 496  * @sh_chan:    DMA channel
 497  * @flags:      DMA transfer flags
 498  * @dest:       destination DMA address, incremented when direction equals
 499  *              DMA_DEV_TO_MEM
 500  * @src:        source DMA address, incremented when direction equals
 501  *              DMA_MEM_TO_DEV
 502  * @len:        DMA transfer length
 503  * @first:      if NULL, set to the current descriptor and cookie set to -EBUSY
 504  * @direction:  needed for slave DMA to decide which address to keep constant,
 505  *              equals DMA_MEM_TO_MEM for MEMCPY
 506  * Returns 0 or an error
 507  * Locks: called with desc_lock held
 508  */
 509 static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
 510         unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
 511         struct sh_desc **first, enum dma_transfer_direction direction)
 512 {
 513         struct sh_desc *new;
 514         size_t copy_size;
 515
 516         if (!*len)
 517                 return NULL;
 518
 519         /* Allocate the link descriptor from the free list */
 520         new = sh_dmae_get_desc(sh_chan);
 521         if (!new) {
 522                 dev_err(sh_chan->dev, "No free link descriptor available\n");
 523                 return NULL;
 524         }
 525
 526         copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
 527
 528         new->hw.sar = *src;
 529         new->hw.dar = *dest;
 530         new->hw.tcr = copy_size;
 531
 532         if (!*first) {
 533                 /* First desc */
 534                 new->async_tx.cookie = -EBUSY;
 535                 *first = new;
 536         } else {
 537                 /* Other desc - invisible to the user */
 538                 new->async_tx.cookie = -EINVAL;
 539         }
 540
 541         dev_dbg(sh_chan->dev,
 542                 "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n",
 543                 copy_size, *len, *src, *dest, &new->async_tx,
 544                 new->async_tx.cookie, sh_chan->xmit_shift);
 545
 546         new->mark = DESC_PREPARED;
 547         new->async_tx.flags = flags;
 548         new->direction = direction;
 549
 550         *len -= copy_size;
 551         if (direction == DMA_MEM_TO_MEM || direction == DMA_MEM_TO_DEV)
 552                 *src += copy_size;
 553         if (direction == DMA_MEM_TO_MEM || direction == DMA_DEV_TO_MEM)
 554                 *dest += copy_size;
 555
 556         return new;
 557 }
 558
 559 /*
 560  * sh_dmae_prep_sg - prepare transfer descriptors from an SG list
 561  *
 562  * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
 563  * converted to scatter-gather to guarantee consistent locking and a correct
 564  * list manipulation. For slave DMA direction carries the usual meaning, and,
 565  * logically, the SG list is RAM and the addr variable contains slave address,
 566  * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM
 567  * and the SG list contains only one element and points at the source buffer.
 568  */
 569 static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
 570         struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
 571         enum dma_transfer_direction direction, unsigned long flags)
 572 {
 573         struct scatterlist *sg;
 574         struct sh_desc *first = NULL, *new = NULL /* compiler... */;
 575         LIST_HEAD(tx_list);
 576         int chunks = 0;
 577         unsigned long irq_flags;
 578         int i;
 579
 580         if (!sg_len)
 581                 return NULL;
 582
 583         for_each_sg(sgl, sg, sg_len, i)
 584                 chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
 585                         (SH_DMA_TCR_MAX + 1);
 586
 587         /* Have to lock the whole loop to protect against concurrent release */
 588         spin_lock_irqsave(&sh_chan->desc_lock, irq_flags);
 589
 590         /*
 591          * Chaining:
 592          * first descriptor is what user is dealing with in all API calls, its
 593          *      cookie is at first set to -EBUSY, at tx-submit to a positive
 594          *      number
 595          * if more than one chunk is needed further chunks have cookie = -EINVAL
 596          * the last chunk, if not equal to the first, has cookie = -ENOSPC
 597          * all chunks are linked onto the tx_list head with their .node heads
 598          *      only during this function, then they are immediately spliced
 599          *      back onto the free list in form of a chain
 600          */
 601         for_each_sg(sgl, sg, sg_len, i) {
 602                 dma_addr_t sg_addr = sg_dma_address(sg);
 603                 size_t len = sg_dma_len(sg);
 604
 605                 if (!len)
 606                         goto err_get_desc;
 607
 608                 do {
 609                         dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
 610                                 i, sg, len, (unsigned long long)sg_addr);
 611
 612                         if (direction == DMA_DEV_TO_MEM)
 613                                 new = sh_dmae_add_desc(sh_chan, flags,
 614                                                 &sg_addr, addr, &len, &first,
 615                                                 direction);
 616                         else
 617                                 new = sh_dmae_add_desc(sh_chan, flags,
 618                                                 addr, &sg_addr, &len, &first,
 619                                                 direction);
 620                         if (!new)
 621                                 goto err_get_desc;
 622
 623                         new->chunks = chunks--;
 624                         list_add_tail(&new->node, &tx_list);
 625                 } while (len);
 626         }
 627
 628         if (new != first)
 629                 new->async_tx.cookie = -ENOSPC;
 630
 631         /* Put them back on the free list, so, they don't get lost */
 632         list_splice_tail(&tx_list, &sh_chan->ld_free);
 633
 634         spin_unlock_irqrestore(&sh_chan->desc_lock, irq_flags);
 635
 636         return &first->async_tx;
 637
 638 err_get_desc:
 639         list_for_each_entry(new, &tx_list, node)
 640                 new->mark = DESC_IDLE;
 641         list_splice(&tx_list, &sh_chan->ld_free);
 642
 643         spin_unlock_irqrestore(&sh_chan->desc_lock, irq_flags);
 644
 645         return NULL;
 646 }
 647
 648 static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
 649         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
 650         size_t len, unsigned long flags)
 651 {
 652         struct sh_dmae_chan *sh_chan;
 653         struct scatterlist sg;
 654
 655         if (!chan || !len)
 656                 return NULL;
 657
 658         sh_chan = to_sh_chan(chan);
 659
 660         sg_init_table(&sg, 1);
 661         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
 662                     offset_in_page(dma_src));
 663         sg_dma_address(&sg) = dma_src;
 664         sg_dma_len(&sg) = len;
 665
 666         return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_MEM_TO_MEM,
 667                                flags);
 668 }
 669
 670 static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
 671         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
 672         enum dma_transfer_direction direction, unsigned long flags)
 673 {
 674         struct sh_dmae_slave *param;
 675         struct sh_dmae_chan *sh_chan;
 676         dma_addr_t slave_addr;
 677
 678         if (!chan)
 679                 return NULL;
 680
 681         sh_chan = to_sh_chan(chan);
 682         param = chan->private;
 683
 684         /* Someone calling slave DMA on a public channel? */
 685         if (!param || !sg_len) {
 686                 dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n",
 687                          __func__, param, sg_len, param ? param->slave_id : -1);
 688                 return NULL;
 689         }
 690
 691         slave_addr = param->config->addr;
 692
 693         /*
 694          * if (param != NULL), this is a successfully requested slave channel,
 695          * therefore param->config != NULL too.
 696          */
 697         return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &slave_addr,
 698                                direction, flags);
 699 }
 700
 701 static int sh_dmae_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 702                            unsigned long arg)
 703 {
 704         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 705         unsigned long flags;
 706
 707         /* Only supports DMA_TERMINATE_ALL */
 708         if (cmd != DMA_TERMINATE_ALL)
 709                 return -ENXIO;
 710
 711         if (!chan)
 712                 return -EINVAL;
 713
 714         spin_lock_irqsave(&sh_chan->desc_lock, flags);
 715         dmae_halt(sh_chan);
 716
 717         if (!list_empty(&sh_chan->ld_queue)) {
 718                 /* Record partial transfer */
 719                 struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
 720                                                   struct sh_desc, node);
 721                 desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
 722                         sh_chan->xmit_shift;
 723         }
 724         spin_unlock_irqrestore(&sh_chan->desc_lock, flags);
 725
 726         sh_dmae_chan_ld_cleanup(sh_chan, true);
 727
 728         return 0;
 729 }
 730
 731 static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
 732 {
 733         struct sh_desc *desc, *_desc;
 734         /* Is the "exposed" head of a chain acked? */
 735         bool head_acked = false;
 736         dma_cookie_t cookie = 0;
 737         dma_async_tx_callback callback = NULL;
 738         void *param = NULL;
 739         unsigned long flags;
 740
 741         spin_lock_irqsave(&sh_chan->desc_lock, flags);
 742         list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
 743                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
 744
 745                 BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
 746                 BUG_ON(desc->mark != DESC_SUBMITTED &&
 747                        desc->mark != DESC_COMPLETED &&
 748                        desc->mark != DESC_WAITING);
 749
 750                 /*
 751                  * queue is ordered, and we use this loop to (1) clean up all
 752                  * completed descriptors, and to (2) update descriptor flags of
 753                  * any chunks in a (partially) completed chain
 754                  */
 755                 if (!all && desc->mark == DESC_SUBMITTED &&
 756                     desc->cookie != cookie)
 757                         break;
 758
 759                 if (tx->cookie > 0)
 760                         cookie = tx->cookie;
 761
 762                 if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
 763                         if (sh_chan->common.completed_cookie != desc->cookie - 1)
 764                                 dev_dbg(sh_chan->dev,
 765                                         "Completing cookie %d, expected %d\n",
 766                                         desc->cookie,
 767                                         sh_chan->common.completed_cookie + 1);
 768                         sh_chan->common.completed_cookie = desc->cookie;
 769                 }
 770
 771                 /* Call callback on the last chunk */
 772                 if (desc->mark == DESC_COMPLETED && tx->callback) {
 773                         desc->mark = DESC_WAITING;
 774                         callback = tx->callback;
 775                         param = tx->callback_param;
 776                         dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
 777                                 tx->cookie, tx, sh_chan->id);
 778                         BUG_ON(desc->chunks != 1);
 779                         break;
 780                 }
 781
 782                 if (tx->cookie > 0 || tx->cookie == -EBUSY) {
 783                         if (desc->mark == DESC_COMPLETED) {
 784                                 BUG_ON(tx->cookie < 0);
 785                                 desc->mark = DESC_WAITING;
 786                         }
 787                         head_acked = async_tx_test_ack(tx);
 788                 } else {
 789                         switch (desc->mark) {
 790                         case DESC_COMPLETED:
 791                                 desc->mark = DESC_WAITING;
 792                                 /* Fall through */
 793                         case DESC_WAITING:
 794                                 if (head_acked)
 795                                         async_tx_ack(&desc->async_tx);
 796                         }
 797                 }
 798
 799                 dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
 800                         tx, tx->cookie);
 801
 802                 if (((desc->mark == DESC_COMPLETED ||
 803                       desc->mark == DESC_WAITING) &&
 804                      async_tx_test_ack(&desc->async_tx)) || all) {
 805                         /* Remove from ld_queue list */
 806                         desc->mark = DESC_IDLE;
 807
 808                         list_move(&desc->node, &sh_chan->ld_free);
 809
 810                         if (list_empty(&sh_chan->ld_queue)) {
 811                                 dev_dbg(sh_chan->dev, "Bring down channel %d\n", sh_chan->id);
 812                                 pm_runtime_put(sh_chan->dev);
 813                         }
 814                 }
 815         }
 816
 817         if (all && !callback)
 818                 /*
 819                  * Terminating and the loop completed normally: forgive
 820                  * uncompleted cookies
 821                  */
 822                 sh_chan->common.completed_cookie = sh_chan->common.cookie;
 823
 824         spin_unlock_irqrestore(&sh_chan->desc_lock, flags);
 825
 826         if (callback)
 827                 callback(param);
 828
 829         return callback;
 830 }
 831
 832 /*
 833  * sh_chan_ld_cleanup - Clean up link descriptors
 834  *
 835  * This function cleans up the ld_queue of DMA channel.
 836  */
 837 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
 838 {
 839         while (__ld_cleanup(sh_chan, all))
 840                 ;
 841 }
 842
 843 /* Called under spin_lock_irq(&sh_chan->desc_lock) */
 844 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
 845 {
 846         struct sh_desc *desc;
 847
 848         /* DMA work check */
 849         if (dmae_is_busy(sh_chan))
 850                 return;
 851
 852         /* Find the first not transferred descriptor */
 853         list_for_each_entry(desc, &sh_chan->ld_queue, node)
 854                 if (desc->mark == DESC_SUBMITTED) {
 855                         dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n",
 856                                 desc->async_tx.cookie, sh_chan->id,
 857                                 desc->hw.tcr, desc->hw.sar, desc->hw.dar);
 858                         /* Get the ld start address from ld_queue */
 859                         dmae_set_reg(sh_chan, &desc->hw);
 860                         dmae_start(sh_chan);
 861                         break;
 862                 }
 863 }
 864
 865 static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
 866 {
 867         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 868
 869         spin_lock_irq(&sh_chan->desc_lock);
 870         if (sh_chan->pm_state == DMAE_PM_ESTABLISHED)
 871                 sh_chan_xfer_ld_queue(sh_chan);
 872         else
 873                 sh_chan->pm_state = DMAE_PM_PENDING;
 874         spin_unlock_irq(&sh_chan->desc_lock);
 875 }
 876
 877 static enum dma_status sh_dmae_tx_status(struct dma_chan *chan,
 878                                         dma_cookie_t cookie,
 879                                         struct dma_tx_state *txstate)
 880 {
 881         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 882         dma_cookie_t last_used;
 883         dma_cookie_t last_complete;
 884         enum dma_status status;
 885         unsigned long flags;
 886
 887         sh_dmae_chan_ld_cleanup(sh_chan, false);
 888
 889         /* First read completed cookie to avoid a skew */
 890         last_complete = chan->completed_cookie;
 891         rmb();
 892         last_used = chan->cookie;
 893         BUG_ON(last_complete < 0);
 894         dma_set_tx_state(txstate, last_complete, last_used, 0);
 895
 896         spin_lock_irqsave(&sh_chan->desc_lock, flags);
 897
 898         status = dma_async_is_complete(cookie, last_complete, last_used);
 899
 900         /*
 901          * If we don't find cookie on the queue, it has been aborted and we have
 902          * to report error
 903          */
 904         if (status != DMA_SUCCESS) {
 905                 struct sh_desc *desc;
 906                 status = DMA_ERROR;
 907                 list_for_each_entry(desc, &sh_chan->ld_queue, node)
 908                         if (desc->cookie == cookie) {
 909                                 status = DMA_IN_PROGRESS;
 910                                 break;
 911                         }
 912         }
 913
 914         spin_unlock_irqrestore(&sh_chan->desc_lock, flags);
 915
 916         return status;
 917 }
 918
 919 static irqreturn_t sh_dmae_interrupt(int irq, void *data)
 920 {
 921         irqreturn_t ret = IRQ_NONE;
 922         struct sh_dmae_chan *sh_chan = data;
 923         u32 chcr;
 924
 925         spin_lock(&sh_chan->desc_lock);
 926
 927         chcr = chcr_read(sh_chan);
 928
 929         if (chcr & CHCR_TE) {
 930                 /* DMA stop */
 931                 dmae_halt(sh_chan);
 932
 933                 ret = IRQ_HANDLED;
 934                 tasklet_schedule(&sh_chan->tasklet);
 935         }
 936
 937         spin_unlock(&sh_chan->desc_lock);
 938
 939         return ret;
 940 }
 941
 942 /* Called from error IRQ or NMI */
 943 static bool sh_dmae_reset(struct sh_dmae_device *shdev)
 944 {
 945         unsigned int handled = 0;
 946         int i;
 947
 948         /* halt the dma controller */
 949         sh_dmae_ctl_stop(shdev);
 950
 951         /* We cannot detect, which channel caused the error, have to reset all */
 952         for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
 953                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
 954                 struct sh_desc *desc;
 955                 LIST_HEAD(dl);
 956
 957                 if (!sh_chan)
 958                         continue;
 959
 960                 spin_lock(&sh_chan->desc_lock);
 961
 962                 /* Stop the channel */
 963                 dmae_halt(sh_chan);
 964
 965                 list_splice_init(&sh_chan->ld_queue, &dl);
 966
 967                 if (!list_empty(&dl)) {
 968                         dev_dbg(sh_chan->dev, "Bring down channel %d\n", sh_chan->id);
 969                         pm_runtime_put(sh_chan->dev);
 970                 }
 971                 sh_chan->pm_state = DMAE_PM_ESTABLISHED;
 972
 973                 spin_unlock(&sh_chan->desc_lock);
 974
 975                 /* Complete all  */
 976                 list_for_each_entry(desc, &dl, node) {
 977                         struct dma_async_tx_descriptor *tx = &desc->async_tx;
 978                         desc->mark = DESC_IDLE;
 979                         if (tx->callback)
 980                                 tx->callback(tx->callback_param);
 981                 }
 982
 983                 spin_lock(&sh_chan->desc_lock);
 984                 list_splice(&dl, &sh_chan->ld_free);
 985                 spin_unlock(&sh_chan->desc_lock);
 986
 987                 handled++;
 988         }
 989
 990         sh_dmae_rst(shdev);
 991
 992         return !!handled;
 993 }
 994
 995 static irqreturn_t sh_dmae_err(int irq, void *data)
 996 {
 997         struct sh_dmae_device *shdev = data;
 998
 999         if (!(dmaor_read(shdev) & DMAOR_AE))
1000                 return IRQ_NONE;
1001
1002         sh_dmae_reset(data);
1003         return IRQ_HANDLED;
1004 }
1005
1006 static void dmae_do_tasklet(unsigned long data)
1007 {
1008         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
1009         struct sh_desc *desc;
1010         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
1011         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
1012
1013         spin_lock_irq(&sh_chan->desc_lock);
1014         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
1015                 if (desc->mark == DESC_SUBMITTED &&
1016                     ((desc->direction == DMA_DEV_TO_MEM &&
1017                       (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
1018                      (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
1019                         dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
1020                                 desc->async_tx.cookie, &desc->async_tx,
1021                                 desc->hw.dar);
1022                         desc->mark = DESC_COMPLETED;
1023                         break;
1024                 }
1025         }
1026         /* Next desc */
1027         sh_chan_xfer_ld_queue(sh_chan);
1028         spin_unlock_irq(&sh_chan->desc_lock);
1029
1030         sh_dmae_chan_ld_cleanup(sh_chan, false);
1031 }
1032
1033 static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
1034 {
1035         /* Fast path out if NMIF is not asserted for this controller */
1036         if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
1037                 return false;
1038
1039         return sh_dmae_reset(shdev);
1040 }
1041
1042 static int sh_dmae_nmi_handler(struct notifier_block *self,
1043                                unsigned long cmd, void *data)
1044 {
1045         struct sh_dmae_device *shdev;
1046         int ret = NOTIFY_DONE;
1047         bool triggered;
1048
1049         /*
1050          * Only concern ourselves with NMI events.
1051          *
1052          * Normally we would check the die chain value, but as this needs
1053          * to be architecture independent, check for NMI context instead.
1054          */
1055         if (!in_nmi())
1056                 return NOTIFY_DONE;
1057
1058         rcu_read_lock();
1059         list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
1060                 /*
1061                  * Only stop if one of the controllers has NMIF asserted,
1062                  * we do not want to interfere with regular address error
1063                  * handling or NMI events that don't concern the DMACs.
1064                  */
1065                 triggered = sh_dmae_nmi_notify(shdev);
1066                 if (triggered == true)
1067                         ret = NOTIFY_OK;
1068         }
1069         rcu_read_unlock();
1070
1071         return ret;
1072 }
1073
1074 static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
1075         .notifier_call  = sh_dmae_nmi_handler,
1076
1077         /* Run before NMI debug handler and KGDB */
1078         .priority       = 1,
1079 };
1080
1081 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
1082                                         int irq, unsigned long flags)
1083 {
1084         int err;
1085         const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
1086         struct platform_device *pdev = to_platform_device(shdev->common.dev);
1087         struct sh_dmae_chan *new_sh_chan;
1088
1089         /* alloc channel */
1090         new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
1091         if (!new_sh_chan) {
1092                 dev_err(shdev->common.dev,
1093                         "No free memory for allocating dma channels!\n");
1094                 return -ENOMEM;
1095         }
1096
1097         new_sh_chan->pm_state = DMAE_PM_ESTABLISHED;
1098
1099         /* reference struct dma_device */
1100         new_sh_chan->common.device = &shdev->common;
1101
1102         new_sh_chan->dev = shdev->common.dev;
1103         new_sh_chan->id = id;
1104         new_sh_chan->irq = irq;
1105         new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
1106
1107         /* Init DMA tasklet */
1108         tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
1109                         (unsigned long)new_sh_chan);
1110
1111         spin_lock_init(&new_sh_chan->desc_lock);
1112
1113         /* Init descripter manage list */
1114         INIT_LIST_HEAD(&new_sh_chan->ld_queue);
1115         INIT_LIST_HEAD(&new_sh_chan->ld_free);
1116
1117         /* Add the channel to DMA device channel list */
1118         list_add_tail(&new_sh_chan->common.device_node,
1119                         &shdev->common.channels);
1120         shdev->common.chancnt++;
1121
1122         if (pdev->id >= 0)
1123                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
1124                          "sh-dmae%d.%d", pdev->id, new_sh_chan->id);
1125         else
1126                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
1127                          "sh-dma%d", new_sh_chan->id);
1128
1129         /* set up channel irq */
1130         err = request_irq(irq, &sh_dmae_interrupt, flags,
1131                           new_sh_chan->dev_id, new_sh_chan);
1132         if (err) {
1133                 dev_err(shdev->common.dev, "DMA channel %d request_irq error "
1134                         "with return %d\n", id, err);
1135                 goto err_no_irq;
1136         }
1137
1138         shdev->chan[id] = new_sh_chan;
1139         return 0;
1140
1141 err_no_irq:
1142         /* remove from dmaengine device node */
1143         list_del(&new_sh_chan->common.device_node);
1144         kfree(new_sh_chan);
1145         return err;
1146 }
1147
1148 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
1149 {
1150         int i;
1151
1152         for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
1153                 if (shdev->chan[i]) {
1154                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
1155
1156                         free_irq(sh_chan->irq, sh_chan);
1157
1158                         list_del(&sh_chan->common.device_node);
1159                         kfree(sh_chan);
1160                         shdev->chan[i] = NULL;
1161                 }
1162         }
1163         shdev->common.chancnt = 0;
1164 }
1165
1166 static int __init sh_dmae_probe(struct platform_device *pdev)
1167 {
1168         struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
1169         unsigned long irqflags = IRQF_DISABLED,
1170                 chan_flag[SH_DMAC_MAX_CHANNELS] = {};
1171         int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
1172         int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
1173         struct sh_dmae_device *shdev;
1174         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
1175
1176         /* get platform data */
1177         if (!pdata || !pdata->channel_num)
1178                 return -ENODEV;
1179
1180         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1181         /* DMARS area is optional */
1182         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1183         /*
1184          * IRQ resources:
1185          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
1186          *    the error IRQ, in which case it is the only IRQ in this resource:
1187          *    start == end. If it is the only IRQ resource, all channels also
1188          *    use the same IRQ.
1189          * 2. DMA channel IRQ resources can be specified one per resource or in
1190          *    ranges (start != end)
1191          * 3. iff all events (channels and, optionally, error) on this
1192          *    controller use the same IRQ, only one IRQ resource can be
1193          *    specified, otherwise there must be one IRQ per channel, even if
1194          *    some of them are equal
1195          * 4. if all IRQs on this controller are equal or if some specific IRQs
1196          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
1197          *    requested with the IRQF_SHARED flag
1198          */
1199         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1200         if (!chan || !errirq_res)
1201                 return -ENODEV;
1202
1203         if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
1204                 dev_err(&pdev->dev, "DMAC register region already claimed\n");
1205                 return -EBUSY;
1206         }
1207
1208         if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
1209                 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
1210                 err = -EBUSY;
1211                 goto ermrdmars;
1212         }
1213
1214         err = -ENOMEM;
1215         shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
1216         if (!shdev) {
1217                 dev_err(&pdev->dev, "Not enough memory\n");
1218                 goto ealloc;
1219         }
1220
1221         shdev->chan_reg = ioremap(chan->start, resource_size(chan));
1222         if (!shdev->chan_reg)
1223                 goto emapchan;
1224         if (dmars) {
1225                 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
1226                 if (!shdev->dmars)
1227                         goto emapdmars;
1228         }
1229
1230         /* platform data */
1231         shdev->pdata = pdata;
1232
1233         if (pdata->chcr_offset)
1234                 shdev->chcr_offset = pdata->chcr_offset;
1235         else
1236                 shdev->chcr_offset = CHCR;
1237
1238         if (pdata->chcr_ie_bit)
1239                 shdev->chcr_ie_bit = pdata->chcr_ie_bit;
1240         else
1241                 shdev->chcr_ie_bit = CHCR_IE;
1242
1243         platform_set_drvdata(pdev, shdev);
1244
1245         shdev->common.dev = &pdev->dev;
1246
1247         pm_runtime_enable(&pdev->dev);
1248         pm_runtime_get_sync(&pdev->dev);
1249
1250         spin_lock_irq(&sh_dmae_lock);
1251         list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
1252         spin_unlock_irq(&sh_dmae_lock);
1253
1254         /* reset dma controller - only needed as a test */
1255         err = sh_dmae_rst(shdev);
1256         if (err)
1257                 goto rst_err;
1258
1259         INIT_LIST_HEAD(&shdev->common.channels);
1260
1261         if (!pdata->slave_only)
1262                 dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
1263         if (pdata->slave && pdata->slave_num)
1264                 dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
1265
1266         shdev->common.device_alloc_chan_resources
1267                 = sh_dmae_alloc_chan_resources;
1268         shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
1269         shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
1270         shdev->common.device_tx_status = sh_dmae_tx_status;
1271         shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
1272
1273         /* Compulsory for DMA_SLAVE fields */
1274         shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg;
1275         shdev->common.device_control = sh_dmae_control;
1276
1277         /* Default transfer size of 32 bytes requires 32-byte alignment */
1278         shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1279
1280 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1281         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1282
1283         if (!chanirq_res)
1284                 chanirq_res = errirq_res;
1285         else
1286                 irqres++;
1287
1288         if (chanirq_res == errirq_res ||
1289             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
1290                 irqflags = IRQF_SHARED;
1291
1292         errirq = errirq_res->start;
1293
1294         err = request_irq(errirq, sh_dmae_err, irqflags,
1295                           "DMAC Address Error", shdev);
1296         if (err) {
1297                 dev_err(&pdev->dev,
1298                         "DMA failed requesting irq #%d, error %d\n",
1299                         errirq, err);
1300                 goto eirq_err;
1301         }
1302
1303 #else
1304         chanirq_res = errirq_res;
1305 #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
1306
1307         if (chanirq_res->start == chanirq_res->end &&
1308             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
1309                 /* Special case - all multiplexed */
1310                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
1311                         if (irq_cnt < SH_DMAC_MAX_CHANNELS) {
1312                                 chan_irq[irq_cnt] = chanirq_res->start;
1313                                 chan_flag[irq_cnt] = IRQF_SHARED;
1314                         } else {
1315                                 irq_cap = 1;
1316                                 break;
1317                         }
1318                 }
1319         } else {
1320                 do {
1321                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
1322                                 if (irq_cnt >= SH_DMAC_MAX_CHANNELS) {
1323                                         irq_cap = 1;
1324                                         break;
1325                                 }
1326
1327                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
1328                                     IORESOURCE_IRQ_SHAREABLE)
1329                                         chan_flag[irq_cnt] = IRQF_SHARED;
1330                                 else
1331                                         chan_flag[irq_cnt] = IRQF_DISABLED;
1332                                 dev_dbg(&pdev->dev,
1333                                         "Found IRQ %d for channel %d\n",
1334                                         i, irq_cnt);
1335                                 chan_irq[irq_cnt++] = i;
1336                         }
1337
1338                         if (irq_cnt >= SH_DMAC_MAX_CHANNELS)
1339                                 break;
1340
1341                         chanirq_res = platform_get_resource(pdev,
1342                                                 IORESOURCE_IRQ, ++irqres);
1343                 } while (irq_cnt < pdata->channel_num && chanirq_res);
1344         }
1345
1346         /* Create DMA Channel */
1347         for (i = 0; i < irq_cnt; i++) {
1348                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
1349                 if (err)
1350                         goto chan_probe_err;
1351         }
1352
1353         if (irq_cap)
1354                 dev_notice(&pdev->dev, "Attempting to register %d DMA "
1355                            "channels when a maximum of %d are supported.\n",
1356                            pdata->channel_num, SH_DMAC_MAX_CHANNELS);
1357
1358         pm_runtime_put(&pdev->dev);
1359
1360         dma_async_device_register(&shdev->common);
1361
1362         return err;
1363
1364 chan_probe_err:
1365         sh_dmae_chan_remove(shdev);
1366
1367 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1368         free_irq(errirq, shdev);
1369 eirq_err:
1370 #endif
1371 rst_err:
1372         spin_lock_irq(&sh_dmae_lock);
1373         list_del_rcu(&shdev->node);
1374         spin_unlock_irq(&sh_dmae_lock);
1375
1376         pm_runtime_put(&pdev->dev);
1377         pm_runtime_disable(&pdev->dev);
1378
1379         if (dmars)
1380                 iounmap(shdev->dmars);
1381
1382         platform_set_drvdata(pdev, NULL);
1383 emapdmars:
1384         iounmap(shdev->chan_reg);
1385         synchronize_rcu();
1386 emapchan:
1387         kfree(shdev);
1388 ealloc:
1389         if (dmars)
1390                 release_mem_region(dmars->start, resource_size(dmars));
1391 ermrdmars:
1392         release_mem_region(chan->start, resource_size(chan));
1393
1394         return err;
1395 }
1396
1397 static int __exit sh_dmae_remove(struct platform_device *pdev)
1398 {
1399         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1400         struct resource *res;
1401         int errirq = platform_get_irq(pdev, 0);
1402
1403         dma_async_device_unregister(&shdev->common);
1404
1405         if (errirq > 0)
1406                 free_irq(errirq, shdev);
1407
1408         spin_lock_irq(&sh_dmae_lock);
1409         list_del_rcu(&shdev->node);
1410         spin_unlock_irq(&sh_dmae_lock);
1411
1412         /* channel data remove */
1413         sh_dmae_chan_remove(shdev);
1414
1415         pm_runtime_disable(&pdev->dev);
1416
1417         if (shdev->dmars)
1418                 iounmap(shdev->dmars);
1419         iounmap(shdev->chan_reg);
1420
1421         platform_set_drvdata(pdev, NULL);
1422
1423         synchronize_rcu();
1424         kfree(shdev);
1425
1426         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1427         if (res)
1428                 release_mem_region(res->start, resource_size(res));
1429         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1430         if (res)
1431                 release_mem_region(res->start, resource_size(res));
1432
1433         return 0;
1434 }
1435
1436 static void sh_dmae_shutdown(struct platform_device *pdev)
1437 {
1438         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1439         sh_dmae_ctl_stop(shdev);
1440 }
1441
1442 static int sh_dmae_runtime_suspend(struct device *dev)
1443 {
1444         return 0;
1445 }
1446
1447 static int sh_dmae_runtime_resume(struct device *dev)
1448 {
1449         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1450
1451         return sh_dmae_rst(shdev);
1452 }
1453
1454 #ifdef CONFIG_PM
1455 static int sh_dmae_suspend(struct device *dev)
1456 {
1457         return 0;
1458 }
1459
1460 static int sh_dmae_resume(struct device *dev)
1461 {
1462         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1463         int i, ret;
1464
1465         ret = sh_dmae_rst(shdev);
1466         if (ret < 0)
1467                 dev_err(dev, "Failed to reset!\n");
1468
1469         for (i = 0; i < shdev->pdata->channel_num; i++) {
1470                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
1471                 struct sh_dmae_slave *param = sh_chan->common.private;
1472
1473                 if (!sh_chan->descs_allocated)
1474                         continue;
1475
1476                 if (param) {
1477                         const struct sh_dmae_slave_config *cfg = param->config;
1478                         dmae_set_dmars(sh_chan, cfg->mid_rid);
1479                         dmae_set_chcr(sh_chan, cfg->chcr);
1480                 } else {
1481                         dmae_init(sh_chan);
1482                 }
1483         }
1484
1485         return 0;
1486 }
1487 #else
1488 #define sh_dmae_suspend NULL
1489 #define sh_dmae_resume NULL
1490 #endif
1491
1492 const struct dev_pm_ops sh_dmae_pm = {
1493         .suspend                = sh_dmae_suspend,
1494         .resume                 = sh_dmae_resume,
1495         .runtime_suspend        = sh_dmae_runtime_suspend,
1496         .runtime_resume         = sh_dmae_runtime_resume,
1497 };
1498
1499 static struct platform_driver sh_dmae_driver = {
1500         .remove         = __exit_p(sh_dmae_remove),
1501         .shutdown       = sh_dmae_shutdown,
1502         .driver = {
1503                 .owner  = THIS_MODULE,
1504                 .name   = "sh-dma-engine",
1505                 .pm     = &sh_dmae_pm,
1506         },
1507 };
1508
1509 static int __init sh_dmae_init(void)
1510 {
1511         /* Wire up NMI handling */
1512         int err = register_die_notifier(&sh_dmae_nmi_notifier);
1513         if (err)
1514                 return err;
1515
1516         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
1517 }
1518 module_init(sh_dmae_init);
1519
1520 static void __exit sh_dmae_exit(void)
1521 {
1522         platform_driver_unregister(&sh_dmae_driver);
1523
1524         unregister_die_notifier(&sh_dmae_nmi_notifier);
1525 }
1526 module_exit(sh_dmae_exit);
1527
1528 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
1529 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
1530 MODULE_LICENSE("GPL");
1531 MODULE_ALIAS("platform:sh-dma-engine");